diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/core/dc_resource.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 45 |
1 files changed, 31 insertions, 14 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 59d48cf819ea..07c22556480b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -54,9 +54,9 @@ #include "dcn10/dcn10_resource.h" #include "dcn20/dcn20_resource.h" #include "dcn21/dcn21_resource.h" -#endif -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) -#include "../dcn30/dcn30_resource.h" +#include "dcn30/dcn30_resource.h" +#include "dcn301/dcn301_resource.h" +#include "dcn302/dcn302_resource.h" #endif #define DC_LOGGER_INIT(logger) @@ -123,15 +123,19 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev)) dc_version = DCN_VERSION_2_1; break; -#endif case FAMILY_NV: dc_version = DCN_VERSION_2_0; -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev)) dc_version = DCN_VERSION_3_0; -#endif + if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev)) + dc_version = DCN_VERSION_3_02; + break; + + case FAMILY_VGH: + dc_version = DCN_VERSION_3_01; break; +#endif default: dc_version = DCE_VERSION_UNKNOWN; break; @@ -197,21 +201,22 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc, case DCN_VERSION_1_01: res_pool = dcn10_create_resource_pool(init_data, dc); break; - - case DCN_VERSION_2_0: res_pool = dcn20_create_resource_pool(init_data, dc); break; case DCN_VERSION_2_1: res_pool = dcn21_create_resource_pool(init_data, dc); break; -#endif -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) case DCN_VERSION_3_0: res_pool = dcn30_create_resource_pool(init_data, dc); break; + case DCN_VERSION_3_01: + res_pool = dcn301_create_resource_pool(init_data, dc); + break; + case DCN_VERSION_3_02: + res_pool = dcn302_create_resource_pool(init_data, dc); + break; #endif - default: break; } @@ -325,7 +330,7 @@ bool resource_construct( } } -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) +#if defined(CONFIG_DRM_AMD_DC_DCN) for (i = 0; i < caps->num_mpc_3dlut; i++) { pool->mpc_lut[i] = dc_create_3dlut_func(); if (pool->mpc_lut[i] == NULL) @@ -796,6 +801,8 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx) } else data->recout.x = 0; + if (stream->src.x > surf_clip.x) + surf_clip.width -= stream->src.x - surf_clip.x; data->recout.width = surf_clip.width * stream->dst.width / stream->src.width; if (data->recout.width + data->recout.x > stream->dst.x + stream->dst.width) data->recout.width = stream->dst.x + stream->dst.width - data->recout.x; @@ -804,6 +811,8 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx) if (stream->src.y < surf_clip.y) data->recout.y += (surf_clip.y - stream->src.y) * stream->dst.height / stream->src.height; + else if (stream->src.y > surf_clip.y) + surf_clip.height -= stream->src.y - surf_clip.y; data->recout.height = surf_clip.height * stream->dst.height / stream->src.height; if (data->recout.height + data->recout.y > stream->dst.y + stream->dst.height) @@ -1481,6 +1490,14 @@ bool dc_add_plane_to_context( free_pipe->clock_source = tail_pipe->clock_source; free_pipe->top_pipe = tail_pipe; tail_pipe->bottom_pipe = free_pipe; + if (!free_pipe->next_odm_pipe && tail_pipe->next_odm_pipe && tail_pipe->next_odm_pipe->bottom_pipe) { + free_pipe->next_odm_pipe = tail_pipe->next_odm_pipe->bottom_pipe; + tail_pipe->next_odm_pipe->bottom_pipe->prev_odm_pipe = free_pipe; + } + if (!free_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe->bottom_pipe) { + free_pipe->prev_odm_pipe = tail_pipe->prev_odm_pipe->bottom_pipe; + tail_pipe->prev_odm_pipe->bottom_pipe->next_odm_pipe = free_pipe; + } } head_pipe = head_pipe->next_odm_pipe; } @@ -2130,7 +2147,7 @@ enum dc_status resource_map_pool_resources( /* Add ABM to the resource if on EDP */ if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal)) { -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) +#if defined(CONFIG_DRM_AMD_DC_DCN) if (pool->abm) pipe_ctx->stream_res.abm = pool->abm; else @@ -2955,7 +2972,7 @@ unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format) case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) +#if defined(CONFIG_DRM_AMD_DC_DCN) case SURFACE_PIXEL_FORMAT_GRPH_RGBE: case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: #endif |