diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dc.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dc.h | 144 |
1 files changed, 143 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 44e4b0465587..e513028faefa 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -39,7 +39,7 @@ #include "inc/hw/dmcu.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.2.27" +#define DC_VER "3.2.35" #define MAX_SURFACES 3 #define MAX_PLANES 6 @@ -70,6 +70,8 @@ struct dc_plane_cap { uint32_t argb8888 : 1; uint32_t nv12 : 1; uint32_t fp16 : 1; + uint32_t p010 : 1; + uint32_t ayuv : 1; } pixel_format_support; // max upscaling factor x1000 // upscaling factors are always >= 1 @@ -109,9 +111,19 @@ struct dc_caps { bool force_dp_tps4_for_cp2520; bool disable_dp_clk_share; bool psp_setup_panel_mode; +#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + bool hw_3d_lut; +#endif struct dc_plane_cap planes[MAX_PLANES]; }; +#if defined(CONFIG_DRM_AMD_DC_DCN2_0) +struct dc_bug_wa { + bool no_connect_phy_config; + bool dedcn20_305_wa; +}; +#endif + struct dc_dcc_surface_param { struct dc_size surface_size; enum surface_pixel_format format; @@ -205,6 +217,9 @@ struct dc_config { bool disable_fractional_pwm; bool allow_seamless_boot_optimization; bool power_down_display_on_boot; + bool edp_not_connected; + bool forced_clocks; + }; enum visual_confirm { @@ -320,6 +335,9 @@ struct dc_debug_options { bool disable_dfs_bypass; bool disable_dpp_power_gate; bool disable_hubp_power_gate; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + bool disable_dsc_power_gate; +#endif bool disable_pplib_wm_range; enum wm_report_mode pplib_wm_report_mode; unsigned int min_disp_clk_khz; @@ -328,6 +346,7 @@ struct dc_debug_options { int sr_exit_time_ns; int sr_enter_plus_exit_time_ns; int urgent_latency_ns; + uint32_t underflow_assert_delay_us; int percent_of_ideal_drambw; int dram_clock_change_latency_ns; bool optimized_watermark; @@ -352,6 +371,13 @@ struct dc_debug_options { unsigned int force_fclk_khz; bool disable_tri_buf; struct dc_bw_validation_profile bw_val_profile; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + bool disable_fec; +#endif + /* This forces a hard min on the DCFCLK requested to SMU/PP + * watermarks are not affected. + */ + unsigned int force_min_dcfclk_mhz; }; struct dc_debug_data { @@ -360,17 +386,54 @@ struct dc_debug_data { uint32_t auxErrorCount; }; +#ifdef CONFIG_DRM_AMD_DC_DCN2_0 +struct dc_phy_addr_space_config { + struct { + uint64_t start_addr; + uint64_t end_addr; + uint64_t fb_top; + uint64_t fb_offset; + uint64_t fb_base; + uint64_t agp_top; + uint64_t agp_bot; + uint64_t agp_base; + } system_aperture; + + struct { + uint64_t page_table_start_addr; + uint64_t page_table_end_addr; + uint64_t page_table_base_addr; + } gart_config; + + bool valid; +}; + +struct dc_virtual_addr_space_config { + uint64_t page_table_base_addr; + uint64_t page_table_start_addr; + uint64_t page_table_end_addr; + uint32_t page_table_block_size_in_bytes; + uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid +}; +#endif + struct dc_bounding_box_overrides { int sr_exit_time_ns; int sr_enter_plus_exit_time_ns; int urgent_latency_ns; int percent_of_ideal_drambw; int dram_clock_change_latency_ns; + /* This forces a hard min on the DCFCLK we use + * for DML. Unlike the debug option for forcing + * DCFCLK, this override affects watermark calculations + */ + int min_dcfclk_mhz; }; struct dc_state; struct resource_pool; struct dce_hwseq; +struct gpu_info_soc_bounding_box_v1_0; struct dc { struct dc_versions versions; struct dc_caps caps; @@ -378,7 +441,13 @@ struct dc { struct dc_config config; struct dc_debug_options debug; struct dc_bounding_box_overrides bb_overrides; +#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + struct dc_bug_wa work_arounds; +#endif struct dc_context *ctx; +#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + struct dc_phy_addr_space_config vm_pa_config; +#endif uint8_t link_count; struct dc_link *links[MAX_PIPES * 2]; @@ -386,6 +455,8 @@ struct dc { struct dc_state *current_state; struct resource_pool *res_pool; + struct clk_mgr *clk_mgr; + /* Display Engine Clock levels */ struct dm_pp_clock_levels sclk_lvls; @@ -414,6 +485,10 @@ struct dc { struct dc_debug_data debug_data; const char *build_id; +#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + struct vm_helper *vm_helper; + const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; +#endif }; enum frame_buffer_mode { @@ -447,6 +522,13 @@ struct dc_init_data { struct dc_config flags; uint32_t log_mask; +#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + /** + * gpu_info FW provided soc bounding box struct or 0 if not + * available in FW + */ + const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; +#endif }; struct dc_callback_init { @@ -454,6 +536,12 @@ struct dc_callback_init { }; struct dc *dc_create(const struct dc_init_data *init_params); +int dc_get_vmid_use_vector(struct dc *dc); +#ifdef CONFIG_DRM_AMD_DC_DCN2_0 +void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); +/* Returns the number of vmids supported */ +int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); +#endif void dc_init_callbacks(struct dc *dc, const struct dc_callback_init *init_params); void dc_destroy(struct dc **dc); @@ -525,6 +613,17 @@ struct dc_transfer_func { }; }; +#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + + +struct dc_3dlut { + struct kref refcount; + struct tetrahedral_params lut_3d; + uint32_t hdr_multiplier; + bool initialized; + struct dc_context *ctx; +}; +#endif /* * This structure is filled in by dc_surface_get_status and contains * the last requested address and the currently active address so the called @@ -540,12 +639,14 @@ struct dc_plane_status { union surface_update_flags { struct { + uint32_t addr_update:1; /* Medium updates */ uint32_t dcc_change:1; uint32_t color_space_change:1; uint32_t horizontal_mirror_change:1; uint32_t per_pixel_alpha_change:1; uint32_t global_alpha_change:1; + uint32_t sdr_white_level:1; uint32_t rotation_change:1; uint32_t swizzle_change:1; uint32_t scaling_change:1; @@ -573,6 +674,9 @@ union surface_update_flags { struct dc_plane_state { struct dc_plane_address address; struct dc_plane_flip_time time; +#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + bool triplebuffer_flips; +#endif struct scaling_taps scaling_quality; struct rect src_rect; struct rect dst_rect; @@ -595,6 +699,12 @@ struct dc_plane_state { enum dc_color_space color_space; +#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + struct dc_3dlut *lut3d_func; + struct dc_transfer_func *in_shaper_func; + struct dc_transfer_func *blend_tf; +#endif + enum surface_pixel_format format; enum dc_rotation_angle rotation; enum plane_stereo_format stereo_format; @@ -660,6 +770,11 @@ struct dc_surface_update { const struct dc_csc_transform *input_csc_color_matrix; const struct fixed31_32 *coeff_reduction_factor; +#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + const struct dc_transfer_func *func_shaper; + const struct dc_3dlut *lut3d_func; + const struct dc_transfer_func *blend_tf; +#endif }; /* @@ -680,6 +795,11 @@ void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); void dc_transfer_func_release(struct dc_transfer_func *dc_tf); struct dc_transfer_func *dc_create_transfer_func(void); +#if defined(CONFIG_DRM_AMD_DC_DCN2_0) +struct dc_3dlut *dc_create_3dlut_func(void); +void dc_3dlut_func_release(struct dc_3dlut *lut); +void dc_3dlut_func_retain(struct dc_3dlut *lut); +#endif /* * This structure holds a surface address. There could be multiple addresses * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such @@ -793,6 +913,10 @@ struct dpcd_caps { bool panel_mode_edp; bool dpcd_display_control_capable; bool ext_receiver_cap_field_present; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + union dpcd_fec_capability fec_cap; + struct dpcd_dsc_capabilities dsc_caps; +#endif }; #include "dc_link.h" @@ -813,6 +937,14 @@ struct dc_container_id { }; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +struct dc_sink_dsc_caps { + // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), + // 'false' if they are sink's DSC caps + bool is_virtual_dpcd_dsc; + struct dsc_dec_dpcd_caps dsc_dec_caps; +}; +#endif /* * The sink structure contains EDID and other display device properties @@ -827,6 +959,10 @@ struct dc_sink { struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; bool converter_disable_audio; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + struct dc_sink_dsc_caps sink_dsc_caps; +#endif + /* private to DC core */ struct dc_link *link; struct dc_context *ctx; @@ -884,4 +1020,10 @@ unsigned int dc_get_target_backlight_pwm(struct dc *dc); bool dc_is_dmcu_initialized(struct dc *dc); +#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) +/******************************************************************************* + * DSC Interfaces + ******************************************************************************/ +#include "dc_dsc.h" +#endif #endif /* DC_INTERFACE_H_ */ |