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path: root/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
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Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c11
1 files changed, 3 insertions, 8 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 0853bc9917c7..f99b1c084590 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -446,25 +446,18 @@ static int map_transmitter_id_to_phy_instance(
switch (transmitter) {
case TRANSMITTER_UNIPHY_A:
return 0;
- break;
case TRANSMITTER_UNIPHY_B:
return 1;
- break;
case TRANSMITTER_UNIPHY_C:
return 2;
- break;
case TRANSMITTER_UNIPHY_D:
return 3;
- break;
case TRANSMITTER_UNIPHY_E:
return 4;
- break;
case TRANSMITTER_UNIPHY_F:
return 5;
- break;
case TRANSMITTER_UNIPHY_G:
return 6;
- break;
default:
ASSERT(0);
return 0;
@@ -865,7 +858,7 @@ static struct clock_source *find_matching_pll(
return pool->clock_sources[DCE112_CLK_SRC_PLL5];
default:
return NULL;
- };
+ }
return 0;
}
@@ -1240,7 +1233,9 @@ static bool dce112_resource_construct(
pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
dc->caps.max_downscale_ratio = 200;
dc->caps.i2c_speed_in_khz = 100;
+ dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
dc->caps.max_cursor_size = 128;
+ dc->caps.min_horizontal_blanking_period = 80;
dc->caps.dual_link_dvi = true;
dc->caps.extended_aux_timeout_support = false;