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path: root/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
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Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c133
1 files changed, 84 insertions, 49 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 9fc8f827f2a1..44825e2c9ebb 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -34,7 +34,7 @@
#include "dcn10/dcn10_mpc.h"
#include "irq/dcn10/irq_service_dcn10.h"
#include "dcn10/dcn10_dpp.h"
-#include "dcn10/dcn10_timing_generator.h"
+#include "dcn10_optc.h"
#include "dcn10/dcn10_hw_sequencer.h"
#include "dce110/dce110_hw_sequencer.h"
#include "dcn10/dcn10_opp.h"
@@ -48,16 +48,17 @@
#include "dce110/dce110_resource.h"
#include "dce112/dce112_resource.h"
#include "dcn10_hubp.h"
+#include "dcn10_hubbub.h"
-#include "vega10/soc15ip.h"
+#include "soc15ip.h"
-#include "raven1/DCN/dcn_1_0_offset.h"
-#include "raven1/DCN/dcn_1_0_sh_mask.h"
+#include "dcn/dcn_1_0_offset.h"
+#include "dcn/dcn_1_0_sh_mask.h"
-#include "raven1/NBIO/nbio_7_0_offset.h"
+#include "nbio/nbio_7_0_offset.h"
-#include "raven1/MMHUB/mmhub_9_1_offset.h"
-#include "raven1/MMHUB/mmhub_9_1_sh_mask.h"
+#include "mmhub/mmhub_9_1_offset.h"
+#include "mmhub/mmhub_9_1_sh_mask.h"
#include "reg_helper.h"
#include "dce/dce_abm.h"
@@ -347,18 +348,18 @@ static const struct dcn_mpc_mask mpc_mask = {
#define tg_regs(id)\
[id] = {TG_COMMON_REG_LIST_DCN1_0(id)}
-static const struct dcn_tg_registers tg_regs[] = {
+static const struct dcn_optc_registers tg_regs[] = {
tg_regs(0),
tg_regs(1),
tg_regs(2),
tg_regs(3),
};
-static const struct dcn_tg_shift tg_shift = {
+static const struct dcn_optc_shift tg_shift = {
TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
};
-static const struct dcn_tg_mask tg_mask = {
+static const struct dcn_optc_mask tg_mask = {
TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
};
@@ -367,25 +368,38 @@ static const struct bios_registers bios_regs = {
NBIO_SR(BIOS_SCRATCH_6)
};
-#define mi_regs(id)\
+#define hubp_regs(id)\
[id] = {\
- MI_REG_LIST_DCN10(id)\
+ HUBP_REG_LIST_DCN10(id)\
}
-static const struct dcn_mi_registers mi_regs[] = {
- mi_regs(0),
- mi_regs(1),
- mi_regs(2),
- mi_regs(3),
+static const struct dcn_mi_registers hubp_regs[] = {
+ hubp_regs(0),
+ hubp_regs(1),
+ hubp_regs(2),
+ hubp_regs(3),
};
-static const struct dcn_mi_shift mi_shift = {
- MI_MASK_SH_LIST_DCN10(__SHIFT)
+static const struct dcn_mi_shift hubp_shift = {
+ HUBP_MASK_SH_LIST_DCN10(__SHIFT)
};
-static const struct dcn_mi_mask mi_mask = {
- MI_MASK_SH_LIST_DCN10(_MASK)
+static const struct dcn_mi_mask hubp_mask = {
+ HUBP_MASK_SH_LIST_DCN10(_MASK)
+};
+
+
+static const struct dcn_hubbub_registers hubbub_reg = {
+ HUBBUB_REG_LIST_DCN10(0)
+};
+
+static const struct dcn_hubbub_shift hubbub_shift = {
+ HUBBUB_MASK_SH_LIST_DCN10(__SHIFT)
+};
+
+static const struct dcn_hubbub_mask hubbub_mask = {
+ HUBBUB_MASK_SH_LIST_DCN10(_MASK)
};
#define clk_src_regs(index, pllid)\
@@ -519,12 +533,28 @@ static struct mpc *dcn10_mpc_create(struct dc_context *ctx)
return &mpc10->base;
}
+static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx)
+{
+ struct hubbub *hubbub = kzalloc(sizeof(struct hubbub),
+ GFP_KERNEL);
+
+ if (!hubbub)
+ return NULL;
+
+ hubbub1_construct(hubbub, ctx,
+ &hubbub_reg,
+ &hubbub_shift,
+ &hubbub_mask);
+
+ return hubbub;
+}
+
static struct timing_generator *dcn10_timing_generator_create(
struct dc_context *ctx,
uint32_t instance)
{
- struct dcn10_timing_generator *tgn10 =
- kzalloc(sizeof(struct dcn10_timing_generator), GFP_KERNEL);
+ struct optc *tgn10 =
+ kzalloc(sizeof(struct optc), GFP_KERNEL);
if (!tgn10)
return NULL;
@@ -647,6 +677,8 @@ static struct dce_hwseq *dcn10_hwseq_create(
hws->regs = &hwseq_reg;
hws->shifts = &hwseq_shift;
hws->masks = &hwseq_mask;
+ hws->wa.DEGVIDCN10_253 = true;
+ hws->wa.false_optc_underflow = true;
}
return hws;
}
@@ -700,6 +732,12 @@ static void destruct(struct dcn10_resource_pool *pool)
kfree(TO_DCN10_MPC(pool->base.mpc));
pool->base.mpc = NULL;
}
+
+ if (pool->base.hubbub != NULL) {
+ kfree(pool->base.hubbub);
+ pool->base.hubbub = NULL;
+ }
+
for (i = 0; i < pool->base.pipe_count; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
@@ -768,7 +806,7 @@ static struct hubp *dcn10_hubp_create(
return NULL;
dcn10_hubp_construct(hubp1, ctx, inst,
- &mi_regs[inst], &mi_shift, &mi_mask);
+ &hubp_regs[inst], &hubp_shift, &hubp_mask);
return &hubp1->base;
}
@@ -1233,8 +1271,8 @@ static bool construct(
dc->caps.max_downscale_ratio = 200;
dc->caps.i2c_speed_in_khz = 100;
dc->caps.max_cursor_size = 256;
-
dc->caps.max_slave_planes = 1;
+ dc->caps.is_apu = true;
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;
@@ -1274,7 +1312,7 @@ static bool construct(
if (pool->base.clock_sources[i] == NULL) {
dm_error("DC: failed to create clock sources!\n");
BREAK_TO_DEBUGGER();
- goto clock_source_create_fail;
+ goto fail;
}
}
@@ -1283,7 +1321,7 @@ static bool construct(
if (pool->base.display_clock == NULL) {
dm_error("DC: failed to create display clock!\n");
BREAK_TO_DEBUGGER();
- goto disp_clk_create_fail;
+ goto fail;
}
}
@@ -1294,7 +1332,7 @@ static bool construct(
if (pool->base.dmcu == NULL) {
dm_error("DC: failed to create dmcu!\n");
BREAK_TO_DEBUGGER();
- goto res_create_fail;
+ goto fail;
}
pool->base.abm = dce_abm_create(ctx,
@@ -1304,7 +1342,7 @@ static bool construct(
if (pool->base.abm == NULL) {
dm_error("DC: failed to create abm!\n");
BREAK_TO_DEBUGGER();
- goto res_create_fail;
+ goto fail;
}
dml_init_instance(&dc->dml, DML_PROJECT_RAVEN1);
@@ -1344,13 +1382,11 @@ static bool construct(
}
{
- #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
struct irq_service_init_data init_data;
init_data.ctx = dc->ctx;
pool->base.irqs = dal_irq_service_dcn10_create(&init_data);
if (!pool->base.irqs)
- goto irqs_create_fail;
- #endif
+ goto fail;
}
/* index to valid pipe resource */
@@ -1368,7 +1404,7 @@ static bool construct(
BREAK_TO_DEBUGGER();
dm_error(
"DC: failed to create memory input!\n");
- goto mi_create_fail;
+ goto fail;
}
pool->base.ipps[j] = dcn10_ipp_create(ctx, i);
@@ -1376,7 +1412,7 @@ static bool construct(
BREAK_TO_DEBUGGER();
dm_error(
"DC: failed to create input pixel processor!\n");
- goto ipp_create_fail;
+ goto fail;
}
pool->base.dpps[j] = dcn10_dpp_create(ctx, i);
@@ -1384,7 +1420,7 @@ static bool construct(
BREAK_TO_DEBUGGER();
dm_error(
"DC: failed to create dpp!\n");
- goto dpp_create_fail;
+ goto fail;
}
pool->base.opps[j] = dcn10_opp_create(ctx, i);
@@ -1392,7 +1428,7 @@ static bool construct(
BREAK_TO_DEBUGGER();
dm_error(
"DC: failed to create output pixel processor!\n");
- goto opp_create_fail;
+ goto fail;
}
pool->base.timing_generators[j] = dcn10_timing_generator_create(
@@ -1400,8 +1436,9 @@ static bool construct(
if (pool->base.timing_generators[j] == NULL) {
BREAK_TO_DEBUGGER();
dm_error("DC: failed to create tg!\n");
- goto otg_create_fail;
+ goto fail;
}
+
/* check next valid pipe */
j++;
}
@@ -1419,13 +1456,20 @@ static bool construct(
if (pool->base.mpc == NULL) {
BREAK_TO_DEBUGGER();
dm_error("DC: failed to create mpc!\n");
- goto mpc_create_fail;
+ goto fail;
+ }
+
+ pool->base.hubbub = dcn10_hubbub_create(ctx);
+ if (pool->base.hubbub == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error("DC: failed to create hubbub!\n");
+ goto fail;
}
if (!resource_construct(num_virtual_links, dc, &pool->base,
(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
&res_create_funcs : &res_create_maximus_funcs)))
- goto res_create_fail;
+ goto fail;
dcn10_hw_sequencer_construct(dc);
dc->caps.max_planes = pool->base.pipe_count;
@@ -1434,16 +1478,7 @@ static bool construct(
return true;
-disp_clk_create_fail:
-mpc_create_fail:
-otg_create_fail:
-opp_create_fail:
-dpp_create_fail:
-ipp_create_fail:
-mi_create_fail:
-irqs_create_fail:
-res_create_fail:
-clock_source_create_fail:
+fail:
destruct(pool);
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