diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h index b99d2527cf03..76b334644f9e 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h @@ -81,7 +81,9 @@ SRI(DP_MSE_RATE_UPDATE, DP, id), \ SRI(DP_PIXEL_FORMAT, DP, id), \ SRI(DP_SEC_CNTL, DP, id), \ + SRI(DP_SEC_CNTL1, DP, id), \ SRI(DP_SEC_CNTL2, DP, id), \ + SRI(DP_SEC_CNTL5, DP, id), \ SRI(DP_SEC_CNTL6, DP, id), \ SRI(DP_STEER_FIFO, DP, id), \ SRI(DP_VID_M, DP, id), \ @@ -126,7 +128,9 @@ struct dcn10_stream_enc_registers { uint32_t DP_MSE_RATE_UPDATE; uint32_t DP_PIXEL_FORMAT; uint32_t DP_SEC_CNTL; + uint32_t DP_SEC_CNTL1; uint32_t DP_SEC_CNTL2; + uint32_t DP_SEC_CNTL5; uint32_t DP_SEC_CNTL6; uint32_t DP_STEER_FIFO; uint32_t DP_VID_M; @@ -169,14 +173,12 @@ struct dcn10_stream_enc_registers { uint32_t DP_SEC_METADATA_TRANSMISSION; uint32_t HDMI_METADATA_PACKET_CONTROL; uint32_t DP_SEC_FRAMING4; -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) uint32_t DP_GSP11_CNTL; uint32_t HDMI_GENERIC_PACKET_CONTROL6; uint32_t HDMI_GENERIC_PACKET_CONTROL7; uint32_t HDMI_GENERIC_PACKET_CONTROL8; uint32_t HDMI_GENERIC_PACKET_CONTROL9; uint32_t HDMI_GENERIC_PACKET_CONTROL10; -#endif uint32_t DIG_CLOCK_PATTERN; }; @@ -413,6 +415,8 @@ struct dcn10_stream_enc_registers { type DP_SEC_GSP3_ENABLE;\ type DP_SEC_GSP4_ENABLE;\ type DP_SEC_GSP5_ENABLE;\ + type DP_SEC_GSP5_LINE_NUM;\ + type DP_SEC_GSP5_LINE_REFERENCE;\ type DP_SEC_GSP6_ENABLE;\ type DP_SEC_GSP7_ENABLE;\ type DP_SEC_GSP7_PPS;\ @@ -505,7 +509,6 @@ struct dcn10_stream_enc_registers { type DP_PIXEL_COMBINE;\ type DP_SST_SDP_SPLITTING -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) #define SE_REG_FIELD_LIST_DCN3_0(type) \ type HDMI_GENERIC8_CONT;\ type HDMI_GENERIC8_SEND;\ @@ -531,22 +534,17 @@ struct dcn10_stream_enc_registers { type DP_SEC_GSP11_PPS;\ type DP_SEC_GSP11_ENABLE;\ type DP_SEC_GSP11_LINE_NUM -#endif struct dcn10_stream_encoder_shift { SE_REG_FIELD_LIST_DCN1_0(uint8_t); SE_REG_FIELD_LIST_DCN2_0(uint8_t); -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) SE_REG_FIELD_LIST_DCN3_0(uint8_t); -#endif }; struct dcn10_stream_encoder_mask { SE_REG_FIELD_LIST_DCN1_0(uint32_t); SE_REG_FIELD_LIST_DCN2_0(uint32_t); -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) SE_REG_FIELD_LIST_DCN3_0(uint32_t); -#endif }; struct dcn10_stream_encoder { |