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path: root/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
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Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c66
1 files changed, 33 insertions, 33 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index d50a9c370637..e04ecf0fc0db 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1882,9 +1882,16 @@ bool dcn20_split_stream_for_odm(
next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe;
next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe;
}
+ if (prev_odm_pipe->top_pipe && prev_odm_pipe->top_pipe->next_odm_pipe) {
+ prev_odm_pipe->top_pipe->next_odm_pipe->bottom_pipe = next_odm_pipe;
+ next_odm_pipe->top_pipe = prev_odm_pipe->top_pipe->next_odm_pipe;
+ }
+ if (prev_odm_pipe->bottom_pipe && prev_odm_pipe->bottom_pipe->next_odm_pipe) {
+ prev_odm_pipe->bottom_pipe->next_odm_pipe->top_pipe = next_odm_pipe;
+ next_odm_pipe->bottom_pipe = prev_odm_pipe->bottom_pipe->next_odm_pipe;
+ }
prev_odm_pipe->next_odm_pipe = next_odm_pipe;
next_odm_pipe->prev_odm_pipe = prev_odm_pipe;
- ASSERT(next_odm_pipe->top_pipe == NULL);
if (prev_odm_pipe->plane_state) {
struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;
@@ -1922,8 +1929,11 @@ bool dcn20_split_stream_for_odm(
sd->ratios.horz_c, sd->h_active - sd->recout.x));
sd->recout.x = 0;
}
- next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
- if (next_odm_pipe->stream->timing.flags.DSC == 1) {
+ if (!next_odm_pipe->top_pipe)
+ next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
+ else
+ next_odm_pipe->stream_res.opp = next_odm_pipe->top_pipe->stream_res.opp;
+ if (next_odm_pipe->stream->timing.flags.DSC == 1 && !next_odm_pipe->top_pipe) {
dcn20_acquire_dsc(dc, res_ctx, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx);
ASSERT(next_odm_pipe->stream_res.dsc);
if (next_odm_pipe->stream_res.dsc == NULL)
@@ -2002,7 +2012,10 @@ void dcn20_populate_dml_writeback_from_context(
}
int dcn20_populate_dml_pipes_from_context(
- struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes)
+ struct dc *dc,
+ struct dc_state *context,
+ display_e2e_pipe_params_st *pipes,
+ bool fast_validate)
{
int pipe_cnt, i;
bool synchronized_vblank = true;
@@ -2033,15 +2046,14 @@ int dcn20_populate_dml_pipes_from_context(
unsigned int v_total;
unsigned int front_porch;
int output_bpc;
-
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
struct audio_check aud_check = {0};
-#endif
+
if (!res_ctx->pipe_ctx[i].stream)
continue;
v_total = timing->v_total;
front_porch = timing->v_front_porch;
+
/* todo:
pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0;
pipes[pipe_cnt].pipe.src.dcc = 0;
@@ -2091,11 +2103,9 @@ int dcn20_populate_dml_pipes_from_context(
case 1:
pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_2to1;
break;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
case 3:
pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_4to1;
break;
-#endif
default:
pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_disabled;
}
@@ -2201,11 +2211,9 @@ int dcn20_populate_dml_pipes_from_context(
/* todo: default max for now, until there is logic reflecting this in dc*/
pipes[pipe_cnt].dout.output_bpc = 12;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
/*fill up the audio sample rate (unit in kHz)*/
get_audio_check(&res_ctx->pipe_ctx[i].stream->audio_info, &aud_check);
pipes[pipe_cnt].dout.max_audio_sample_rate = aud_check.max_audiosample_rate / 1000;
-#endif
/*
* For graphic plane, cursor number is 1, nv12 is 0
* bw calculations due to cursor on/off
@@ -2252,13 +2260,10 @@ int dcn20_populate_dml_pipes_from_context(
if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) {
pipes[pipe_cnt].pipe.src.viewport_width /= 2;
pipes[pipe_cnt].pipe.dest.recout_width /= 2;
- }
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
- else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1) {
+ } else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1) {
pipes[pipe_cnt].pipe.src.viewport_width /= 4;
pipes[pipe_cnt].pipe.dest.recout_width /= 4;
}
-#endif
} else {
struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
@@ -2287,12 +2292,8 @@ int dcn20_populate_dml_pipes_from_context(
pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height;
pipes[pipe_cnt].pipe.src.surface_width_c = pln->plane_size.chroma_size.width;
pipes[pipe_cnt].pipe.src.surface_height_c = pln->plane_size.chroma_size.height;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
if (pln->format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA
|| pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
-#else
- if (pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
-#endif
pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;
pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
@@ -2308,10 +2309,8 @@ int dcn20_populate_dml_pipes_from_context(
pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width;
if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1)
pipes[pipe_cnt].pipe.dest.full_recout_width *= 2;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1)
pipes[pipe_cnt].pipe.dest.full_recout_width *= 4;
-#endif
else {
struct pipe_ctx *split_pipe = res_ctx->pipe_ctx[i].bottom_pipe;
@@ -2368,11 +2367,9 @@ int dcn20_populate_dml_pipes_from_context(
case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
pipes[pipe_cnt].pipe.src.source_format = dm_444_8;
break;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
pipes[pipe_cnt].pipe.src.source_format = dm_rgbe_alpha;
break;
-#endif
default:
pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
break;
@@ -2582,7 +2579,7 @@ struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
return secondary_pipe;
}
-static void dcn20_merge_pipes_for_validate(
+void dcn20_merge_pipes_for_validate(
struct dc *dc,
struct dc_state *context)
{
@@ -2749,7 +2746,6 @@ int dcn20_validate_apply_pipe_split_flags(
split[i] = 2;
v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1;
}
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
if (dc->debug.force_odm_combine_4to1 & (1 << pipe->stream_res.tg->inst)) {
split[i] = 4;
v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_4to1;
@@ -2759,7 +2755,6 @@ int dcn20_validate_apply_pipe_split_flags(
pipe->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
split[i] = 4;
}
-#endif
v->ODMCombineEnabled[pipe_plane] =
v->ODMCombineEnablePerState[vlevel][pipe_plane];
@@ -2836,7 +2831,8 @@ bool dcn20_fast_validate_bw(
display_e2e_pipe_params_st *pipes,
int *pipe_cnt_out,
int *pipe_split_from,
- int *vlevel_out)
+ int *vlevel_out,
+ bool fast_validate)
{
bool out = false;
int split[MAX_PIPES] = { 0 };
@@ -2848,7 +2844,7 @@ bool dcn20_fast_validate_bw(
dcn20_merge_pipes_for_validate(dc, context);
- pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes);
+ pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
*pipe_cnt_out = pipe_cnt;
@@ -2952,7 +2948,8 @@ static void dcn20_calculate_wm(
display_e2e_pipe_params_st *pipes,
int *out_pipe_cnt,
int *pipe_split_from,
- int vlevel)
+ int vlevel,
+ bool fast_validate)
{
int pipe_cnt, i, pipe_idx;
@@ -2997,10 +2994,10 @@ static void dcn20_calculate_wm(
if (pipe_cnt != pipe_idx) {
if (dc->res_pool->funcs->populate_dml_pipes)
pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
- context, pipes);
+ context, pipes, fast_validate);
else
pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
- context, pipes);
+ context, pipes, fast_validate);
}
*out_pipe_cnt = pipe_cnt;
@@ -3145,7 +3142,7 @@ static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *co
BW_VAL_TRACE_COUNT();
- out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
+ out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate);
if (pipe_cnt == 0)
goto validate_out;
@@ -3160,7 +3157,7 @@ static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *co
goto validate_out;
}
- dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
+ dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
BW_VAL_TRACE_END_WATERMARKS();
@@ -3801,7 +3798,9 @@ static bool dcn20_resource_construct(
dc->caps.max_downscale_ratio = 200;
dc->caps.i2c_speed_in_khz = 100;
+ dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
dc->caps.max_cursor_size = 256;
+ dc->caps.min_horizontal_blanking_period = 80;
dc->caps.dmdata_alloc_size = 2048;
dc->caps.max_slave_planes = 1;
@@ -3821,6 +3820,7 @@ static bool dcn20_resource_construct(
dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
dc->caps.color.dpp.post_csc = 0;
dc->caps.color.dpp.gamma_corr = 0;
+ dc->caps.color.dpp.dgam_rom_for_yuv = 1;
dc->caps.color.dpp.hw_3d_lut = 1;
dc->caps.color.dpp.ogam_ram = 1;
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