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path: root/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
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Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h7
1 files changed, 1 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
index 949b61351ede..ffd37696b6b9 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
@@ -107,11 +107,9 @@ enum dentist_divider_range {
CLK_SRI(CLK3_CLK_PLL_REQ, CLK3, 0), \
CLK_SRI(CLK3_CLK2_DFS_CNTL, CLK3, 0)
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
// TODO:
#define CLK_REG_LIST_DCN3() \
SR(DENTIST_DISPCLK_CNTL)
-#endif
#define CLK_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
@@ -185,10 +183,9 @@ struct clk_mgr_registers {
uint32_t CLK3_CLK2_DFS_CNTL;
uint32_t CLK3_CLK_PLL_REQ;
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
uint32_t CLK0_CLK2_DFS_CNTL;
uint32_t CLK0_CLK_PLL_REQ;
-#endif
+
uint32_t MP1_SMN_C2PMSG_67;
uint32_t MP1_SMN_C2PMSG_83;
uint32_t MP1_SMN_C2PMSG_91;
@@ -285,12 +282,10 @@ struct clk_mgr_internal {
bool periodic_retraining_disabled;
unsigned int cur_phyclk_req_table[MAX_PIPES * 2];
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
bool smu_present;
void *wm_range_table;
long long wm_range_table_addr;
-#endif
};
struct clk_mgr_internal_funcs {