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path: root/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
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Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h50
1 files changed, 49 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
index 4c8e2c6fb6db..8759ec03aede 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
@@ -35,6 +35,9 @@
******************************************************************************/
#define MAX_PIPES 6
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+#define MAX_DWB_PIPES 1
+#endif
struct gamma_curve {
uint32_t offset;
@@ -77,6 +80,37 @@ struct pwl_result_data {
uint32_t delta_blue_reg;
};
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+struct dc_rgb {
+ uint32_t red;
+ uint32_t green;
+ uint32_t blue;
+};
+
+struct tetrahedral_17x17x17 {
+ struct dc_rgb lut0[1229];
+ struct dc_rgb lut1[1228];
+ struct dc_rgb lut2[1228];
+ struct dc_rgb lut3[1228];
+};
+struct tetrahedral_9x9x9 {
+ struct dc_rgb lut0[183];
+ struct dc_rgb lut1[182];
+ struct dc_rgb lut2[182];
+ struct dc_rgb lut3[182];
+};
+
+struct tetrahedral_params {
+ union {
+ struct tetrahedral_17x17x17 tetrahedral_17;
+ struct tetrahedral_9x9x9 tetrahedral_9;
+ };
+ bool use_tetrahedral_9;
+ bool use_12bits;
+
+};
+#endif
+
/* arr_curve_points - regamma regions/segments specification
* arr_points - beginning and end point specified separately (only one on DCE)
* corner_points - beginning and end point for all 3 colors (DCN)
@@ -160,6 +194,14 @@ enum opp_regamma {
OPP_REGAMMA_USER
};
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+enum optc_dsc_mode {
+ OPTC_DSC_DISABLED = 0,
+ OPTC_DSC_ENABLED_444 = 1, /* 'RGB 444' or 'Simple YCbCr 4:2:2' (4:2:2 upsampled to 4:4:4) */
+ OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED = 2 /* Native 4:2:2 or 4:2:0 */
+};
+#endif
+
struct dc_bias_and_scale {
uint16_t scale_red;
uint16_t bias_red;
@@ -181,7 +223,12 @@ enum test_pattern_mode {
TEST_PATTERN_MODE_VERTICALBARS,
TEST_PATTERN_MODE_HORIZONTALBARS,
TEST_PATTERN_MODE_SINGLERAMP_RGB,
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ TEST_PATTERN_MODE_DUALRAMP_RGB,
+ TEST_PATTERN_MODE_XR_BIAS_RGB
+#else
TEST_PATTERN_MODE_DUALRAMP_RGB
+#endif
};
enum test_pattern_color_format {
@@ -203,7 +250,8 @@ enum controller_dp_test_pattern {
CONTROLLER_DP_TEST_PATTERN_RESERVED_8,
CONTROLLER_DP_TEST_PATTERN_RESERVED_9,
CONTROLLER_DP_TEST_PATTERN_RESERVED_A,
- CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA
+ CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA,
+ CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR
};
enum dc_lut_mode {