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path: root/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
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Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h58
1 files changed, 58 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 33905468e2b9..4d56d48a3179 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -65,11 +65,19 @@ struct dce_hwseq {
struct pipe_ctx;
struct dc_state;
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+struct dc_stream_status;
+struct dc_writeback_info;
+#endif
struct dchub_init_data;
struct dc_static_screen_events;
struct resource_pool;
struct resource_context;
struct stream_resource;
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+struct dc_phy_addr_space_config;
+struct dc_virtual_addr_space_config;
+#endif
struct hw_sequencer_funcs {
@@ -102,6 +110,16 @@ struct hw_sequencer_funcs {
uint16_t *matrix,
int opp_id);
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ void (*program_triplebuffer)(
+ const struct dc *dc,
+ struct pipe_ctx *pipe_ctx,
+ bool enableTripleBuffer);
+ void (*set_flip_control_gsl)(
+ struct pipe_ctx *pipe_ctx,
+ bool flip_immediate);
+#endif
+
void (*update_plane_addr)(
const struct dc *dc,
struct pipe_ctx *pipe_ctx);
@@ -114,6 +132,17 @@ struct hw_sequencer_funcs {
struct dce_hwseq *hws,
struct dchub_init_data *dh_data);
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ int (*init_sys_ctx)(
+ struct dce_hwseq *hws,
+ struct dc *dc,
+ struct dc_phy_addr_space_config *pa_config);
+ void (*init_vm_ctx)(
+ struct dce_hwseq *hws,
+ struct dc *dc,
+ struct dc_virtual_addr_space_config *va_config,
+ int vmid);
+#endif
void (*update_mpcc)(
struct dc *dc,
struct pipe_ctx *pipe_ctx);
@@ -158,6 +187,11 @@ struct hw_sequencer_funcs {
void (*update_info_frame)(struct pipe_ctx *pipe_ctx);
+ void (*send_immediate_sdp_message)(
+ struct pipe_ctx *pipe_ctx,
+ const uint8_t *custom_sdp_message,
+ unsigned int sdp_message_size);
+
void (*enable_stream)(struct pipe_ctx *pipe_ctx);
void (*disable_stream)(struct pipe_ctx *pipe_ctx,
@@ -176,6 +210,7 @@ struct hw_sequencer_funcs {
struct dc *dc,
struct pipe_ctx *pipe,
bool lock);
+
void (*pipe_control_lock_global)(
struct dc *dc,
struct pipe_ctx *pipe,
@@ -192,6 +227,13 @@ struct hw_sequencer_funcs {
struct dc *dc,
struct dc_state *context);
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ bool (*update_bandwidth)(
+ struct dc *dc,
+ struct dc_state *context);
+ bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx);
+#endif
+
void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
int vmin, int vmax);
@@ -235,7 +277,23 @@ struct hw_sequencer_funcs {
void (*setup_periodic_interrupt)(struct pipe_ctx *pipe_ctx, enum vline_select vline);
void (*setup_vupdate_interrupt)(struct pipe_ctx *pipe_ctx);
+ bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ void (*update_odm)(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
+ void (*program_all_writeback_pipes_in_tree)(
+ struct dc *dc,
+ const struct dc_stream_state *stream,
+ struct dc_state *context);
+ void (*update_writeback)(struct dc *dc,
+ const struct dc_stream_status *stream_status,
+ struct dc_writeback_info *wb_info);
+ void (*enable_writeback)(struct dc *dc,
+ const struct dc_stream_status *stream_status,
+ struct dc_writeback_info *wb_info);
+ void (*disable_writeback)(struct dc *dc,
+ unsigned int dwb_pipe_inst);
+#endif
};
void color_space_to_black_color(