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-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/core_status.h3
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/core_types.h11
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h41
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h7
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h9
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h2
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h4
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h6
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h5
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h86
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h3
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h4
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h19
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw/opp.h5
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h2
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h8
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h15
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/link_hwss.h1
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/resource.h2
19 files changed, 154 insertions, 79 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_status.h b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
index f932801235c6..d34b0b0eea65 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_status.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
@@ -50,6 +50,9 @@ enum dc_status {
DC_FAIL_CLK_BELOW_MIN = 22, /*THIS IS MIN PER IP*/
DC_FAIL_CLK_BELOW_CFG_REQUIRED = 23, /*THIS IS hard_min in PPLIB*/
+ DC_NOT_SUPPORTED = 24,
+ DC_UNSUPPORTED_VALUE = 25,
+
DC_ERROR_UNEXPECTED = -1
};
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 6e6bc66e49f0..2d77eac66cb0 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -109,7 +109,8 @@ struct resource_funcs {
int (*populate_dml_pipes)(
struct dc *dc,
struct dc_state *context,
- display_e2e_pipe_params_st *pipes);
+ display_e2e_pipe_params_st *pipes,
+ bool fast_validate);
enum dc_status (*validate_global)(
struct dc *dc,
@@ -151,7 +152,7 @@ struct resource_funcs {
void (*update_bw_bounding_box)(
struct dc *dc,
struct clk_bw_params *bw_params);
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
bool (*acquire_post_bldn_3dlut)(
struct resource_context *res_ctx,
const struct resource_pool *pool,
@@ -209,7 +210,7 @@ struct resource_pool {
unsigned int underlay_pipe_index;
unsigned int stream_enc_count;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
struct dc_3dlut *mpc_lut[MAX_PIPES];
struct dc_transfer_func *mpc_shaper[MAX_PIPES];
#endif
@@ -241,7 +242,7 @@ struct resource_pool {
struct dmcu *dmcu;
struct dmub_psr *psr;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
struct abm *multiple_abms[MAX_PIPES];
#endif
@@ -341,7 +342,7 @@ struct resource_context {
uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES];
uint8_t dp_clock_source_ref_count;
bool is_dsc_acquired[MAX_PIPES];
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
bool is_mpc_3dlut_acquired[MAX_PIPES];
#endif
};
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
index 947d6106f341..3a29f379d0c8 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
@@ -43,7 +43,6 @@
#define DCN_MINIMUM_DISPCLK_Khz 100000
#define DCN_MINIMUM_DPPCLK_Khz 100000
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
struct dcn3_clk_internal {
int dummy;
/*TODO:
@@ -61,7 +60,21 @@ struct dcn3_clk_internal {
*/
};
-#endif
+struct dcn301_clk_internal {
+ int dummy;
+ uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk
+ uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
+ uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk
+ uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
+ uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider
+ uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow
+
+ uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
+ uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
+ uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
+ uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
+};
+
/* Will these bw structures be ASIC specific? */
#define MAX_NUM_DPM_LVL 8
@@ -74,12 +87,10 @@ struct clk_limit_table_entry {
unsigned int fclk_mhz;
unsigned int memclk_mhz;
unsigned int socclk_mhz;
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
unsigned int dtbclk_mhz;
unsigned int dispclk_mhz;
unsigned int dppclk_mhz;
unsigned int phyclk_mhz;
-#endif
};
/* This table is contiguous */
@@ -97,8 +108,6 @@ struct wm_range_table_entry {
bool valid;
};
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
-
struct nv_wm_range_entry {
bool valid;
@@ -116,7 +125,6 @@ struct nv_wm_range_entry {
double sr_enter_plus_exit_time_us;
} dml_input;
};
-#endif
struct clk_log_info {
bool enabled;
@@ -188,14 +196,10 @@ struct clk_bypass {
* D occupied, C will be emptry.
*/
struct wm_table {
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
union {
struct nv_wm_range_entry nv_entries[WM_SET_COUNT];
-#endif
- struct wm_range_table_entry entries[WM_SET_COUNT];
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
+ struct wm_range_table_entry entries[WM_SET_COUNT];
};
-#endif
};
struct dummy_pstate_entry {
@@ -246,7 +250,6 @@ struct clk_mgr_funcs {
/* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */
void (*notify_link_rate_change)(struct clk_mgr *clk_mgr, struct dc_link *link);
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
/*
* Send message to PMFW to set hard min memclk frequency
* When current_mode = false, set DPM0
@@ -259,7 +262,14 @@ struct clk_mgr_funcs {
/* Get current memclk states from PMFW, update relevant structures */
void (*get_memclk_states_from_smu)(struct clk_mgr *clk_mgr);
-#endif
+};
+
+struct dpm_clocks;
+struct wartermarks;
+
+struct smu_watermark_set {
+ struct watermarks *wm_set;
+ union large_integer mc_address;
};
struct clk_mgr {
@@ -267,14 +277,13 @@ struct clk_mgr {
struct clk_mgr_funcs *funcs;
struct dc_clocks clks;
bool psr_allow_active_cache;
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
bool force_smu_not_present;
-#endif
int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes
int dentist_vco_freq_khz;
struct clk_state_registers_and_bypass boot_snapshot;
struct clk_bw_params *bw_params;
struct pp_smu_wm_range_sets ranges;
+ struct smu_watermark_set smu_wm_set;
};
/* forward declarations */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
index 949b61351ede..ffd37696b6b9 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
@@ -107,11 +107,9 @@ enum dentist_divider_range {
CLK_SRI(CLK3_CLK_PLL_REQ, CLK3, 0), \
CLK_SRI(CLK3_CLK2_DFS_CNTL, CLK3, 0)
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
// TODO:
#define CLK_REG_LIST_DCN3() \
SR(DENTIST_DISPCLK_CNTL)
-#endif
#define CLK_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
@@ -185,10 +183,9 @@ struct clk_mgr_registers {
uint32_t CLK3_CLK2_DFS_CNTL;
uint32_t CLK3_CLK_PLL_REQ;
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
uint32_t CLK0_CLK2_DFS_CNTL;
uint32_t CLK0_CLK_PLL_REQ;
-#endif
+
uint32_t MP1_SMN_C2PMSG_67;
uint32_t MP1_SMN_C2PMSG_83;
uint32_t MP1_SMN_C2PMSG_91;
@@ -285,12 +282,10 @@ struct clk_mgr_internal {
bool periodic_retraining_disabled;
unsigned int cur_phyclk_req_table[MAX_PIPES * 2];
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
bool smu_present;
void *wm_range_table;
long long wm_range_table_addr;
-#endif
};
struct clk_mgr_internal_funcs {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
index 65f182c8bf14..d9fd28b34f2a 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
@@ -31,9 +31,7 @@ enum dcc_control {
dcc_control__256_256_xxx,
dcc_control__128_128_xxx,
dcc_control__256_64_64,
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
dcc_control__256_128_128,
-#endif
};
enum segment_order {
@@ -65,9 +63,7 @@ enum dcn_hubbub_page_table_depth {
enum dcn_hubbub_page_table_block_size {
DCN_PAGE_TABLE_BLOCK_SIZE_4KB = 0,
DCN_PAGE_TABLE_BLOCK_SIZE_64KB = 4,
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
DCN_PAGE_TABLE_BLOCK_SIZE_32KB = 3
-#endif
};
struct dcn_hubbub_phys_addr_config {
@@ -152,11 +148,16 @@ struct hubbub_funcs {
void (*apply_DEDCN21_147_wa)(struct hubbub *hubbub);
void (*force_wm_propagate_to_pipes)(struct hubbub *hubbub);
+
+ void (*force_pstate_change_control)(struct hubbub *hubbub, bool force, bool allow);
+
+ void (*init_watermarks)(struct hubbub *hubbub);
};
struct hubbub {
const struct hubbub_funcs *funcs;
struct dc_context *ctx;
+ bool riommu_active;
};
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
index 5315f1f86b21..69d9fbfb4bec 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
@@ -66,7 +66,7 @@ struct dmcu_funcs {
bool (*setup_psr)(struct dmcu *dmcu,
struct dc_link *link,
struct psr_context *psr_context);
- void (*get_psr_state)(struct dmcu *dmcu, uint32_t *psr_state);
+ void (*get_psr_state)(struct dmcu *dmcu, enum dc_psr_state *dc_psr_state);
void (*set_psr_wait_loop)(struct dmcu *dmcu,
unsigned int wait_loop_number);
void (*get_psr_wait_loop)(struct dmcu *dmcu,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
index 0491720c5fe9..ddbe4bb52724 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
@@ -47,7 +47,7 @@ struct dpp_input_csc_matrix {
uint16_t regval[12];
};
-static const struct dpp_input_csc_matrix dpp_input_csc_matrix[] = {
+static const struct dpp_input_csc_matrix __maybe_unused dpp_input_csc_matrix[] = {
{COLOR_SPACE_SRGB,
{0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
{COLOR_SPACE_SRGB_LIMITED,
@@ -121,13 +121,11 @@ struct CM_bias_params {
};
struct dpp_funcs {
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
bool (*dpp_program_gamcor_lut)(
struct dpp *dpp_base, const struct pwl_params *params);
void (*dpp_set_pre_degam)(struct dpp *dpp_base,
enum dc_transfer_func_predefined tr);
-#endif
void (*dpp_program_cm_dealpha)(struct dpp *dpp_base,
uint32_t enable, uint32_t additive_blending);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
index 3407e5da5534..ec28cb9c3a8e 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
@@ -72,14 +72,14 @@ enum wbscl_coef_filter_type_sel {
};
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
enum dwb_boundary_mode {
DWBSCL_BOUNDARY_MODE_EDGE = 0,
DWBSCL_BOUNDARY_MODE_BLACK = 1
};
#endif
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
enum dwb_output_csc_mode {
DWB_OUTPUT_CSC_DISABLE = 0,
DWB_OUTPUT_CSC_COEF_A = 1,
@@ -209,7 +209,7 @@ struct dwbc_funcs {
struct dwb_warmup_params *warmup_params);
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
void (*dwb_program_output_csc)(
struct dwbc *dwbc,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
index 286cceeb9c24..315e3061c592 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
@@ -48,10 +48,8 @@ enum cursor_lines_per_chunk {
enum hubp_ind_block_size {
hubp_ind_block_unconstrained = 0,
hubp_ind_block_64b,
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
hubp_ind_block_128b,
hubp_ind_block_64b_no_128bcl,
-#endif
};
struct hubp {
@@ -187,6 +185,9 @@ struct hubp_funcs {
struct _vcs_dpi_display_rq_regs_st *dml_rq_regs,
struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr,
struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr);
+ void (*set_unbounded_requesting)(
+ struct hubp *hubp,
+ bool enable);
};
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
index f62ccf242f56..43e33f47734d 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
@@ -150,14 +150,12 @@ enum ipp_degamma_mode {
IPP_DEGAMMA_MODE_USER_PWL
};
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
enum gamcor_mode {
GAMCOR_MODE_BYPASS,
GAMCOR_MODE_RESERVED_1,
GAMCOR_MODE_USER_PWL,
GAMCOR_MODE_RESERVED_3
};
-#endif
enum ipp_output_format {
IPP_OUTPUT_FORMAT_12_BIT_FIX,
@@ -266,4 +264,88 @@ enum dc_lut_mode {
LUT_RAM_A,
LUT_RAM_B
};
+
+/**
+ * speakersToChannels
+ *
+ * @brief
+ * translate speakers to channels
+ *
+ * FL - Front Left
+ * FR - Front Right
+ * RL - Rear Left
+ * RR - Rear Right
+ * RC - Rear Center
+ * FC - Front Center
+ * FLC - Front Left Center
+ * FRC - Front Right Center
+ * RLC - Rear Left Center
+ * RRC - Rear Right Center
+ * LFE - Low Freq Effect
+ *
+ * FC
+ * FLC FRC
+ * FL FR
+ *
+ * LFE
+ * ()
+ *
+ *
+ * RL RR
+ * RLC RRC
+ * RC
+ *
+ * ch 8 7 6 5 4 3 2 1
+ * 0b00000011 - - - - - - FR FL
+ * 0b00000111 - - - - - LFE FR FL
+ * 0b00001011 - - - - FC - FR FL
+ * 0b00001111 - - - - FC LFE FR FL
+ * 0b00010011 - - - RC - - FR FL
+ * 0b00010111 - - - RC - LFE FR FL
+ * 0b00011011 - - - RC FC - FR FL
+ * 0b00011111 - - - RC FC LFE FR FL
+ * 0b00110011 - - RR RL - - FR FL
+ * 0b00110111 - - RR RL - LFE FR FL
+ * 0b00111011 - - RR RL FC - FR FL
+ * 0b00111111 - - RR RL FC LFE FR FL
+ * 0b01110011 - RC RR RL - - FR FL
+ * 0b01110111 - RC RR RL - LFE FR FL
+ * 0b01111011 - RC RR RL FC - FR FL
+ * 0b01111111 - RC RR RL FC LFE FR FL
+ * 0b11110011 RRC RLC RR RL - - FR FL
+ * 0b11110111 RRC RLC RR RL - LFE FR FL
+ * 0b11111011 RRC RLC RR RL FC - FR FL
+ * 0b11111111 RRC RLC RR RL FC LFE FR FL
+ * 0b11000011 FRC FLC - - - - FR FL
+ * 0b11000111 FRC FLC - - - LFE FR FL
+ * 0b11001011 FRC FLC - - FC - FR FL
+ * 0b11001111 FRC FLC - - FC LFE FR FL
+ * 0b11010011 FRC FLC - RC - - FR FL
+ * 0b11010111 FRC FLC - RC - LFE FR FL
+ * 0b11011011 FRC FLC - RC FC - FR FL
+ * 0b11011111 FRC FLC - RC FC LFE FR FL
+ * 0b11110011 FRC FLC RR RL - - FR FL
+ * 0b11110111 FRC FLC RR RL - LFE FR FL
+ * 0b11111011 FRC FLC RR RL FC - FR FL
+ * 0b11111111 FRC FLC RR RL FC LFE FR FL
+ *
+ * @param
+ * speakers - speaker information as it comes from CEA audio block
+ */
+/* translate speakers to channels */
+
+union audio_cea_channels {
+ uint8_t all;
+ struct audio_cea_channels_bits {
+ uint32_t FL:1;
+ uint32_t FR:1;
+ uint32_t LFE:1;
+ uint32_t FC:1;
+ uint32_t RL_RC:1;
+ uint32_t RR:1;
+ uint32_t RC_RLC_FLC:1;
+ uint32_t RRC_FRC:1;
+ } channels;
+};
+
#endif /* __DAL_HW_SHARED_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
index c2b392a533b1..7f5acd8fb918 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
@@ -90,7 +90,8 @@ union psr_error_status {
struct {
unsigned char LINK_CRC_ERROR :1;
unsigned char RFB_STORAGE_ERROR :1;
- unsigned char RESERVED :6;
+ unsigned char VSC_SDP_ERROR :1;
+ unsigned char RESERVED :5;
} bits;
unsigned char raw;
};
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h
index aeab7fd782b8..15cb782f129b 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h
@@ -43,9 +43,7 @@ struct mcif_arb_params {
unsigned int arbitration_slice;
unsigned int slice_lines;
unsigned int max_scaled_time;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
unsigned int dram_speed_change_duration;
-#endif
};
struct mcif_irq_params {
@@ -75,11 +73,9 @@ struct mcif_wb {
struct mcif_wb_funcs {
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
void (*warmup_mcif)(
struct mcif_wb *mcif_wb,
struct mcif_warmup_params *params);
-#endif
void (*enable_mcif)(struct mcif_wb *mcif_wb);
void (*disable_mcif)(struct mcif_wb *mcif_wb);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
index b2892eab5e02..879f502ae530 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
@@ -32,11 +32,7 @@
#define MAX_MPCC 6
#define MAX_OPP 6
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
#define MAX_DWB 2
-#else
-#define MAX_DWB 1
-#endif
enum mpc_output_csc_mode {
MPC_OUTPUT_CSC_DISABLE = 0,
@@ -77,12 +73,11 @@ struct mpcc_blnd_cfg {
int bottom_outside_gain;
};
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
struct mpc_grph_gamut_adjustment {
struct fixed31_32 temperature_matrix[CSC_TEMPERATURE_MATRIX_SIZE];
enum graphics_gamut_adjust_type gamut_adjust_type;
};
-#endif
+
struct mpcc_sm_cfg {
bool enable;
/* 0-single plane,2-row subsampling,4-column subsampling,6-checkboard subsampling */
@@ -106,13 +101,12 @@ struct mpc_denorm_clamp {
int clamp_min_b_cb;
};
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
struct mpc_dwb_flow_control {
int flow_ctrl_mode;
int flow_ctrl_cnt0;
int flow_ctrl_cnt1;
};
-#endif
+
/*
* MPCC connection and blending configuration for a single MPCC instance.
* This struct is used as a node in an MPC tree.
@@ -123,9 +117,7 @@ struct mpcc {
struct mpcc *mpcc_bot; /* pointer to bottom layer MPCC. NULL when not connected */
struct mpcc_blnd_cfg blnd_cfg; /* The blending configuration for this MPCC */
struct mpcc_sm_cfg sm_cfg; /* stereo mix setting for this MPCC */
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
bool shared_bottom; /* TRUE if MPCC output to both OPP and DWB endpoints, else FALSE */
-#endif
};
/*
@@ -247,7 +239,6 @@ struct mpc_funcs {
int opp_id,
bool lock);
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
/*
* Add DPP into 'secondary' MPC tree based on specified blending position.
* Only used for planes that are part of blending chain for DWB output
@@ -290,7 +281,6 @@ struct mpc_funcs {
struct mpcc* (*get_mpcc_for_dpp_from_secondary)(
struct mpc_tree *tree,
int dpp_id);
-#endif
struct mpcc* (*get_mpcc_for_dpp)(
struct mpc_tree *tree,
int dpp_id);
@@ -330,7 +320,6 @@ struct mpc_funcs {
struct mpc *mpc,
int mpcc_id,
bool power_on);
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
void (*set_dwb_mux)(
struct mpc *mpc,
int dwb_id,
@@ -350,9 +339,7 @@ struct mpc_funcs {
bool enable,
bool rate_2x_mode,
struct mpc_dwb_flow_control *flow_control);
-#endif
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
void (*set_gamut_remap)(
struct mpc *mpc,
int mpcc_id,
@@ -372,8 +359,6 @@ struct mpc_funcs {
int (*release_rmu)(struct mpc *mpc, int mpcc_id);
-#endif
-
};
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
index 2717352eb697..7617fabbd16e 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
@@ -313,6 +313,11 @@ struct opp_funcs {
int height,
int offset);
+ void (*opp_program_dpg_dimensions)(
+ struct output_pixel_processor *opp,
+ int width,
+ int height);
+
bool (*dpg_is_blanked)(
struct output_pixel_processor *opp);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
index 0184cefb083b..47c7e4c3a51b 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
@@ -104,10 +104,8 @@ struct stream_encoder {
struct dc_bios *bp;
enum engine_id id;
uint32_t stream_enc_inst;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
struct vpg *vpg;
struct afmt *afmt;
-#endif
};
struct enc_state {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index 084432132b16..f7632fe25976 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -98,19 +98,15 @@ enum crc_selection {
INTERSECT_WINDOW_NOT_A_NOT_B,
};
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
enum otg_out_mux_dest {
OUT_MUX_DIO = 0,
};
-#endif
enum h_timing_div_mode {
H_TIMING_NO_DIV,
H_TIMING_DIV_BY2,
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
H_TIMING_RESERVED,
H_TIMING_DIV_BY4,
-#endif
};
struct crc_params {
@@ -275,7 +271,7 @@ struct timing_generator_funcs {
struct dc_crtc_timing *hw_crtc_timing);
void (*set_vtg_params)(struct timing_generator *optc,
- const struct dc_crtc_timing *dc_crtc_timing);
+ const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2);
void (*set_dsc_config)(struct timing_generator *optc,
enum optc_dsc_mode dsc_mode,
@@ -288,7 +284,6 @@ struct timing_generator_funcs {
void (*set_gsl_source_select)(struct timing_generator *optc,
int group_idx,
uint32_t gsl_ready_signal);
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
void (*set_out_mux)(struct timing_generator *tg, enum otg_out_mux_dest dest);
void (*set_vrr_m_const)(struct timing_generator *optc,
double vtotal_avg);
@@ -296,7 +291,6 @@ struct timing_generator_funcs {
uint32_t window_start, uint32_t window_end);
void (*set_vtotal_change_limit)(struct timing_generator *optc,
uint32_t limit);
-#endif
};
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 64c1be818b0e..62804dc7b698 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -50,6 +50,7 @@ struct dpp;
struct dce_hwseq;
struct hw_sequencer_funcs {
+ void (*hardware_release)(struct dc *dc);
/* Embedded Display Related */
void (*edp_power_control)(struct dc_link *link, bool enable);
void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up);
@@ -67,8 +68,6 @@ struct hw_sequencer_funcs {
int num_planes, struct dc_state *context);
void (*program_front_end_for_ctx)(struct dc *dc,
struct dc_state *context);
- bool (*disconnect_pipes)(struct dc *dc,
- struct dc_state *context);
void (*wait_for_pending_cleared)(struct dc *dc,
struct dc_state *context);
void (*post_unlock_program_front_end)(struct dc *dc,
@@ -215,11 +214,19 @@ struct hw_sequencer_funcs {
void (*set_pipe)(struct pipe_ctx *pipe_ctx);
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
/* Idle Optimization Related */
bool (*apply_idle_power_optimizations)(struct dc *dc, bool enable);
-#endif
+ bool (*is_abm_supported)(struct dc *dc,
+ struct dc_state *context, struct dc_stream_state *stream);
+
+ void (*set_disp_pattern_generator)(const struct dc *dc,
+ struct pipe_ctx *pipe_ctx,
+ enum controller_dp_test_pattern test_pattern,
+ enum controller_dp_color_space color_space,
+ enum dc_color_depth color_depth,
+ const struct tg_color *solid_color,
+ int width, int height, int offset);
};
void color_space_to_black_color(
diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
index 9af7ee5bc8ee..33590a728fc5 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
@@ -51,6 +51,7 @@ void dp_enable_link_phy(
const struct dc_link_settings *link_settings);
void dp_receiver_power_ctrl(struct dc_link *link, bool on);
+void edp_add_delay_for_T9(struct dc_link *link);
bool edp_receiver_ready_T9(struct dc_link *link);
bool edp_receiver_ready_T7(struct dc_link *link);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h
index dbd74d548de3..d89815a46190 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
@@ -48,9 +48,7 @@ struct resource_caps {
int num_ddc;
int num_vmid;
int num_dsc;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
int num_mpc_3dlut;
-#endif
};
struct resource_straps {