diff options
Diffstat (limited to 'drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h | 4457 |
1 files changed, 4457 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h new file mode 100644 index 000000000000..ae798f768853 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h @@ -0,0 +1,4457 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef DCE_6_0_D_H +#define DCE_6_0_D_H + +#define ixATTR00 0x0000 +#define ixATTR01 0x0001 +#define ixATTR02 0x0002 +#define ixATTR03 0x0003 +#define ixATTR04 0x0004 +#define ixATTR05 0x0005 +#define ixATTR06 0x0006 +#define ixATTR07 0x0007 +#define ixATTR08 0x0008 +#define ixATTR09 0x0009 +#define ixATTR0A 0x000A +#define ixATTR0B 0x000B +#define ixATTR0C 0x000C +#define ixATTR0D 0x000D +#define ixATTR0E 0x000E +#define ixATTR0F 0x000F +#define ixATTR10 0x0010 +#define ixATTR11 0x0011 +#define ixATTR12 0x0012 +#define ixATTR13 0x0013 +#define ixATTR14 0x0014 +#define ixAUDIO_DESCRIPTOR0 0x0001 +#define ixAUDIO_DESCRIPTOR10 0x000B +#define ixAUDIO_DESCRIPTOR1 0x0002 +#define ixAUDIO_DESCRIPTOR11 0x000C +#define ixAUDIO_DESCRIPTOR12 0x000D +#define ixAUDIO_DESCRIPTOR13 0x000E +#define ixAUDIO_DESCRIPTOR2 0x0003 +#define ixAUDIO_DESCRIPTOR3 0x0004 +#define ixAUDIO_DESCRIPTOR4 0x0005 +#define ixAUDIO_DESCRIPTOR5 0x0006 +#define ixAUDIO_DESCRIPTOR6 0x0007 +#define ixAUDIO_DESCRIPTOR7 0x0008 +#define ixAUDIO_DESCRIPTOR8 0x0009 +#define ixAUDIO_DESCRIPTOR9 0x000A +#define ixAZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002A +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002B +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002C +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002D +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002E +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002F +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003A +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003B +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003C +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003D +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003E +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003F +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005A +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005B +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005C +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005D +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005E +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005F +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270D +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270E +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273E +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2F09 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2F0B +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2F0A +#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17FF +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1F05 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1F0F +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1F0B +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1F04 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1F0A +#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377C +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377B +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377A +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371C +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371D +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371E +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371F +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3F09 +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3F0C +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3F0E +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0F02 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0F04 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0F00 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378A +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378B +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378C +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378D +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378E +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378F +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 +#define ixAZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZALIA_STREAM_DEBUG 0x0005 +#define ixAZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixCRT00 0x0000 +#define ixCRT01 0x0001 +#define ixCRT02 0x0002 +#define ixCRT03 0x0003 +#define ixCRT04 0x0004 +#define ixCRT05 0x0005 +#define ixCRT06 0x0006 +#define ixCRT07 0x0007 +#define ixCRT08 0x0008 +#define ixCRT09 0x0009 +#define ixCRT0A 0x000A +#define ixCRT0B 0x000B +#define ixCRT0C 0x000C +#define ixCRT0D 0x000D +#define ixCRT0E 0x000E +#define ixCRT0F 0x000F +#define ixCRT10 0x0010 +#define ixCRT11 0x0011 +#define ixCRT12 0x0012 +#define ixCRT13 0x0013 +#define ixCRT14 0x0014 +#define ixCRT15 0x0015 +#define ixCRT16 0x0016 +#define ixCRT17 0x0017 +#define ixCRT18 0x0018 +#define ixCRT1E 0x001E +#define ixCRT1F 0x001F +#define ixCRT22 0x0022 +#define ixDCIO_DEBUG10 0x0010 +#define ixDCIO_DEBUG1 0x0001 +#define ixDCIO_DEBUG11 0x0011 +#define ixDCIO_DEBUG12 0x0012 +#define ixDCIO_DEBUG13 0x0013 +#define ixDCIO_DEBUG2 0x0002 +#define ixDCIO_DEBUG3 0x0003 +#define ixDCIO_DEBUG4 0x0004 +#define ixDCIO_DEBUG5 0x0005 +#define ixDCIO_DEBUG6 0x0006 +#define ixDCIO_DEBUG7 0x0007 +#define ixDCIO_DEBUG8 0x0008 +#define ixDCIO_DEBUG9 0x0009 +#define ixDCIO_DEBUGA 0x000A +#define ixDCIO_DEBUGB 0x000B +#define ixDCIO_DEBUGC 0x000C +#define ixDCIO_DEBUGD 0x000D +#define ixDCIO_DEBUGE 0x000E +#define ixDCIO_DEBUGF 0x000F +#define ixDCIO_DEBUG_ID 0x0000 +#define ixDMIF_DEBUG02_CORE0 0x0002 +#define ixDMIF_DEBUG02_CORE1 0x000A +#define ixDP_AUX1_DEBUG_A 0x0010 +#define ixDP_AUX1_DEBUG_B 0x0011 +#define ixDP_AUX1_DEBUG_C 0x0012 +#define ixDP_AUX1_DEBUG_D 0x0013 +#define ixDP_AUX1_DEBUG_E 0x0014 +#define ixDP_AUX1_DEBUG_F 0x0015 +#define ixDP_AUX1_DEBUG_G 0x0016 +#define ixDP_AUX1_DEBUG_H 0x0017 +#define ixDP_AUX1_DEBUG_I 0x0018 +#define ixDP_AUX2_DEBUG_A 0x0020 +#define ixDP_AUX2_DEBUG_B 0x0021 +#define ixDP_AUX2_DEBUG_C 0x0022 +#define ixDP_AUX2_DEBUG_D 0x0023 +#define ixDP_AUX2_DEBUG_E 0x0024 +#define ixDP_AUX2_DEBUG_F 0x0025 +#define ixDP_AUX2_DEBUG_G 0x0026 +#define ixDP_AUX2_DEBUG_H 0x0027 +#define ixDP_AUX2_DEBUG_I 0x0028 +#define ixDP_AUX3_DEBUG_A 0x0030 +#define ixDP_AUX3_DEBUG_B 0x0031 +#define ixDP_AUX3_DEBUG_C 0x0032 +#define ixDP_AUX3_DEBUG_D 0x0033 +#define ixDP_AUX3_DEBUG_E 0x0034 +#define ixDP_AUX3_DEBUG_F 0x0035 +#define ixDP_AUX3_DEBUG_G 0x0036 +#define ixDP_AUX3_DEBUG_H 0x0037 +#define ixDP_AUX3_DEBUG_I 0x0038 +#define ixDP_AUX4_DEBUG_A 0x0040 +#define ixDP_AUX4_DEBUG_B 0x0041 +#define ixDP_AUX4_DEBUG_C 0x0042 +#define ixDP_AUX4_DEBUG_D 0x0043 +#define ixDP_AUX4_DEBUG_E 0x0044 +#define ixDP_AUX4_DEBUG_F 0x0045 +#define ixDP_AUX4_DEBUG_G 0x0046 +#define ixDP_AUX4_DEBUG_H 0x0047 +#define ixDP_AUX4_DEBUG_I 0x0048 +#define ixDP_AUX5_DEBUG_A 0x0070 +#define ixDP_AUX5_DEBUG_B 0x0071 +#define ixDP_AUX5_DEBUG_C 0x0072 +#define ixDP_AUX5_DEBUG_D 0x0073 +#define ixDP_AUX5_DEBUG_E 0x0074 +#define ixDP_AUX5_DEBUG_F 0x0075 +#define ixDP_AUX5_DEBUG_G 0x0076 +#define ixDP_AUX5_DEBUG_H 0x0077 +#define ixDP_AUX5_DEBUG_I 0x0078 +#define ixDP_AUX6_DEBUG_A 0x0080 +#define ixDP_AUX6_DEBUG_B 0x0081 +#define ixDP_AUX6_DEBUG_C 0x0082 +#define ixDP_AUX6_DEBUG_D 0x0083 +#define ixDP_AUX6_DEBUG_E 0x0084 +#define ixDP_AUX6_DEBUG_F 0x0085 +#define ixDP_AUX6_DEBUG_G 0x0086 +#define ixDP_AUX6_DEBUG_H 0x0087 +#define ixDP_AUX6_DEBUG_I 0x0088 +#define ixFMT_DEBUG0 0x0001 +#define ixFMT_DEBUG1 0x0002 +#define ixFMT_DEBUG2 0x0003 +#define ixFMT_DEBUG_ID 0x0000 +#define ixGRA00 0x0000 +#define ixGRA01 0x0001 +#define ixGRA02 0x0002 +#define ixGRA03 0x0003 +#define ixGRA04 0x0004 +#define ixGRA05 0x0005 +#define ixGRA06 0x0006 +#define ixGRA07 0x0007 +#define ixGRA08 0x0008 +#define ixIDDCCIF02_DBG_DCCIF_C 0x0009 +#define ixIDDCCIF04_DBG_DCCIF_E 0x000B +#define ixIDDCCIF05_DBG_DCCIF_F 0x000C +#define ixMVP_DEBUG_12 0x000C +#define ixMVP_DEBUG_13 0x000D +#define ixMVP_DEBUG_14 0x000E +#define ixMVP_DEBUG_15 0x000F +#define ixMVP_DEBUG_16 0x0010 +#define ixMVP_DEBUG_17 0x0011 +#define ixSEQ00 0x0000 +#define ixSEQ01 0x0001 +#define ixSEQ02 0x0002 +#define ixSEQ03 0x0003 +#define ixSEQ04 0x0004 +#define ixSINK_DESCRIPTION0 0x0005 +#define ixSINK_DESCRIPTION10 0x000F +#define ixSINK_DESCRIPTION1 0x0006 +#define ixSINK_DESCRIPTION11 0x0010 +#define ixSINK_DESCRIPTION12 0x0011 +#define ixSINK_DESCRIPTION13 0x0012 +#define ixSINK_DESCRIPTION14 0x0013 +#define ixSINK_DESCRIPTION15 0x0014 +#define ixSINK_DESCRIPTION16 0x0015 +#define ixSINK_DESCRIPTION17 0x0016 +#define ixSINK_DESCRIPTION2 0x0007 +#define ixSINK_DESCRIPTION3 0x0008 +#define ixSINK_DESCRIPTION4 0x0009 +#define ixSINK_DESCRIPTION5 0x000A +#define ixSINK_DESCRIPTION6 0x000B +#define ixSINK_DESCRIPTION7 0x000C +#define ixSINK_DESCRIPTION8 0x000D +#define ixSINK_DESCRIPTION9 0x000E +#define ixVGADCC_DBG_DCCIF_C 0x007E +#define mmABM_TEST_DEBUG_DATA 0x169F +#define mmABM_TEST_DEBUG_INDEX 0x169E +#define mmAFMT_60958_0 0x1C41 +#define mmAFMT_60958_1 0x1C42 +#define mmAFMT_60958_2 0x1C48 +#define mmAFMT_AUDIO_CRC_CONTROL 0x1C43 +#define mmAFMT_AUDIO_CRC_RESULT 0x1C49 +#define mmAFMT_AUDIO_DBG_DTO_CNTL 0x1C52 +#define mmAFMT_AUDIO_INFO0 0x1C3F +#define mmAFMT_AUDIO_INFO1 0x1C40 +#define mmAFMT_AUDIO_PACKET_CONTROL 0x1C4B +#define mmAFMT_AUDIO_PACKET_CONTROL2 0x1C17 +#define mmAFMT_AUDIO_SRC_CONTROL 0x1C4F +#define mmAFMT_AVI_INFO0 0x1C21 +#define mmAFMT_AVI_INFO1 0x1C22 +#define mmAFMT_AVI_INFO2 0x1C23 +#define mmAFMT_AVI_INFO3 0x1C24 +#define mmAFMT_GENERIC_0 0x1C28 +#define mmAFMT_GENERIC_1 0x1C29 +#define mmAFMT_GENERIC_2 0x1C2A +#define mmAFMT_GENERIC_3 0x1C2B +#define mmAFMT_GENERIC_4 0x1C2C +#define mmAFMT_GENERIC_5 0x1C2D +#define mmAFMT_GENERIC_6 0x1C2E +#define mmAFMT_GENERIC_7 0x1C2F +#define mmAFMT_GENERIC_HDR 0x1C27 +#define mmAFMT_INFOFRAME_CONTROL0 0x1C4D +#define mmAFMT_INTERRUPT_STATUS 0x1C14 +#define mmAFMT_ISRC1_0 0x1C18 +#define mmAFMT_ISRC1_1 0x1C19 +#define mmAFMT_ISRC1_2 0x1C1A +#define mmAFMT_ISRC1_3 0x1C1B +#define mmAFMT_ISRC1_4 0x1C1C +#define mmAFMT_ISRC2_0 0x1C1D +#define mmAFMT_ISRC2_1 0x1C1E +#define mmAFMT_ISRC2_2 0x1C1F +#define mmAFMT_ISRC2_3 0x1C20 +#define mmAFMT_MPEG_INFO0 0x1C25 +#define mmAFMT_MPEG_INFO1 0x1C26 +#define mmAFMT_RAMP_CONTROL0 0x1C44 +#define mmAFMT_RAMP_CONTROL1 0x1C45 +#define mmAFMT_RAMP_CONTROL2 0x1C46 +#define mmAFMT_RAMP_CONTROL3 0x1C47 +#define mmAFMT_STATUS 0x1C4A +#define mmAFMT_VBI_PACKET_CONTROL 0x1C4C +#define mmATTRDR 0x00F0 +#define mmATTRDW 0x00F0 +#define mmATTRX 0x00F0 +#define mmAUX_ARB_CONTROL 0x1882 +#define mmAUX_CONTROL 0x1880 +#define mmAUX_DPHY_RX_CONTROL0 0x188A +#define mmAUX_DPHY_RX_CONTROL1 0x188B +#define mmAUX_DPHY_RX_STATUS 0x188D +#define mmAUX_DPHY_TX_CONTROL 0x1889 +#define mmAUX_DPHY_TX_REF_CONTROL 0x1888 +#define mmAUX_DPHY_TX_STATUS 0x188C +#define mmAUX_GTC_SYNC_CONTROL 0x188E +#define mmAUX_GTC_SYNC_DATA 0x1890 +#define mmAUX_INTERRUPT_CONTROL 0x1883 +#define mmAUX_LS_DATA 0x1887 +#define mmAUX_LS_STATUS 0x1885 +#define mmAUXN_IMPCAL 0x190C +#define mmAUXP_IMPCAL 0x190B +#define mmAUX_SW_CONTROL 0x1881 +#define mmAUX_SW_DATA 0x1886 +#define mmAUX_SW_STATUS 0x1884 +#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x17C9 +#define mmAZALIA_AUDIO_DTO 0x17BA +#define mmAZALIA_AUDIO_DTO_CONTROL 0x17BB +#define mmAZALIA_BDL_DMA_CONTROL 0x17BF +#define mmAZALIA_CONTROLLER_DEBUG 0x17CF +#define mmAZALIA_CORB_DMA_CONTROL 0x17C1 +#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x17CA +#define mmAZALIA_DATA_DMA_CONTROL 0x17BE +#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x17D5 +#define mmAZALIA_F0_CODEC_DEBUG 0x17DF +#define mmAZALIA_F0_CODEC_ENDPOINT_DATA 0x1781 +#define mmAZALIA_F0_CODEC_ENDPOINT_INDEX 0x1780 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x17DE +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x17DB +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x17DC +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x17DD +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x17D7 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x17DA +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x17D9 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x17D8 +#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x17D6 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x17D3 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x17D2 +#define mmAZALIA_GLOBAL_CAPABILITIES 0x17CB +#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x17CC +#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x17CD +#define mmAZALIA_RIRB_AND_DP_CONTROL 0x17C0 +#define mmAZALIA_SCLK_CONTROL 0x17BC +#define mmAZALIA_STREAM_DATA 0x17E9 +#define mmAZALIA_STREAM_INDEX 0x17E8 +#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x17BD +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1781 +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1780 +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1787 +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1786 +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x178D +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x178C +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1793 +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1792 +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1799 +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1798 +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x179F +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x179E +#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x17E9 +#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x17E8 +#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x17ED +#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x17EC +#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x17F1 +#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x17F0 +#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x17F5 +#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x17F4 +#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x17F9 +#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x17F8 +#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x17FD +#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x17FC +#define mmAZ_TEST_DEBUG_DATA 0x17D1 +#define mmAZ_TEST_DEBUG_INDEX 0x17D0 +#define mmBL1_PWM_ABM_CNTL 0x162E +#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x1628 +#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x162F +#define mmBL1_PWM_CURRENT_ABM_LEVEL 0x162B +#define mmBL1_PWM_FINAL_DUTY_CYCLE 0x162C +#define mmBL1_PWM_GRP2_REG_LOCK 0x1630 +#define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x162D +#define mmBL1_PWM_TARGET_ABM_LEVEL 0x162A +#define mmBL1_PWM_USER_LEVEL 0x1629 +#define mmBL_PWM_CNTL 0x191E +#define mmBL_PWM_CNTL2 0x191F +#define mmBL_PWM_GRP1_REG_LOCK 0x1921 +#define mmBL_PWM_PERIOD_CNTL 0x1920 +#define mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x19FE +#define mmBPHYC_DAC_MACRO_CNTL 0x19FD +#define mmCC_DC_PIPE_DIS 0x177F +#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x17D4 +#define mmCOMM_MATRIXA_TRANS_C11_C12 0x1A43 +#define mmCOMM_MATRIXA_TRANS_C13_C14 0x1A44 +#define mmCOMM_MATRIXA_TRANS_C21_C22 0x1A45 +#define mmCOMM_MATRIXA_TRANS_C23_C24 0x1A46 +#define mmCOMM_MATRIXA_TRANS_C31_C32 0x1A47 +#define mmCOMM_MATRIXA_TRANS_C33_C34 0x1A48 +#define mmCOMM_MATRIXB_TRANS_C11_C12 0x1A49 +#define mmCOMM_MATRIXB_TRANS_C13_C14 0x1A4A +#define mmCOMM_MATRIXB_TRANS_C21_C22 0x1A4B +#define mmCOMM_MATRIXB_TRANS_C23_C24 0x1A4C +#define mmCOMM_MATRIXB_TRANS_C31_C32 0x1A4D +#define mmCOMM_MATRIXB_TRANS_C33_C34 0x1A4E +#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x1B78 +#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x1BC3 +#define mmCRTC0_CRTC_BLACK_COLOR 0x1BA2 +#define mmCRTC0_CRTC_BLANK_CONTROL 0x1B9D +#define mmCRTC0_CRTC_BLANK_DATA_COLOR 0x1BA1 +#define mmCRTC0_CRTC_CONTROL 0x1B9C +#define mmCRTC0_CRTC_COUNT_CONTROL 0x1BA9 +#define mmCRTC0_CRTC_COUNT_RESET 0x1BAA +#define mmCRTC0_CRTC_DCFE_CLOCK_CONTROL 0x1B7C +#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x1BB6 +#define mmCRTC0_CRTC_DTMTEST_CNTL 0x1B92 +#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x1B93 +#define mmCRTC0_CRTC_FLOW_CONTROL 0x1B99 +#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x1B98 +#define mmCRTC0_CRTC_GSL_CONTROL 0x1B7B +#define mmCRTC0_CRTC_GSL_VSYNC_GAP 0x1B79 +#define mmCRTC0_CRTC_GSL_WINDOW 0x1B7A +#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x1B7D +#define mmCRTC0_CRTC_H_BLANK_START_END 0x1B81 +#define mmCRTC0_CRTC_H_SYNC_A 0x1B82 +#define mmCRTC0_CRTC_H_SYNC_A_CNTL 0x1B83 +#define mmCRTC0_CRTC_H_SYNC_B 0x1B84 +#define mmCRTC0_CRTC_H_SYNC_B_CNTL 0x1B85 +#define mmCRTC0_CRTC_H_TOTAL 0x1B80 +#define mmCRTC0_CRTC_INTERLACE_CONTROL 0x1B9E +#define mmCRTC0_CRTC_INTERLACE_STATUS 0x1B9F +#define mmCRTC0_CRTC_INTERRUPT_CONTROL 0x1BB4 +#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1BAB +#define mmCRTC0_CRTC_MASTER_EN 0x1BC2 +#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x1BBF +#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1BC0 +#define mmCRTC0_CRTC_MVP_STATUS 0x1BC1 +#define mmCRTC0_CRTC_NOM_VERT_POSITION 0x1BA5 +#define mmCRTC0_CRTC_OVERSCAN_COLOR 0x1BA0 +#define mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x1BB0 +#define mmCRTC0_CRTC_SNAPSHOT_FRAME 0x1BB2 +#define mmCRTC0_CRTC_SNAPSHOT_POSITION 0x1BB1 +#define mmCRTC0_CRTC_SNAPSHOT_STATUS 0x1BAF +#define mmCRTC0_CRTC_START_LINE_CONTROL 0x1BB3 +#define mmCRTC0_CRTC_STATUS 0x1BA3 +#define mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x1BA6 +#define mmCRTC0_CRTC_STATUS_HV_COUNT 0x1BA8 +#define mmCRTC0_CRTC_STATUS_POSITION 0x1BA4 +#define mmCRTC0_CRTC_STATUS_VF_COUNT 0x1BA7 +#define mmCRTC0_CRTC_STEREO_CONTROL 0x1BAE +#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x1B9B +#define mmCRTC0_CRTC_STEREO_STATUS 0x1BAD +#define mmCRTC0_CRTC_TEST_DEBUG_DATA 0x1BC7 +#define mmCRTC0_CRTC_TEST_DEBUG_INDEX 0x1BC6 +#define mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x1BBC +#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1BBA +#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x1BBB +#define mmCRTC0_CRTC_TRIGA_CNTL 0x1B94 +#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x1B95 +#define mmCRTC0_CRTC_TRIGB_CNTL 0x1B96 +#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x1B97 +#define mmCRTC0_CRTC_UPDATE_LOCK 0x1BB5 +#define mmCRTC0_CRTC_VBI_END 0x1B86 +#define mmCRTC0_CRTC_V_BLANK_START_END 0x1B8D +#define mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x1BAC +#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1BB7 +#define mmCRTC0_CRTC_V_SYNC_A 0x1B8E +#define mmCRTC0_CRTC_V_SYNC_A_CNTL 0x1B8F +#define mmCRTC0_CRTC_V_SYNC_B 0x1B90 +#define mmCRTC0_CRTC_V_SYNC_B_CNTL 0x1B91 +#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x1B8C +#define mmCRTC0_CRTC_V_TOTAL 0x1B87 +#define mmCRTC0_CRTC_V_TOTAL_CONTROL 0x1B8A +#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x1B8B +#define mmCRTC0_CRTC_V_TOTAL_MAX 0x1B89 +#define mmCRTC0_CRTC_V_TOTAL_MIN 0x1B88 +#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x1BC4 +#define mmCRTC0_DCFE_DBG_SEL 0x1B7E +#define mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL 0x1B7F +#define mmCRTC0_MASTER_UPDATE_LOCK 0x1BBD +#define mmCRTC0_MASTER_UPDATE_MODE 0x1BBE +#define mmCRTC0_PIXEL_RATE_CNTL 0x0140 +#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x1E78 +#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x1EC3 +#define mmCRTC1_CRTC_BLACK_COLOR 0x1EA2 +#define mmCRTC1_CRTC_BLANK_CONTROL 0x1E9D +#define mmCRTC1_CRTC_BLANK_DATA_COLOR 0x1EA1 +#define mmCRTC1_CRTC_CONTROL 0x1E9C +#define mmCRTC1_CRTC_COUNT_CONTROL 0x1EA9 +#define mmCRTC1_CRTC_COUNT_RESET 0x1EAA +#define mmCRTC1_CRTC_DCFE_CLOCK_CONTROL 0x1E7C +#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x1EB6 +#define mmCRTC1_CRTC_DTMTEST_CNTL 0x1E92 +#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x1E93 +#define mmCRTC1_CRTC_FLOW_CONTROL 0x1E99 +#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x1E98 +#define mmCRTC1_CRTC_GSL_CONTROL 0x1E7B +#define mmCRTC1_CRTC_GSL_VSYNC_GAP 0x1E79 +#define mmCRTC1_CRTC_GSL_WINDOW 0x1E7A +#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x1E7D +#define mmCRTC1_CRTC_H_BLANK_START_END 0x1E81 +#define mmCRTC1_CRTC_H_SYNC_A 0x1E82 +#define mmCRTC1_CRTC_H_SYNC_A_CNTL 0x1E83 +#define mmCRTC1_CRTC_H_SYNC_B 0x1E84 +#define mmCRTC1_CRTC_H_SYNC_B_CNTL 0x1E85 +#define mmCRTC1_CRTC_H_TOTAL 0x1E80 +#define mmCRTC1_CRTC_INTERLACE_CONTROL 0x1E9E +#define mmCRTC1_CRTC_INTERLACE_STATUS 0x1E9F +#define mmCRTC1_CRTC_INTERRUPT_CONTROL 0x1EB4 +#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1EAB +#define mmCRTC1_CRTC_MASTER_EN 0x1EC2 +#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x1EBF +#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1EC0 +#define mmCRTC1_CRTC_MVP_STATUS 0x1EC1 +#define mmCRTC1_CRTC_NOM_VERT_POSITION 0x1EA5 +#define mmCRTC1_CRTC_OVERSCAN_COLOR 0x1EA0 +#define mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x1EB0 +#define mmCRTC1_CRTC_SNAPSHOT_FRAME 0x1EB2 +#define mmCRTC1_CRTC_SNAPSHOT_POSITION 0x1EB1 +#define mmCRTC1_CRTC_SNAPSHOT_STATUS 0x1EAF +#define mmCRTC1_CRTC_START_LINE_CONTROL 0x1EB3 +#define mmCRTC1_CRTC_STATUS 0x1EA3 +#define mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x1EA6 +#define mmCRTC1_CRTC_STATUS_HV_COUNT 0x1EA8 +#define mmCRTC1_CRTC_STATUS_POSITION 0x1EA4 +#define mmCRTC1_CRTC_STATUS_VF_COUNT 0x1EA7 +#define mmCRTC1_CRTC_STEREO_CONTROL 0x1EAE +#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x1E9B +#define mmCRTC1_CRTC_STEREO_STATUS 0x1EAD +#define mmCRTC1_CRTC_TEST_DEBUG_DATA 0x1EC7 +#define mmCRTC1_CRTC_TEST_DEBUG_INDEX 0x1EC6 +#define mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x1EBC +#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x1EBA +#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x1EBB +#define mmCRTC1_CRTC_TRIGA_CNTL 0x1E94 +#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x1E95 +#define mmCRTC1_CRTC_TRIGB_CNTL 0x1E96 +#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x1E97 +#define mmCRTC1_CRTC_UPDATE_LOCK 0x1EB5 +#define mmCRTC1_CRTC_VBI_END 0x1E86 +#define mmCRTC1_CRTC_V_BLANK_START_END 0x1E8D +#define mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x1EAC +#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1EB7 +#define mmCRTC1_CRTC_V_SYNC_A 0x1E8E +#define mmCRTC1_CRTC_V_SYNC_A_CNTL 0x1E8F +#define mmCRTC1_CRTC_V_SYNC_B 0x1E90 +#define mmCRTC1_CRTC_V_SYNC_B_CNTL 0x1E91 +#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x1E8C +#define mmCRTC1_CRTC_V_TOTAL 0x1E87 +#define mmCRTC1_CRTC_V_TOTAL_CONTROL 0x1E8A +#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x1E8B +#define mmCRTC1_CRTC_V_TOTAL_MAX 0x1E89 +#define mmCRTC1_CRTC_V_TOTAL_MIN 0x1E88 +#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x1EC4 +#define mmCRTC1_DCFE_DBG_SEL 0x1E7E +#define mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL 0x1E7F +#define mmCRTC1_MASTER_UPDATE_LOCK 0x1EBD +#define mmCRTC1_MASTER_UPDATE_MODE 0x1EBE +#define mmCRTC1_PIXEL_RATE_CNTL 0x0144 +#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x4178 +#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x41C3 +#define mmCRTC2_CRTC_BLACK_COLOR 0x41A2 +#define mmCRTC2_CRTC_BLANK_CONTROL 0x419D +#define mmCRTC2_CRTC_BLANK_DATA_COLOR 0x41A1 +#define mmCRTC2_CRTC_CONTROL 0x419C +#define mmCRTC2_CRTC_COUNT_CONTROL 0x41A9 +#define mmCRTC2_CRTC_COUNT_RESET 0x41AA +#define mmCRTC2_CRTC_DCFE_CLOCK_CONTROL 0x417C +#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x41B6 +#define mmCRTC2_CRTC_DTMTEST_CNTL 0x4192 +#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x4193 +#define mmCRTC2_CRTC_FLOW_CONTROL 0x4199 +#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x4198 +#define mmCRTC2_CRTC_GSL_CONTROL 0x417B +#define mmCRTC2_CRTC_GSL_VSYNC_GAP 0x4179 +#define mmCRTC2_CRTC_GSL_WINDOW 0x417A +#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x417D +#define mmCRTC2_CRTC_H_BLANK_START_END 0x4181 +#define mmCRTC2_CRTC_H_SYNC_A 0x4182 +#define mmCRTC2_CRTC_H_SYNC_A_CNTL 0x4183 +#define mmCRTC2_CRTC_H_SYNC_B 0x4184 +#define mmCRTC2_CRTC_H_SYNC_B_CNTL 0x4185 +#define mmCRTC2_CRTC_H_TOTAL 0x4180 +#define mmCRTC2_CRTC_INTERLACE_CONTROL 0x419E +#define mmCRTC2_CRTC_INTERLACE_STATUS 0x419F +#define mmCRTC2_CRTC_INTERRUPT_CONTROL 0x41B4 +#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x41AB +#define mmCRTC2_CRTC_MASTER_EN 0x41C2 +#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x41BF +#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x41C0 +#define mmCRTC2_CRTC_MVP_STATUS 0x41C1 +#define mmCRTC2_CRTC_NOM_VERT_POSITION 0x41A5 +#define mmCRTC2_CRTC_OVERSCAN_COLOR 0x41A0 +#define mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x41B0 +#define mmCRTC2_CRTC_SNAPSHOT_FRAME 0x41B2 +#define mmCRTC2_CRTC_SNAPSHOT_POSITION 0x41B1 +#define mmCRTC2_CRTC_SNAPSHOT_STATUS 0x41AF +#define mmCRTC2_CRTC_START_LINE_CONTROL 0x41B3 +#define mmCRTC2_CRTC_STATUS 0x41A3 +#define mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x41A6 +#define mmCRTC2_CRTC_STATUS_HV_COUNT 0x41A8 +#define mmCRTC2_CRTC_STATUS_POSITION 0x41A4 +#define mmCRTC2_CRTC_STATUS_VF_COUNT 0x41A7 +#define mmCRTC2_CRTC_STEREO_CONTROL 0x41AE +#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x419B +#define mmCRTC2_CRTC_STEREO_STATUS 0x41AD +#define mmCRTC2_CRTC_TEST_DEBUG_DATA 0x41C7 +#define mmCRTC2_CRTC_TEST_DEBUG_INDEX 0x41C6 +#define mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x41BC +#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x41BA +#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x41BB +#define mmCRTC2_CRTC_TRIGA_CNTL 0x4194 +#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x4195 +#define mmCRTC2_CRTC_TRIGB_CNTL 0x4196 +#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x4197 +#define mmCRTC2_CRTC_UPDATE_LOCK 0x41B5 +#define mmCRTC2_CRTC_VBI_END 0x4186 +#define mmCRTC2_CRTC_V_BLANK_START_END 0x418D +#define mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x41AC +#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x41B7 +#define mmCRTC2_CRTC_V_SYNC_A 0x418E +#define mmCRTC2_CRTC_V_SYNC_A_CNTL 0x418F +#define mmCRTC2_CRTC_V_SYNC_B 0x4190 +#define mmCRTC2_CRTC_V_SYNC_B_CNTL 0x4191 +#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x418C +#define mmCRTC2_CRTC_V_TOTAL 0x4187 +#define mmCRTC2_CRTC_V_TOTAL_CONTROL 0x418A +#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x418B +#define mmCRTC2_CRTC_V_TOTAL_MAX 0x4189 +#define mmCRTC2_CRTC_V_TOTAL_MIN 0x4188 +#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x41C4 +#define mmCRTC2_DCFE_DBG_SEL 0x417E +#define mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL 0x417F +#define mmCRTC2_MASTER_UPDATE_LOCK 0x41BD +#define mmCRTC2_MASTER_UPDATE_MODE 0x41BE +#define mmCRTC2_PIXEL_RATE_CNTL 0x0148 +#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x4478 +#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x44C3 +#define mmCRTC3_CRTC_BLACK_COLOR 0x44A2 +#define mmCRTC3_CRTC_BLANK_CONTROL 0x449D +#define mmCRTC3_CRTC_BLANK_DATA_COLOR 0x44A1 +#define mmCRTC3_CRTC_CONTROL 0x449C +#define mmCRTC3_CRTC_COUNT_CONTROL 0x44A9 +#define mmCRTC3_CRTC_COUNT_RESET 0x44AA +#define mmCRTC3_CRTC_DCFE_CLOCK_CONTROL 0x447C +#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x44B6 +#define mmCRTC3_CRTC_DTMTEST_CNTL 0x4492 +#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x4493 +#define mmCRTC3_CRTC_FLOW_CONTROL 0x4499 +#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x4498 +#define mmCRTC3_CRTC_GSL_CONTROL 0x447B +#define mmCRTC3_CRTC_GSL_VSYNC_GAP 0x4479 +#define mmCRTC3_CRTC_GSL_WINDOW 0x447A +#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x447D +#define mmCRTC3_CRTC_H_BLANK_START_END 0x4481 +#define mmCRTC3_CRTC_H_SYNC_A 0x4482 +#define mmCRTC3_CRTC_H_SYNC_A_CNTL 0x4483 +#define mmCRTC3_CRTC_H_SYNC_B 0x4484 +#define mmCRTC3_CRTC_H_SYNC_B_CNTL 0x4485 +#define mmCRTC3_CRTC_H_TOTAL 0x4480 +#define mmCRTC3_CRTC_INTERLACE_CONTROL 0x449E +#define mmCRTC3_CRTC_INTERLACE_STATUS 0x449F +#define mmCRTC3_CRTC_INTERRUPT_CONTROL 0x44B4 +#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x44AB +#define mmCRTC3_CRTC_MASTER_EN 0x44C2 +#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x44BF +#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x44C0 +#define mmCRTC3_CRTC_MVP_STATUS 0x44C1 +#define mmCRTC3_CRTC_NOM_VERT_POSITION 0x44A5 +#define mmCRTC3_CRTC_OVERSCAN_COLOR 0x44A0 +#define mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x44B0 +#define mmCRTC3_CRTC_SNAPSHOT_FRAME 0x44B2 +#define mmCRTC3_CRTC_SNAPSHOT_POSITION 0x44B1 +#define mmCRTC3_CRTC_SNAPSHOT_STATUS 0x44AF +#define mmCRTC3_CRTC_START_LINE_CONTROL 0x44B3 +#define mmCRTC3_CRTC_STATUS 0x44A3 +#define mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x44A6 +#define mmCRTC3_CRTC_STATUS_HV_COUNT 0x44A8 +#define mmCRTC3_CRTC_STATUS_POSITION 0x44A4 +#define mmCRTC3_CRTC_STATUS_VF_COUNT 0x44A7 +#define mmCRTC3_CRTC_STEREO_CONTROL 0x44AE +#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x449B +#define mmCRTC3_CRTC_STEREO_STATUS 0x44AD +#define mmCRTC3_CRTC_TEST_DEBUG_DATA 0x44C7 +#define mmCRTC3_CRTC_TEST_DEBUG_INDEX 0x44C6 +#define mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x44BC +#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x44BA +#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x44BB +#define mmCRTC3_CRTC_TRIGA_CNTL 0x4494 +#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x4495 +#define mmCRTC3_CRTC_TRIGB_CNTL 0x4496 +#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x4497 +#define mmCRTC3_CRTC_UPDATE_LOCK 0x44B5 +#define mmCRTC3_CRTC_VBI_END 0x4486 +#define mmCRTC3_CRTC_V_BLANK_START_END 0x448D +#define mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x44AC +#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x44B7 +#define mmCRTC3_CRTC_V_SYNC_A 0x448E +#define mmCRTC3_CRTC_V_SYNC_A_CNTL 0x448F +#define mmCRTC3_CRTC_V_SYNC_B 0x4490 +#define mmCRTC3_CRTC_V_SYNC_B_CNTL 0x4491 +#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x448C +#define mmCRTC3_CRTC_V_TOTAL 0x4487 +#define mmCRTC3_CRTC_V_TOTAL_CONTROL 0x448A +#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x448B +#define mmCRTC3_CRTC_V_TOTAL_MAX 0x4489 +#define mmCRTC3_CRTC_V_TOTAL_MIN 0x4488 +#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x44C4 +#define mmCRTC3_DCFE_DBG_SEL 0x447E +#define mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL 0x447F +#define mmCRTC_3D_STRUCTURE_CONTROL 0x1B78 +#define mmCRTC3_MASTER_UPDATE_LOCK 0x44BD +#define mmCRTC3_MASTER_UPDATE_MODE 0x44BE +#define mmCRTC3_PIXEL_RATE_CNTL 0x014C +#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x4778 +#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x47C3 +#define mmCRTC4_CRTC_BLACK_COLOR 0x47A2 +#define mmCRTC4_CRTC_BLANK_CONTROL 0x479D +#define mmCRTC4_CRTC_BLANK_DATA_COLOR 0x47A1 +#define mmCRTC4_CRTC_CONTROL 0x479C +#define mmCRTC4_CRTC_COUNT_CONTROL 0x47A9 +#define mmCRTC4_CRTC_COUNT_RESET 0x47AA +#define mmCRTC4_CRTC_DCFE_CLOCK_CONTROL 0x477C +#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x47B6 +#define mmCRTC4_CRTC_DTMTEST_CNTL 0x4792 +#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x4793 +#define mmCRTC4_CRTC_FLOW_CONTROL 0x4799 +#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x4798 +#define mmCRTC4_CRTC_GSL_CONTROL 0x477B +#define mmCRTC4_CRTC_GSL_VSYNC_GAP 0x4779 +#define mmCRTC4_CRTC_GSL_WINDOW 0x477A +#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x477D +#define mmCRTC4_CRTC_H_BLANK_START_END 0x4781 +#define mmCRTC4_CRTC_H_SYNC_A 0x4782 +#define mmCRTC4_CRTC_H_SYNC_A_CNTL 0x4783 +#define mmCRTC4_CRTC_H_SYNC_B 0x4784 +#define mmCRTC4_CRTC_H_SYNC_B_CNTL 0x4785 +#define mmCRTC4_CRTC_H_TOTAL 0x4780 +#define mmCRTC4_CRTC_INTERLACE_CONTROL 0x479E +#define mmCRTC4_CRTC_INTERLACE_STATUS 0x479F +#define mmCRTC4_CRTC_INTERRUPT_CONTROL 0x47B4 +#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x47AB +#define mmCRTC4_CRTC_MASTER_EN 0x47C2 +#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x47BF +#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x47C0 +#define mmCRTC4_CRTC_MVP_STATUS 0x47C1 +#define mmCRTC4_CRTC_NOM_VERT_POSITION 0x47A5 +#define mmCRTC4_CRTC_OVERSCAN_COLOR 0x47A0 +#define mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x47B0 +#define mmCRTC4_CRTC_SNAPSHOT_FRAME 0x47B2 +#define mmCRTC4_CRTC_SNAPSHOT_POSITION 0x47B1 +#define mmCRTC4_CRTC_SNAPSHOT_STATUS 0x47AF +#define mmCRTC4_CRTC_START_LINE_CONTROL 0x47B3 +#define mmCRTC4_CRTC_STATUS 0x47A3 +#define mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x47A6 +#define mmCRTC4_CRTC_STATUS_HV_COUNT 0x47A8 +#define mmCRTC4_CRTC_STATUS_POSITION 0x47A4 +#define mmCRTC4_CRTC_STATUS_VF_COUNT 0x47A7 +#define mmCRTC4_CRTC_STEREO_CONTROL 0x47AE +#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x479B +#define mmCRTC4_CRTC_STEREO_STATUS 0x47AD +#define mmCRTC4_CRTC_TEST_DEBUG_DATA 0x47C7 +#define mmCRTC4_CRTC_TEST_DEBUG_INDEX 0x47C6 +#define mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x47BC +#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x47BA +#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x47BB +#define mmCRTC4_CRTC_TRIGA_CNTL 0x4794 +#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x4795 +#define mmCRTC4_CRTC_TRIGB_CNTL 0x4796 +#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x4797 +#define mmCRTC4_CRTC_UPDATE_LOCK 0x47B5 +#define mmCRTC4_CRTC_VBI_END 0x4786 +#define mmCRTC4_CRTC_V_BLANK_START_END 0x478D +#define mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x47AC +#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x47B7 +#define mmCRTC4_CRTC_V_SYNC_A 0x478E +#define mmCRTC4_CRTC_V_SYNC_A_CNTL 0x478F +#define mmCRTC4_CRTC_V_SYNC_B 0x4790 +#define mmCRTC4_CRTC_V_SYNC_B_CNTL 0x4791 +#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x478C +#define mmCRTC4_CRTC_V_TOTAL 0x4787 +#define mmCRTC4_CRTC_V_TOTAL_CONTROL 0x478A +#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x478B +#define mmCRTC4_CRTC_V_TOTAL_MAX 0x4789 +#define mmCRTC4_CRTC_V_TOTAL_MIN 0x4788 +#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x47C4 +#define mmCRTC4_DCFE_DBG_SEL 0x477E +#define mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL 0x477F +#define mmCRTC4_MASTER_UPDATE_LOCK 0x47BD +#define mmCRTC4_MASTER_UPDATE_MODE 0x47BE +#define mmCRTC4_PIXEL_RATE_CNTL 0x0150 +#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x4A78 +#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x4AC3 +#define mmCRTC5_CRTC_BLACK_COLOR 0x4AA2 +#define mmCRTC5_CRTC_BLANK_CONTROL 0x4A9D +#define mmCRTC5_CRTC_BLANK_DATA_COLOR 0x4AA1 +#define mmCRTC5_CRTC_CONTROL 0x4A9C +#define mmCRTC5_CRTC_COUNT_CONTROL 0x4AA9 +#define mmCRTC5_CRTC_COUNT_RESET 0x4AAA +#define mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 0x4A7C +#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x4AB6 +#define mmCRTC5_CRTC_DTMTEST_CNTL 0x4A92 +#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x4A93 +#define mmCRTC5_CRTC_FLOW_CONTROL 0x4A99 +#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x4A98 +#define mmCRTC5_CRTC_GSL_CONTROL 0x4A7B +#define mmCRTC5_CRTC_GSL_VSYNC_GAP 0x4A79 +#define mmCRTC5_CRTC_GSL_WINDOW 0x4A7A +#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x4A7D +#define mmCRTC5_CRTC_H_BLANK_START_END 0x4A81 +#define mmCRTC5_CRTC_H_SYNC_A 0x4A82 +#define mmCRTC5_CRTC_H_SYNC_A_CNTL 0x4A83 +#define mmCRTC5_CRTC_H_SYNC_B 0x4A84 +#define mmCRTC5_CRTC_H_SYNC_B_CNTL 0x4A85 +#define mmCRTC5_CRTC_H_TOTAL 0x4A80 +#define mmCRTC5_CRTC_INTERLACE_CONTROL 0x4A9E +#define mmCRTC5_CRTC_INTERLACE_STATUS 0x4A9F +#define mmCRTC5_CRTC_INTERRUPT_CONTROL 0x4AB4 +#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x4AAB +#define mmCRTC5_CRTC_MASTER_EN 0x4AC2 +#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x4ABF +#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x4AC0 +#define mmCRTC5_CRTC_MVP_STATUS 0x4AC1 +#define mmCRTC5_CRTC_NOM_VERT_POSITION 0x4AA5 +#define mmCRTC5_CRTC_OVERSCAN_COLOR 0x4AA0 +#define mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x4AB0 +#define mmCRTC5_CRTC_SNAPSHOT_FRAME 0x4AB2 +#define mmCRTC5_CRTC_SNAPSHOT_POSITION 0x4AB1 +#define mmCRTC5_CRTC_SNAPSHOT_STATUS 0x4AAF +#define mmCRTC5_CRTC_START_LINE_CONTROL 0x4AB3 +#define mmCRTC5_CRTC_STATUS 0x4AA3 +#define mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x4AA6 +#define mmCRTC5_CRTC_STATUS_HV_COUNT 0x4AA8 +#define mmCRTC5_CRTC_STATUS_POSITION 0x4AA4 +#define mmCRTC5_CRTC_STATUS_VF_COUNT 0x4AA7 +#define mmCRTC5_CRTC_STEREO_CONTROL 0x4AAE +#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x4A9B +#define mmCRTC5_CRTC_STEREO_STATUS 0x4AAD +#define mmCRTC5_CRTC_TEST_DEBUG_DATA 0x4AC7 +#define mmCRTC5_CRTC_TEST_DEBUG_INDEX 0x4AC6 +#define mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x4ABC +#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x4ABA +#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x4ABB +#define mmCRTC5_CRTC_TRIGA_CNTL 0x4A94 +#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x4A95 +#define mmCRTC5_CRTC_TRIGB_CNTL 0x4A96 +#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x4A97 +#define mmCRTC5_CRTC_UPDATE_LOCK 0x4AB5 +#define mmCRTC5_CRTC_VBI_END 0x4A86 +#define mmCRTC5_CRTC_V_BLANK_START_END 0x4A8D +#define mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x4AAC +#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x4AB7 +#define mmCRTC5_CRTC_V_SYNC_A 0x4A8E +#define mmCRTC5_CRTC_V_SYNC_A_CNTL 0x4A8F +#define mmCRTC5_CRTC_V_SYNC_B 0x4A90 +#define mmCRTC5_CRTC_V_SYNC_B_CNTL 0x4A91 +#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x4A8C +#define mmCRTC5_CRTC_V_TOTAL 0x4A87 +#define mmCRTC5_CRTC_V_TOTAL_CONTROL 0x4A8A +#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x4A8B +#define mmCRTC5_CRTC_V_TOTAL_MAX 0x4A89 +#define mmCRTC5_CRTC_V_TOTAL_MIN 0x4A88 +#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x4AC4 +#define mmCRTC5_DCFE_DBG_SEL 0x4A7E +#define mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL 0x4A7F +#define mmCRTC5_MASTER_UPDATE_LOCK 0x4ABD +#define mmCRTC5_MASTER_UPDATE_MODE 0x4ABE +#define mmCRTC5_PIXEL_RATE_CNTL 0x0154 +#define mmCRTC8_DATA 0x00ED +#define mmCRTC8_IDX 0x00ED +#define mmCRTC_ALLOW_STOP_OFF_V_CNT 0x1BC3 +#define mmCRTC_BLACK_COLOR 0x1BA2 +#define mmCRTC_BLANK_CONTROL 0x1B9D +#define mmCRTC_BLANK_DATA_COLOR 0x1BA1 +#define mmCRTC_CONTROL 0x1B9C +#define mmCRTC_COUNT_CONTROL 0x1BA9 +#define mmCRTC_COUNT_RESET 0x1BAA +#define mmCRTC_DCFE_CLOCK_CONTROL 0x1B7C +#define mmCRTC_DOUBLE_BUFFER_CONTROL 0x1BB6 +#define mmCRTC_DTMTEST_CNTL 0x1B92 +#define mmCRTC_DTMTEST_STATUS_POSITION 0x1B93 +#define mmCRTC_FLOW_CONTROL 0x1B99 +#define mmCRTC_FORCE_COUNT_NOW_CNTL 0x1B98 +#define mmCRTC_GSL_CONTROL 0x1B7B +#define mmCRTC_GSL_VSYNC_GAP 0x1B79 +#define mmCRTC_GSL_WINDOW 0x1B7A +#define mmCRTC_H_BLANK_EARLY_NUM 0x1B7D +#define mmCRTC_H_BLANK_START_END 0x1B81 +#define mmCRTC_H_SYNC_A 0x1B82 +#define mmCRTC_H_SYNC_A_CNTL 0x1B83 +#define mmCRTC_H_SYNC_B 0x1B84 +#define mmCRTC_H_SYNC_B_CNTL 0x1B85 +#define mmCRTC_H_TOTAL 0x1B80 +#define mmCRTC_INTERLACE_CONTROL 0x1B9E +#define mmCRTC_INTERLACE_STATUS 0x1B9F +#define mmCRTC_INTERRUPT_CONTROL 0x1BB4 +#define mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1BAB +#define mmCRTC_MASTER_EN 0x1BC2 +#define mmCRTC_MVP_INBAND_CNTL_INSERT 0x1BBF +#define mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1BC0 +#define mmCRTC_MVP_STATUS 0x1BC1 +#define mmCRTC_NOM_VERT_POSITION 0x1BA5 +#define mmCRTC_OVERSCAN_COLOR 0x1BA0 +#define mmCRTC_SNAPSHOT_CONTROL 0x1BB0 +#define mmCRTC_SNAPSHOT_FRAME 0x1BB2 +#define mmCRTC_SNAPSHOT_POSITION 0x1BB1 +#define mmCRTC_SNAPSHOT_STATUS 0x1BAF +#define mmCRTC_START_LINE_CONTROL 0x1BB3 +#define mmCRTC_STATUS 0x1BA3 +#define mmCRTC_STATUS_FRAME_COUNT 0x1BA6 +#define mmCRTC_STATUS_HV_COUNT 0x1BA8 +#define mmCRTC_STATUS_POSITION 0x1BA4 +#define mmCRTC_STATUS_VF_COUNT 0x1BA7 +#define mmCRTC_STEREO_CONTROL 0x1BAE +#define mmCRTC_STEREO_FORCE_NEXT_EYE 0x1B9B +#define mmCRTC_STEREO_STATUS 0x1BAD +#define mmCRTC_TEST_DEBUG_DATA 0x1BC7 +#define mmCRTC_TEST_DEBUG_INDEX 0x1BC6 +#define mmCRTC_TEST_PATTERN_COLOR 0x1BBC +#define mmCRTC_TEST_PATTERN_CONTROL 0x1BBA +#define mmCRTC_TEST_PATTERN_PARAMETERS 0x1BBB +#define mmCRTC_TRIGA_CNTL 0x1B94 +#define mmCRTC_TRIGA_MANUAL_TRIG 0x1B95 +#define mmCRTC_TRIGB_CNTL 0x1B96 +#define mmCRTC_TRIGB_MANUAL_TRIG 0x1B97 +#define mmCRTC_UPDATE_LOCK 0x1BB5 +#define mmCRTC_VBI_END 0x1B86 +#define mmCRTC_V_BLANK_START_END 0x1B8D +#define mmCRTC_VERT_SYNC_CONTROL 0x1BAC +#define mmCRTC_VGA_PARAMETER_CAPTURE_MODE 0x1BB7 +#define mmCRTC_V_SYNC_A 0x1B8E +#define mmCRTC_V_SYNC_A_CNTL 0x1B8F +#define mmCRTC_V_SYNC_B 0x1B90 +#define mmCRTC_V_SYNC_B_CNTL 0x1B91 +#define mmCRTC_VSYNC_NOM_INT_STATUS 0x1B8C +#define mmCRTC_V_TOTAL 0x1B87 +#define mmCRTC_V_TOTAL_CONTROL 0x1B8A +#define mmCRTC_V_TOTAL_INT_STATUS 0x1B8B +#define mmCRTC_V_TOTAL_MAX 0x1B89 +#define mmCRTC_V_TOTAL_MIN 0x1B88 +#define mmCRTC_V_UPDATE_INT_STATUS 0x1BC4 +#define mmCUR_COLOR1 0x1A6C +#define mmCUR_COLOR2 0x1A6D +#define mmCUR_CONTROL 0x1A66 +#define mmCUR_HOT_SPOT 0x1A6B +#define mmCUR_POSITION 0x1A6A +#define mmCUR_REQUEST_FILTER_CNTL 0x1A99 +#define mmCUR_SIZE 0x1A68 +#define mmCUR_SURFACE_ADDRESS 0x1A67 +#define mmCUR_SURFACE_ADDRESS_HIGH 0x1A69 +#define mmCUR_UPDATE 0x1A6E +#define mmD1VGA_CONTROL 0x00CC +#define mmD2VGA_CONTROL 0x00CE +#define mmD3VGA_CONTROL 0x00F8 +#define mmD4VGA_CONTROL 0x00F9 +#define mmD5VGA_CONTROL 0x00FA +#define mmD6VGA_CONTROL 0x00FB +#define mmDAC_AUTODETECT_CONTROL 0x19EE +#define mmDAC_AUTODETECT_CONTROL2 0x19EF +#define mmDAC_AUTODETECT_CONTROL3 0x19F0 +#define mmDAC_AUTODETECT_INT_CONTROL 0x19F2 +#define mmDAC_AUTODETECT_STATUS 0x19F1 +#define mmDAC_CLK_ENABLE 0x0128 +#define mmDAC_COMPARATOR_ENABLE 0x19F7 +#define mmDAC_COMPARATOR_OUTPUT 0x19F8 +#define mmDAC_CONTROL 0x19F6 +#define mmDAC_CRC_CONTROL 0x19E7 +#define mmDAC_CRC_EN 0x19E6 +#define mmDAC_CRC_SIG_CONTROL 0x19EB +#define mmDAC_CRC_SIG_CONTROL_MASK 0x19E9 +#define mmDAC_CRC_SIG_RGB 0x19EA +#define mmDAC_CRC_SIG_RGB_MASK 0x19E8 +#define mmDAC_DATA 0x00F2 +#define mmDAC_DFT_CONFIG 0x19FA +#define mmDAC_ENABLE 0x19E4 +#define mmDAC_FIFO_STATUS 0x19FB +#define mmDAC_FORCE_DATA 0x19F4 +#define mmDAC_FORCE_OUTPUT_CNTL 0x19F3 +#define mmDAC_MACRO_CNTL_RESERVED0 0x19FC +#define mmDAC_MACRO_CNTL_RESERVED1 0x19FD +#define mmDAC_MACRO_CNTL_RESERVED2 0x19FE +#define mmDAC_MACRO_CNTL_RESERVED3 0x19FF +#define mmDAC_MASK 0x00F1 +#define mmDAC_POWERDOWN 0x19F5 +#define mmDAC_PWR_CNTL 0x19F9 +#define mmDAC_R_INDEX 0x00F1 +#define mmDAC_SOURCE_SELECT 0x19E5 +#define mmDAC_STEREOSYNC_SELECT 0x19ED +#define mmDAC_SYNC_TRISTATE_CONTROL 0x19EC +#define mmDAC_W_INDEX 0x00F2 +#define mmDC_ABM1_ACE_CNTL_MISC 0x1641 +#define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x163A +#define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x163B +#define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x163C +#define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x163D +#define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x163E +#define mmDC_ABM1_ACE_THRES_12 0x163F +#define mmDC_ABM1_ACE_THRES_34 0x1640 +#define mmDC_ABM1_BL_MASTER_LOCK 0x169C +#define mmDC_ABM1_CNTL 0x1638 +#define mmDC_ABM1_DEBUG_MISC 0x1649 +#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1656 +#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1659 +#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1657 +#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x165A +#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1658 +#define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x164A +#define mmDC_ABM1_HG_MISC_CTRL 0x164B +#define mmDC_ABM1_HG_RESULT_10 0x1664 +#define mmDC_ABM1_HG_RESULT_1 0x165B +#define mmDC_ABM1_HG_RESULT_11 0x1665 +#define mmDC_ABM1_HG_RESULT_12 0x1666 +#define mmDC_ABM1_HG_RESULT_13 0x1667 +#define mmDC_ABM1_HG_RESULT_14 0x1668 +#define mmDC_ABM1_HG_RESULT_15 0x1669 +#define mmDC_ABM1_HG_RESULT_16 0x166A +#define mmDC_ABM1_HG_RESULT_17 0x166B +#define mmDC_ABM1_HG_RESULT_18 0x166C +#define mmDC_ABM1_HG_RESULT_19 0x166D +#define mmDC_ABM1_HG_RESULT_20 0x166E +#define mmDC_ABM1_HG_RESULT_2 0x165C +#define mmDC_ABM1_HG_RESULT_21 0x166F +#define mmDC_ABM1_HG_RESULT_22 0x1670 +#define mmDC_ABM1_HG_RESULT_23 0x1671 +#define mmDC_ABM1_HG_RESULT_24 0x1672 +#define mmDC_ABM1_HG_RESULT_3 0x165D +#define mmDC_ABM1_HG_RESULT_4 0x165E +#define mmDC_ABM1_HG_RESULT_5 0x165F +#define mmDC_ABM1_HG_RESULT_6 0x1660 +#define mmDC_ABM1_HG_RESULT_7 0x1661 +#define mmDC_ABM1_HG_RESULT_8 0x1662 +#define mmDC_ABM1_HG_RESULT_9 0x1663 +#define mmDC_ABM1_HG_SAMPLE_RATE 0x1654 +#define mmDC_ABM1_IPCSC_COEFF_SEL 0x1639 +#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x164E +#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1653 +#define mmDC_ABM1_LS_MIN_MAX_LUMA 0x164D +#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1651 +#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1652 +#define mmDC_ABM1_LS_OVR_SCAN_BIN 0x1650 +#define mmDC_ABM1_LS_PIXEL_COUNT 0x164F +#define mmDC_ABM1_LS_SAMPLE_RATE 0x1655 +#define mmDC_ABM1_LS_SUM_OF_LUMA 0x164C +#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x169B +#define mmDCCG_AUDIO_DTO0_MODULE 0x016D +#define mmDCCG_AUDIO_DTO0_PHASE 0x016C +#define mmDCCG_AUDIO_DTO1_MODULE 0x0171 +#define mmDCCG_AUDIO_DTO1_PHASE 0x0170 +#define mmDCCG_AUDIO_DTO_SOURCE 0x016B +#define mmDCCG_CAC_STATUS 0x0137 +#define mmDCCG_GATE_DISABLE_CNTL 0x0134 +#define mmDCCG_GTC_CNTL 0x0120 +#define mmDCCG_GTC_CURRENT 0x0123 +#define mmDCCG_GTC_DTO_MODULO 0x0122 +#define mmDCCG_PERFMON_CNTL 0x0133 +#define mmDCCG_PLL0_PLL_ANALOG 0x1708 +#define mmDCCG_PLL0_PLL_CNTL 0x1707 +#define mmDCCG_PLL0_PLL_DEBUG_CNTL 0x170B +#define mmDCCG_PLL0_PLL_DISPCLK_CURRENT_DTO_PHASE 0x170F +#define mmDCCG_PLL0_PLL_DISPCLK_DTO_CNTL 0x170E +#define mmDCCG_PLL0_PLL_DS_CNTL 0x1705 +#define mmDCCG_PLL0_PLL_FB_DIV 0x1701 +#define mmDCCG_PLL0_PLL_IDCLK_CNTL 0x1706 +#define mmDCCG_PLL0_PLL_POST_DIV 0x1702 +#define mmDCCG_PLL0_PLL_REF_DIV 0x1700 +#define mmDCCG_PLL0_PLL_SS_AMOUNT_DSFRAC 0x1703 +#define mmDCCG_PLL0_PLL_SS_CNTL 0x1704 +#define mmDCCG_PLL0_PLL_UNLOCK_DETECT_CNTL 0x170A +#define mmDCCG_PLL0_PLL_UPDATE_CNTL 0x170D +#define mmDCCG_PLL0_PLL_UPDATE_LOCK 0x170C +#define mmDCCG_PLL0_PLL_VREG_CNTL 0x1709 +#define mmDCCG_PLL1_PLL_ANALOG 0x1718 +#define mmDCCG_PLL1_PLL_CNTL 0x1717 +#define mmDCCG_PLL1_PLL_DEBUG_CNTL 0x171B +#define mmDCCG_PLL1_PLL_DISPCLK_CURRENT_DTO_PHASE 0x171F +#define mmDCCG_PLL1_PLL_DISPCLK_DTO_CNTL 0x171E +#define mmDCCG_PLL1_PLL_DS_CNTL 0x1715 +#define mmDCCG_PLL1_PLL_FB_DIV 0x1711 +#define mmDCCG_PLL1_PLL_IDCLK_CNTL 0x1716 +#define mmDCCG_PLL1_PLL_POST_DIV 0x1712 +#define mmDCCG_PLL1_PLL_REF_DIV 0x1710 +#define mmDCCG_PLL1_PLL_SS_AMOUNT_DSFRAC 0x1713 +#define mmDCCG_PLL1_PLL_SS_CNTL 0x1714 +#define mmDCCG_PLL1_PLL_UNLOCK_DETECT_CNTL 0x171A +#define mmDCCG_PLL1_PLL_UPDATE_CNTL 0x171D +#define mmDCCG_PLL1_PLL_UPDATE_LOCK 0x171C +#define mmDCCG_PLL1_PLL_VREG_CNTL 0x1719 +#define mmDCCG_PLL2_PLL_ANALOG 0x1728 +#define mmDCCG_PLL2_PLL_CNTL 0x1727 +#define mmDCCG_PLL2_PLL_DEBUG_CNTL 0x172B +#define mmDCCG_PLL2_PLL_DISPCLK_CURRENT_DTO_PHASE 0x172F +#define mmDCCG_PLL2_PLL_DISPCLK_DTO_CNTL 0x172E +#define mmDCCG_PLL2_PLL_DS_CNTL 0x1725 +#define mmDCCG_PLL2_PLL_FB_DIV 0x1721 +#define mmDCCG_PLL2_PLL_IDCLK_CNTL 0x1726 +#define mmDCCG_PLL2_PLL_POST_DIV 0x1722 +#define mmDCCG_PLL2_PLL_REF_DIV 0x1720 +#define mmDCCG_PLL2_PLL_SS_AMOUNT_DSFRAC 0x1723 +#define mmDCCG_PLL2_PLL_SS_CNTL 0x1724 +#define mmDCCG_PLL2_PLL_UNLOCK_DETECT_CNTL 0x172A +#define mmDCCG_PLL2_PLL_UPDATE_CNTL 0x172D +#define mmDCCG_PLL2_PLL_UPDATE_LOCK 0x172C +#define mmDCCG_PLL2_PLL_VREG_CNTL 0x1729 +#define mmDCCG_SOFT_RESET 0x015F +#define mmDCCG_TEST_CLK_SEL 0x017E +#define mmDCCG_TEST_DEBUG_DATA 0x017D +#define mmDCCG_TEST_DEBUG_INDEX 0x017C +#define mmDCCG_VPCLK_CNTL 0x031F +#define mmDCDEBUG_BUS_CLK1_SEL 0x1860 +#define mmDCDEBUG_BUS_CLK2_SEL 0x1861 +#define mmDCDEBUG_BUS_CLK3_SEL 0x1862 +#define mmDCDEBUG_BUS_CLK4_SEL 0x1863 +#define mmDCDEBUG_OUT_CNTL 0x186B +#define mmDCDEBUG_OUT_DATA 0x186E +#define mmDCDEBUG_OUT_PIN_OVERRIDE 0x186A +#define mmDC_DMCU_SCRATCH 0x1618 +#define mmDC_DVODATA_CONFIG 0x1905 +#define mmDCFE0_SOFT_RESET 0x0158 +#define mmDCFE1_SOFT_RESET 0x0159 +#define mmDCFE2_SOFT_RESET 0x015A +#define mmDCFE3_SOFT_RESET 0x015B +#define mmDCFE4_SOFT_RESET 0x015C +#define mmDCFE5_SOFT_RESET 0x015D +#define mmDCFE_DBG_SEL 0x1B7E +#define mmDCFE_MEM_LIGHT_SLEEP_CNTL 0x1B7F +#define mmDC_GENERICA 0x1900 +#define mmDC_GENERICB 0x1901 +#define mmDC_GPIO_DDC1_A 0x194D +#define mmDC_GPIO_DDC1_EN 0x194E +#define mmDC_GPIO_DDC1_MASK 0x194C +#define mmDC_GPIO_DDC1_Y 0x194F +#define mmDC_GPIO_DDC2_A 0x1951 +#define mmDC_GPIO_DDC2_EN 0x1952 +#define mmDC_GPIO_DDC2_MASK 0x1950 +#define mmDC_GPIO_DDC2_Y 0x1953 +#define mmDC_GPIO_DDC3_A 0x1955 +#define mmDC_GPIO_DDC3_EN 0x1956 +#define mmDC_GPIO_DDC3_MASK 0x1954 +#define mmDC_GPIO_DDC3_Y 0x1957 +#define mmDC_GPIO_DDC4_A 0x1959 +#define mmDC_GPIO_DDC4_EN 0x195A +#define mmDC_GPIO_DDC4_MASK 0x1958 +#define mmDC_GPIO_DDC4_Y 0x195B +#define mmDC_GPIO_DDC5_A 0x195D +#define mmDC_GPIO_DDC5_EN 0x195E +#define mmDC_GPIO_DDC5_MASK 0x195C +#define mmDC_GPIO_DDC5_Y 0x195F +#define mmDC_GPIO_DDC6_A 0x1961 +#define mmDC_GPIO_DDC6_EN 0x1962 +#define mmDC_GPIO_DDC6_MASK 0x1960 +#define mmDC_GPIO_DDC6_Y 0x1963 +#define mmDC_GPIO_DDCVGA_A 0x1971 +#define mmDC_GPIO_DDCVGA_EN 0x1972 +#define mmDC_GPIO_DDCVGA_MASK 0x1970 +#define mmDC_GPIO_DDCVGA_Y 0x1973 +#define mmDC_GPIO_DEBUG 0x1904 +#define mmDC_GPIO_DVODATA_A 0x1949 +#define mmDC_GPIO_DVODATA_EN 0x194A +#define mmDC_GPIO_DVODATA_MASK 0x1948 +#define mmDC_GPIO_DVODATA_Y 0x194B +#define mmDC_GPIO_GENERIC_A 0x1945 +#define mmDC_GPIO_GENERIC_EN 0x1946 +#define mmDC_GPIO_GENERIC_MASK 0x1944 +#define mmDC_GPIO_GENERIC_Y 0x1947 +#define mmDC_GPIO_GENLK_A 0x1969 +#define mmDC_GPIO_GENLK_EN 0x196A +#define mmDC_GPIO_GENLK_MASK 0x1968 +#define mmDC_GPIO_GENLK_Y 0x196B +#define mmDC_GPIO_HPD_A 0x196D +#define mmDC_GPIO_HPD_EN 0x196E +#define mmDC_GPIO_HPD_MASK 0x196C +#define mmDC_GPIO_HPD_Y 0x196F +#define mmDC_GPIO_I2CPAD_A 0x1975 +#define mmDC_GPIO_I2CPAD_EN 0x1976 +#define mmDC_GPIO_I2CPAD_MASK 0x1974 +#define mmDC_GPIO_I2CPAD_STRENGTH 0x197A +#define mmDC_GPIO_I2CPAD_Y 0x1977 +#define mmDC_GPIO_PAD_STRENGTH_1 0x1978 +#define mmDC_GPIO_PAD_STRENGTH_2 0x1979 +#define mmDC_GPIO_PWRSEQ_A 0x1941 +#define mmDC_GPIO_PWRSEQ_EN 0x1942 +#define mmDC_GPIO_PWRSEQ_MASK 0x1940 +#define mmDC_GPIO_PWRSEQ_Y 0x1943 +#define mmDC_GPIO_SYNCA_A 0x1965 +#define mmDC_GPIO_SYNCA_EN 0x1966 +#define mmDC_GPIO_SYNCA_MASK 0x1964 +#define mmDC_GPIO_SYNCA_Y 0x1967 +#define mmDC_GPU_TIMER_READ 0x1929 +#define mmDC_GPU_TIMER_READ_CNTL 0x192A +#define mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x1928 +#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x1927 +#define mmDC_HPD1_CONTROL 0x1809 +#define mmDC_HPD1_FAST_TRAIN_CNTL 0x1864 +#define mmDC_HPD1_INT_CONTROL 0x1808 +#define mmDC_HPD1_INT_STATUS 0x1807 +#define mmDC_HPD1_TOGGLE_FILT_CNTL 0x18BC +#define mmDC_HPD2_CONTROL 0x180C +#define mmDC_HPD2_FAST_TRAIN_CNTL 0x1865 +#define mmDC_HPD2_INT_CONTROL 0x180B +#define mmDC_HPD2_INT_STATUS 0x180A +#define mmDC_HPD2_TOGGLE_FILT_CNTL 0x18BD +#define mmDC_HPD3_CONTROL 0x180F +#define mmDC_HPD3_FAST_TRAIN_CNTL 0x1866 +#define mmDC_HPD3_INT_CONTROL 0x180E +#define mmDC_HPD3_INT_STATUS 0x180D +#define mmDC_HPD3_TOGGLE_FILT_CNTL 0x18BE +#define mmDC_HPD4_CONTROL 0x1812 +#define mmDC_HPD4_FAST_TRAIN_CNTL 0x1867 +#define mmDC_HPD4_INT_CONTROL 0x1811 +#define mmDC_HPD4_INT_STATUS 0x1810 +#define mmDC_HPD4_TOGGLE_FILT_CNTL 0x18FC +#define mmDC_HPD5_CONTROL 0x1815 +#define mmDC_HPD5_FAST_TRAIN_CNTL 0x1868 +#define mmDC_HPD5_INT_CONTROL 0x1814 +#define mmDC_HPD5_INT_STATUS 0x1813 +#define mmDC_HPD5_TOGGLE_FILT_CNTL 0x18FD +#define mmDC_HPD6_CONTROL 0x1818 +#define mmDC_HPD6_FAST_TRAIN_CNTL 0x1869 +#define mmDC_HPD6_INT_CONTROL 0x1817 +#define mmDC_HPD6_INT_STATUS 0x1816 +#define mmDC_HPD6_TOGGLE_FILT_CNTL 0x18FE +#define mmDC_I2C_ARBITRATION 0x181A +#define mmDC_I2C_CONTROL 0x1819 +#define mmDC_I2C_DATA 0x1833 +#define mmDC_I2C_DDC1_HW_STATUS 0x181D +#define mmDC_I2C_DDC1_SETUP 0x1824 +#define mmDC_I2C_DDC1_SPEED 0x1823 +#define mmDC_I2C_DDC2_HW_STATUS 0x181E +#define mmDC_I2C_DDC2_SETUP 0x1826 +#define mmDC_I2C_DDC2_SPEED 0x1825 +#define mmDC_I2C_DDC3_HW_STATUS 0x181F +#define mmDC_I2C_DDC3_SETUP 0x1828 +#define mmDC_I2C_DDC3_SPEED 0x1827 +#define mmDC_I2C_DDC4_HW_STATUS 0x1820 +#define mmDC_I2C_DDC4_SETUP 0x182A +#define mmDC_I2C_DDC4_SPEED 0x1829 +#define mmDC_I2C_DDC5_HW_STATUS 0x1821 +#define mmDC_I2C_DDC5_SETUP 0x182C +#define mmDC_I2C_DDC5_SPEED 0x182B +#define mmDC_I2C_DDC6_HW_STATUS 0x1822 +#define mmDC_I2C_DDC6_SETUP 0x182E +#define mmDC_I2C_DDC6_SPEED 0x182D +#define mmDC_I2C_DDCVGA_HW_STATUS 0x1855 +#define mmDC_I2C_DDCVGA_SETUP 0x1857 +#define mmDC_I2C_DDCVGA_SPEED 0x1856 +#define mmDC_I2C_EDID_DETECT_CTRL 0x186F +#define mmDC_I2C_INTERRUPT_CONTROL 0x181B +#define mmDC_I2C_SW_STATUS 0x181C +#define mmDC_I2C_TRANSACTION0 0x182F +#define mmDC_I2C_TRANSACTION1 0x1830 +#define mmDC_I2C_TRANSACTION2 0x1831 +#define mmDC_I2C_TRANSACTION3 0x1832 +#define mmDCI_CLK_CNTL 0x031E +#define mmDCI_CLK_RAMP_CNTL 0x0324 +#define mmDCI_DEBUG_CONFIG 0x0323 +#define mmDCI_MEM_PWR_CNTL 0x0326 +#define mmDCI_MEM_PWR_STATE 0x031B +#define mmDCI_MEM_PWR_STATE2 0x0322 +#define mmDCIO_DEBUG 0x192E +#define mmDCIO_GSL0_CNTL 0x1924 +#define mmDCIO_GSL1_CNTL 0x1925 +#define mmDCIO_GSL2_CNTL 0x1926 +#define mmDCIO_GSL_GENLK_PAD_CNTL 0x1922 +#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x1923 +#define mmDCIO_IMPCAL_CNTL_AB 0x190D +#define mmDCIO_IMPCAL_CNTL_CD 0x1911 +#define mmDCIO_IMPCAL_CNTL_EF 0x1915 +#define mmDCIO_TEST_DEBUG_DATA 0x1930 +#define mmDCIO_TEST_DEBUG_INDEX 0x192F +#define mmDCIO_UNIPHY0_UNIPHY_ANG_BIST_CNTL 0x198C +#define mmDCIO_UNIPHY0_UNIPHY_CHANNEL_XBAR_CNTL 0x198E +#define mmDCIO_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION 0x198A +#define mmDCIO_UNIPHY0_UNIPHY_LINK_CNTL 0x198D +#define mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL1 0x1986 +#define mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL2 0x1987 +#define mmDCIO_UNIPHY0_UNIPHY_PLL_FBDIV 0x1985 +#define mmDCIO_UNIPHY0_UNIPHY_PLL_SS_CNTL 0x1989 +#define mmDCIO_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE 0x1988 +#define mmDCIO_UNIPHY0_UNIPHY_POWER_CONTROL 0x1984 +#define mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT 0x198B +#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL1 0x1980 +#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL2 0x1981 +#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL3 0x1982 +#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL4 0x1983 +#define mmDCIO_UNIPHY1_UNIPHY_ANG_BIST_CNTL 0x199C +#define mmDCIO_UNIPHY1_UNIPHY_CHANNEL_XBAR_CNTL 0x199E +#define mmDCIO_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION 0x199A +#define mmDCIO_UNIPHY1_UNIPHY_LINK_CNTL 0x199D +#define mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL1 0x1996 +#define mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL2 0x1997 +#define mmDCIO_UNIPHY1_UNIPHY_PLL_FBDIV 0x1995 +#define mmDCIO_UNIPHY1_UNIPHY_PLL_SS_CNTL 0x1999 +#define mmDCIO_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE 0x1998 +#define mmDCIO_UNIPHY1_UNIPHY_POWER_CONTROL 0x1994 +#define mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT 0x199B +#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL1 0x1990 +#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL2 0x1991 +#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL3 0x1992 +#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL4 0x1993 +#define mmDCIO_UNIPHY2_UNIPHY_ANG_BIST_CNTL 0x19AC +#define mmDCIO_UNIPHY2_UNIPHY_CHANNEL_XBAR_CNTL 0x19AE +#define mmDCIO_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION 0x19AA +#define mmDCIO_UNIPHY2_UNIPHY_LINK_CNTL 0x19AD +#define mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL1 0x19A6 +#define mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL2 0x19A7 +#define mmDCIO_UNIPHY2_UNIPHY_PLL_FBDIV 0x19A5 +#define mmDCIO_UNIPHY2_UNIPHY_PLL_SS_CNTL 0x19A9 +#define mmDCIO_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE 0x19A8 +#define mmDCIO_UNIPHY2_UNIPHY_POWER_CONTROL 0x19A4 +#define mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT 0x19AB +#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL1 0x19A0 +#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL2 0x19A1 +#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL3 0x19A2 +#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL4 0x19A3 +#define mmDCIO_UNIPHY3_UNIPHY_ANG_BIST_CNTL 0x19BC +#define mmDCIO_UNIPHY3_UNIPHY_CHANNEL_XBAR_CNTL 0x19BE +#define mmDCIO_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION 0x19BA +#define mmDCIO_UNIPHY3_UNIPHY_LINK_CNTL 0x19BD +#define mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL1 0x19B6 +#define mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL2 0x19B7 +#define mmDCIO_UNIPHY3_UNIPHY_PLL_FBDIV 0x19B5 +#define mmDCIO_UNIPHY3_UNIPHY_PLL_SS_CNTL 0x19B9 +#define mmDCIO_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE 0x19B8 +#define mmDCIO_UNIPHY3_UNIPHY_POWER_CONTROL 0x19B4 +#define mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT 0x19BB +#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL1 0x19B0 +#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL2 0x19B1 +#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL3 0x19B2 +#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL4 0x19B3 +#define mmDCIO_UNIPHY4_UNIPHY_ANG_BIST_CNTL 0x19CC +#define mmDCIO_UNIPHY4_UNIPHY_CHANNEL_XBAR_CNTL 0x19CE +#define mmDCIO_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION 0x19CA +#define mmDCIO_UNIPHY4_UNIPHY_LINK_CNTL 0x19CD +#define mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL1 0x19C6 +#define mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL2 0x19C7 +#define mmDCIO_UNIPHY4_UNIPHY_PLL_FBDIV 0x19C5 +#define mmDCIO_UNIPHY4_UNIPHY_PLL_SS_CNTL 0x19C9 +#define mmDCIO_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE 0x19C8 +#define mmDCIO_UNIPHY4_UNIPHY_POWER_CONTROL 0x19C4 +#define mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT 0x19CB +#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL1 0x19C0 +#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL2 0x19C1 +#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL3 0x19C2 +#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL4 0x19C3 +#define mmDCIO_UNIPHY5_UNIPHY_ANG_BIST_CNTL 0x19DC +#define mmDCIO_UNIPHY5_UNIPHY_CHANNEL_XBAR_CNTL 0x19DE +#define mmDCIO_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION 0x19DA +#define mmDCIO_UNIPHY5_UNIPHY_LINK_CNTL 0x19DD +#define mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL1 0x19D6 +#define mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL2 0x19D7 +#define mmDCIO_UNIPHY5_UNIPHY_PLL_FBDIV 0x19D5 +#define mmDCIO_UNIPHY5_UNIPHY_PLL_SS_CNTL 0x19D9 +#define mmDCIO_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE 0x19D8 +#define mmDCIO_UNIPHY5_UNIPHY_POWER_CONTROL 0x19D4 +#define mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT 0x19DB +#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL1 0x19D0 +#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL2 0x19D1 +#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL3 0x19D2 +#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL4 0x19D3 +#define mmDCI_SOFT_RESET 0x015E +#define mmDCI_TEST_DEBUG_DATA 0x0321 +#define mmDCI_TEST_DEBUG_INDEX 0x0320 +#define mmDC_LUT_30_COLOR 0x1A7C +#define mmDC_LUT_AUTOFILL 0x1A7F +#define mmDC_LUT_BLACK_OFFSET_BLUE 0x1A81 +#define mmDC_LUT_BLACK_OFFSET_GREEN 0x1A82 +#define mmDC_LUT_BLACK_OFFSET_RED 0x1A83 +#define mmDC_LUT_CONTROL 0x1A80 +#define mmDC_LUT_PWL_DATA 0x1A7B +#define mmDC_LUT_RW_INDEX 0x1A79 +#define mmDC_LUT_RW_MODE 0x1A78 +#define mmDC_LUT_SEQ_COLOR 0x1A7A +#define mmDC_LUT_VGA_ACCESS_ENABLE 0x1A7D +#define mmDC_LUT_WHITE_OFFSET_BLUE 0x1A84 +#define mmDC_LUT_WHITE_OFFSET_GREEN 0x1A85 +#define mmDC_LUT_WHITE_OFFSET_RED 0x1A86 +#define mmDC_LUT_WRITE_EN_MASK 0x1A7E +#define mmDC_MVP_LB_CONTROL 0x1ADB +#define mmDCO_CLK_CNTL 0x192B +#define mmDCO_CLK_RAMP_CNTL 0x192C +#define mmDCO_LIGHT_SLEEP_DIS 0x1907 +#define mmDCO_MEM_POWER_STATE 0x1906 +#define mmDCO_SOFT_RESET 0x0167 +#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x1A43 +#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x1A44 +#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x1A45 +#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x1A46 +#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x1A47 +#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x1A48 +#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x1A49 +#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x1A4A +#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x1A4B +#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x1A4C +#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x1A4D +#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x1A4E +#define mmDCP0_CUR_COLOR1 0x1A6C +#define mmDCP0_CUR_COLOR2 0x1A6D +#define mmDCP0_CUR_CONTROL 0x1A66 +#define mmDCP0_CUR_HOT_SPOT 0x1A6B +#define mmDCP0_CUR_POSITION 0x1A6A +#define mmDCP0_CUR_REQUEST_FILTER_CNTL 0x1A99 +#define mmDCP0_CUR_SIZE 0x1A68 +#define mmDCP0_CUR_SURFACE_ADDRESS 0x1A67 +#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x1A69 +#define mmDCP0_CUR_UPDATE 0x1A6E +#define mmDCP0_DC_LUT_30_COLOR 0x1A7C +#define mmDCP0_DC_LUT_AUTOFILL 0x1A7F +#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x1A81 +#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x1A82 +#define mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x1A83 +#define mmDCP0_DC_LUT_CONTROL 0x1A80 +#define mmDCP0_DC_LUT_PWL_DATA 0x1A7B +#define mmDCP0_DC_LUT_RW_INDEX 0x1A79 +#define mmDCP0_DC_LUT_RW_MODE 0x1A78 +#define mmDCP0_DC_LUT_SEQ_COLOR 0x1A7A +#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x1A7D +#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x1A84 +#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x1A85 +#define mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x1A86 +#define mmDCP0_DC_LUT_WRITE_EN_MASK 0x1A7E +#define mmDCP0_DCP_CRC_CONTROL 0x1A87 +#define mmDCP0_DCP_CRC_CURRENT 0x1A89 +#define mmDCP0_DCP_CRC_LAST 0x1A8B +#define mmDCP0_DCP_CRC_MASK 0x1A88 +#define mmDCP0_DCP_DEBUG 0x1A8D +#define mmDCP0_DCP_DEBUG2 0x1A98 +#define mmDCP0_DCP_FP_CONVERTED_FIELD 0x1A65 +#define mmDCP0_DCP_GSL_CONTROL 0x1A90 +#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1A91 +#define mmDCP0_DCP_RANDOM_SEEDS 0x1A61 +#define mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x1A60 +#define mmDCP0_DCP_TEST_DEBUG_DATA 0x1A96 +#define mmDCP0_DCP_TEST_DEBUG_INDEX 0x1A95 +#define mmDCP0_DEGAMMA_CONTROL 0x1A58 +#define mmDCP0_DENORM_CONTROL 0x1A50 +#define mmDCP0_GAMUT_REMAP_C11_C12 0x1A5A +#define mmDCP0_GAMUT_REMAP_C13_C14 0x1A5B +#define mmDCP0_GAMUT_REMAP_C21_C22 0x1A5C +#define mmDCP0_GAMUT_REMAP_C23_C24 0x1A5D +#define mmDCP0_GAMUT_REMAP_C31_C32 0x1A5E +#define mmDCP0_GAMUT_REMAP_C33_C34 0x1A5F +#define mmDCP0_GAMUT_REMAP_CONTROL 0x1A59 +#define mmDCP0_GRPH_COMPRESS_PITCH 0x1A1A +#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x1A19 +#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1A1B +#define mmDCP0_GRPH_CONTROL 0x1A01 +#define mmDCP0_GRPH_DFQ_CONTROL 0x1A14 +#define mmDCP0_GRPH_DFQ_STATUS 0x1A15 +#define mmDCP0_GRPH_ENABLE 0x1A00 +#define mmDCP0_GRPH_FLIP_CONTROL 0x1A12 +#define mmDCP0_GRPH_INTERRUPT_CONTROL 0x1A17 +#define mmDCP0_GRPH_INTERRUPT_STATUS 0x1A16 +#define mmDCP0_GRPH_LUT_10BIT_BYPASS 0x1A02 +#define mmDCP0_GRPH_PITCH 0x1A06 +#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x1A04 +#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1A07 +#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x1A05 +#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1A08 +#define mmDCP0_GRPH_STEREOSYNC_FLIP 0x1A97 +#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1A18 +#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x1A13 +#define mmDCP0_GRPH_SURFACE_OFFSET_X 0x1A09 +#define mmDCP0_GRPH_SURFACE_OFFSET_Y 0x1A0A +#define mmDCP0_GRPH_SWAP_CNTL 0x1A03 +#define mmDCP0_GRPH_UPDATE 0x1A11 +#define mmDCP0_GRPH_X_END 0x1A0D +#define mmDCP0_GRPH_X_START 0x1A0B +#define mmDCP0_GRPH_Y_END 0x1A0E +#define mmDCP0_GRPH_Y_START 0x1A0C +#define mmDCP0_INPUT_CSC_C11_C12 0x1A36 +#define mmDCP0_INPUT_CSC_C13_C14 0x1A37 +#define mmDCP0_INPUT_CSC_C21_C22 0x1A38 +#define mmDCP0_INPUT_CSC_C23_C24 0x1A39 +#define mmDCP0_INPUT_CSC_C31_C32 0x1A3A +#define mmDCP0_INPUT_CSC_C33_C34 0x1A3B +#define mmDCP0_INPUT_CSC_CONTROL 0x1A35 +#define mmDCP0_INPUT_GAMMA_CONTROL 0x1A10 +#define mmDCP0_KEY_CONTROL 0x1A53 +#define mmDCP0_KEY_RANGE_ALPHA 0x1A54 +#define mmDCP0_KEY_RANGE_BLUE 0x1A57 +#define mmDCP0_KEY_RANGE_GREEN 0x1A56 +#define mmDCP0_KEY_RANGE_RED 0x1A55 +#define mmDCP0_OUTPUT_CSC_C11_C12 0x1A3D +#define mmDCP0_OUTPUT_CSC_C13_C14 0x1A3E +#define mmDCP0_OUTPUT_CSC_C21_C22 0x1A3F +#define mmDCP0_OUTPUT_CSC_C23_C24 0x1A40 +#define mmDCP0_OUTPUT_CSC_C31_C32 0x1A41 +#define mmDCP0_OUTPUT_CSC_C33_C34 0x1A42 +#define mmDCP0_OUTPUT_CSC_CONTROL 0x1A3C +#define mmDCP0_OUT_ROUND_CONTROL 0x1A51 +#define mmDCP0_OVL_CONTROL1 0x1A1D +#define mmDCP0_OVL_CONTROL2 0x1A1E +#define mmDCP0_OVL_DFQ_CONTROL 0x1A29 +#define mmDCP0_OVL_DFQ_STATUS 0x1A2A +#define mmDCP0_OVL_ENABLE 0x1A1C +#define mmDCP0_OVL_END 0x1A26 +#define mmDCP0_OVL_PITCH 0x1A21 +#define mmDCP0_OVLSCL_EDGE_PIXEL_CNTL 0x1A2C +#define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS 0x1A92 +#define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1A94 +#define mmDCP0_OVL_START 0x1A25 +#define mmDCP0_OVL_STEREOSYNC_FLIP 0x1A93 +#define mmDCP0_OVL_SURFACE_ADDRESS 0x1A20 +#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH 0x1A22 +#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1A2B +#define mmDCP0_OVL_SURFACE_ADDRESS_INUSE 0x1A28 +#define mmDCP0_OVL_SURFACE_OFFSET_X 0x1A23 +#define mmDCP0_OVL_SURFACE_OFFSET_Y 0x1A24 +#define mmDCP0_OVL_SWAP_CNTL 0x1A1F +#define mmDCP0_OVL_UPDATE 0x1A27 +#define mmDCP0_PRESCALE_GRPH_CONTROL 0x1A2D +#define mmDCP0_PRESCALE_OVL_CONTROL 0x1A31 +#define mmDCP0_PRESCALE_VALUES_GRPH_B 0x1A30 +#define mmDCP0_PRESCALE_VALUES_GRPH_G 0x1A2F +#define mmDCP0_PRESCALE_VALUES_GRPH_R 0x1A2E +#define mmDCP0_PRESCALE_VALUES_OVL_CB 0x1A32 +#define mmDCP0_PRESCALE_VALUES_OVL_CR 0x1A34 +#define mmDCP0_PRESCALE_VALUES_OVL_Y 0x1A33 +#define mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x1AA6 +#define mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x1AA7 +#define mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x1AA8 +#define mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x1AAD +#define mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x1AAE +#define mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x1AAF +#define mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x1AA9 +#define mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x1AAA +#define mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x1AAB +#define mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x1AAC +#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x1AA5 +#define mmDCP0_REGAMMA_CNTLA_START_CNTL 0x1AA4 +#define mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x1AB2 +#define mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x1AB3 +#define mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x1AB4 +#define mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x1AB9 +#define mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x1ABA +#define mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x1ABB +#define mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x1AB5 +#define mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x1AB6 +#define mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x1AB7 +#define mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x1AB8 +#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x1AB1 +#define mmDCP0_REGAMMA_CNTLB_START_CNTL 0x1AB0 +#define mmDCP0_REGAMMA_CONTROL 0x1AA0 +#define mmDCP0_REGAMMA_LUT_DATA 0x1AA2 +#define mmDCP0_REGAMMA_LUT_INDEX 0x1AA1 +#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x1AA3 +#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x1D43 +#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x1D44 +#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x1D45 +#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x1D46 +#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x1D47 +#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x1D48 +#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x1D49 +#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x1D4A +#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x1D4B +#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x1D4C +#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x1D4D +#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x1D4E +#define mmDCP1_CUR_COLOR1 0x1D6C +#define mmDCP1_CUR_COLOR2 0x1D6D +#define mmDCP1_CUR_CONTROL 0x1D66 +#define mmDCP1_CUR_HOT_SPOT 0x1D6B +#define mmDCP1_CUR_POSITION 0x1D6A +#define mmDCP1_CUR_REQUEST_FILTER_CNTL 0x1D99 +#define mmDCP1_CUR_SIZE 0x1D68 +#define mmDCP1_CUR_SURFACE_ADDRESS 0x1D67 +#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x1D69 +#define mmDCP1_CUR_UPDATE 0x1D6E +#define mmDCP1_DC_LUT_30_COLOR 0x1D7C +#define mmDCP1_DC_LUT_AUTOFILL 0x1D7F +#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x1D81 +#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x1D82 +#define mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x1D83 +#define mmDCP1_DC_LUT_CONTROL 0x1D80 +#define mmDCP1_DC_LUT_PWL_DATA 0x1D7B +#define mmDCP1_DC_LUT_RW_INDEX 0x1D79 +#define mmDCP1_DC_LUT_RW_MODE 0x1D78 +#define mmDCP1_DC_LUT_SEQ_COLOR 0x1D7A +#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x1D7D +#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x1D84 +#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x1D85 +#define mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x1D86 +#define mmDCP1_DC_LUT_WRITE_EN_MASK 0x1D7E +#define mmDCP1_DCP_CRC_CONTROL 0x1D87 +#define mmDCP1_DCP_CRC_CURRENT 0x1D89 +#define mmDCP1_DCP_CRC_LAST 0x1D8B +#define mmDCP1_DCP_CRC_MASK 0x1D88 +#define mmDCP1_DCP_DEBUG 0x1D8D +#define mmDCP1_DCP_DEBUG2 0x1D98 +#define mmDCP1_DCP_FP_CONVERTED_FIELD 0x1D65 +#define mmDCP1_DCP_GSL_CONTROL 0x1D90 +#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1D91 +#define mmDCP1_DCP_RANDOM_SEEDS 0x1D61 +#define mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x1D60 +#define mmDCP1_DCP_TEST_DEBUG_DATA 0x1D96 +#define mmDCP1_DCP_TEST_DEBUG_INDEX 0x1D95 +#define mmDCP1_DEGAMMA_CONTROL 0x1D58 +#define mmDCP1_DENORM_CONTROL 0x1D50 +#define mmDCP1_GAMUT_REMAP_C11_C12 0x1D5A +#define mmDCP1_GAMUT_REMAP_C13_C14 0x1D5B +#define mmDCP1_GAMUT_REMAP_C21_C22 0x1D5C +#define mmDCP1_GAMUT_REMAP_C23_C24 0x1D5D +#define mmDCP1_GAMUT_REMAP_C31_C32 0x1D5E +#define mmDCP1_GAMUT_REMAP_C33_C34 0x1D5F +#define mmDCP1_GAMUT_REMAP_CONTROL 0x1D59 +#define mmDCP1_GRPH_COMPRESS_PITCH 0x1D1A +#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x1D19 +#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1D1B +#define mmDCP1_GRPH_CONTROL 0x1D01 +#define mmDCP1_GRPH_DFQ_CONTROL 0x1D14 +#define mmDCP1_GRPH_DFQ_STATUS 0x1D15 +#define mmDCP1_GRPH_ENABLE 0x1D00 +#define mmDCP1_GRPH_FLIP_CONTROL 0x1D12 +#define mmDCP1_GRPH_INTERRUPT_CONTROL 0x1D17 +#define mmDCP1_GRPH_INTERRUPT_STATUS 0x1D16 +#define mmDCP1_GRPH_LUT_10BIT_BYPASS 0x1D02 +#define mmDCP1_GRPH_PITCH 0x1D06 +#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x1D04 +#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1D07 +#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x1D05 +#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1D08 +#define mmDCP1_GRPH_STEREOSYNC_FLIP 0x1D97 +#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1D18 +#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x1D13 +#define mmDCP1_GRPH_SURFACE_OFFSET_X 0x1D09 +#define mmDCP1_GRPH_SURFACE_OFFSET_Y 0x1D0A +#define mmDCP1_GRPH_SWAP_CNTL 0x1D03 +#define mmDCP1_GRPH_UPDATE 0x1D11 +#define mmDCP1_GRPH_X_END 0x1D0D +#define mmDCP1_GRPH_X_START 0x1D0B +#define mmDCP1_GRPH_Y_END 0x1D0E +#define mmDCP1_GRPH_Y_START 0x1D0C +#define mmDCP1_INPUT_CSC_C11_C12 0x1D36 +#define mmDCP1_INPUT_CSC_C13_C14 0x1D37 +#define mmDCP1_INPUT_CSC_C21_C22 0x1D38 +#define mmDCP1_INPUT_CSC_C23_C24 0x1D39 +#define mmDCP1_INPUT_CSC_C31_C32 0x1D3A +#define mmDCP1_INPUT_CSC_C33_C34 0x1D3B +#define mmDCP1_INPUT_CSC_CONTROL 0x1D35 +#define mmDCP1_INPUT_GAMMA_CONTROL 0x1D10 +#define mmDCP1_KEY_CONTROL 0x1D53 +#define mmDCP1_KEY_RANGE_ALPHA 0x1D54 +#define mmDCP1_KEY_RANGE_BLUE 0x1D57 +#define mmDCP1_KEY_RANGE_GREEN 0x1D56 +#define mmDCP1_KEY_RANGE_RED 0x1D55 +#define mmDCP1_OUTPUT_CSC_C11_C12 0x1D3D +#define mmDCP1_OUTPUT_CSC_C13_C14 0x1D3E +#define mmDCP1_OUTPUT_CSC_C21_C22 0x1D3F +#define mmDCP1_OUTPUT_CSC_C23_C24 0x1D40 +#define mmDCP1_OUTPUT_CSC_C31_C32 0x1D41 +#define mmDCP1_OUTPUT_CSC_C33_C34 0x1D42 +#define mmDCP1_OUTPUT_CSC_CONTROL 0x1D3C +#define mmDCP1_OUT_ROUND_CONTROL 0x1D51 +#define mmDCP1_OVL_CONTROL1 0x1D1D +#define mmDCP1_OVL_CONTROL2 0x1D1E +#define mmDCP1_OVL_DFQ_CONTROL 0x1D29 +#define mmDCP1_OVL_DFQ_STATUS 0x1D2A +#define mmDCP1_OVL_ENABLE 0x1D1C +#define mmDCP1_OVL_END 0x1D26 +#define mmDCP1_OVL_PITCH 0x1D21 +#define mmDCP1_OVLSCL_EDGE_PIXEL_CNTL 0x1D2C +#define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS 0x1D92 +#define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1D94 +#define mmDCP1_OVL_START 0x1D25 +#define mmDCP1_OVL_STEREOSYNC_FLIP 0x1D93 +#define mmDCP1_OVL_SURFACE_ADDRESS 0x1D20 +#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH 0x1D22 +#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1D2B +#define mmDCP1_OVL_SURFACE_ADDRESS_INUSE 0x1D28 +#define mmDCP1_OVL_SURFACE_OFFSET_X 0x1D23 +#define mmDCP1_OVL_SURFACE_OFFSET_Y 0x1D24 +#define mmDCP1_OVL_SWAP_CNTL 0x1D1F +#define mmDCP1_OVL_UPDATE 0x1D27 +#define mmDCP1_PRESCALE_GRPH_CONTROL 0x1D2D +#define mmDCP1_PRESCALE_OVL_CONTROL 0x1D31 +#define mmDCP1_PRESCALE_VALUES_GRPH_B 0x1D30 +#define mmDCP1_PRESCALE_VALUES_GRPH_G 0x1D2F +#define mmDCP1_PRESCALE_VALUES_GRPH_R 0x1D2E +#define mmDCP1_PRESCALE_VALUES_OVL_CB 0x1D32 +#define mmDCP1_PRESCALE_VALUES_OVL_CR 0x1D34 +#define mmDCP1_PRESCALE_VALUES_OVL_Y 0x1D33 +#define mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x1DA6 +#define mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x1DA7 +#define mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x1DA8 +#define mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x1DAD +#define mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x1DAE +#define mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x1DAF +#define mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x1DA9 +#define mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x1DAA +#define mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x1DAB +#define mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x1DAC +#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x1DA5 +#define mmDCP1_REGAMMA_CNTLA_START_CNTL 0x1DA4 +#define mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x1DB2 +#define mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x1DB3 +#define mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x1DB4 +#define mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x1DB9 +#define mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x1DBA +#define mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x1DBB +#define mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x1DB5 +#define mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x1DB6 +#define mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x1DB7 +#define mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x1DB8 +#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x1DB1 +#define mmDCP1_REGAMMA_CNTLB_START_CNTL 0x1DB0 +#define mmDCP1_REGAMMA_CONTROL 0x1DA0 +#define mmDCP1_REGAMMA_LUT_DATA 0x1DA2 +#define mmDCP1_REGAMMA_LUT_INDEX 0x1DA1 +#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x1DA3 +#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x4043 +#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x4044 +#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x4045 +#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x4046 +#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x4047 +#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x4048 +#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x4049 +#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x404A +#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x404B +#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x404C +#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x404D +#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x404E +#define mmDCP2_CUR_COLOR1 0x406C +#define mmDCP2_CUR_COLOR2 0x406D +#define mmDCP2_CUR_CONTROL 0x4066 +#define mmDCP2_CUR_HOT_SPOT 0x406B +#define mmDCP2_CUR_POSITION 0x406A +#define mmDCP2_CUR_REQUEST_FILTER_CNTL 0x4099 +#define mmDCP2_CUR_SIZE 0x4068 +#define mmDCP2_CUR_SURFACE_ADDRESS 0x4067 +#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x4069 +#define mmDCP2_CUR_UPDATE 0x406E +#define mmDCP2_DC_LUT_30_COLOR 0x407C +#define mmDCP2_DC_LUT_AUTOFILL 0x407F +#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x4081 +#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x4082 +#define mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x4083 +#define mmDCP2_DC_LUT_CONTROL 0x4080 +#define mmDCP2_DC_LUT_PWL_DATA 0x407B +#define mmDCP2_DC_LUT_RW_INDEX 0x4079 +#define mmDCP2_DC_LUT_RW_MODE 0x4078 +#define mmDCP2_DC_LUT_SEQ_COLOR 0x407A +#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x407D +#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x4084 +#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x4085 +#define mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x4086 +#define mmDCP2_DC_LUT_WRITE_EN_MASK 0x407E +#define mmDCP2_DCP_CRC_CONTROL 0x4087 +#define mmDCP2_DCP_CRC_CURRENT 0x4089 +#define mmDCP2_DCP_CRC_LAST 0x408B +#define mmDCP2_DCP_CRC_MASK 0x4088 +#define mmDCP2_DCP_DEBUG 0x408D +#define mmDCP2_DCP_DEBUG2 0x4098 +#define mmDCP2_DCP_FP_CONVERTED_FIELD 0x4065 +#define mmDCP2_DCP_GSL_CONTROL 0x4090 +#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4091 +#define mmDCP2_DCP_RANDOM_SEEDS 0x4061 +#define mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x4060 +#define mmDCP2_DCP_TEST_DEBUG_DATA 0x4096 +#define mmDCP2_DCP_TEST_DEBUG_INDEX 0x4095 +#define mmDCP2_DEGAMMA_CONTROL 0x4058 +#define mmDCP2_DENORM_CONTROL 0x4050 +#define mmDCP2_GAMUT_REMAP_C11_C12 0x405A +#define mmDCP2_GAMUT_REMAP_C13_C14 0x405B +#define mmDCP2_GAMUT_REMAP_C21_C22 0x405C +#define mmDCP2_GAMUT_REMAP_C23_C24 0x405D +#define mmDCP2_GAMUT_REMAP_C31_C32 0x405E +#define mmDCP2_GAMUT_REMAP_C33_C34 0x405F +#define mmDCP2_GAMUT_REMAP_CONTROL 0x4059 +#define mmDCP2_GRPH_COMPRESS_PITCH 0x401A +#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x4019 +#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x401B +#define mmDCP2_GRPH_CONTROL 0x4001 +#define mmDCP2_GRPH_DFQ_CONTROL 0x4014 +#define mmDCP2_GRPH_DFQ_STATUS 0x4015 +#define mmDCP2_GRPH_ENABLE 0x4000 +#define mmDCP2_GRPH_FLIP_CONTROL 0x4012 +#define mmDCP2_GRPH_INTERRUPT_CONTROL 0x4017 +#define mmDCP2_GRPH_INTERRUPT_STATUS 0x4016 +#define mmDCP2_GRPH_LUT_10BIT_BYPASS 0x4002 +#define mmDCP2_GRPH_PITCH 0x4006 +#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x4004 +#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4007 +#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x4005 +#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4008 +#define mmDCP2_GRPH_STEREOSYNC_FLIP 0x4097 +#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4018 +#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x4013 +#define mmDCP2_GRPH_SURFACE_OFFSET_X 0x4009 +#define mmDCP2_GRPH_SURFACE_OFFSET_Y 0x400A +#define mmDCP2_GRPH_SWAP_CNTL 0x4003 +#define mmDCP2_GRPH_UPDATE 0x4011 +#define mmDCP2_GRPH_X_END 0x400D +#define mmDCP2_GRPH_X_START 0x400B +#define mmDCP2_GRPH_Y_END 0x400E +#define mmDCP2_GRPH_Y_START 0x400C +#define mmDCP2_INPUT_CSC_C11_C12 0x4036 +#define mmDCP2_INPUT_CSC_C13_C14 0x4037 +#define mmDCP2_INPUT_CSC_C21_C22 0x4038 +#define mmDCP2_INPUT_CSC_C23_C24 0x4039 +#define mmDCP2_INPUT_CSC_C31_C32 0x403A +#define mmDCP2_INPUT_CSC_C33_C34 0x403B +#define mmDCP2_INPUT_CSC_CONTROL 0x4035 +#define mmDCP2_INPUT_GAMMA_CONTROL 0x4010 +#define mmDCP2_KEY_CONTROL 0x4053 +#define mmDCP2_KEY_RANGE_ALPHA 0x4054 +#define mmDCP2_KEY_RANGE_BLUE 0x4057 +#define mmDCP2_KEY_RANGE_GREEN 0x4056 +#define mmDCP2_KEY_RANGE_RED 0x4055 +#define mmDCP2_OUTPUT_CSC_C11_C12 0x403D +#define mmDCP2_OUTPUT_CSC_C13_C14 0x403E +#define mmDCP2_OUTPUT_CSC_C21_C22 0x403F +#define mmDCP2_OUTPUT_CSC_C23_C24 0x4040 +#define mmDCP2_OUTPUT_CSC_C31_C32 0x4041 +#define mmDCP2_OUTPUT_CSC_C33_C34 0x4042 +#define mmDCP2_OUTPUT_CSC_CONTROL 0x403C +#define mmDCP2_OUT_ROUND_CONTROL 0x4051 +#define mmDCP2_OVL_CONTROL1 0x401D +#define mmDCP2_OVL_CONTROL2 0x401E +#define mmDCP2_OVL_DFQ_CONTROL 0x4029 +#define mmDCP2_OVL_DFQ_STATUS 0x402A +#define mmDCP2_OVL_ENABLE 0x401C +#define mmDCP2_OVL_END 0x4026 +#define mmDCP2_OVL_PITCH 0x4021 +#define mmDCP2_OVLSCL_EDGE_PIXEL_CNTL 0x402C +#define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS 0x4092 +#define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4094 +#define mmDCP2_OVL_START 0x4025 +#define mmDCP2_OVL_STEREOSYNC_FLIP 0x4093 +#define mmDCP2_OVL_SURFACE_ADDRESS 0x4020 +#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH 0x4022 +#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x402B +#define mmDCP2_OVL_SURFACE_ADDRESS_INUSE 0x4028 +#define mmDCP2_OVL_SURFACE_OFFSET_X 0x4023 +#define mmDCP2_OVL_SURFACE_OFFSET_Y 0x4024 +#define mmDCP2_OVL_SWAP_CNTL 0x401F +#define mmDCP2_OVL_UPDATE 0x4027 +#define mmDCP2_PRESCALE_GRPH_CONTROL 0x402D +#define mmDCP2_PRESCALE_OVL_CONTROL 0x4031 +#define mmDCP2_PRESCALE_VALUES_GRPH_B 0x4030 +#define mmDCP2_PRESCALE_VALUES_GRPH_G 0x402F +#define mmDCP2_PRESCALE_VALUES_GRPH_R 0x402E +#define mmDCP2_PRESCALE_VALUES_OVL_CB 0x4032 +#define mmDCP2_PRESCALE_VALUES_OVL_CR 0x4034 +#define mmDCP2_PRESCALE_VALUES_OVL_Y 0x4033 +#define mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x40A6 +#define mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x40A7 +#define mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x40A8 +#define mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x40AD +#define mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x40AE +#define mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x40AF +#define mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x40A9 +#define mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x40AA +#define mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x40AB +#define mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x40AC +#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x40A5 +#define mmDCP2_REGAMMA_CNTLA_START_CNTL 0x40A4 +#define mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x40B2 +#define mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x40B3 +#define mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x40B4 +#define mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x40B9 +#define mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x40BA +#define mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x40BB +#define mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x40B5 +#define mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x40B6 +#define mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x40B7 +#define mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x40B8 +#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x40B1 +#define mmDCP2_REGAMMA_CNTLB_START_CNTL 0x40B0 +#define mmDCP2_REGAMMA_CONTROL 0x40A0 +#define mmDCP2_REGAMMA_LUT_DATA 0x40A2 +#define mmDCP2_REGAMMA_LUT_INDEX 0x40A1 +#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x40A3 +#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x4343 +#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x4344 +#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x4345 +#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x4346 +#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x4347 +#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x4348 +#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x4349 +#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x434A +#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x434B +#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x434C +#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x434D +#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x434E +#define mmDCP3_CUR_COLOR1 0x436C +#define mmDCP3_CUR_COLOR2 0x436D +#define mmDCP3_CUR_CONTROL 0x4366 +#define mmDCP3_CUR_HOT_SPOT 0x436B +#define mmDCP3_CUR_POSITION 0x436A +#define mmDCP3_CUR_REQUEST_FILTER_CNTL 0x4399 +#define mmDCP3_CUR_SIZE 0x4368 +#define mmDCP3_CUR_SURFACE_ADDRESS 0x4367 +#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x4369 +#define mmDCP3_CUR_UPDATE 0x436E +#define mmDCP3_DC_LUT_30_COLOR 0x437C +#define mmDCP3_DC_LUT_AUTOFILL 0x437F +#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x4381 +#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x4382 +#define mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x4383 +#define mmDCP3_DC_LUT_CONTROL 0x4380 +#define mmDCP3_DC_LUT_PWL_DATA 0x437B +#define mmDCP3_DC_LUT_RW_INDEX 0x4379 +#define mmDCP3_DC_LUT_RW_MODE 0x4378 +#define mmDCP3_DC_LUT_SEQ_COLOR 0x437A +#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x437D +#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x4384 +#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x4385 +#define mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x4386 +#define mmDCP3_DC_LUT_WRITE_EN_MASK 0x437E +#define mmDCP3_DCP_CRC_CONTROL 0x4387 +#define mmDCP3_DCP_CRC_CURRENT 0x4389 +#define mmDCP3_DCP_CRC_LAST 0x438B +#define mmDCP3_DCP_CRC_MASK 0x4388 +#define mmDCP3_DCP_DEBUG 0x438D +#define mmDCP3_DCP_DEBUG2 0x4398 +#define mmDCP3_DCP_FP_CONVERTED_FIELD 0x4365 +#define mmDCP3_DCP_GSL_CONTROL 0x4390 +#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4391 +#define mmDCP3_DCP_RANDOM_SEEDS 0x4361 +#define mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x4360 +#define mmDCP3_DCP_TEST_DEBUG_DATA 0x4396 +#define mmDCP3_DCP_TEST_DEBUG_INDEX 0x4395 +#define mmDCP3_DEGAMMA_CONTROL 0x4358 +#define mmDCP3_DENORM_CONTROL 0x4350 +#define mmDCP3_GAMUT_REMAP_C11_C12 0x435A +#define mmDCP3_GAMUT_REMAP_C13_C14 0x435B +#define mmDCP3_GAMUT_REMAP_C21_C22 0x435C +#define mmDCP3_GAMUT_REMAP_C23_C24 0x435D +#define mmDCP3_GAMUT_REMAP_C31_C32 0x435E +#define mmDCP3_GAMUT_REMAP_C33_C34 0x435F +#define mmDCP3_GAMUT_REMAP_CONTROL 0x4359 +#define mmDCP3_GRPH_COMPRESS_PITCH 0x431A +#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x4319 +#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x431B +#define mmDCP3_GRPH_CONTROL 0x4301 +#define mmDCP3_GRPH_DFQ_CONTROL 0x4314 +#define mmDCP3_GRPH_DFQ_STATUS 0x4315 +#define mmDCP3_GRPH_ENABLE 0x4300 +#define mmDCP3_GRPH_FLIP_CONTROL 0x4312 +#define mmDCP3_GRPH_INTERRUPT_CONTROL 0x4317 +#define mmDCP3_GRPH_INTERRUPT_STATUS 0x4316 +#define mmDCP3_GRPH_LUT_10BIT_BYPASS 0x4302 +#define mmDCP3_GRPH_PITCH 0x4306 +#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x4304 +#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4307 +#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x4305 +#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4308 +#define mmDCP3_GRPH_STEREOSYNC_FLIP 0x4397 +#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4318 +#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x4313 +#define mmDCP3_GRPH_SURFACE_OFFSET_X 0x4309 +#define mmDCP3_GRPH_SURFACE_OFFSET_Y 0x430A +#define mmDCP3_GRPH_SWAP_CNTL 0x4303 +#define mmDCP3_GRPH_UPDATE 0x4311 +#define mmDCP3_GRPH_X_END 0x430D +#define mmDCP3_GRPH_X_START 0x430B +#define mmDCP3_GRPH_Y_END 0x430E +#define mmDCP3_GRPH_Y_START 0x430C +#define mmDCP3_INPUT_CSC_C11_C12 0x4336 +#define mmDCP3_INPUT_CSC_C13_C14 0x4337 +#define mmDCP3_INPUT_CSC_C21_C22 0x4338 +#define mmDCP3_INPUT_CSC_C23_C24 0x4339 +#define mmDCP3_INPUT_CSC_C31_C32 0x433A +#define mmDCP3_INPUT_CSC_C33_C34 0x433B +#define mmDCP3_INPUT_CSC_CONTROL 0x4335 +#define mmDCP3_INPUT_GAMMA_CONTROL 0x4310 +#define mmDCP3_KEY_CONTROL 0x4353 +#define mmDCP3_KEY_RANGE_ALPHA 0x4354 +#define mmDCP3_KEY_RANGE_BLUE 0x4357 +#define mmDCP3_KEY_RANGE_GREEN 0x4356 +#define mmDCP3_KEY_RANGE_RED 0x4355 +#define mmDCP3_OUTPUT_CSC_C11_C12 0x433D +#define mmDCP3_OUTPUT_CSC_C13_C14 0x433E +#define mmDCP3_OUTPUT_CSC_C21_C22 0x433F +#define mmDCP3_OUTPUT_CSC_C23_C24 0x4340 +#define mmDCP3_OUTPUT_CSC_C31_C32 0x4341 +#define mmDCP3_OUTPUT_CSC_C33_C34 0x4342 +#define mmDCP3_OUTPUT_CSC_CONTROL 0x433C +#define mmDCP3_OUT_ROUND_CONTROL 0x4351 +#define mmDCP3_OVL_CONTROL1 0x431D +#define mmDCP3_OVL_CONTROL2 0x431E +#define mmDCP3_OVL_DFQ_CONTROL 0x4329 +#define mmDCP3_OVL_DFQ_STATUS 0x432A +#define mmDCP3_OVL_ENABLE 0x431C +#define mmDCP3_OVL_END 0x4326 +#define mmDCP3_OVL_PITCH 0x4321 +#define mmDCP3_OVLSCL_EDGE_PIXEL_CNTL 0x432C +#define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS 0x4392 +#define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4394 +#define mmDCP3_OVL_START 0x4325 +#define mmDCP3_OVL_STEREOSYNC_FLIP 0x4393 +#define mmDCP3_OVL_SURFACE_ADDRESS 0x4320 +#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH 0x4322 +#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x432B +#define mmDCP3_OVL_SURFACE_ADDRESS_INUSE 0x4328 +#define mmDCP3_OVL_SURFACE_OFFSET_X 0x4323 +#define mmDCP3_OVL_SURFACE_OFFSET_Y 0x4324 +#define mmDCP3_OVL_SWAP_CNTL 0x431F +#define mmDCP3_OVL_UPDATE 0x4327 +#define mmDCP3_PRESCALE_GRPH_CONTROL 0x432D +#define mmDCP3_PRESCALE_OVL_CONTROL 0x4331 +#define mmDCP3_PRESCALE_VALUES_GRPH_B 0x4330 +#define mmDCP3_PRESCALE_VALUES_GRPH_G 0x432F +#define mmDCP3_PRESCALE_VALUES_GRPH_R 0x432E +#define mmDCP3_PRESCALE_VALUES_OVL_CB 0x4332 +#define mmDCP3_PRESCALE_VALUES_OVL_CR 0x4334 +#define mmDCP3_PRESCALE_VALUES_OVL_Y 0x4333 +#define mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x43A6 +#define mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x43A7 +#define mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x43A8 +#define mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x43AD +#define mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x43AE +#define mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x43AF +#define mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x43A9 +#define mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x43AA +#define mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x43AB +#define mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x43AC +#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x43A5 +#define mmDCP3_REGAMMA_CNTLA_START_CNTL 0x43A4 +#define mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x43B2 +#define mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x43B3 +#define mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x43B4 +#define mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x43B9 +#define mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x43BA +#define mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x43BB +#define mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x43B5 +#define mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x43B6 +#define mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x43B7 +#define mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x43B8 +#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x43B1 +#define mmDCP3_REGAMMA_CNTLB_START_CNTL 0x43B0 +#define mmDCP3_REGAMMA_CONTROL 0x43A0 +#define mmDCP3_REGAMMA_LUT_DATA 0x43A2 +#define mmDCP3_REGAMMA_LUT_INDEX 0x43A1 +#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x43A3 +#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x4643 +#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x4644 +#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x4645 +#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x4646 +#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x4647 +#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x4648 +#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x4649 +#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x464A +#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x464B +#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x464C +#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x464D +#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x464E +#define mmDCP4_CUR_COLOR1 0x466C +#define mmDCP4_CUR_COLOR2 0x466D +#define mmDCP4_CUR_CONTROL 0x4666 +#define mmDCP4_CUR_HOT_SPOT 0x466B +#define mmDCP4_CUR_POSITION 0x466A +#define mmDCP4_CUR_REQUEST_FILTER_CNTL 0x4699 +#define mmDCP4_CUR_SIZE 0x4668 +#define mmDCP4_CUR_SURFACE_ADDRESS 0x4667 +#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x4669 +#define mmDCP4_CUR_UPDATE 0x466E +#define mmDCP4_DC_LUT_30_COLOR 0x467C +#define mmDCP4_DC_LUT_AUTOFILL 0x467F +#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x4681 +#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x4682 +#define mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x4683 +#define mmDCP4_DC_LUT_CONTROL 0x4680 +#define mmDCP4_DC_LUT_PWL_DATA 0x467B +#define mmDCP4_DC_LUT_RW_INDEX 0x4679 +#define mmDCP4_DC_LUT_RW_MODE 0x4678 +#define mmDCP4_DC_LUT_SEQ_COLOR 0x467A +#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x467D +#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x4684 +#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x4685 +#define mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x4686 +#define mmDCP4_DC_LUT_WRITE_EN_MASK 0x467E +#define mmDCP4_DCP_CRC_CONTROL 0x4687 +#define mmDCP4_DCP_CRC_CURRENT 0x4689 +#define mmDCP4_DCP_CRC_LAST 0x468B +#define mmDCP4_DCP_CRC_MASK 0x4688 +#define mmDCP4_DCP_DEBUG 0x468D +#define mmDCP4_DCP_DEBUG2 0x4698 +#define mmDCP4_DCP_FP_CONVERTED_FIELD 0x4665 +#define mmDCP4_DCP_GSL_CONTROL 0x4690 +#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4691 +#define mmDCP4_DCP_RANDOM_SEEDS 0x4661 +#define mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x4660 +#define mmDCP4_DCP_TEST_DEBUG_DATA 0x4696 +#define mmDCP4_DCP_TEST_DEBUG_INDEX 0x4695 +#define mmDCP4_DEGAMMA_CONTROL 0x4658 +#define mmDCP4_DENORM_CONTROL 0x4650 +#define mmDCP4_GAMUT_REMAP_C11_C12 0x465A +#define mmDCP4_GAMUT_REMAP_C13_C14 0x465B +#define mmDCP4_GAMUT_REMAP_C21_C22 0x465C +#define mmDCP4_GAMUT_REMAP_C23_C24 0x465D +#define mmDCP4_GAMUT_REMAP_C31_C32 0x465E +#define mmDCP4_GAMUT_REMAP_C33_C34 0x465F +#define mmDCP4_GAMUT_REMAP_CONTROL 0x4659 +#define mmDCP4_GRPH_COMPRESS_PITCH 0x461A +#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x4619 +#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x461B +#define mmDCP4_GRPH_CONTROL 0x4601 +#define mmDCP4_GRPH_DFQ_CONTROL 0x4614 +#define mmDCP4_GRPH_DFQ_STATUS 0x4615 +#define mmDCP4_GRPH_ENABLE 0x4600 +#define mmDCP4_GRPH_FLIP_CONTROL 0x4612 +#define mmDCP4_GRPH_INTERRUPT_CONTROL 0x4617 +#define mmDCP4_GRPH_INTERRUPT_STATUS 0x4616 +#define mmDCP4_GRPH_LUT_10BIT_BYPASS 0x4602 +#define mmDCP4_GRPH_PITCH 0x4606 +#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x4604 +#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4607 +#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x4605 +#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4608 +#define mmDCP4_GRPH_STEREOSYNC_FLIP 0x4697 +#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4618 +#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x4613 +#define mmDCP4_GRPH_SURFACE_OFFSET_X 0x4609 +#define mmDCP4_GRPH_SURFACE_OFFSET_Y 0x460A +#define mmDCP4_GRPH_SWAP_CNTL 0x4603 +#define mmDCP4_GRPH_UPDATE 0x4611 +#define mmDCP4_GRPH_X_END 0x460D +#define mmDCP4_GRPH_X_START 0x460B +#define mmDCP4_GRPH_Y_END 0x460E +#define mmDCP4_GRPH_Y_START 0x460C +#define mmDCP4_INPUT_CSC_C11_C12 0x4636 +#define mmDCP4_INPUT_CSC_C13_C14 0x4637 +#define mmDCP4_INPUT_CSC_C21_C22 0x4638 +#define mmDCP4_INPUT_CSC_C23_C24 0x4639 +#define mmDCP4_INPUT_CSC_C31_C32 0x463A +#define mmDCP4_INPUT_CSC_C33_C34 0x463B +#define mmDCP4_INPUT_CSC_CONTROL 0x4635 +#define mmDCP4_INPUT_GAMMA_CONTROL 0x4610 +#define mmDCP4_KEY_CONTROL 0x4653 +#define mmDCP4_KEY_RANGE_ALPHA 0x4654 +#define mmDCP4_KEY_RANGE_BLUE 0x4657 +#define mmDCP4_KEY_RANGE_GREEN 0x4656 +#define mmDCP4_KEY_RANGE_RED 0x4655 +#define mmDCP4_OUTPUT_CSC_C11_C12 0x463D +#define mmDCP4_OUTPUT_CSC_C13_C14 0x463E +#define mmDCP4_OUTPUT_CSC_C21_C22 0x463F +#define mmDCP4_OUTPUT_CSC_C23_C24 0x4640 +#define mmDCP4_OUTPUT_CSC_C31_C32 0x4641 +#define mmDCP4_OUTPUT_CSC_C33_C34 0x4642 +#define mmDCP4_OUTPUT_CSC_CONTROL 0x463C +#define mmDCP4_OUT_ROUND_CONTROL 0x4651 +#define mmDCP4_OVL_CONTROL1 0x461D +#define mmDCP4_OVL_CONTROL2 0x461E +#define mmDCP4_OVL_DFQ_CONTROL 0x4629 +#define mmDCP4_OVL_DFQ_STATUS 0x462A +#define mmDCP4_OVL_ENABLE 0x461C +#define mmDCP4_OVL_END 0x4626 +#define mmDCP4_OVL_PITCH 0x4621 +#define mmDCP4_OVLSCL_EDGE_PIXEL_CNTL 0x462C +#define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS 0x4692 +#define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4694 +#define mmDCP4_OVL_START 0x4625 +#define mmDCP4_OVL_STEREOSYNC_FLIP 0x4693 +#define mmDCP4_OVL_SURFACE_ADDRESS 0x4620 +#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH 0x4622 +#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x462B +#define mmDCP4_OVL_SURFACE_ADDRESS_INUSE 0x4628 +#define mmDCP4_OVL_SURFACE_OFFSET_X 0x4623 +#define mmDCP4_OVL_SURFACE_OFFSET_Y 0x4624 +#define mmDCP4_OVL_SWAP_CNTL 0x461F +#define mmDCP4_OVL_UPDATE 0x4627 +#define mmDCP4_PRESCALE_GRPH_CONTROL 0x462D +#define mmDCP4_PRESCALE_OVL_CONTROL 0x4631 +#define mmDCP4_PRESCALE_VALUES_GRPH_B 0x4630 +#define mmDCP4_PRESCALE_VALUES_GRPH_G 0x462F +#define mmDCP4_PRESCALE_VALUES_GRPH_R 0x462E +#define mmDCP4_PRESCALE_VALUES_OVL_CB 0x4632 +#define mmDCP4_PRESCALE_VALUES_OVL_CR 0x4634 +#define mmDCP4_PRESCALE_VALUES_OVL_Y 0x4633 +#define mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x46A6 +#define mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x46A7 +#define mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x46A8 +#define mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x46AD +#define mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x46AE +#define mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x46AF +#define mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x46A9 +#define mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x46AA +#define mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x46AB +#define mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x46AC +#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x46A5 +#define mmDCP4_REGAMMA_CNTLA_START_CNTL 0x46A4 +#define mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x46B2 +#define mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x46B3 +#define mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x46B4 +#define mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x46B9 +#define mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x46BA +#define mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x46BB +#define mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x46B5 +#define mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x46B6 +#define mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x46B7 +#define mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x46B8 +#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x46B1 +#define mmDCP4_REGAMMA_CNTLB_START_CNTL 0x46B0 +#define mmDCP4_REGAMMA_CONTROL 0x46A0 +#define mmDCP4_REGAMMA_LUT_DATA 0x46A2 +#define mmDCP4_REGAMMA_LUT_INDEX 0x46A1 +#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x46A3 +#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x4943 +#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x4944 +#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x4945 +#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x4946 +#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x4947 +#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x4948 +#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x4949 +#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x494A +#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x494B +#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x494C +#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x494D +#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x494E +#define mmDCP5_CUR_COLOR1 0x496C +#define mmDCP5_CUR_COLOR2 0x496D +#define mmDCP5_CUR_CONTROL 0x4966 +#define mmDCP5_CUR_HOT_SPOT 0x496B +#define mmDCP5_CUR_POSITION 0x496A +#define mmDCP5_CUR_REQUEST_FILTER_CNTL 0x4999 +#define mmDCP5_CUR_SIZE 0x4968 +#define mmDCP5_CUR_SURFACE_ADDRESS 0x4967 +#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x4969 +#define mmDCP5_CUR_UPDATE 0x496E +#define mmDCP5_DC_LUT_30_COLOR 0x497C +#define mmDCP5_DC_LUT_AUTOFILL 0x497F +#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x4981 +#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x4982 +#define mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x4983 +#define mmDCP5_DC_LUT_CONTROL 0x4980 +#define mmDCP5_DC_LUT_PWL_DATA 0x497B +#define mmDCP5_DC_LUT_RW_INDEX 0x4979 +#define mmDCP5_DC_LUT_RW_MODE 0x4978 +#define mmDCP5_DC_LUT_SEQ_COLOR 0x497A +#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x497D +#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x4984 +#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x4985 +#define mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x4986 +#define mmDCP5_DC_LUT_WRITE_EN_MASK 0x497E +#define mmDCP5_DCP_CRC_CONTROL 0x4987 +#define mmDCP5_DCP_CRC_CURRENT 0x4989 +#define mmDCP5_DCP_CRC_LAST 0x498B +#define mmDCP5_DCP_CRC_MASK 0x4988 +#define mmDCP5_DCP_DEBUG 0x498D +#define mmDCP5_DCP_DEBUG2 0x4998 +#define mmDCP5_DCP_FP_CONVERTED_FIELD 0x4965 +#define mmDCP5_DCP_GSL_CONTROL 0x4990 +#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4991 +#define mmDCP5_DCP_RANDOM_SEEDS 0x4961 +#define mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x4960 +#define mmDCP5_DCP_TEST_DEBUG_DATA 0x4996 +#define mmDCP5_DCP_TEST_DEBUG_INDEX 0x4995 +#define mmDCP5_DEGAMMA_CONTROL 0x4958 +#define mmDCP5_DENORM_CONTROL 0x4950 +#define mmDCP5_GAMUT_REMAP_C11_C12 0x495A +#define mmDCP5_GAMUT_REMAP_C13_C14 0x495B +#define mmDCP5_GAMUT_REMAP_C21_C22 0x495C +#define mmDCP5_GAMUT_REMAP_C23_C24 0x495D +#define mmDCP5_GAMUT_REMAP_C31_C32 0x495E +#define mmDCP5_GAMUT_REMAP_C33_C34 0x495F +#define mmDCP5_GAMUT_REMAP_CONTROL 0x4959 +#define mmDCP5_GRPH_COMPRESS_PITCH 0x491A +#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x4919 +#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x491B +#define mmDCP5_GRPH_CONTROL 0x4901 +#define mmDCP5_GRPH_DFQ_CONTROL 0x4914 +#define mmDCP5_GRPH_DFQ_STATUS 0x4915 +#define mmDCP5_GRPH_ENABLE 0x4900 +#define mmDCP5_GRPH_FLIP_CONTROL 0x4912 +#define mmDCP5_GRPH_INTERRUPT_CONTROL 0x4917 +#define mmDCP5_GRPH_INTERRUPT_STATUS 0x4916 +#define mmDCP5_GRPH_LUT_10BIT_BYPASS 0x4902 +#define mmDCP5_GRPH_PITCH 0x4906 +#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x4904 +#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4907 +#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x4905 +#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4908 +#define mmDCP5_GRPH_STEREOSYNC_FLIP 0x4997 +#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4918 +#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x4913 +#define mmDCP5_GRPH_SURFACE_OFFSET_X 0x4909 +#define mmDCP5_GRPH_SURFACE_OFFSET_Y 0x490A +#define mmDCP5_GRPH_SWAP_CNTL 0x4903 +#define mmDCP5_GRPH_UPDATE 0x4911 +#define mmDCP5_GRPH_X_END 0x490D +#define mmDCP5_GRPH_X_START 0x490B +#define mmDCP5_GRPH_Y_END 0x490E +#define mmDCP5_GRPH_Y_START 0x490C +#define mmDCP5_INPUT_CSC_C11_C12 0x4936 +#define mmDCP5_INPUT_CSC_C13_C14 0x4937 +#define mmDCP5_INPUT_CSC_C21_C22 0x4938 +#define mmDCP5_INPUT_CSC_C23_C24 0x4939 +#define mmDCP5_INPUT_CSC_C31_C32 0x493A +#define mmDCP5_INPUT_CSC_C33_C34 0x493B +#define mmDCP5_INPUT_CSC_CONTROL 0x4935 +#define mmDCP5_INPUT_GAMMA_CONTROL 0x4910 +#define mmDCP5_KEY_CONTROL 0x4953 +#define mmDCP5_KEY_RANGE_ALPHA 0x4954 +#define mmDCP5_KEY_RANGE_BLUE 0x4957 +#define mmDCP5_KEY_RANGE_GREEN 0x4956 +#define mmDCP5_KEY_RANGE_RED 0x4955 +#define mmDCP5_OUTPUT_CSC_C11_C12 0x493D +#define mmDCP5_OUTPUT_CSC_C13_C14 0x493E +#define mmDCP5_OUTPUT_CSC_C21_C22 0x493F +#define mmDCP5_OUTPUT_CSC_C23_C24 0x4940 +#define mmDCP5_OUTPUT_CSC_C31_C32 0x4941 +#define mmDCP5_OUTPUT_CSC_C33_C34 0x4942 +#define mmDCP5_OUTPUT_CSC_CONTROL 0x493C +#define mmDCP5_OUT_ROUND_CONTROL 0x4951 +#define mmDCP5_OVL_CONTROL1 0x491D +#define mmDCP5_OVL_CONTROL2 0x491E +#define mmDCP5_OVL_DFQ_CONTROL 0x4929 +#define mmDCP5_OVL_DFQ_STATUS 0x492A +#define mmDCP5_OVL_ENABLE 0x491C +#define mmDCP5_OVL_END 0x4926 +#define mmDCP5_OVL_PITCH 0x4921 +#define mmDCP5_OVLSCL_EDGE_PIXEL_CNTL 0x492C +#define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS 0x4992 +#define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4994 +#define mmDCP5_OVL_START 0x4925 +#define mmDCP5_OVL_STEREOSYNC_FLIP 0x4993 +#define mmDCP5_OVL_SURFACE_ADDRESS 0x4920 +#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH 0x4922 +#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x492B +#define mmDCP5_OVL_SURFACE_ADDRESS_INUSE 0x4928 +#define mmDCP5_OVL_SURFACE_OFFSET_X 0x4923 +#define mmDCP5_OVL_SURFACE_OFFSET_Y 0x4924 +#define mmDCP5_OVL_SWAP_CNTL 0x491F +#define mmDCP5_OVL_UPDATE 0x4927 +#define mmDCP5_PRESCALE_GRPH_CONTROL 0x492D +#define mmDCP5_PRESCALE_OVL_CONTROL 0x4931 +#define mmDCP5_PRESCALE_VALUES_GRPH_B 0x4930 +#define mmDCP5_PRESCALE_VALUES_GRPH_G 0x492F +#define mmDCP5_PRESCALE_VALUES_GRPH_R 0x492E +#define mmDCP5_PRESCALE_VALUES_OVL_CB 0x4932 +#define mmDCP5_PRESCALE_VALUES_OVL_CR 0x4934 +#define mmDCP5_PRESCALE_VALUES_OVL_Y 0x4933 +#define mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x49A6 +#define mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x49A7 +#define mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x49A8 +#define mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x49AD +#define mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x49AE +#define mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x49AF +#define mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x49A9 +#define mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x49AA +#define mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x49AB +#define mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x49AC +#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x49A5 +#define mmDCP5_REGAMMA_CNTLA_START_CNTL 0x49A4 +#define mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x49B2 +#define mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x49B3 +#define mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x49B4 +#define mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x49B9 +#define mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x49BA +#define mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x49BB +#define mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x49B5 +#define mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x49B6 +#define mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x49B7 +#define mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x49B8 +#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x49B1 +#define mmDCP5_REGAMMA_CNTLB_START_CNTL 0x49B0 +#define mmDCP5_REGAMMA_CONTROL 0x49A0 +#define mmDCP5_REGAMMA_LUT_DATA 0x49A2 +#define mmDCP5_REGAMMA_LUT_INDEX 0x49A1 +#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x49A3 +#define mmDC_PAD_EXTERN_SIG 0x1902 +#define mmDCP_CRC_CONTROL 0x1A87 +#define mmDCP_CRC_CURRENT 0x1A89 +#define mmDCP_CRC_LAST 0x1A8B +#define mmDCP_CRC_MASK 0x1A88 +#define mmDCP_DEBUG 0x1A8D +#define mmDCP_DEBUG2 0x1A98 +#define mmDCP_FP_CONVERTED_FIELD 0x1A65 +#define mmDC_PGCNTL_STATUS_REG 0x177E +#define mmDC_PGFSM_CONFIG_REG 0x177C +#define mmDC_PGFSM_WRITE_REG 0x177D +#define mmDCP_GSL_CONTROL 0x1A90 +#define mmDCPG_TEST_DEBUG_DATA 0x177B +#define mmDCPG_TEST_DEBUG_INDEX 0x1779 +#define mmDC_PINSTRAPS 0x1917 +#define mmDCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1A91 +#define mmDCP_RANDOM_SEEDS 0x1A61 +#define mmDCP_SPATIAL_DITHER_CNTL 0x1A60 +#define mmDCP_TEST_DEBUG_DATA 0x1A96 +#define mmDCP_TEST_DEBUG_INDEX 0x1A95 +#define mmDC_RBBMIF_RDWR_CNTL1 0x031A +#define mmDC_RBBMIF_RDWR_CNTL2 0x031D +#define mmDC_REF_CLK_CNTL 0x1903 +#define mmDC_XDMA_INTERFACE_CNTL 0x0327 +#define mmDEGAMMA_CONTROL 0x1A58 +#define mmDENORM_CONTROL 0x1A50 +#define mmDENTIST_DISPCLK_CNTL 0x0124 +#define mmDIG0_AFMT_60958_0 0x1C41 +#define mmDIG0_AFMT_60958_1 0x1C42 +#define mmDIG0_AFMT_60958_2 0x1C48 +#define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x1C43 +#define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x1C49 +#define mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL 0x1C52 +#define mmDIG0_AFMT_AUDIO_INFO0 0x1C3F +#define mmDIG0_AFMT_AUDIO_INFO1 0x1C40 +#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x1C4B +#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x1C17 +#define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x1C4F +#define mmDIG0_AFMT_AVI_INFO0 0x1C21 +#define mmDIG0_AFMT_AVI_INFO1 0x1C22 +#define mmDIG0_AFMT_AVI_INFO2 0x1C23 +#define mmDIG0_AFMT_AVI_INFO3 0x1C24 +#define mmDIG0_AFMT_GENERIC_0 0x1C28 +#define mmDIG0_AFMT_GENERIC_1 0x1C29 +#define mmDIG0_AFMT_GENERIC_2 0x1C2A +#define mmDIG0_AFMT_GENERIC_3 0x1C2B +#define mmDIG0_AFMT_GENERIC_4 0x1C2C +#define mmDIG0_AFMT_GENERIC_5 0x1C2D +#define mmDIG0_AFMT_GENERIC_6 0x1C2E +#define mmDIG0_AFMT_GENERIC_7 0x1C2F +#define mmDIG0_AFMT_GENERIC_HDR 0x1C27 +#define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x1C4D +#define mmDIG0_AFMT_INTERRUPT_STATUS 0x1C14 +#define mmDIG0_AFMT_ISRC1_0 0x1C18 +#define mmDIG0_AFMT_ISRC1_1 0x1C19 +#define mmDIG0_AFMT_ISRC1_2 0x1C1A +#define mmDIG0_AFMT_ISRC1_3 0x1C1B +#define mmDIG0_AFMT_ISRC1_4 0x1C1C +#define mmDIG0_AFMT_ISRC2_0 0x1C1D +#define mmDIG0_AFMT_ISRC2_1 0x1C1E +#define mmDIG0_AFMT_ISRC2_2 0x1C1F +#define mmDIG0_AFMT_ISRC2_3 0x1C20 +#define mmDIG0_AFMT_MPEG_INFO0 0x1C25 +#define mmDIG0_AFMT_MPEG_INFO1 0x1C26 +#define mmDIG0_AFMT_RAMP_CONTROL0 0x1C44 +#define mmDIG0_AFMT_RAMP_CONTROL1 0x1C45 +#define mmDIG0_AFMT_RAMP_CONTROL2 0x1C46 +#define mmDIG0_AFMT_RAMP_CONTROL3 0x1C47 +#define mmDIG0_AFMT_STATUS 0x1C4A +#define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x1C4C +#define mmDIG0_DIG_BE_CNTL 0x1C50 +#define mmDIG0_DIG_BE_EN_CNTL 0x1C51 +#define mmDIG0_DIG_CLOCK_PATTERN 0x1C03 +#define mmDIG0_DIG_DISPCLK_SWITCH_CNTL 0x1C08 +#define mmDIG0_DIG_DISPCLK_SWITCH_STATUS 0x1C09 +#define mmDIG0_DIG_FE_CNTL 0x1C00 +#define mmDIG0_DIG_FIFO_STATUS 0x1C0A +#define mmDIG0_DIG_LANE_ENABLE 0x1C8D +#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x1C01 +#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x1C02 +#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x1C05 +#define mmDIG0_DIG_TEST_PATTERN 0x1C04 +#define mmDIG0_HDMI_ACR_32_0 0x1C37 +#define mmDIG0_HDMI_ACR_32_1 0x1C38 +#define mmDIG0_HDMI_ACR_44_0 0x1C39 +#define mmDIG0_HDMI_ACR_44_1 0x1C3A +#define mmDIG0_HDMI_ACR_48_0 0x1C3B +#define mmDIG0_HDMI_ACR_48_1 0x1C3C +#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x1C0F +#define mmDIG0_HDMI_ACR_STATUS_0 0x1C3D +#define mmDIG0_HDMI_ACR_STATUS_1 0x1C3E +#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x1C0E +#define mmDIG0_HDMI_CONTROL 0x1C0C +#define mmDIG0_HDMI_GC 0x1C16 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x1C13 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x1C30 +#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x1C11 +#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x1C12 +#define mmDIG0_HDMI_STATUS 0x1C0D +#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x1C10 +#define mmDIG0_LVDS_DATA_CNTL 0x1C8C +#define mmDIG0_TMDS_CNTL 0x1C7C +#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x1C7E +#define mmDIG0_TMDS_CONTROL_CHAR 0x1C7D +#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x1C86 +#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x1C87 +#define mmDIG0_TMDS_CTL_BITS 0x1C83 +#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x1C84 +#define mmDIG0_TMDS_DEBUG 0x1C82 +#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x1C7F +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x1C80 +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x1C81 +#define mmDIG1_AFMT_60958_0 0x1F41 +#define mmDIG1_AFMT_60958_1 0x1F42 +#define mmDIG1_AFMT_60958_2 0x1F48 +#define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x1F43 +#define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x1F49 +#define mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL 0x1F52 +#define mmDIG1_AFMT_AUDIO_INFO0 0x1F3F +#define mmDIG1_AFMT_AUDIO_INFO1 0x1F40 +#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x1F4B +#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x1F17 +#define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x1F4F +#define mmDIG1_AFMT_AVI_INFO0 0x1F21 +#define mmDIG1_AFMT_AVI_INFO1 0x1F22 +#define mmDIG1_AFMT_AVI_INFO2 0x1F23 +#define mmDIG1_AFMT_AVI_INFO3 0x1F24 +#define mmDIG1_AFMT_GENERIC_0 0x1F28 +#define mmDIG1_AFMT_GENERIC_1 0x1F29 +#define mmDIG1_AFMT_GENERIC_2 0x1F2A +#define mmDIG1_AFMT_GENERIC_3 0x1F2B +#define mmDIG1_AFMT_GENERIC_4 0x1F2C +#define mmDIG1_AFMT_GENERIC_5 0x1F2D +#define mmDIG1_AFMT_GENERIC_6 0x1F2E +#define mmDIG1_AFMT_GENERIC_7 0x1F2F +#define mmDIG1_AFMT_GENERIC_HDR 0x1F27 +#define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x1F4D +#define mmDIG1_AFMT_INTERRUPT_STATUS 0x1F14 +#define mmDIG1_AFMT_ISRC1_0 0x1F18 +#define mmDIG1_AFMT_ISRC1_1 0x1F19 +#define mmDIG1_AFMT_ISRC1_2 0x1F1A +#define mmDIG1_AFMT_ISRC1_3 0x1F1B +#define mmDIG1_AFMT_ISRC1_4 0x1F1C +#define mmDIG1_AFMT_ISRC2_0 0x1F1D +#define mmDIG1_AFMT_ISRC2_1 0x1F1E +#define mmDIG1_AFMT_ISRC2_2 0x1F1F +#define mmDIG1_AFMT_ISRC2_3 0x1F20 +#define mmDIG1_AFMT_MPEG_INFO0 0x1F25 +#define mmDIG1_AFMT_MPEG_INFO1 0x1F26 +#define mmDIG1_AFMT_RAMP_CONTROL0 0x1F44 +#define mmDIG1_AFMT_RAMP_CONTROL1 0x1F45 +#define mmDIG1_AFMT_RAMP_CONTROL2 0x1F46 +#define mmDIG1_AFMT_RAMP_CONTROL3 0x1F47 +#define mmDIG1_AFMT_STATUS 0x1F4A +#define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x1F4C +#define mmDIG1_DIG_BE_CNTL 0x1F50 +#define mmDIG1_DIG_BE_EN_CNTL 0x1F51 +#define mmDIG1_DIG_CLOCK_PATTERN 0x1F03 +#define mmDIG1_DIG_DISPCLK_SWITCH_CNTL 0x1F08 +#define mmDIG1_DIG_DISPCLK_SWITCH_STATUS 0x1F09 +#define mmDIG1_DIG_FE_CNTL 0x1F00 +#define mmDIG1_DIG_FIFO_STATUS 0x1F0A +#define mmDIG1_DIG_LANE_ENABLE 0x1F8D +#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x1F01 +#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x1F02 +#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x1F05 +#define mmDIG1_DIG_TEST_PATTERN 0x1F04 +#define mmDIG1_HDMI_ACR_32_0 0x1F37 +#define mmDIG1_HDMI_ACR_32_1 0x1F38 +#define mmDIG1_HDMI_ACR_44_0 0x1F39 +#define mmDIG1_HDMI_ACR_44_1 0x1F3A +#define mmDIG1_HDMI_ACR_48_0 0x1F3B +#define mmDIG1_HDMI_ACR_48_1 0x1F3C +#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x1F0F +#define mmDIG1_HDMI_ACR_STATUS_0 0x1F3D +#define mmDIG1_HDMI_ACR_STATUS_1 0x1F3E +#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x1F0E +#define mmDIG1_HDMI_CONTROL 0x1F0C +#define mmDIG1_HDMI_GC 0x1F16 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x1F13 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x1F30 +#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x1F11 +#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x1F12 +#define mmDIG1_HDMI_STATUS 0x1F0D +#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x1F10 +#define mmDIG1_LVDS_DATA_CNTL 0x1F8C +#define mmDIG1_TMDS_CNTL 0x1F7C +#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x1F7E +#define mmDIG1_TMDS_CONTROL_CHAR 0x1F7D +#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x1F86 +#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x1F87 +#define mmDIG1_TMDS_CTL_BITS 0x1F83 +#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x1F84 +#define mmDIG1_TMDS_DEBUG 0x1F82 +#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x1F7F +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x1F80 +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x1F81 +#define mmDIG2_AFMT_60958_0 0x4241 +#define mmDIG2_AFMT_60958_1 0x4242 +#define mmDIG2_AFMT_60958_2 0x4248 +#define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x4243 +#define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x4249 +#define mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL 0x4252 +#define mmDIG2_AFMT_AUDIO_INFO0 0x423F +#define mmDIG2_AFMT_AUDIO_INFO1 0x4240 +#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x424B +#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x4217 +#define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x424F +#define mmDIG2_AFMT_AVI_INFO0 0x4221 +#define mmDIG2_AFMT_AVI_INFO1 0x4222 +#define mmDIG2_AFMT_AVI_INFO2 0x4223 +#define mmDIG2_AFMT_AVI_INFO3 0x4224 +#define mmDIG2_AFMT_GENERIC_0 0x4228 +#define mmDIG2_AFMT_GENERIC_1 0x4229 +#define mmDIG2_AFMT_GENERIC_2 0x422A +#define mmDIG2_AFMT_GENERIC_3 0x422B +#define mmDIG2_AFMT_GENERIC_4 0x422C +#define mmDIG2_AFMT_GENERIC_5 0x422D +#define mmDIG2_AFMT_GENERIC_6 0x422E +#define mmDIG2_AFMT_GENERIC_7 0x422F +#define mmDIG2_AFMT_GENERIC_HDR 0x4227 +#define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x424D +#define mmDIG2_AFMT_INTERRUPT_STATUS 0x4214 +#define mmDIG2_AFMT_ISRC1_0 0x4218 +#define mmDIG2_AFMT_ISRC1_1 0x4219 +#define mmDIG2_AFMT_ISRC1_2 0x421A +#define mmDIG2_AFMT_ISRC1_3 0x421B +#define mmDIG2_AFMT_ISRC1_4 0x421C +#define mmDIG2_AFMT_ISRC2_0 0x421D +#define mmDIG2_AFMT_ISRC2_1 0x421E +#define mmDIG2_AFMT_ISRC2_2 0x421F +#define mmDIG2_AFMT_ISRC2_3 0x4220 +#define mmDIG2_AFMT_MPEG_INFO0 0x4225 +#define mmDIG2_AFMT_MPEG_INFO1 0x4226 +#define mmDIG2_AFMT_RAMP_CONTROL0 0x4244 +#define mmDIG2_AFMT_RAMP_CONTROL1 0x4245 +#define mmDIG2_AFMT_RAMP_CONTROL2 0x4246 +#define mmDIG2_AFMT_RAMP_CONTROL3 0x4247 +#define mmDIG2_AFMT_STATUS 0x424A +#define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x424C +#define mmDIG2_DIG_BE_CNTL 0x4250 +#define mmDIG2_DIG_BE_EN_CNTL 0x4251 +#define mmDIG2_DIG_CLOCK_PATTERN 0x4203 +#define mmDIG2_DIG_DISPCLK_SWITCH_CNTL 0x4208 +#define mmDIG2_DIG_DISPCLK_SWITCH_STATUS 0x4209 +#define mmDIG2_DIG_FE_CNTL 0x4200 +#define mmDIG2_DIG_FIFO_STATUS 0x420A +#define mmDIG2_DIG_LANE_ENABLE 0x428D +#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x4201 +#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x4202 +#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x4205 +#define mmDIG2_DIG_TEST_PATTERN 0x4204 +#define mmDIG2_HDMI_ACR_32_0 0x4237 +#define mmDIG2_HDMI_ACR_32_1 0x4238 +#define mmDIG2_HDMI_ACR_44_0 0x4239 +#define mmDIG2_HDMI_ACR_44_1 0x423A +#define mmDIG2_HDMI_ACR_48_0 0x423B +#define mmDIG2_HDMI_ACR_48_1 0x423C +#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x420F +#define mmDIG2_HDMI_ACR_STATUS_0 0x423D +#define mmDIG2_HDMI_ACR_STATUS_1 0x423E +#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x420E +#define mmDIG2_HDMI_CONTROL 0x420C +#define mmDIG2_HDMI_GC 0x4216 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x4213 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x4230 +#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x4211 +#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x4212 +#define mmDIG2_HDMI_STATUS 0x420D +#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x4210 +#define mmDIG2_LVDS_DATA_CNTL 0x428C +#define mmDIG2_TMDS_CNTL 0x427C +#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x427E +#define mmDIG2_TMDS_CONTROL_CHAR 0x427D +#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x4286 +#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x4287 +#define mmDIG2_TMDS_CTL_BITS 0x4283 +#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x4284 +#define mmDIG2_TMDS_DEBUG 0x4282 +#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x427F +#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x4280 +#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x4281 +#define mmDIG3_AFMT_60958_0 0x4541 +#define mmDIG3_AFMT_60958_1 0x4542 +#define mmDIG3_AFMT_60958_2 0x4548 +#define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x4543 +#define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x4549 +#define mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL 0x4552 +#define mmDIG3_AFMT_AUDIO_INFO0 0x453F +#define mmDIG3_AFMT_AUDIO_INFO1 0x4540 +#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x454B +#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x4517 +#define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x454F +#define mmDIG3_AFMT_AVI_INFO0 0x4521 +#define mmDIG3_AFMT_AVI_INFO1 0x4522 +#define mmDIG3_AFMT_AVI_INFO2 0x4523 +#define mmDIG3_AFMT_AVI_INFO3 0x4524 +#define mmDIG3_AFMT_GENERIC_0 0x4528 +#define mmDIG3_AFMT_GENERIC_1 0x4529 +#define mmDIG3_AFMT_GENERIC_2 0x452A +#define mmDIG3_AFMT_GENERIC_3 0x452B +#define mmDIG3_AFMT_GENERIC_4 0x452C +#define mmDIG3_AFMT_GENERIC_5 0x452D +#define mmDIG3_AFMT_GENERIC_6 0x452E +#define mmDIG3_AFMT_GENERIC_7 0x452F +#define mmDIG3_AFMT_GENERIC_HDR 0x4527 +#define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x454D +#define mmDIG3_AFMT_INTERRUPT_STATUS 0x4514 +#define mmDIG3_AFMT_ISRC1_0 0x4518 +#define mmDIG3_AFMT_ISRC1_1 0x4519 +#define mmDIG3_AFMT_ISRC1_2 0x451A +#define mmDIG3_AFMT_ISRC1_3 0x451B +#define mmDIG3_AFMT_ISRC1_4 0x451C +#define mmDIG3_AFMT_ISRC2_0 0x451D +#define mmDIG3_AFMT_ISRC2_1 0x451E +#define mmDIG3_AFMT_ISRC2_2 0x451F +#define mmDIG3_AFMT_ISRC2_3 0x4520 +#define mmDIG3_AFMT_MPEG_INFO0 0x4525 +#define mmDIG3_AFMT_MPEG_INFO1 0x4526 +#define mmDIG3_AFMT_RAMP_CONTROL0 0x4544 +#define mmDIG3_AFMT_RAMP_CONTROL1 0x4545 +#define mmDIG3_AFMT_RAMP_CONTROL2 0x4546 +#define mmDIG3_AFMT_RAMP_CONTROL3 0x4547 +#define mmDIG3_AFMT_STATUS 0x454A +#define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x454C +#define mmDIG3_DIG_BE_CNTL 0x4550 +#define mmDIG3_DIG_BE_EN_CNTL 0x4551 +#define mmDIG3_DIG_CLOCK_PATTERN 0x4503 +#define mmDIG3_DIG_DISPCLK_SWITCH_CNTL 0x4508 +#define mmDIG3_DIG_DISPCLK_SWITCH_STATUS 0x4509 +#define mmDIG3_DIG_FE_CNTL 0x4500 +#define mmDIG3_DIG_FIFO_STATUS 0x450A +#define mmDIG3_DIG_LANE_ENABLE 0x458D +#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x4501 +#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x4502 +#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x4505 +#define mmDIG3_DIG_TEST_PATTERN 0x4504 +#define mmDIG3_HDMI_ACR_32_0 0x4537 +#define mmDIG3_HDMI_ACR_32_1 0x4538 +#define mmDIG3_HDMI_ACR_44_0 0x4539 +#define mmDIG3_HDMI_ACR_44_1 0x453A +#define mmDIG3_HDMI_ACR_48_0 0x453B +#define mmDIG3_HDMI_ACR_48_1 0x453C +#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x450F +#define mmDIG3_HDMI_ACR_STATUS_0 0x453D +#define mmDIG3_HDMI_ACR_STATUS_1 0x453E +#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x450E +#define mmDIG3_HDMI_CONTROL 0x450C +#define mmDIG3_HDMI_GC 0x4516 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x4513 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x4530 +#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x4511 +#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x4512 +#define mmDIG3_HDMI_STATUS 0x450D +#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x4510 +#define mmDIG3_LVDS_DATA_CNTL 0x458C +#define mmDIG3_TMDS_CNTL 0x457C +#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x457E +#define mmDIG3_TMDS_CONTROL_CHAR 0x457D +#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x4586 +#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x4587 +#define mmDIG3_TMDS_CTL_BITS 0x4583 +#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x4584 +#define mmDIG3_TMDS_DEBUG 0x4582 +#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x457F +#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x4580 +#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x4581 +#define mmDIG4_AFMT_60958_0 0x4841 +#define mmDIG4_AFMT_60958_1 0x4842 +#define mmDIG4_AFMT_60958_2 0x4848 +#define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x4843 +#define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x4849 +#define mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL 0x4852 +#define mmDIG4_AFMT_AUDIO_INFO0 0x483F +#define mmDIG4_AFMT_AUDIO_INFO1 0x4840 +#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x484B +#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x4817 +#define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x484F +#define mmDIG4_AFMT_AVI_INFO0 0x4821 +#define mmDIG4_AFMT_AVI_INFO1 0x4822 +#define mmDIG4_AFMT_AVI_INFO2 0x4823 +#define mmDIG4_AFMT_AVI_INFO3 0x4824 +#define mmDIG4_AFMT_GENERIC_0 0x4828 +#define mmDIG4_AFMT_GENERIC_1 0x4829 +#define mmDIG4_AFMT_GENERIC_2 0x482A +#define mmDIG4_AFMT_GENERIC_3 0x482B +#define mmDIG4_AFMT_GENERIC_4 0x482C +#define mmDIG4_AFMT_GENERIC_5 0x482D +#define mmDIG4_AFMT_GENERIC_6 0x482E +#define mmDIG4_AFMT_GENERIC_7 0x482F +#define mmDIG4_AFMT_GENERIC_HDR 0x4827 +#define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x484D +#define mmDIG4_AFMT_INTERRUPT_STATUS 0x4814 +#define mmDIG4_AFMT_ISRC1_0 0x4818 +#define mmDIG4_AFMT_ISRC1_1 0x4819 +#define mmDIG4_AFMT_ISRC1_2 0x481A +#define mmDIG4_AFMT_ISRC1_3 0x481B +#define mmDIG4_AFMT_ISRC1_4 0x481C +#define mmDIG4_AFMT_ISRC2_0 0x481D +#define mmDIG4_AFMT_ISRC2_1 0x481E +#define mmDIG4_AFMT_ISRC2_2 0x481F +#define mmDIG4_AFMT_ISRC2_3 0x4820 +#define mmDIG4_AFMT_MPEG_INFO0 0x4825 +#define mmDIG4_AFMT_MPEG_INFO1 0x4826 +#define mmDIG4_AFMT_RAMP_CONTROL0 0x4844 +#define mmDIG4_AFMT_RAMP_CONTROL1 0x4845 +#define mmDIG4_AFMT_RAMP_CONTROL2 0x4846 +#define mmDIG4_AFMT_RAMP_CONTROL3 0x4847 +#define mmDIG4_AFMT_STATUS 0x484A +#define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x484C +#define mmDIG4_DIG_BE_CNTL 0x4850 +#define mmDIG4_DIG_BE_EN_CNTL 0x4851 +#define mmDIG4_DIG_CLOCK_PATTERN 0x4803 +#define mmDIG4_DIG_DISPCLK_SWITCH_CNTL 0x4808 +#define mmDIG4_DIG_DISPCLK_SWITCH_STATUS 0x4809 +#define mmDIG4_DIG_FE_CNTL 0x4800 +#define mmDIG4_DIG_FIFO_STATUS 0x480A +#define mmDIG4_DIG_LANE_ENABLE 0x488D +#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x4801 +#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x4802 +#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x4805 +#define mmDIG4_DIG_TEST_PATTERN 0x4804 +#define mmDIG4_HDMI_ACR_32_0 0x4837 +#define mmDIG4_HDMI_ACR_32_1 0x4838 +#define mmDIG4_HDMI_ACR_44_0 0x4839 +#define mmDIG4_HDMI_ACR_44_1 0x483A +#define mmDIG4_HDMI_ACR_48_0 0x483B +#define mmDIG4_HDMI_ACR_48_1 0x483C +#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x480F +#define mmDIG4_HDMI_ACR_STATUS_0 0x483D +#define mmDIG4_HDMI_ACR_STATUS_1 0x483E +#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x480E +#define mmDIG4_HDMI_CONTROL 0x480C +#define mmDIG4_HDMI_GC 0x4816 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x4813 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x4830 +#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x4811 +#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x4812 +#define mmDIG4_HDMI_STATUS 0x480D +#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x4810 +#define mmDIG4_LVDS_DATA_CNTL 0x488C +#define mmDIG4_TMDS_CNTL 0x487C +#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x487E +#define mmDIG4_TMDS_CONTROL_CHAR 0x487D +#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x4886 +#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x4887 +#define mmDIG4_TMDS_CTL_BITS 0x4883 +#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x4884 +#define mmDIG4_TMDS_DEBUG 0x4882 +#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x487F +#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x4880 +#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x4881 +#define mmDIG5_AFMT_60958_0 0x4B41 +#define mmDIG5_AFMT_60958_1 0x4B42 +#define mmDIG5_AFMT_60958_2 0x4B48 +#define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x4B43 +#define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x4B49 +#define mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL 0x4B52 +#define mmDIG5_AFMT_AUDIO_INFO0 0x4B3F +#define mmDIG5_AFMT_AUDIO_INFO1 0x4B40 +#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x4B4B +#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x4B17 +#define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x4B4F +#define mmDIG5_AFMT_AVI_INFO0 0x4B21 +#define mmDIG5_AFMT_AVI_INFO1 0x4B22 +#define mmDIG5_AFMT_AVI_INFO2 0x4B23 +#define mmDIG5_AFMT_AVI_INFO3 0x4B24 +#define mmDIG5_AFMT_GENERIC_0 0x4B28 +#define mmDIG5_AFMT_GENERIC_1 0x4B29 +#define mmDIG5_AFMT_GENERIC_2 0x4B2A +#define mmDIG5_AFMT_GENERIC_3 0x4B2B +#define mmDIG5_AFMT_GENERIC_4 0x4B2C +#define mmDIG5_AFMT_GENERIC_5 0x4B2D +#define mmDIG5_AFMT_GENERIC_6 0x4B2E +#define mmDIG5_AFMT_GENERIC_7 0x4B2F +#define mmDIG5_AFMT_GENERIC_HDR 0x4B27 +#define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x4B4D +#define mmDIG5_AFMT_INTERRUPT_STATUS 0x4B14 +#define mmDIG5_AFMT_ISRC1_0 0x4B18 +#define mmDIG5_AFMT_ISRC1_1 0x4B19 +#define mmDIG5_AFMT_ISRC1_2 0x4B1A +#define mmDIG5_AFMT_ISRC1_3 0x4B1B +#define mmDIG5_AFMT_ISRC1_4 0x4B1C +#define mmDIG5_AFMT_ISRC2_0 0x4B1D +#define mmDIG5_AFMT_ISRC2_1 0x4B1E +#define mmDIG5_AFMT_ISRC2_2 0x4B1F +#define mmDIG5_AFMT_ISRC2_3 0x4B20 +#define mmDIG5_AFMT_MPEG_INFO0 0x4B25 +#define mmDIG5_AFMT_MPEG_INFO1 0x4B26 +#define mmDIG5_AFMT_RAMP_CONTROL0 0x4B44 +#define mmDIG5_AFMT_RAMP_CONTROL1 0x4B45 +#define mmDIG5_AFMT_RAMP_CONTROL2 0x4B46 +#define mmDIG5_AFMT_RAMP_CONTROL3 0x4B47 +#define mmDIG5_AFMT_STATUS 0x4B4A +#define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x4B4C +#define mmDIG5_DIG_BE_CNTL 0x4B50 +#define mmDIG5_DIG_BE_EN_CNTL 0x4B51 +#define mmDIG5_DIG_CLOCK_PATTERN 0x4B03 +#define mmDIG5_DIG_DISPCLK_SWITCH_CNTL 0x4B08 +#define mmDIG5_DIG_DISPCLK_SWITCH_STATUS 0x4B09 +#define mmDIG5_DIG_FE_CNTL 0x4B00 +#define mmDIG5_DIG_FIFO_STATUS 0x4B0A +#define mmDIG5_DIG_LANE_ENABLE 0x4B8D +#define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x4B01 +#define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x4B02 +#define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x4B05 +#define mmDIG5_DIG_TEST_PATTERN 0x4B04 +#define mmDIG5_HDMI_ACR_32_0 0x4B37 +#define mmDIG5_HDMI_ACR_32_1 0x4B38 +#define mmDIG5_HDMI_ACR_44_0 0x4B39 +#define mmDIG5_HDMI_ACR_44_1 0x4B3A +#define mmDIG5_HDMI_ACR_48_0 0x4B3B +#define mmDIG5_HDMI_ACR_48_1 0x4B3C +#define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x4B0F +#define mmDIG5_HDMI_ACR_STATUS_0 0x4B3D +#define mmDIG5_HDMI_ACR_STATUS_1 0x4B3E +#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x4B0E +#define mmDIG5_HDMI_CONTROL 0x4B0C +#define mmDIG5_HDMI_GC 0x4B16 +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x4B13 +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x4B30 +#define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x4B11 +#define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x4B12 +#define mmDIG5_HDMI_STATUS 0x4B0D +#define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x4B10 +#define mmDIG5_LVDS_DATA_CNTL 0x4B8C +#define mmDIG5_TMDS_CNTL 0x4B7C +#define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x4B7E +#define mmDIG5_TMDS_CONTROL_CHAR 0x4B7D +#define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x4B86 +#define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x4B87 +#define mmDIG5_TMDS_CTL_BITS 0x4B83 +#define mmDIG5_TMDS_DCBALANCER_CONTROL 0x4B84 +#define mmDIG5_TMDS_DEBUG 0x4B82 +#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x4B7F +#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x4B80 +#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x4B81 +#define mmDIG_BE_CNTL 0x1C50 +#define mmDIG_BE_EN_CNTL 0x1C51 +#define mmDIG_CLOCK_PATTERN 0x1C03 +#define mmDIG_DISPCLK_SWITCH_CNTL 0x1C08 +#define mmDIG_DISPCLK_SWITCH_STATUS 0x1C09 +#define mmDIG_FE_CNTL 0x1C00 +#define mmDIG_FIFO_STATUS 0x1C0A +#define mmDIG_LANE_ENABLE 0x1C8D +#define mmDIG_OUTPUT_CRC_CNTL 0x1C01 +#define mmDIG_OUTPUT_CRC_RESULT 0x1C02 +#define mmDIG_RANDOM_PATTERN_SEED 0x1C05 +#define mmDIG_SOFT_RESET 0x013D +#define mmDIG_TEST_PATTERN 0x1C04 +#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0135 +#define mmDISPCLK_FREQ_CHANGE_CNTL 0x0131 +#define mmDISP_INTERRUPT_STATUS 0x183D +#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x183E +#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x183F +#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x1840 +#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x1853 +#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x1854 +#define mmDISPOUT_STEREOSYNC_SEL 0x18BF +#define mmDISPPLL_BG_CNTL 0x013C +#define mmDISP_TIMER_CONTROL 0x1842 +#define mmDMCU_CTRL 0x1600 +#define mmDMCU_ERAM_RD_CTRL 0x160B +#define mmDMCU_ERAM_RD_DATA 0x160C +#define mmDMCU_ERAM_WR_CTRL 0x1609 +#define mmDMCU_ERAM_WR_DATA 0x160A +#define mmDMCU_EVENT_TRIGGER 0x1611 +#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x161A +#define mmDMCU_FW_CS_HI 0x1606 +#define mmDMCU_FW_CS_LO 0x1607 +#define mmDMCU_FW_END_ADDR 0x1604 +#define mmDMCU_FW_ISR_START_ADDR 0x1605 +#define mmDMCU_FW_START_ADDR 0x1603 +#define mmDMCU_INT_CNT 0x1619 +#define mmDMCU_INTERRUPT_STATUS 0x1614 +#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x1615 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x1616 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x1617 +#define mmDMCU_IRAM_RD_CTRL 0x160F +#define mmDMCU_IRAM_RD_DATA 0x1610 +#define mmDMCU_IRAM_WR_CTRL 0x160D +#define mmDMCU_IRAM_WR_DATA 0x160E +#define mmDMCU_PC_START_ADDR 0x1602 +#define mmDMCU_RAM_ACCESS_CTRL 0x1608 +#define mmDMCU_STATUS 0x1601 +#define mmDMCU_TEST_DEBUG_DATA 0x1627 +#define mmDMCU_TEST_DEBUG_INDEX 0x1626 +#define mmDMCU_UC_CLK_GATING_CNTL 0x161B +#define mmDMCU_UC_INTERNAL_INT_STATUS 0x1612 +#define mmDMIF_ADDR_CALC 0x0300 +#define mmDMIF_ADDR_CONFIG 0x02F5 +#define mmDMIF_ARBITRATION_CONTROL 0x02F9 +#define mmDMIF_CONTROL 0x02F6 +#define mmDMIF_HW_DEBUG 0x02F8 +#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x1B30 +#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x1B31 +#define mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 0x1B34 +#define mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1B36 +#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x1B35 +#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1B37 +#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x1B33 +#define mmDMIF_PG0_DPG_TEST_DEBUG_DATA 0x1B39 +#define mmDMIF_PG0_DPG_TEST_DEBUG_INDEX 0x1B38 +#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x1E30 +#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x1E31 +#define mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 0x1E34 +#define mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1E36 +#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x1E35 +#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1E37 +#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x1E33 +#define mmDMIF_PG1_DPG_TEST_DEBUG_DATA 0x1E39 +#define mmDMIF_PG1_DPG_TEST_DEBUG_INDEX 0x1E38 +#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x4130 +#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x4131 +#define mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 0x4134 +#define mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4136 +#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x4135 +#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4137 +#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x4133 +#define mmDMIF_PG2_DPG_TEST_DEBUG_DATA 0x4139 +#define mmDMIF_PG2_DPG_TEST_DEBUG_INDEX 0x4138 +#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x4430 +#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x4431 +#define mmDMIF_PG3_DPG_PIPE_DPM_CONTROL 0x4434 +#define mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4436 +#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x4435 +#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4437 +#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x4433 +#define mmDMIF_PG3_DPG_TEST_DEBUG_DATA 0x4439 +#define mmDMIF_PG3_DPG_TEST_DEBUG_INDEX 0x4438 +#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x4730 +#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x4731 +#define mmDMIF_PG4_DPG_PIPE_DPM_CONTROL 0x4734 +#define mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4736 +#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x4735 +#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4737 +#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x4733 +#define mmDMIF_PG4_DPG_TEST_DEBUG_DATA 0x4739 +#define mmDMIF_PG4_DPG_TEST_DEBUG_INDEX 0x4738 +#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x4A30 +#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x4A31 +#define mmDMIF_PG5_DPG_PIPE_DPM_CONTROL 0x4A34 +#define mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4A36 +#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x4A35 +#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4A37 +#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x4A33 +#define mmDMIF_PG5_DPG_TEST_DEBUG_DATA 0x4A39 +#define mmDMIF_PG5_DPG_TEST_DEBUG_INDEX 0x4A38 +#define mmDMIF_STATUS 0x02F7 +#define mmDMIF_STATUS2 0x0301 +#define mmDMIF_TEST_DEBUG_DATA 0x0313 +#define mmDMIF_TEST_DEBUG_INDEX 0x0312 +#define mmDOUT_DCE_VCE_CONTROL 0x18FF +#define mmDOUT_POWER_MANAGEMENT_CNTL 0x1841 +#define mmDOUT_SCRATCH0 0x1844 +#define mmDOUT_SCRATCH1 0x1845 +#define mmDOUT_SCRATCH2 0x1846 +#define mmDOUT_SCRATCH3 0x1847 +#define mmDOUT_SCRATCH4 0x1848 +#define mmDOUT_SCRATCH5 0x1849 +#define mmDOUT_SCRATCH6 0x184A +#define mmDOUT_SCRATCH7 0x184B +#define mmDOUT_TEST_DEBUG_DATA 0x184E +#define mmDOUT_TEST_DEBUG_INDEX 0x184D +#define mmDP0_DP_CONFIG 0x1CC2 +#define mmDP0_DP_DPHY_8B10B_CNTL 0x1CD3 +#define mmDP0_DP_DPHY_CNTL 0x1CD0 +#define mmDP0_DP_DPHY_CRC_CNTL 0x1CD7 +#define mmDP0_DP_DPHY_CRC_EN 0x1CD6 +#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x1CC6 +#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x1CC7 +#define mmDP0_DP_DPHY_CRC_RESULT 0x1CD8 +#define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE +#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x1CE9 +#define mmDP0_DP_DPHY_PRBS_CNTL 0x1CD4 +#define mmDP0_DP_DPHY_SYM0 0x1CD2 +#define mmDP0_DP_DPHY_SYM1 0x1CE0 +#define mmDP0_DP_DPHY_SYM2 0x1CDF +#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x1CD1 +#define mmDP0_DP_HBR2_EYE_PATTERN 0x1CC8 +#define mmDP0_DP_LINK_CNTL 0x1CC0 +#define mmDP0_DP_LINK_FRAMING_CNTL 0x1CCC +#define mmDP0_DP_MSA_COLORIMETRY 0x1CDA +#define mmDP0_DP_MSA_MISC 0x1CC5 +#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x1CEA +#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x1CEB +#define mmDP0_DP_MSE_LINK_TIMING 0x1CE8 +#define mmDP0_DP_MSE_MISC_CNTL 0x1CDB +#define mmDP0_DP_MSE_RATE_CNTL 0x1CE1 +#define mmDP0_DP_MSE_RATE_UPDATE 0x1CE3 +#define mmDP0_DP_MSE_SAT0 0x1CE4 +#define mmDP0_DP_MSE_SAT1 0x1CE5 +#define mmDP0_DP_MSE_SAT2 0x1CE6 +#define mmDP0_DP_MSE_SAT_UPDATE 0x1CE7 +#define mmDP0_DP_PIXEL_FORMAT 0x1CC1 +#define mmDP0_DP_SEC_AUD_M 0x1CA7 +#define mmDP0_DP_SEC_AUD_M_READBACK 0x1CA8 +#define mmDP0_DP_SEC_AUD_N 0x1CA5 +#define mmDP0_DP_SEC_AUD_N_READBACK 0x1CA6 +#define mmDP0_DP_SEC_CNTL 0x1CA0 +#define mmDP0_DP_SEC_CNTL1 0x1CAB +#define mmDP0_DP_SEC_FRAMING1 0x1CA1 +#define mmDP0_DP_SEC_FRAMING2 0x1CA2 +#define mmDP0_DP_SEC_FRAMING3 0x1CA3 +#define mmDP0_DP_SEC_FRAMING4 0x1CA4 +#define mmDP0_DP_SEC_PACKET_CNTL 0x1CAA +#define mmDP0_DP_SEC_TIMESTAMP 0x1CA9 +#define mmDP0_DP_STEER_FIFO 0x1CC4 +#define mmDP0_DP_TEST_DEBUG_DATA 0x1CFD +#define mmDP0_DP_TEST_DEBUG_INDEX 0x1CFC +#define mmDP0_DP_VID_INTERRUPT_CNTL 0x1CCF +#define mmDP0_DP_VID_M 0x1CCB +#define mmDP0_DP_VID_MSA_VBID 0x1CCD +#define mmDP0_DP_VID_N 0x1CCA +#define mmDP0_DP_VID_STREAM_CNTL 0x1CC3 +#define mmDP0_DP_VID_TIMING 0x1CC9 +#define mmDP1_DP_CONFIG 0x1FC2 +#define mmDP1_DP_DPHY_8B10B_CNTL 0x1FD3 +#define mmDP1_DP_DPHY_CNTL 0x1FD0 +#define mmDP1_DP_DPHY_CRC_CNTL 0x1FD7 +#define mmDP1_DP_DPHY_CRC_EN 0x1FD6 +#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x1FC6 +#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x1FC7 +#define mmDP1_DP_DPHY_CRC_RESULT 0x1FD8 +#define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE +#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x1FE9 +#define mmDP1_DP_DPHY_PRBS_CNTL 0x1FD4 +#define mmDP1_DP_DPHY_SYM0 0x1FD2 +#define mmDP1_DP_DPHY_SYM1 0x1FE0 +#define mmDP1_DP_DPHY_SYM2 0x1FDF +#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x1FD1 +#define mmDP1_DP_HBR2_EYE_PATTERN 0x1FC8 +#define mmDP1_DP_LINK_CNTL 0x1FC0 +#define mmDP1_DP_LINK_FRAMING_CNTL 0x1FCC +#define mmDP1_DP_MSA_COLORIMETRY 0x1FDA +#define mmDP1_DP_MSA_MISC 0x1FC5 +#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x1FEA +#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x1FEB +#define mmDP1_DP_MSE_LINK_TIMING 0x1FE8 +#define mmDP1_DP_MSE_MISC_CNTL 0x1FDB +#define mmDP1_DP_MSE_RATE_CNTL 0x1FE1 +#define mmDP1_DP_MSE_RATE_UPDATE 0x1FE3 +#define mmDP1_DP_MSE_SAT0 0x1FE4 +#define mmDP1_DP_MSE_SAT1 0x1FE5 +#define mmDP1_DP_MSE_SAT2 0x1FE6 +#define mmDP1_DP_MSE_SAT_UPDATE 0x1FE7 +#define mmDP1_DP_PIXEL_FORMAT 0x1FC1 +#define mmDP1_DP_SEC_AUD_M 0x1FA7 +#define mmDP1_DP_SEC_AUD_M_READBACK 0x1FA8 +#define mmDP1_DP_SEC_AUD_N 0x1FA5 +#define mmDP1_DP_SEC_AUD_N_READBACK 0x1FA6 +#define mmDP1_DP_SEC_CNTL 0x1FA0 +#define mmDP1_DP_SEC_CNTL1 0x1FAB +#define mmDP1_DP_SEC_FRAMING1 0x1FA1 +#define mmDP1_DP_SEC_FRAMING2 0x1FA2 +#define mmDP1_DP_SEC_FRAMING3 0x1FA3 +#define mmDP1_DP_SEC_FRAMING4 0x1FA4 +#define mmDP1_DP_SEC_PACKET_CNTL 0x1FAA +#define mmDP1_DP_SEC_TIMESTAMP 0x1FA9 +#define mmDP1_DP_STEER_FIFO 0x1FC4 +#define mmDP1_DP_TEST_DEBUG_DATA 0x1FFD +#define mmDP1_DP_TEST_DEBUG_INDEX 0x1FFC +#define mmDP1_DP_VID_INTERRUPT_CNTL 0x1FCF +#define mmDP1_DP_VID_M 0x1FCB +#define mmDP1_DP_VID_MSA_VBID 0x1FCD +#define mmDP1_DP_VID_N 0x1FCA +#define mmDP1_DP_VID_STREAM_CNTL 0x1FC3 +#define mmDP1_DP_VID_TIMING 0x1FC9 +#define mmDP2_DP_CONFIG 0x42C2 +#define mmDP2_DP_DPHY_8B10B_CNTL 0x42D3 +#define mmDP2_DP_DPHY_CNTL 0x42D0 +#define mmDP2_DP_DPHY_CRC_CNTL 0x42D7 +#define mmDP2_DP_DPHY_CRC_EN 0x42D6 +#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x42C6 +#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x42C7 +#define mmDP2_DP_DPHY_CRC_RESULT 0x42D8 +#define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE +#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x42E9 +#define mmDP2_DP_DPHY_PRBS_CNTL 0x42D4 +#define mmDP2_DP_DPHY_SYM0 0x42D2 +#define mmDP2_DP_DPHY_SYM1 0x42E0 +#define mmDP2_DP_DPHY_SYM2 0x42DF +#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x42D1 +#define mmDP2_DP_HBR2_EYE_PATTERN 0x42C8 +#define mmDP2_DP_LINK_CNTL 0x42C0 +#define mmDP2_DP_LINK_FRAMING_CNTL 0x42CC +#define mmDP2_DP_MSA_COLORIMETRY 0x42DA +#define mmDP2_DP_MSA_MISC 0x42C5 +#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x42EA +#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x42EB +#define mmDP2_DP_MSE_LINK_TIMING 0x42E8 +#define mmDP2_DP_MSE_MISC_CNTL 0x42DB +#define mmDP2_DP_MSE_RATE_CNTL 0x42E1 +#define mmDP2_DP_MSE_RATE_UPDATE 0x42E3 +#define mmDP2_DP_MSE_SAT0 0x42E4 +#define mmDP2_DP_MSE_SAT1 0x42E5 +#define mmDP2_DP_MSE_SAT2 0x42E6 +#define mmDP2_DP_MSE_SAT_UPDATE 0x42E7 +#define mmDP2_DP_PIXEL_FORMAT 0x42C1 +#define mmDP2_DP_SEC_AUD_M 0x42A7 +#define mmDP2_DP_SEC_AUD_M_READBACK 0x42A8 +#define mmDP2_DP_SEC_AUD_N 0x42A5 +#define mmDP2_DP_SEC_AUD_N_READBACK 0x42A6 +#define mmDP2_DP_SEC_CNTL 0x42A0 +#define mmDP2_DP_SEC_CNTL1 0x42AB +#define mmDP2_DP_SEC_FRAMING1 0x42A1 +#define mmDP2_DP_SEC_FRAMING2 0x42A2 +#define mmDP2_DP_SEC_FRAMING3 0x42A3 +#define mmDP2_DP_SEC_FRAMING4 0x42A4 +#define mmDP2_DP_SEC_PACKET_CNTL 0x42AA +#define mmDP2_DP_SEC_TIMESTAMP 0x42A9 +#define mmDP2_DP_STEER_FIFO 0x42C4 +#define mmDP2_DP_TEST_DEBUG_DATA 0x42FD +#define mmDP2_DP_TEST_DEBUG_INDEX 0x42FC +#define mmDP2_DP_VID_INTERRUPT_CNTL 0x42CF +#define mmDP2_DP_VID_M 0x42CB +#define mmDP2_DP_VID_MSA_VBID 0x42CD +#define mmDP2_DP_VID_N 0x42CA +#define mmDP2_DP_VID_STREAM_CNTL 0x42C3 +#define mmDP2_DP_VID_TIMING 0x42C9 +#define mmDP3_DP_CONFIG 0x45C2 +#define mmDP3_DP_DPHY_8B10B_CNTL 0x45D3 +#define mmDP3_DP_DPHY_CNTL 0x45D0 +#define mmDP3_DP_DPHY_CRC_CNTL 0x45D7 +#define mmDP3_DP_DPHY_CRC_EN 0x45D6 +#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x45C6 +#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x45C7 +#define mmDP3_DP_DPHY_CRC_RESULT 0x45D8 +#define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE +#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x45E9 +#define mmDP3_DP_DPHY_PRBS_CNTL 0x45D4 +#define mmDP3_DP_DPHY_SYM0 0x45D2 +#define mmDP3_DP_DPHY_SYM1 0x45E0 +#define mmDP3_DP_DPHY_SYM2 0x45DF +#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x45D1 +#define mmDP3_DP_HBR2_EYE_PATTERN 0x45C8 +#define mmDP3_DP_LINK_CNTL 0x45C0 +#define mmDP3_DP_LINK_FRAMING_CNTL 0x45CC +#define mmDP3_DP_MSA_COLORIMETRY 0x45DA +#define mmDP3_DP_MSA_MISC 0x45C5 +#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x45EA +#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x45EB +#define mmDP3_DP_MSE_LINK_TIMING 0x45E8 +#define mmDP3_DP_MSE_MISC_CNTL 0x45DB +#define mmDP3_DP_MSE_RATE_CNTL 0x45E1 +#define mmDP3_DP_MSE_RATE_UPDATE 0x45E3 +#define mmDP3_DP_MSE_SAT0 0x45E4 +#define mmDP3_DP_MSE_SAT1 0x45E5 +#define mmDP3_DP_MSE_SAT2 0x45E6 +#define mmDP3_DP_MSE_SAT_UPDATE 0x45E7 +#define mmDP3_DP_PIXEL_FORMAT 0x45C1 +#define mmDP3_DP_SEC_AUD_M 0x45A7 +#define mmDP3_DP_SEC_AUD_M_READBACK 0x45A8 +#define mmDP3_DP_SEC_AUD_N 0x45A5 +#define mmDP3_DP_SEC_AUD_N_READBACK 0x45A6 +#define mmDP3_DP_SEC_CNTL 0x45A0 +#define mmDP3_DP_SEC_CNTL1 0x45AB +#define mmDP3_DP_SEC_FRAMING1 0x45A1 +#define mmDP3_DP_SEC_FRAMING2 0x45A2 +#define mmDP3_DP_SEC_FRAMING3 0x45A3 +#define mmDP3_DP_SEC_FRAMING4 0x45A4 +#define mmDP3_DP_SEC_PACKET_CNTL 0x45AA +#define mmDP3_DP_SEC_TIMESTAMP 0x45A9 +#define mmDP3_DP_STEER_FIFO 0x45C4 +#define mmDP3_DP_TEST_DEBUG_DATA 0x45FD +#define mmDP3_DP_TEST_DEBUG_INDEX 0x45FC +#define mmDP3_DP_VID_INTERRUPT_CNTL 0x45CF +#define mmDP3_DP_VID_M 0x45CB +#define mmDP3_DP_VID_MSA_VBID 0x45CD +#define mmDP3_DP_VID_N 0x45CA +#define mmDP3_DP_VID_STREAM_CNTL 0x45C3 +#define mmDP3_DP_VID_TIMING 0x45C9 +#define mmDP4_DP_CONFIG 0x48C2 +#define mmDP4_DP_DPHY_8B10B_CNTL 0x48D3 +#define mmDP4_DP_DPHY_CNTL 0x48D0 +#define mmDP4_DP_DPHY_CRC_CNTL 0x48D7 +#define mmDP4_DP_DPHY_CRC_EN 0x48D6 +#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x48C6 +#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x48C7 +#define mmDP4_DP_DPHY_CRC_RESULT 0x48D8 +#define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE +#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x48E9 +#define mmDP4_DP_DPHY_PRBS_CNTL 0x48D4 +#define mmDP4_DP_DPHY_SYM0 0x48D2 +#define mmDP4_DP_DPHY_SYM1 0x48E0 +#define mmDP4_DP_DPHY_SYM2 0x48DF +#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x48D1 +#define mmDP4_DP_HBR2_EYE_PATTERN 0x48C8 +#define mmDP4_DP_LINK_CNTL 0x48C0 +#define mmDP4_DP_LINK_FRAMING_CNTL 0x48CC +#define mmDP4_DP_MSA_COLORIMETRY 0x48DA +#define mmDP4_DP_MSA_MISC 0x48C5 +#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x48EA +#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x48EB +#define mmDP4_DP_MSE_LINK_TIMING 0x48E8 +#define mmDP4_DP_MSE_MISC_CNTL 0x48DB +#define mmDP4_DP_MSE_RATE_CNTL 0x48E1 +#define mmDP4_DP_MSE_RATE_UPDATE 0x48E3 +#define mmDP4_DP_MSE_SAT0 0x48E4 +#define mmDP4_DP_MSE_SAT1 0x48E5 +#define mmDP4_DP_MSE_SAT2 0x48E6 +#define mmDP4_DP_MSE_SAT_UPDATE 0x48E7 +#define mmDP4_DP_PIXEL_FORMAT 0x48C1 +#define mmDP4_DP_SEC_AUD_M 0x48A7 +#define mmDP4_DP_SEC_AUD_M_READBACK 0x48A8 +#define mmDP4_DP_SEC_AUD_N 0x48A5 +#define mmDP4_DP_SEC_AUD_N_READBACK 0x48A6 +#define mmDP4_DP_SEC_CNTL 0x48A0 +#define mmDP4_DP_SEC_CNTL1 0x48AB +#define mmDP4_DP_SEC_FRAMING1 0x48A1 +#define mmDP4_DP_SEC_FRAMING2 0x48A2 +#define mmDP4_DP_SEC_FRAMING3 0x48A3 +#define mmDP4_DP_SEC_FRAMING4 0x48A4 +#define mmDP4_DP_SEC_PACKET_CNTL 0x48AA +#define mmDP4_DP_SEC_TIMESTAMP 0x48A9 +#define mmDP4_DP_STEER_FIFO 0x48C4 +#define mmDP4_DP_TEST_DEBUG_DATA 0x48FD +#define mmDP4_DP_TEST_DEBUG_INDEX 0x48FC +#define mmDP4_DP_VID_INTERRUPT_CNTL 0x48CF +#define mmDP4_DP_VID_M 0x48CB +#define mmDP4_DP_VID_MSA_VBID 0x48CD +#define mmDP4_DP_VID_N 0x48CA +#define mmDP4_DP_VID_STREAM_CNTL 0x48C3 +#define mmDP4_DP_VID_TIMING 0x48C9 +#define mmDP5_DP_CONFIG 0x4BC2 +#define mmDP5_DP_DPHY_8B10B_CNTL 0x4BD3 +#define mmDP5_DP_DPHY_CNTL 0x4BD0 +#define mmDP5_DP_DPHY_CRC_CNTL 0x4BD7 +#define mmDP5_DP_DPHY_CRC_EN 0x4BD6 +#define mmDP5_DP_DPHY_CRC_MST_CNTL 0x4BC6 +#define mmDP5_DP_DPHY_CRC_MST_STATUS 0x4BC7 +#define mmDP5_DP_DPHY_CRC_RESULT 0x4BD8 +#define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE +#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x4BE9 +#define mmDP5_DP_DPHY_PRBS_CNTL 0x4BD4 +#define mmDP5_DP_DPHY_SYM0 0x4BD2 +#define mmDP5_DP_DPHY_SYM1 0x4BE0 +#define mmDP5_DP_DPHY_SYM2 0x4BDF +#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x4BD1 +#define mmDP5_DP_HBR2_EYE_PATTERN 0x4BC8 +#define mmDP5_DP_LINK_CNTL 0x4BC0 +#define mmDP5_DP_LINK_FRAMING_CNTL 0x4BCC +#define mmDP5_DP_MSA_COLORIMETRY 0x4BDA +#define mmDP5_DP_MSA_MISC 0x4BC5 +#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x4BEA +#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x4BEB +#define mmDP5_DP_MSE_LINK_TIMING 0x4BE8 +#define mmDP5_DP_MSE_MISC_CNTL 0x4BDB +#define mmDP5_DP_MSE_RATE_CNTL 0x4BE1 +#define mmDP5_DP_MSE_RATE_UPDATE 0x4BE3 +#define mmDP5_DP_MSE_SAT0 0x4BE4 +#define mmDP5_DP_MSE_SAT1 0x4BE5 +#define mmDP5_DP_MSE_SAT2 0x4BE6 +#define mmDP5_DP_MSE_SAT_UPDATE 0x4BE7 +#define mmDP5_DP_PIXEL_FORMAT 0x4BC1 +#define mmDP5_DP_SEC_AUD_M 0x4BA7 +#define mmDP5_DP_SEC_AUD_M_READBACK 0x4BA8 +#define mmDP5_DP_SEC_AUD_N 0x4BA5 +#define mmDP5_DP_SEC_AUD_N_READBACK 0x4BA6 +#define mmDP5_DP_SEC_CNTL 0x4BA0 +#define mmDP5_DP_SEC_CNTL1 0x4BAB +#define mmDP5_DP_SEC_FRAMING1 0x4BA1 +#define mmDP5_DP_SEC_FRAMING2 0x4BA2 +#define mmDP5_DP_SEC_FRAMING3 0x4BA3 +#define mmDP5_DP_SEC_FRAMING4 0x4BA4 +#define mmDP5_DP_SEC_PACKET_CNTL 0x4BAA +#define mmDP5_DP_SEC_TIMESTAMP 0x4BA9 +#define mmDP5_DP_STEER_FIFO 0x4BC4 +#define mmDP5_DP_TEST_DEBUG_DATA 0x4BFD +#define mmDP5_DP_TEST_DEBUG_INDEX 0x4BFC +#define mmDP5_DP_VID_INTERRUPT_CNTL 0x4BCF +#define mmDP5_DP_VID_M 0x4BCB +#define mmDP5_DP_VID_MSA_VBID 0x4BCD +#define mmDP5_DP_VID_N 0x4BCA +#define mmDP5_DP_VID_STREAM_CNTL 0x4BC3 +#define mmDP5_DP_VID_TIMING 0x4BC9 +#define mmDP_AUX0_AUX_ARB_CONTROL 0x1882 +#define mmDP_AUX0_AUX_CONTROL 0x1880 +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x188A +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x188B +#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x188D +#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1889 +#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1888 +#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x188C +#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x188E +#define mmDP_AUX0_AUX_GTC_SYNC_DATA 0x1890 +#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1883 +#define mmDP_AUX0_AUX_LS_DATA 0x1887 +#define mmDP_AUX0_AUX_LS_STATUS 0x1885 +#define mmDP_AUX0_AUX_SW_CONTROL 0x1881 +#define mmDP_AUX0_AUX_SW_DATA 0x1886 +#define mmDP_AUX0_AUX_SW_STATUS 0x1884 +#define mmDP_AUX1_AUX_ARB_CONTROL 0x1896 +#define mmDP_AUX1_AUX_CONTROL 0x1894 +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x189E +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x189F +#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x18A1 +#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x189D +#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x189C +#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x18A0 +#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x18A2 +#define mmDP_AUX1_AUX_GTC_SYNC_DATA 0x18A4 +#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1897 +#define mmDP_AUX1_AUX_LS_DATA 0x189B +#define mmDP_AUX1_AUX_LS_STATUS 0x1899 +#define mmDP_AUX1_AUX_SW_CONTROL 0x1895 +#define mmDP_AUX1_AUX_SW_DATA 0x189A +#define mmDP_AUX1_AUX_SW_STATUS 0x1898 +#define mmDP_AUX2_AUX_ARB_CONTROL 0x18AA +#define mmDP_AUX2_AUX_CONTROL 0x18A8 +#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x18B2 +#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x18B3 +#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x18B5 +#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x18B1 +#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x18B0 +#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x18B4 +#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x18B6 +#define mmDP_AUX2_AUX_GTC_SYNC_DATA 0x18B8 +#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x18AB +#define mmDP_AUX2_AUX_LS_DATA 0x18AF +#define mmDP_AUX2_AUX_LS_STATUS 0x18AD +#define mmDP_AUX2_AUX_SW_CONTROL 0x18A9 +#define mmDP_AUX2_AUX_SW_DATA 0x18AE +#define mmDP_AUX2_AUX_SW_STATUS 0x18AC +#define mmDP_AUX3_AUX_ARB_CONTROL 0x18C2 +#define mmDP_AUX3_AUX_CONTROL 0x18C0 +#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x18CA +#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x18CB +#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x18CD +#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x18C9 +#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x18C8 +#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x18CC +#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x18CE +#define mmDP_AUX3_AUX_GTC_SYNC_DATA 0x18D0 +#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x18C3 +#define mmDP_AUX3_AUX_LS_DATA 0x18C7 +#define mmDP_AUX3_AUX_LS_STATUS 0x18C5 +#define mmDP_AUX3_AUX_SW_CONTROL 0x18C1 +#define mmDP_AUX3_AUX_SW_DATA 0x18C6 +#define mmDP_AUX3_AUX_SW_STATUS 0x18C4 +#define mmDP_AUX4_AUX_ARB_CONTROL 0x18D6 +#define mmDP_AUX4_AUX_CONTROL 0x18D4 +#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x18DE +#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x18DF +#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x18E1 +#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x18DD +#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x18DC +#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x18E0 +#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x18E2 +#define mmDP_AUX4_AUX_GTC_SYNC_DATA 0x18E4 +#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x18D7 +#define mmDP_AUX4_AUX_LS_DATA 0x18DB +#define mmDP_AUX4_AUX_LS_STATUS 0x18D9 +#define mmDP_AUX4_AUX_SW_CONTROL 0x18D5 +#define mmDP_AUX4_AUX_SW_DATA 0x18DA +#define mmDP_AUX4_AUX_SW_STATUS 0x18D8 +#define mmDP_AUX5_AUX_ARB_CONTROL 0x18EA +#define mmDP_AUX5_AUX_CONTROL 0x18E8 +#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x18F2 +#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x18F3 +#define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x18F5 +#define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x18F1 +#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x18F0 +#define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x18F4 +#define mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x18F6 +#define mmDP_AUX5_AUX_GTC_SYNC_DATA 0x18F8 +#define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x18EB +#define mmDP_AUX5_AUX_LS_DATA 0x18EF +#define mmDP_AUX5_AUX_LS_STATUS 0x18ED +#define mmDP_AUX5_AUX_SW_CONTROL 0x18E9 +#define mmDP_AUX5_AUX_SW_DATA 0x18EE +#define mmDP_AUX5_AUX_SW_STATUS 0x18EC +#define mmDP_CONFIG 0x1CC2 +#define mmDP_DPHY_8B10B_CNTL 0x1CD3 +#define mmDP_DPHY_CNTL 0x1CD0 +#define mmDP_DPHY_CRC_CNTL 0x1CD7 +#define mmDP_DPHY_CRC_EN 0x1CD6 +#define mmDP_DPHY_CRC_MST_CNTL 0x1CC6 +#define mmDP_DPHY_CRC_MST_STATUS 0x1CC7 +#define mmDP_DPHY_CRC_RESULT 0x1CD8 +#define mmDP_DPHY_FAST_TRAINING 0x1CCE +#define mmDP_DPHY_FAST_TRAINING_STATUS 0x1CE9 +#define mmDP_DPHY_PRBS_CNTL 0x1CD4 +#define mmDP_DPHY_SYM0 0x1CD2 +#define mmDP_DPHY_SYM1 0x1CE0 +#define mmDP_DPHY_SYM2 0x1CDF +#define mmDP_DPHY_TRAINING_PATTERN_SEL 0x1CD1 +#define mmDP_DTO0_MODULO 0x0142 +#define mmDP_DTO0_PHASE 0x0141 +#define mmDP_DTO1_MODULO 0x0146 +#define mmDP_DTO1_PHASE 0x0145 +#define mmDP_DTO2_MODULO 0x014A +#define mmDP_DTO2_PHASE 0x0149 +#define mmDP_DTO3_MODULO 0x014E +#define mmDP_DTO3_PHASE 0x014D +#define mmDP_DTO4_MODULO 0x0152 +#define mmDP_DTO4_PHASE 0x0151 +#define mmDP_DTO5_MODULO 0x0156 +#define mmDP_DTO5_PHASE 0x0155 +#define mmDPG_PIPE_ARBITRATION_CONTROL1 0x1B30 +#define mmDPG_PIPE_ARBITRATION_CONTROL2 0x1B31 +#define mmDPG_PIPE_DPM_CONTROL 0x1B34 +#define mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1B36 +#define mmDPG_PIPE_STUTTER_CONTROL 0x1B35 +#define mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1B37 +#define mmDPG_PIPE_URGENCY_CONTROL 0x1B33 +#define mmDPG_TEST_DEBUG_DATA 0x1B39 +#define mmDPG_TEST_DEBUG_INDEX 0x1B38 +#define mmDP_HBR2_EYE_PATTERN 0x1CC8 +#define mmDP_LINK_CNTL 0x1CC0 +#define mmDP_LINK_FRAMING_CNTL 0x1CCC +#define mmDP_MSA_COLORIMETRY 0x1CDA +#define mmDP_MSA_MISC 0x1CC5 +#define mmDP_MSA_V_TIMING_OVERRIDE1 0x1CEA +#define mmDP_MSA_V_TIMING_OVERRIDE2 0x1CEB +#define mmDP_MSE_LINK_TIMING 0x1CE8 +#define mmDP_MSE_MISC_CNTL 0x1CDB +#define mmDP_MSE_RATE_CNTL 0x1CE1 +#define mmDP_MSE_RATE_UPDATE 0x1CE3 +#define mmDP_MSE_SAT0 0x1CE4 +#define mmDP_MSE_SAT1 0x1CE5 +#define mmDP_MSE_SAT2 0x1CE6 +#define mmDP_MSE_SAT_UPDATE 0x1CE7 +#define mmDP_PIXEL_FORMAT 0x1CC1 +#define mmDP_SEC_AUD_M 0x1CA7 +#define mmDP_SEC_AUD_M_READBACK 0x1CA8 +#define mmDP_SEC_AUD_N 0x1CA5 +#define mmDP_SEC_AUD_N_READBACK 0x1CA6 +#define mmDP_SEC_CNTL 0x1CA0 +#define mmDP_SEC_CNTL1 0x1CAB +#define mmDP_SEC_FRAMING1 0x1CA1 +#define mmDP_SEC_FRAMING2 0x1CA2 +#define mmDP_SEC_FRAMING3 0x1CA3 +#define mmDP_SEC_FRAMING4 0x1CA4 +#define mmDP_SEC_PACKET_CNTL 0x1CAA +#define mmDP_SEC_TIMESTAMP 0x1CA9 +#define mmDP_STEER_FIFO 0x1CC4 +#define mmDP_TEST_DEBUG_DATA 0x1CFD +#define mmDP_TEST_DEBUG_INDEX 0x1CFC +#define mmDP_VID_INTERRUPT_CNTL 0x1CCF +#define mmDP_VID_M 0x1CCB +#define mmDP_VID_MSA_VBID 0x1CCD +#define mmDP_VID_N 0x1CCA +#define mmDP_VID_STREAM_CNTL 0x1CC3 +#define mmDP_VID_TIMING 0x1CC9 +#define mmDVOACLKC_CNTL 0x016A +#define mmDVOACLKC_MVP_CNTL 0x0169 +#define mmDVOACLKD_CNTL 0x0168 +#define mmDVO_CLK_ENABLE 0x0129 +#define mmDVO_CONTROL 0x185B +#define mmDVO_CRC2_SIG_MASK 0x185D +#define mmDVO_CRC2_SIG_RESULT 0x185E +#define mmDVO_CRC_EN 0x185C +#define mmDVO_ENABLE 0x1858 +#define mmDVO_FIFO_ERROR_STATUS 0x185F +#define mmDVO_OUTPUT 0x185A +#define mmDVO_SKEW_ADJUST 0x197D +#define mmDVO_SOURCE_SELECT 0x1859 +#define mmDVO_STRENGTH_CONTROL 0x197B +#define mmDVO_VREF_CONTROL 0x197C +#define mmEXT_OVERSCAN_LEFT_RIGHT 0x1B5E +#define mmEXT_OVERSCAN_TOP_BOTTOM 0x1B5F +#define mmFBC_CLIENT_REGION_MASK 0x16EB +#define mmFBC_CNTL 0x16D0 +#define mmFBC_COMP_CNTL 0x16D4 +#define mmFBC_COMP_MODE 0x16D5 +#define mmFBC_CSM_REGION_OFFSET_01 0x16E9 +#define mmFBC_CSM_REGION_OFFSET_23 0x16EA +#define mmFBC_DEBUG0 0x16D6 +#define mmFBC_DEBUG1 0x16D7 +#define mmFBC_DEBUG2 0x16D8 +#define mmFBC_DEBUG_COMP 0x16EC +#define mmFBC_DEBUG_CSR 0x16ED +#define mmFBC_DEBUG_CSR_RDATA 0x16EE +#define mmFBC_DEBUG_CSR_RDATA_HI 0x16F6 +#define mmFBC_DEBUG_CSR_WDATA 0x16EF +#define mmFBC_DEBUG_CSR_WDATA_HI 0x16F7 +#define mmFBC_IDLE_FORCE_CLEAR_MASK 0x16D2 +#define mmFBC_IDLE_MASK 0x16D1 +#define mmFBC_IND_LUT0 0x16D9 +#define mmFBC_IND_LUT10 0x16E3 +#define mmFBC_IND_LUT1 0x16DA +#define mmFBC_IND_LUT11 0x16E4 +#define mmFBC_IND_LUT12 0x16E5 +#define mmFBC_IND_LUT13 0x16E6 +#define mmFBC_IND_LUT14 0x16E7 +#define mmFBC_IND_LUT15 0x16E8 +#define mmFBC_IND_LUT2 0x16DB +#define mmFBC_IND_LUT3 0x16DC +#define mmFBC_IND_LUT4 0x16DD +#define mmFBC_IND_LUT5 0x16DE +#define mmFBC_IND_LUT6 0x16DF +#define mmFBC_IND_LUT7 0x16E0 +#define mmFBC_IND_LUT8 0x16E1 +#define mmFBC_IND_LUT9 0x16E2 +#define mmFBC_MISC 0x16F0 +#define mmFBC_START_STOP_DELAY 0x16D3 +#define mmFBC_STATUS 0x16F1 +#define mmFBC_TEST_DEBUG_DATA 0x16F5 +#define mmFBC_TEST_DEBUG_INDEX 0x16F4 +#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1BF2 +#define mmFMT0_FMT_CLAMP_CNTL 0x1BF9 +#define mmFMT0_FMT_CONTROL 0x1BEE +#define mmFMT0_FMT_CRC_CNTL 0x1BFA +#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x1BFE +#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1BFC +#define mmFMT0_FMT_CRC_SIG_RED_GREEN 0x1BFD +#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x1BFB +#define mmFMT0_FMT_DEBUG_CNTL 0x1BFF +#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1BF5 +#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1BF4 +#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1BF3 +#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x1BED +#define mmFMT0_FMT_FORCE_DATA_0_1 0x1BF0 +#define mmFMT0_FMT_FORCE_DATA_2_3 0x1BF1 +#define mmFMT0_FMT_FORCE_OUTPUT_CNTL 0x1BEF +#define mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1BF6 +#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1BF7 +#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1BF8 +#define mmFMT0_FMT_TEST_DEBUG_DATA 0x1BEC +#define mmFMT0_FMT_TEST_DEBUG_INDEX 0x1BEB +#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x1EF2 +#define mmFMT1_FMT_CLAMP_CNTL 0x1EF9 +#define mmFMT1_FMT_CONTROL 0x1EEE +#define mmFMT1_FMT_CRC_CNTL 0x1EFA +#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x1EFE +#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1EFC +#define mmFMT1_FMT_CRC_SIG_RED_GREEN 0x1EFD +#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x1EFB +#define mmFMT1_FMT_DEBUG_CNTL 0x1EFF +#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x1EF5 +#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x1EF4 +#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x1EF3 +#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1EED +#define mmFMT1_FMT_FORCE_DATA_0_1 0x1EF0 +#define mmFMT1_FMT_FORCE_DATA_2_3 0x1EF1 +#define mmFMT1_FMT_FORCE_OUTPUT_CNTL 0x1EEF +#define mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1EF6 +#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1EF7 +#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1EF8 +#define mmFMT1_FMT_TEST_DEBUG_DATA 0x1EEC +#define mmFMT1_FMT_TEST_DEBUG_INDEX 0x1EEB +#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x41F2 +#define mmFMT2_FMT_CLAMP_CNTL 0x41F9 +#define mmFMT2_FMT_CONTROL 0x41EE +#define mmFMT2_FMT_CRC_CNTL 0x41FA +#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x41FE +#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x41FC +#define mmFMT2_FMT_CRC_SIG_RED_GREEN 0x41FD +#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x41FB +#define mmFMT2_FMT_DEBUG_CNTL 0x41FF +#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x41F5 +#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x41F4 +#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x41F3 +#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x41ED +#define mmFMT2_FMT_FORCE_DATA_0_1 0x41F0 +#define mmFMT2_FMT_FORCE_DATA_2_3 0x41F1 +#define mmFMT2_FMT_FORCE_OUTPUT_CNTL 0x41EF +#define mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x41F6 +#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x41F7 +#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x41F8 +#define mmFMT2_FMT_TEST_DEBUG_DATA 0x41EC +#define mmFMT2_FMT_TEST_DEBUG_INDEX 0x41EB +#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x44F2 +#define mmFMT3_FMT_CLAMP_CNTL 0x44F9 +#define mmFMT3_FMT_CONTROL 0x44EE +#define mmFMT3_FMT_CRC_CNTL 0x44FA +#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x44FE +#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x44FC +#define mmFMT3_FMT_CRC_SIG_RED_GREEN 0x44FD +#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x44FB +#define mmFMT3_FMT_DEBUG_CNTL 0x44FF +#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x44F5 +#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x44F4 +#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x44F3 +#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x44ED +#define mmFMT3_FMT_FORCE_DATA_0_1 0x44F0 +#define mmFMT3_FMT_FORCE_DATA_2_3 0x44F1 +#define mmFMT3_FMT_FORCE_OUTPUT_CNTL 0x44EF +#define mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x44F6 +#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x44F7 +#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x44F8 +#define mmFMT3_FMT_TEST_DEBUG_DATA 0x44EC +#define mmFMT3_FMT_TEST_DEBUG_INDEX 0x44EB +#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x47F2 +#define mmFMT4_FMT_CLAMP_CNTL 0x47F9 +#define mmFMT4_FMT_CONTROL 0x47EE +#define mmFMT4_FMT_CRC_CNTL 0x47FA +#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x47FE +#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x47FC +#define mmFMT4_FMT_CRC_SIG_RED_GREEN 0x47FD +#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x47FB +#define mmFMT4_FMT_DEBUG_CNTL 0x47FF +#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x47F5 +#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x47F4 +#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x47F3 +#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x47ED +#define mmFMT4_FMT_FORCE_DATA_0_1 0x47F0 +#define mmFMT4_FMT_FORCE_DATA_2_3 0x47F1 +#define mmFMT4_FMT_FORCE_OUTPUT_CNTL 0x47EF +#define mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x47F6 +#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x47F7 +#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x47F8 +#define mmFMT4_FMT_TEST_DEBUG_DATA 0x47EC +#define mmFMT4_FMT_TEST_DEBUG_INDEX 0x47EB +#define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x4AF2 +#define mmFMT5_FMT_CLAMP_CNTL 0x4AF9 +#define mmFMT5_FMT_CONTROL 0x4AEE +#define mmFMT5_FMT_CRC_CNTL 0x4AFA +#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x4AFE +#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x4AFC +#define mmFMT5_FMT_CRC_SIG_RED_GREEN 0x4AFD +#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x4AFB +#define mmFMT5_FMT_DEBUG_CNTL 0x4AFF +#define mmFMT5_FMT_DITHER_RAND_B_SEED 0x4AF5 +#define mmFMT5_FMT_DITHER_RAND_G_SEED 0x4AF4 +#define mmFMT5_FMT_DITHER_RAND_R_SEED 0x4AF3 +#define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x4AED +#define mmFMT5_FMT_FORCE_DATA_0_1 0x4AF0 +#define mmFMT5_FMT_FORCE_DATA_2_3 0x4AF1 +#define mmFMT5_FMT_FORCE_OUTPUT_CNTL 0x4AEF +#define mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x4AF6 +#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x4AF7 +#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x4AF8 +#define mmFMT5_FMT_TEST_DEBUG_DATA 0x4AEC +#define mmFMT5_FMT_TEST_DEBUG_INDEX 0x4AEB +#define mmFMT_BIT_DEPTH_CONTROL 0x1BF2 +#define mmFMT_CLAMP_CNTL 0x1BF9 +#define mmFMT_CONTROL 0x1BEE +#define mmFMT_CRC_CNTL 0x1BFA +#define mmFMT_CRC_SIG_BLUE_CONTROL 0x1BFE +#define mmFMT_CRC_SIG_BLUE_CONTROL_MASK 0x1BFC +#define mmFMT_CRC_SIG_RED_GREEN 0x1BFD +#define mmFMT_CRC_SIG_RED_GREEN_MASK 0x1BFB +#define mmFMT_DEBUG_CNTL 0x1BFF +#define mmFMT_DITHER_RAND_B_SEED 0x1BF5 +#define mmFMT_DITHER_RAND_G_SEED 0x1BF4 +#define mmFMT_DITHER_RAND_R_SEED 0x1BF3 +#define mmFMT_DYNAMIC_EXP_CNTL 0x1BED +#define mmFMT_FORCE_DATA_0_1 0x1BF0 +#define mmFMT_FORCE_DATA_2_3 0x1BF1 +#define mmFMT_FORCE_OUTPUT_CNTL 0x1BEF +#define mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1BF6 +#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1BF7 +#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1BF8 +#define mmFMT_TEST_DEBUG_DATA 0x1BEC +#define mmFMT_TEST_DEBUG_INDEX 0x1BEB +#define mmGAMUT_REMAP_C11_C12 0x1A5A +#define mmGAMUT_REMAP_C13_C14 0x1A5B +#define mmGAMUT_REMAP_C21_C22 0x1A5C +#define mmGAMUT_REMAP_C23_C24 0x1A5D +#define mmGAMUT_REMAP_C31_C32 0x1A5E +#define mmGAMUT_REMAP_C33_C34 0x1A5F +#define mmGAMUT_REMAP_CONTROL 0x1A59 +#define mmGENENB 0x00F0 +#define mmGENERIC_I2C_CONTROL 0x1834 +#define mmGENERIC_I2C_DATA 0x183A +#define mmGENERIC_I2C_INTERRUPT_CONTROL 0x1835 +#define mmGENERIC_I2C_PIN_DEBUG 0x183C +#define mmGENERIC_I2C_PIN_SELECTION 0x183B +#define mmGENERIC_I2C_SETUP 0x1838 +#define mmGENERIC_I2C_SPEED 0x1837 +#define mmGENERIC_I2C_STATUS 0x1836 +#define mmGENERIC_I2C_TRANSACTION 0x1839 +#define mmGENFC_RD 0x00F2 +#define mmGENFC_WT 0x00EE +#define mmGENMO_RD 0x00F3 +#define mmGENMO_WT 0x00F0 +#define mmGENS0 0x00F0 +#define mmGENS1 0x00EE +#define mmGRPH8_DATA 0x00F3 +#define mmGRPH8_IDX 0x00F3 +#define mmGRPH_COMPRESS_PITCH 0x1A1A +#define mmGRPH_COMPRESS_SURFACE_ADDRESS 0x1A19 +#define mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1A1B +#define mmGRPH_CONTROL 0x1A01 +#define mmGRPH_DFQ_CONTROL 0x1A14 +#define mmGRPH_DFQ_STATUS 0x1A15 +#define mmGRPH_ENABLE 0x1A00 +#define mmGRPH_FLIP_CONTROL 0x1A12 +#define mmGRPH_INTERRUPT_CONTROL 0x1A17 +#define mmGRPH_INTERRUPT_STATUS 0x1A16 +#define mmGRPH_LUT_10BIT_BYPASS 0x1A02 +#define mmGRPH_PITCH 0x1A06 +#define mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1A04 +#define mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1A07 +#define mmGRPH_SECONDARY_SURFACE_ADDRESS 0x1A05 +#define mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1A08 +#define mmGRPH_STEREOSYNC_FLIP 0x1A97 +#define mmGRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1A18 +#define mmGRPH_SURFACE_ADDRESS_INUSE 0x1A13 +#define mmGRPH_SURFACE_OFFSET_X 0x1A09 +#define mmGRPH_SURFACE_OFFSET_Y 0x1A0A +#define mmGRPH_SWAP_CNTL 0x1A03 +#define mmGRPH_UPDATE 0x1A11 +#define mmGRPH_X_END 0x1A0D +#define mmGRPH_X_START 0x1A0B +#define mmGRPH_Y_END 0x1A0E +#define mmGRPH_Y_START 0x1A0C +#define mmHDMI_ACR_32_0 0x1C37 +#define mmHDMI_ACR_32_1 0x1C38 +#define mmHDMI_ACR_44_0 0x1C39 +#define mmHDMI_ACR_44_1 0x1C3A +#define mmHDMI_ACR_48_0 0x1C3B +#define mmHDMI_ACR_48_1 0x1C3C +#define mmHDMI_ACR_PACKET_CONTROL 0x1C0F +#define mmHDMI_ACR_STATUS_0 0x1C3D +#define mmHDMI_ACR_STATUS_1 0x1C3E +#define mmHDMI_AUDIO_PACKET_CONTROL 0x1C0E +#define mmHDMI_CONTROL 0x1C0C +#define mmHDMI_GC 0x1C16 +#define mmHDMI_GENERIC_PACKET_CONTROL0 0x1C13 +#define mmHDMI_GENERIC_PACKET_CONTROL1 0x1C30 +#define mmHDMI_INFOFRAME_CONTROL0 0x1C11 +#define mmHDMI_INFOFRAME_CONTROL1 0x1C12 +#define mmHDMI_STATUS 0x1C0D +#define mmHDMI_VBI_PACKET_CONTROL 0x1C10 +#define mmINPUT_CSC_C11_C12 0x1A36 +#define mmINPUT_CSC_C13_C14 0x1A37 +#define mmINPUT_CSC_C21_C22 0x1A38 +#define mmINPUT_CSC_C23_C24 0x1A39 +#define mmINPUT_CSC_C31_C32 0x1A3A +#define mmINPUT_CSC_C33_C34 0x1A3B +#define mmINPUT_CSC_CONTROL 0x1A35 +#define mmINPUT_GAMMA_CONTROL 0x1A10 +#define mmKEY_CONTROL 0x1A53 +#define mmKEY_RANGE_ALPHA 0x1A54 +#define mmKEY_RANGE_BLUE 0x1A57 +#define mmKEY_RANGE_GREEN 0x1A56 +#define mmKEY_RANGE_RED 0x1A55 +#define mmLB0_DC_MVP_LB_CONTROL 0x1ADB +#define mmLB0_LB_DEBUG 0x1AFC +#define mmLB0_LB_DEBUG2 0x1AC9 +#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x1AC8 +#define mmLB0_LB_SYNC_RESET_SEL 0x1ACA +#define mmLB0_LB_TEST_DEBUG_DATA 0x1AFF +#define mmLB0_LB_TEST_DEBUG_INDEX 0x1AFE +#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x1AD9 +#define mmLB0_MVP_AFR_FLIP_MODE 0x1AD8 +#define mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x1ADA +#define mmLB1_DC_MVP_LB_CONTROL 0x1DDB +#define mmLB1_LB_DEBUG 0x1DFC +#define mmLB1_LB_DEBUG2 0x1DC9 +#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x1DC8 +#define mmLB1_LB_SYNC_RESET_SEL 0x1DCA +#define mmLB1_LB_TEST_DEBUG_DATA 0x1DFF +#define mmLB1_LB_TEST_DEBUG_INDEX 0x1DFE +#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x1DD9 +#define mmLB1_MVP_AFR_FLIP_MODE 0x1DD8 +#define mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x1DDA +#define mmLB2_DC_MVP_LB_CONTROL 0x40DB +#define mmLB2_LB_DEBUG 0x40FC +#define mmLB2_LB_DEBUG2 0x40C9 +#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x40C8 +#define mmLB2_LB_SYNC_RESET_SEL 0x40CA +#define mmLB2_LB_TEST_DEBUG_DATA 0x40FF +#define mmLB2_LB_TEST_DEBUG_INDEX 0x40FE +#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x40D9 +#define mmLB2_MVP_AFR_FLIP_MODE 0x40D8 +#define mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x40DA +#define mmLB3_DC_MVP_LB_CONTROL 0x43DB +#define mmLB3_LB_DEBUG 0x43FC +#define mmLB3_LB_DEBUG2 0x43C9 +#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x43C8 +#define mmLB3_LB_SYNC_RESET_SEL 0x43CA +#define mmLB3_LB_TEST_DEBUG_DATA 0x43FF +#define mmLB3_LB_TEST_DEBUG_INDEX 0x43FE +#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x43D9 +#define mmLB3_MVP_AFR_FLIP_MODE 0x43D8 +#define mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x43DA +#define mmLB4_DC_MVP_LB_CONTROL 0x46DB +#define mmLB4_LB_DEBUG 0x46FC +#define mmLB4_LB_DEBUG2 0x46C9 +#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x46C8 +#define mmLB4_LB_SYNC_RESET_SEL 0x46CA +#define mmLB4_LB_TEST_DEBUG_DATA 0x46FF +#define mmLB4_LB_TEST_DEBUG_INDEX 0x46FE +#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x46D9 +#define mmLB4_MVP_AFR_FLIP_MODE 0x46D8 +#define mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x46DA +#define mmLB5_DC_MVP_LB_CONTROL 0x49DB +#define mmLB5_LB_DEBUG 0x49FC +#define mmLB5_LB_DEBUG2 0x49C9 +#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x49C8 +#define mmLB5_LB_SYNC_RESET_SEL 0x49CA +#define mmLB5_LB_TEST_DEBUG_DATA 0x49FF +#define mmLB5_LB_TEST_DEBUG_INDEX 0x49FE +#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x49D9 +#define mmLB5_MVP_AFR_FLIP_MODE 0x49D8 +#define mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x49DA +#define mmLB_DEBUG 0x1AFC +#define mmLB_DEBUG2 0x1AC9 +#define mmLB_NO_OUTSTANDING_REQ_STATUS 0x1AC8 +#define mmLB_SYNC_RESET_SEL 0x1ACA +#define mmLB_TEST_DEBUG_DATA 0x1AFF +#define mmLB_TEST_DEBUG_INDEX 0x1AFE +#define mmLIGHT_SLEEP_CNTL 0x0132 +#define mmLOW_POWER_TILING_CONTROL 0x0325 +#define mmLVDS_DATA_CNTL 0x1C8C +#define mmLVTMA_PWRSEQ_CNTL 0x1919 +#define mmLVTMA_PWRSEQ_DELAY1 0x191C +#define mmLVTMA_PWRSEQ_DELAY2 0x191D +#define mmLVTMA_PWRSEQ_REF_DIV 0x191B +#define mmLVTMA_PWRSEQ_STATE 0x191A +#define mmMASTER_COMM_CMD_REG 0x161F +#define mmMASTER_COMM_CNTL_REG 0x1620 +#define mmMASTER_COMM_DATA_REG1 0x161C +#define mmMASTER_COMM_DATA_REG2 0x161D +#define mmMASTER_COMM_DATA_REG3 0x161E +#define mmMASTER_UPDATE_LOCK 0x1BBD +#define mmMASTER_UPDATE_MODE 0x1BBE +#define mmMC_DC_INTERFACE_NACK_STATUS 0x031C +#define mmMCIF_CONTROL 0x0314 +#define mmMCIF_MEM_CONTROL 0x0319 +#define mmMCIF_TEST_DEBUG_DATA 0x0317 +#define mmMCIF_TEST_DEBUG_INDEX 0x0316 +#define mmMCIF_VMID 0x0318 +#define mmMCIF_WRITE_COMBINE_CONTROL 0x0315 +#define mmMICROSECOND_TIME_BASE_DIV 0x013B +#define mmMILLISECOND_TIME_BASE_DIV 0x0130 +#define mmMVP_AFR_FLIP_FIFO_CNTL 0x1AD9 +#define mmMVP_AFR_FLIP_MODE 0x1AD8 +#define mmMVP_BLACK_KEYER 0x1686 +#define mmMVP_CONTROL1 0x1680 +#define mmMVP_CONTROL2 0x1681 +#define mmMVP_CONTROL3 0x168A +#define mmMVP_CRC_CNTL 0x1687 +#define mmMVP_CRC_RESULT_BLUE_GREEN 0x1688 +#define mmMVP_CRC_RESULT_RED 0x1689 +#define mmMVP_DEBUG 0x168F +#define mmMVP_FIFO_CONTROL 0x1682 +#define mmMVP_FIFO_STATUS 0x1683 +#define mmMVP_FLIP_LINE_NUM_INSERT 0x1ADA +#define mmMVP_INBAND_CNTL_CAP 0x1685 +#define mmMVP_RECEIVE_CNT_CNTL1 0x168B +#define mmMVP_RECEIVE_CNT_CNTL2 0x168C +#define mmMVP_SLAVE_STATUS 0x1684 +#define mmMVP_TEST_DEBUG_DATA 0x168E +#define mmMVP_TEST_DEBUG_INDEX 0x168D +#define mmOUTPUT_CSC_C11_C12 0x1A3D +#define mmOUTPUT_CSC_C13_C14 0x1A3E +#define mmOUTPUT_CSC_C21_C22 0x1A3F +#define mmOUTPUT_CSC_C23_C24 0x1A40 +#define mmOUTPUT_CSC_C31_C32 0x1A41 +#define mmOUTPUT_CSC_C33_C34 0x1A42 +#define mmOUTPUT_CSC_CONTROL 0x1A3C +#define mmOUT_ROUND_CONTROL 0x1A51 +#define mmOVL_CONTROL1 0x1A1D +#define mmOVL_CONTROL2 0x1A1E +#define mmOVL_DFQ_CONTROL 0x1A29 +#define mmOVL_DFQ_STATUS 0x1A2A +#define mmOVL_ENABLE 0x1A1C +#define mmOVL_END 0x1A26 +#define mmOVL_PITCH 0x1A21 +#define mmOVLSCL_EDGE_PIXEL_CNTL 0x1A2C +#define mmOVL_SECONDARY_SURFACE_ADDRESS 0x1A92 +#define mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1A94 +#define mmOVL_START 0x1A25 +#define mmOVL_STEREOSYNC_FLIP 0x1A93 +#define mmOVL_SURFACE_ADDRESS 0x1A20 +#define mmOVL_SURFACE_ADDRESS_HIGH 0x1A22 +#define mmOVL_SURFACE_ADDRESS_HIGH_INUSE 0x1A2B +#define mmOVL_SURFACE_ADDRESS_INUSE 0x1A28 +#define mmOVL_SURFACE_OFFSET_X 0x1A23 +#define mmOVL_SURFACE_OFFSET_Y 0x1A24 +#define mmOVL_SWAP_CNTL 0x1A1F +#define mmOVL_UPDATE 0x1A27 +#define mmPHY_AUX_CNTL 0x197F +#define mmPIPE0_ARBITRATION_CONTROL3 0x02FA +#define mmPIPE0_DMIF_BUFFER_CONTROL 0x0328 +#define mmPIPE0_MAX_REQUESTS 0x0302 +#define mmPIPE0_PG_CONFIG 0x1760 +#define mmPIPE0_PG_ENABLE 0x1761 +#define mmPIPE0_PG_STATUS 0x1762 +#define mmPIPE1_ARBITRATION_CONTROL3 0x02FB +#define mmPIPE1_DMIF_BUFFER_CONTROL 0x0330 +#define mmPIPE1_MAX_REQUESTS 0x0303 +#define mmPIPE1_PG_CONFIG 0x1764 +#define mmPIPE1_PG_ENABLE 0x1765 +#define mmPIPE1_PG_STATUS 0x1766 +#define mmPIPE2_ARBITRATION_CONTROL3 0x02FC +#define mmPIPE2_DMIF_BUFFER_CONTROL 0x0338 +#define mmPIPE2_MAX_REQUESTS 0x0304 +#define mmPIPE2_PG_CONFIG 0x1768 +#define mmPIPE2_PG_ENABLE 0x1769 +#define mmPIPE2_PG_STATUS 0x176A +#define mmPIPE3_ARBITRATION_CONTROL3 0x02FD +#define mmPIPE3_DMIF_BUFFER_CONTROL 0x0340 +#define mmPIPE3_MAX_REQUESTS 0x0305 +#define mmPIPE3_PG_CONFIG 0x176C +#define mmPIPE3_PG_ENABLE 0x176D +#define mmPIPE3_PG_STATUS 0x176E +#define mmPIPE4_ARBITRATION_CONTROL3 0x02FE +#define mmPIPE4_DMIF_BUFFER_CONTROL 0x0348 +#define mmPIPE4_MAX_REQUESTS 0x0306 +#define mmPIPE4_PG_CONFIG 0x1770 +#define mmPIPE4_PG_ENABLE 0x1771 +#define mmPIPE4_PG_STATUS 0x1772 +#define mmPIPE5_ARBITRATION_CONTROL3 0x02FF +#define mmPIPE5_DMIF_BUFFER_CONTROL 0x0350 +#define mmPIPE5_MAX_REQUESTS 0x0307 +#define mmPIPE5_PG_CONFIG 0x1774 +#define mmPIPE5_PG_ENABLE 0x1775 +#define mmPIPE5_PG_STATUS 0x1776 +#define mmPIXCLK0_RESYNC_CNTL 0x013A +#define mmPIXCLK1_RESYNC_CNTL 0x0138 +#define mmPIXCLK2_RESYNC_CNTL 0x0139 +#define mmPLL_ANALOG 0x1708 +#define mmPLL_CNTL 0x1707 +#define mmPLL_DEBUG_CNTL 0x170B +#define mmPLL_DISPCLK_CURRENT_DTO_PHASE 0x170F +#define mmPLL_DISPCLK_DTO_CNTL 0x170E +#define mmPLL_DS_CNTL 0x1705 +#define mmPLL_FB_DIV 0x1701 +#define mmPLL_IDCLK_CNTL 0x1706 +#define mmPLL_POST_DIV 0x1702 +#define mmPLL_REF_DIV 0x1700 +#define mmPLL_SS_AMOUNT_DSFRAC 0x1703 +#define mmPLL_SS_CNTL 0x1704 +#define mmPLL_UNLOCK_DETECT_CNTL 0x170A +#define mmPLL_UPDATE_CNTL 0x170D +#define mmPLL_UPDATE_LOCK 0x170C +#define mmPLL_VREG_CNTL 0x1709 +#define mmPRESCALE_GRPH_CONTROL 0x1A2D +#define mmPRESCALE_OVL_CONTROL 0x1A31 +#define mmPRESCALE_VALUES_GRPH_B 0x1A30 +#define mmPRESCALE_VALUES_GRPH_G 0x1A2F +#define mmPRESCALE_VALUES_GRPH_R 0x1A2E +#define mmPRESCALE_VALUES_OVL_CB 0x1A32 +#define mmPRESCALE_VALUES_OVL_CR 0x1A34 +#define mmPRESCALE_VALUES_OVL_Y 0x1A33 +#define mmREGAMMA_CNTLA_END_CNTL1 0x1AA6 +#define mmREGAMMA_CNTLA_END_CNTL2 0x1AA7 +#define mmREGAMMA_CNTLA_REGION_0_1 0x1AA8 +#define mmREGAMMA_CNTLA_REGION_10_11 0x1AAD +#define mmREGAMMA_CNTLA_REGION_12_13 0x1AAE +#define mmREGAMMA_CNTLA_REGION_14_15 0x1AAF +#define mmREGAMMA_CNTLA_REGION_2_3 0x1AA9 +#define mmREGAMMA_CNTLA_REGION_4_5 0x1AAA +#define mmREGAMMA_CNTLA_REGION_6_7 0x1AAB +#define mmREGAMMA_CNTLA_REGION_8_9 0x1AAC +#define mmREGAMMA_CNTLA_SLOPE_CNTL 0x1AA5 +#define mmREGAMMA_CNTLA_START_CNTL 0x1AA4 +#define mmREGAMMA_CNTLB_END_CNTL1 0x1AB2 +#define mmREGAMMA_CNTLB_END_CNTL2 0x1AB3 +#define mmREGAMMA_CNTLB_REGION_0_1 0x1AB4 +#define mmREGAMMA_CNTLB_REGION_10_11 0x1AB9 +#define mmREGAMMA_CNTLB_REGION_12_13 0x1ABA +#define mmREGAMMA_CNTLB_REGION_14_15 0x1ABB +#define mmREGAMMA_CNTLB_REGION_2_3 0x1AB5 +#define mmREGAMMA_CNTLB_REGION_4_5 0x1AB6 +#define mmREGAMMA_CNTLB_REGION_6_7 0x1AB7 +#define mmREGAMMA_CNTLB_REGION_8_9 0x1AB8 +#define mmREGAMMA_CNTLB_SLOPE_CNTL 0x1AB1 +#define mmREGAMMA_CNTLB_START_CNTL 0x1AB0 +#define mmREGAMMA_CONTROL 0x1AA0 +#define mmREGAMMA_LUT_DATA 0x1AA2 +#define mmREGAMMA_LUT_INDEX 0x1AA1 +#define mmREGAMMA_LUT_WRITE_EN_MASK 0x1AA3 +#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x1B5E +#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x1B5F +#define mmSCL0_SCL_ALU_CONTROL 0x1B54 +#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x1B47 +#define mmSCL0_SCL_BYPASS_CONTROL 0x1B45 +#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1B55 +#define mmSCL0_SCL_COEF_RAM_SELECT 0x1B40 +#define mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1B41 +#define mmSCL0_SCL_CONTROL 0x1B44 +#define mmSCL0_SCL_DEBUG 0x1B6A +#define mmSCL0_SCL_DEBUG2 0x1B69 +#define mmSCL0_SCL_F_SHARP_CONTROL 0x1B53 +#define mmSCL0_SCL_HORZ_FILTER_CONTROL 0x1B4A +#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x1B4B +#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x1B46 +#define mmSCL0_SCL_MODE_CHANGE_DET1 0x1B60 +#define mmSCL0_SCL_MODE_CHANGE_DET2 0x1B61 +#define mmSCL0_SCL_MODE_CHANGE_DET3 0x1B62 +#define mmSCL0_SCL_MODE_CHANGE_MASK 0x1B63 +#define mmSCL0_SCL_TAP_CONTROL 0x1B43 +#define mmSCL0_SCL_TEST_DEBUG_DATA 0x1B6C +#define mmSCL0_SCL_TEST_DEBUG_INDEX 0x1B6B +#define mmSCL0_SCL_UPDATE 0x1B51 +#define mmSCL0_SCL_VERT_FILTER_CONTROL 0x1B4E +#define mmSCL0_SCL_VERT_FILTER_INIT 0x1B50 +#define mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x1B57 +#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x1B4F +#define mmSCL0_VIEWPORT_SIZE 0x1B5D +#define mmSCL0_VIEWPORT_START 0x1B5C +#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x1E5E +#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x1E5F +#define mmSCL1_SCL_ALU_CONTROL 0x1E54 +#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x1E47 +#define mmSCL1_SCL_BYPASS_CONTROL 0x1E45 +#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1E55 +#define mmSCL1_SCL_COEF_RAM_SELECT 0x1E40 +#define mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1E41 +#define mmSCL1_SCL_CONTROL 0x1E44 +#define mmSCL1_SCL_DEBUG 0x1E6A +#define mmSCL1_SCL_DEBUG2 0x1E69 +#define mmSCL1_SCL_F_SHARP_CONTROL 0x1E53 +#define mmSCL1_SCL_HORZ_FILTER_CONTROL 0x1E4A +#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x1E4B +#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x1E46 +#define mmSCL1_SCL_MODE_CHANGE_DET1 0x1E60 +#define mmSCL1_SCL_MODE_CHANGE_DET2 0x1E61 +#define mmSCL1_SCL_MODE_CHANGE_DET3 0x1E62 +#define mmSCL1_SCL_MODE_CHANGE_MASK 0x1E63 +#define mmSCL1_SCL_TAP_CONTROL 0x1E43 +#define mmSCL1_SCL_TEST_DEBUG_DATA 0x1E6C +#define mmSCL1_SCL_TEST_DEBUG_INDEX 0x1E6B +#define mmSCL1_SCL_UPDATE 0x1E51 +#define mmSCL1_SCL_VERT_FILTER_CONTROL 0x1E4E +#define mmSCL1_SCL_VERT_FILTER_INIT 0x1E50 +#define mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x1E57 +#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x1E4F +#define mmSCL1_VIEWPORT_SIZE 0x1E5D +#define mmSCL1_VIEWPORT_START 0x1E5C +#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x415E +#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x415F +#define mmSCL2_SCL_ALU_CONTROL 0x4154 +#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x4147 +#define mmSCL2_SCL_BYPASS_CONTROL 0x4145 +#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x4155 +#define mmSCL2_SCL_COEF_RAM_SELECT 0x4140 +#define mmSCL2_SCL_COEF_RAM_TAP_DATA 0x4141 +#define mmSCL2_SCL_CONTROL 0x4144 +#define mmSCL2_SCL_DEBUG 0x416A +#define mmSCL2_SCL_DEBUG2 0x4169 +#define mmSCL2_SCL_F_SHARP_CONTROL 0x4153 +#define mmSCL2_SCL_HORZ_FILTER_CONTROL 0x414A +#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x414B +#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x4146 +#define mmSCL2_SCL_MODE_CHANGE_DET1 0x4160 +#define mmSCL2_SCL_MODE_CHANGE_DET2 0x4161 +#define mmSCL2_SCL_MODE_CHANGE_DET3 0x4162 +#define mmSCL2_SCL_MODE_CHANGE_MASK 0x4163 +#define mmSCL2_SCL_TAP_CONTROL 0x4143 +#define mmSCL2_SCL_TEST_DEBUG_DATA 0x416C +#define mmSCL2_SCL_TEST_DEBUG_INDEX 0x416B +#define mmSCL2_SCL_UPDATE 0x4151 +#define mmSCL2_SCL_VERT_FILTER_CONTROL 0x414E +#define mmSCL2_SCL_VERT_FILTER_INIT 0x4150 +#define mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x4157 +#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x414F +#define mmSCL2_VIEWPORT_SIZE 0x415D +#define mmSCL2_VIEWPORT_START 0x415C +#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x445E +#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x445F +#define mmSCL3_SCL_ALU_CONTROL 0x4454 +#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x4447 +#define mmSCL3_SCL_BYPASS_CONTROL 0x4445 +#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4455 +#define mmSCL3_SCL_COEF_RAM_SELECT 0x4440 +#define mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4441 +#define mmSCL3_SCL_CONTROL 0x4444 +#define mmSCL3_SCL_DEBUG 0x446A +#define mmSCL3_SCL_DEBUG2 0x4469 +#define mmSCL3_SCL_F_SHARP_CONTROL 0x4453 +#define mmSCL3_SCL_HORZ_FILTER_CONTROL 0x444A +#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x444B +#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x4446 +#define mmSCL3_SCL_MODE_CHANGE_DET1 0x4460 +#define mmSCL3_SCL_MODE_CHANGE_DET2 0x4461 +#define mmSCL3_SCL_MODE_CHANGE_DET3 0x4462 +#define mmSCL3_SCL_MODE_CHANGE_MASK 0x4463 +#define mmSCL3_SCL_TAP_CONTROL 0x4443 +#define mmSCL3_SCL_TEST_DEBUG_DATA 0x446C +#define mmSCL3_SCL_TEST_DEBUG_INDEX 0x446B +#define mmSCL3_SCL_UPDATE 0x4451 +#define mmSCL3_SCL_VERT_FILTER_CONTROL 0x444E +#define mmSCL3_SCL_VERT_FILTER_INIT 0x4450 +#define mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x4457 +#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x444F +#define mmSCL3_VIEWPORT_SIZE 0x445D +#define mmSCL3_VIEWPORT_START 0x445C +#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x475E +#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x475F +#define mmSCL4_SCL_ALU_CONTROL 0x4754 +#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x4747 +#define mmSCL4_SCL_BYPASS_CONTROL 0x4745 +#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4755 +#define mmSCL4_SCL_COEF_RAM_SELECT 0x4740 +#define mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4741 +#define mmSCL4_SCL_CONTROL 0x4744 +#define mmSCL4_SCL_DEBUG 0x476A +#define mmSCL4_SCL_DEBUG2 0x4769 +#define mmSCL4_SCL_F_SHARP_CONTROL 0x4753 +#define mmSCL4_SCL_HORZ_FILTER_CONTROL 0x474A +#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x474B +#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x4746 +#define mmSCL4_SCL_MODE_CHANGE_DET1 0x4760 +#define mmSCL4_SCL_MODE_CHANGE_DET2 0x4761 +#define mmSCL4_SCL_MODE_CHANGE_DET3 0x4762 +#define mmSCL4_SCL_MODE_CHANGE_MASK 0x4763 +#define mmSCL4_SCL_TAP_CONTROL 0x4743 +#define mmSCL4_SCL_TEST_DEBUG_DATA 0x476C +#define mmSCL4_SCL_TEST_DEBUG_INDEX 0x476B +#define mmSCL4_SCL_UPDATE 0x4751 +#define mmSCL4_SCL_VERT_FILTER_CONTROL 0x474E +#define mmSCL4_SCL_VERT_FILTER_INIT 0x4750 +#define mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x4757 +#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x474F +#define mmSCL4_VIEWPORT_SIZE 0x475D +#define mmSCL4_VIEWPORT_START 0x475C +#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x4A5E +#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x4A5F +#define mmSCL5_SCL_ALU_CONTROL 0x4A54 +#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x4A47 +#define mmSCL5_SCL_BYPASS_CONTROL 0x4A45 +#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4A55 +#define mmSCL5_SCL_COEF_RAM_SELECT 0x4A40 +#define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4A41 +#define mmSCL5_SCL_CONTROL 0x4A44 +#define mmSCL5_SCL_DEBUG 0x4A6A +#define mmSCL5_SCL_DEBUG2 0x4A69 +#define mmSCL5_SCL_F_SHARP_CONTROL 0x4A53 +#define mmSCL5_SCL_HORZ_FILTER_CONTROL 0x4A4A +#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x4A4B +#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x4A46 +#define mmSCL5_SCL_MODE_CHANGE_DET1 0x4A60 +#define mmSCL5_SCL_MODE_CHANGE_DET2 0x4A61 +#define mmSCL5_SCL_MODE_CHANGE_DET3 0x4A62 +#define mmSCL5_SCL_MODE_CHANGE_MASK 0x4A63 +#define mmSCL5_SCL_TAP_CONTROL 0x4A43 +#define mmSCL5_SCL_TEST_DEBUG_DATA 0x4A6C +#define mmSCL5_SCL_TEST_DEBUG_INDEX 0x4A6B +#define mmSCL5_SCL_UPDATE 0x4A51 +#define mmSCL5_SCL_VERT_FILTER_CONTROL 0x4A4E +#define mmSCL5_SCL_VERT_FILTER_INIT 0x4A50 +#define mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x4A57 +#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x4A4F +#define mmSCL5_VIEWPORT_SIZE 0x4A5D +#define mmSCL5_VIEWPORT_START 0x4A5C +#define mmSCL_ALU_CONTROL 0x1B54 +#define mmSCL_AUTOMATIC_MODE_CONTROL 0x1B47 +#define mmSCL_BYPASS_CONTROL 0x1B45 +#define mmSCL_COEF_RAM_CONFLICT_STATUS 0x1B55 +#define mmSCL_COEF_RAM_SELECT 0x1B40 +#define mmSCL_COEF_RAM_TAP_DATA 0x1B41 +#define mmSCL_CONTROL 0x1B44 +#define mmSCL_DEBUG 0x1B6A +#define mmSCL_DEBUG2 0x1B69 +#define mmSCL_F_SHARP_CONTROL 0x1B53 +#define mmSCL_HORZ_FILTER_CONTROL 0x1B4A +#define mmSCL_HORZ_FILTER_SCALE_RATIO 0x1B4B +#define mmSCLK_CGTT_BLK_CTRL_REG 0x0136 +#define mmSCL_MANUAL_REPLICATE_CONTROL 0x1B46 +#define mmSCL_MODE_CHANGE_DET1 0x1B60 +#define mmSCL_MODE_CHANGE_DET2 0x1B61 +#define mmSCL_MODE_CHANGE_DET3 0x1B62 +#define mmSCL_MODE_CHANGE_MASK 0x1B63 +#define mmSCL_TAP_CONTROL 0x1B43 +#define mmSCL_TEST_DEBUG_DATA 0x1B6C +#define mmSCL_TEST_DEBUG_INDEX 0x1B6B +#define mmSCL_UPDATE 0x1B51 +#define mmSCL_VERT_FILTER_CONTROL 0x1B4E +#define mmSCL_VERT_FILTER_INIT 0x1B50 +#define mmSCL_VERT_FILTER_INIT_BOT 0x1B57 +#define mmSCL_VERT_FILTER_SCALE_RATIO 0x1B4F +#define mmSEQ8_DATA 0x00F1 +#define mmSEQ8_IDX 0x00F1 +#define mmSLAVE_COMM_CMD_REG 0x1624 +#define mmSLAVE_COMM_CNTL_REG 0x1625 +#define mmSLAVE_COMM_DATA_REG1 0x1621 +#define mmSLAVE_COMM_DATA_REG2 0x1622 +#define mmSLAVE_COMM_DATA_REG3 0x1623 +#define mmSYMCLKA_CLOCK_ENABLE 0x0160 +#define mmSYMCLKB_CLOCK_ENABLE 0x0161 +#define mmSYMCLKC_CLOCK_ENABLE 0x0162 +#define mmSYMCLKD_CLOCK_ENABLE 0x0163 +#define mmSYMCLKE_CLOCK_ENABLE 0x0164 +#define mmSYMCLKF_CLOCK_ENABLE 0x0165 +#define mmTMDS_CNTL 0x1C7C +#define mmTMDS_CONTROL0_FEEDBACK 0x1C7E +#define mmTMDS_CONTROL_CHAR 0x1C7D +#define mmTMDS_CTL0_1_GEN_CNTL 0x1C86 +#define mmTMDS_CTL2_3_GEN_CNTL 0x1C87 +#define mmTMDS_CTL_BITS 0x1C83 +#define mmTMDS_DCBALANCER_CONTROL 0x1C84 +#define mmTMDS_DEBUG 0x1C82 +#define mmTMDS_STEREOSYNC_CTL_SEL 0x1C7F +#define mmTMDS_SYNC_CHAR_PATTERN_0_1 0x1C80 +#define mmTMDS_SYNC_CHAR_PATTERN_2_3 0x1C81 +#define mmUNIPHYAB_TPG_CONTROL 0x1931 +#define mmUNIPHYAB_TPG_SEED 0x1932 +#define mmUNIPHY_ANG_BIST_CNTL 0x198C +#define mmUNIPHYCD_TPG_CONTROL 0x1933 +#define mmUNIPHYCD_TPG_SEED 0x1934 +#define mmUNIPHY_CHANNEL_XBAR_CNTL 0x198E +#define mmUNIPHY_DATA_SYNCHRONIZATION 0x198A +#define mmUNIPHYEF_TPG_CONTROL 0x1935 +#define mmUNIPHYEF_TPG_SEED 0x1936 +#define mmUNIPHY_IMPCAL_LINKA 0x1908 +#define mmUNIPHY_IMPCAL_LINKB 0x1909 +#define mmUNIPHY_IMPCAL_LINKC 0x190F +#define mmUNIPHY_IMPCAL_LINKD 0x1910 +#define mmUNIPHY_IMPCAL_LINKE 0x1913 +#define mmUNIPHY_IMPCAL_LINKF 0x1914 +#define mmUNIPHY_IMPCAL_PERIOD 0x190A +#define mmUNIPHY_IMPCAL_PSW_AB 0x190E +#define mmUNIPHY_IMPCAL_PSW_CD 0x1912 +#define mmUNIPHY_IMPCAL_PSW_EF 0x1916 +#define mmUNIPHY_LINK_CNTL 0x198D +#define mmUNIPHY_PLL_CONTROL1 0x1986 +#define mmUNIPHY_PLL_CONTROL2 0x1987 +#define mmUNIPHY_PLL_FBDIV 0x1985 +#define mmUNIPHY_PLL_SS_CNTL 0x1989 +#define mmUNIPHY_PLL_SS_STEP_SIZE 0x1988 +#define mmUNIPHY_POWER_CONTROL 0x1984 +#define mmUNIPHY_REG_TEST_OUTPUT 0x198B +#define mmUNIPHY_SOFT_RESET 0x0166 +#define mmUNIPHY_TX_CONTROL1 0x1980 +#define mmUNIPHY_TX_CONTROL2 0x1981 +#define mmUNIPHY_TX_CONTROL3 0x1982 +#define mmUNIPHY_TX_CONTROL4 0x1983 +#define mmVGA25_PPLL_ANALOG 0x00E4 +#define mmVGA25_PPLL_FB_DIV 0x00DC +#define mmVGA25_PPLL_POST_DIV 0x00E0 +#define mmVGA25_PPLL_REF_DIV 0x00D8 +#define mmVGA28_PPLL_ANALOG 0x00E5 +#define mmVGA28_PPLL_FB_DIV 0x00DD +#define mmVGA28_PPLL_POST_DIV 0x00E1 +#define mmVGA28_PPLL_REF_DIV 0x00D9 +#define mmVGA41_PPLL_ANALOG 0x00E6 +#define mmVGA41_PPLL_FB_DIV 0x00DE +#define mmVGA41_PPLL_POST_DIV 0x00E2 +#define mmVGA41_PPLL_REF_DIV 0x00DA +#define mmVGA_CACHE_CONTROL 0x00CB +#define mmVGA_DEBUG_READBACK_DATA 0x00D7 +#define mmVGA_DEBUG_READBACK_INDEX 0x00D6 +#define mmVGA_DISPBUF1_SURFACE_ADDR 0x00C6 +#define mmVGA_DISPBUF2_SURFACE_ADDR 0x00C8 +#define mmVGA_HDP_CONTROL 0x00CA +#define mmVGA_HW_DEBUG 0x00CF +#define mmVGA_INTERRUPT_CONTROL 0x00D1 +#define mmVGA_INTERRUPT_STATUS 0x00D3 +#define mmVGA_MAIN_CONTROL 0x00D4 +#define mmVGA_MEMORY_BASE_ADDRESS 0x00C4 +#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x00C9 +#define mmVGA_MEM_READ_PAGE_ADDR 0x0013 +#define mmVGA_MEM_WRITE_PAGE_ADDR 0x0012 +#define mmVGA_MODE_CONTROL 0x00C2 +#define mmVGA_RENDER_CONTROL 0x00C0 +#define mmVGA_SEQUENCER_RESET_CONTROL 0x00C1 +#define mmVGA_SOURCE_SELECT 0x00FC +#define mmVGA_STATUS 0x00D0 +#define mmVGA_STATUS_CLEAR 0x00D2 +#define mmVGA_SURFACE_PITCH_SELECT 0x00C3 +#define mmVGA_TEST_CONTROL 0x00D5 +#define mmVGA_TEST_DEBUG_DATA 0x00C7 +#define mmVGA_TEST_DEBUG_INDEX 0x00C5 +#define mmVIEWPORT_SIZE 0x1B5D +#define mmVIEWPORT_START 0x1B5C +#define mmXDMA_CLOCK_GATING_CNTL 0x0409 +#define mmXDMA_IF_BIF_STATUS 0x0418 +#define mmXDMA_INTERRUPT 0x0406 +#define mmXDMA_LOCAL_SURFACE_TILING1 0x03F4 +#define mmXDMA_LOCAL_SURFACE_TILING2 0x03F5 +#define mmXDMA_MC_PCIE_CLIENT_CONFIG 0x03E9 +#define mmXDMA_MEM_POWER_CNTL 0x040B +#define mmXDMA_MSTR_CMD_URGENT_CNTL 0x03F6 +#define mmXDMA_MSTR_CNTL 0x03E0 +#define mmXDMA_MSTR_HEIGHT 0x03E3 +#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR 0x03F1 +#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH 0x03F2 +#define mmXDMA_MSTR_LOCAL_SURFACE_PITCH 0x03F3 +#define mmXDMA_MSTR_MEM_CLIENT_CONFIG 0x03EA +#define mmXDMA_MSTR_MEM_NACK_STATUS 0x040D +#define mmXDMA_MSTR_MEM_URGENT_CNTL 0x03F7 +#define mmXDMA_MSTR_PCIE_NACK_STATUS 0x040C +#define mmXDMA_MSTR_READ_COMMAND 0x03E1 +#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS 0x03E6 +#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x03E7 +#define mmXDMA_MSTR_REMOTE_SURFACE_BASE 0x03E4 +#define mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x03E5 +#define mmXDMA_MSTR_STATUS 0x03E8 +#define mmXDMA_RBBMIF_RDWR_CNTL 0x040A +#define mmXDMA_SLV_CNTL 0x03FB +#define mmXDMA_SLV_FLIP_PENDING 0x0407 +#define mmXDMA_SLV_MEM_CLIENT_CONFIG 0x03FD +#define mmXDMA_SLV_MEM_NACK_STATUS 0x040F +#define mmXDMA_SLV_PCIE_NACK_STATUS 0x040E +#define mmXDMA_SLV_READ_LATENCY_AVE 0x0405 +#define mmXDMA_SLV_READ_LATENCY_MINMAX 0x0404 +#define mmXDMA_SLV_READ_LATENCY_TIMER 0x0412 +#define mmXDMA_SLV_READ_URGENT_CNTL 0x03FF +#define mmXDMA_SLV_REMOTE_GPU_ADDRESS 0x0402 +#define mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x0403 +#define mmXDMA_SLV_SLS_PITCH 0x03FE +#define mmXDMA_SLV_WB_RATE_CNTL 0x0401 +#define mmXDMA_SLV_WRITE_URGENT_CNTL 0x0400 +#define mmXDMA_TEST_DEBUG_DATA 0x041D +#define mmXDMA_TEST_DEBUG_INDEX 0x041C + +/* Registers that spilled out of sid.h */ +#define mmDATA_FORMAT 0x1AC0 +#define mmDESKTOP_HEIGHT 0x1AC1 +#define mmDC_LB_MEMORY_SPLIT 0x1AC3 +#define mmPRIORITY_A_CNT 0x1AC6 +#define mmPRIORITY_B_CNT 0x1AC7 +#define mmDPG_PIPE_ARBITRATION_CONTROL3 0x1B32 +#define mmINT_MASK 0x1AD0 +#define mmVLINE_STATUS 0x1AEE +#define mmVBLANK_STATUS 0x1AEF + + +#endif |