diff options
Diffstat (limited to 'drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h | 1784 |
1 files changed, 1784 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h new file mode 100644 index 000000000000..c75aee25619e --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h @@ -0,0 +1,1784 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef GFX_6_0_D_H +#define GFX_6_0_D_H + +#define ixCLIPPER_DEBUG_REG00 0x0000 +#define ixCLIPPER_DEBUG_REG01 0x0001 +#define ixCLIPPER_DEBUG_REG02 0x0002 +#define ixCLIPPER_DEBUG_REG03 0x0003 +#define ixCLIPPER_DEBUG_REG04 0x0004 +#define ixCLIPPER_DEBUG_REG05 0x0005 +#define ixCLIPPER_DEBUG_REG06 0x0006 +#define ixCLIPPER_DEBUG_REG07 0x0007 +#define ixCLIPPER_DEBUG_REG08 0x0008 +#define ixCLIPPER_DEBUG_REG09 0x0009 +#define ixCLIPPER_DEBUG_REG10 0x000A +#define ixCLIPPER_DEBUG_REG11 0x000B +#define ixCLIPPER_DEBUG_REG12 0x000C +#define ixCLIPPER_DEBUG_REG13 0x000D +#define ixCLIPPER_DEBUG_REG14 0x000E +#define ixCLIPPER_DEBUG_REG15 0x000F +#define ixCLIPPER_DEBUG_REG16 0x0010 +#define ixCLIPPER_DEBUG_REG17 0x0011 +#define ixCLIPPER_DEBUG_REG18 0x0012 +#define ixCLIPPER_DEBUG_REG19 0x0013 +#define ixGDS_DEBUG_REG0 0x0000 +#define ixGDS_DEBUG_REG1 0x0001 +#define ixGDS_DEBUG_REG2 0x0002 +#define ixGDS_DEBUG_REG3 0x0003 +#define ixGDS_DEBUG_REG4 0x0004 +#define ixGDS_DEBUG_REG5 0x0005 +#define ixGDS_DEBUG_REG6 0x0006 +#define ixIA_DEBUG_REG0 0x0000 +#define ixIA_DEBUG_REG1 0x0001 +#define ixIA_DEBUG_REG2 0x0002 +#define ixIA_DEBUG_REG3 0x0003 +#define ixIA_DEBUG_REG4 0x0004 +#define ixIA_DEBUG_REG5 0x0005 +#define ixIA_DEBUG_REG6 0x0006 +#define ixIA_DEBUG_REG7 0x0007 +#define ixIA_DEBUG_REG8 0x0008 +#define ixIA_DEBUG_REG9 0x0009 +#define ixPA_SC_DEBUG_REG0 0x0000 +#define ixPA_SC_DEBUG_REG1 0x0001 +#define ixSETUP_DEBUG_REG0 0x0018 +#define ixSETUP_DEBUG_REG1 0x0019 +#define ixSETUP_DEBUG_REG2 0x001A +#define ixSETUP_DEBUG_REG3 0x001B +#define ixSETUP_DEBUG_REG4 0x001C +#define ixSETUP_DEBUG_REG5 0x001D +#define ixSQ_DEBUG_CTRL_LOCAL 0x0009 +#define ixSQ_DEBUG_STS_LOCAL 0x0008 +#define ixSQ_INTERRUPT_WORD_AUTO 0x20C0 +#define ixSQ_INTERRUPT_WORD_CMN 0x20C0 +#define ixSQ_INTERRUPT_WORD_WAVE 0x20C0 +#define ixSQ_WAVE_EXEC_HI 0x027F +#define ixSQ_WAVE_EXEC_LO 0x027E +#define ixSQ_WAVE_GPR_ALLOC 0x0015 +#define ixSQ_WAVE_HW_ID 0x0014 +#define ixSQ_WAVE_IB_DBG0 0x001C +#define ixSQ_WAVE_IB_STS 0x0017 +#define ixSQ_WAVE_INST_DW0 0x001A +#define ixSQ_WAVE_INST_DW1 0x001B +#define ixSQ_WAVE_LDS_ALLOC 0x0016 +#define ixSQ_WAVE_M0 0x027C +#define ixSQ_WAVE_MODE 0x0011 +#define ixSQ_WAVE_PC_HI 0x0019 +#define ixSQ_WAVE_PC_LO 0x0018 +#define ixSQ_WAVE_STATUS 0x0012 +#define ixSQ_WAVE_TBA_HI 0x026D +#define ixSQ_WAVE_TBA_LO 0x026C +#define ixSQ_WAVE_TMA_HI 0x026F +#define ixSQ_WAVE_TMA_LO 0x026E +#define ixSQ_WAVE_TRAPSTS 0x0013 +#define ixSQ_WAVE_TTMP0 0x0270 +#define ixSQ_WAVE_TTMP10 0x027A +#define ixSQ_WAVE_TTMP1 0x0271 +#define ixSQ_WAVE_TTMP11 0x027B +#define ixSQ_WAVE_TTMP2 0x0272 +#define ixSQ_WAVE_TTMP3 0x0273 +#define ixSQ_WAVE_TTMP4 0x0274 +#define ixSQ_WAVE_TTMP5 0x0275 +#define ixSQ_WAVE_TTMP6 0x0276 +#define ixSQ_WAVE_TTMP7 0x0277 +#define ixSQ_WAVE_TTMP8 0x0278 +#define ixSQ_WAVE_TTMP9 0x0279 +#define ixSXIFCCG_DEBUG_REG0 0x0014 +#define ixSXIFCCG_DEBUG_REG1 0x0015 +#define ixSXIFCCG_DEBUG_REG2 0x0016 +#define ixSXIFCCG_DEBUG_REG3 0x0017 +#define ixVGT_DEBUG_REG0 0x0000 +#define ixVGT_DEBUG_REG10 0x000A +#define ixVGT_DEBUG_REG1 0x0001 +#define ixVGT_DEBUG_REG11 0x000B +#define ixVGT_DEBUG_REG12 0x000C +#define ixVGT_DEBUG_REG13 0x000D +#define ixVGT_DEBUG_REG14 0x000E +#define ixVGT_DEBUG_REG15 0x000F +#define ixVGT_DEBUG_REG16 0x0010 +#define ixVGT_DEBUG_REG17 0x0011 +#define ixVGT_DEBUG_REG18 0x0012 +#define ixVGT_DEBUG_REG19 0x0013 +#define ixVGT_DEBUG_REG20 0x0014 +#define ixVGT_DEBUG_REG2 0x0002 +#define ixVGT_DEBUG_REG21 0x0015 +#define ixVGT_DEBUG_REG22 0x0016 +#define ixVGT_DEBUG_REG23 0x0017 +#define ixVGT_DEBUG_REG24 0x0018 +#define ixVGT_DEBUG_REG25 0x0019 +#define ixVGT_DEBUG_REG26 0x001A +#define ixVGT_DEBUG_REG27 0x001B +#define ixVGT_DEBUG_REG28 0x001C +#define ixVGT_DEBUG_REG29 0x001D +#define ixVGT_DEBUG_REG30 0x001E +#define ixVGT_DEBUG_REG3 0x0003 +#define ixVGT_DEBUG_REG31 0x001F +#define ixVGT_DEBUG_REG32 0x0020 +#define ixVGT_DEBUG_REG33 0x0021 +#define ixVGT_DEBUG_REG34 0x0022 +#define ixVGT_DEBUG_REG35 0x0023 +#define ixVGT_DEBUG_REG36 0x0024 +#define ixVGT_DEBUG_REG4 0x0004 +#define ixVGT_DEBUG_REG5 0x0005 +#define ixVGT_DEBUG_REG6 0x0006 +#define ixVGT_DEBUG_REG7 0x0007 +#define ixVGT_DEBUG_REG8 0x0008 +#define ixVGT_DEBUG_REG9 0x0009 +#define mmBCI_DEBUG_READ 0x24E3 +#define mmCB_BLEND0_CONTROL 0xA1E0 +#define mmCB_BLEND1_CONTROL 0xA1E1 +#define mmCB_BLEND2_CONTROL 0xA1E2 +#define mmCB_BLEND3_CONTROL 0xA1E3 +#define mmCB_BLEND4_CONTROL 0xA1E4 +#define mmCB_BLEND5_CONTROL 0xA1E5 +#define mmCB_BLEND6_CONTROL 0xA1E6 +#define mmCB_BLEND7_CONTROL 0xA1E7 +#define mmCB_BLEND_ALPHA 0xA108 +#define mmCB_BLEND_BLUE 0xA107 +#define mmCB_BLEND_GREEN 0xA106 +#define mmCB_BLEND_RED 0xA105 +#define mmCB_CGTT_SCLK_CTRL 0x2698 +#define mmCB_COLOR0_ATTRIB 0xA31D +#define mmCB_COLOR0_BASE 0xA318 +#define mmCB_COLOR0_CLEAR_WORD0 0xA323 +#define mmCB_COLOR0_CLEAR_WORD1 0xA324 +#define mmCB_COLOR0_CMASK 0xA31F +#define mmCB_COLOR0_CMASK_SLICE 0xA320 +#define mmCB_COLOR0_FMASK 0xA321 +#define mmCB_COLOR0_FMASK_SLICE 0xA322 +#define mmCB_COLOR0_INFO 0xA31C +#define mmCB_COLOR0_PITCH 0xA319 +#define mmCB_COLOR0_SLICE 0xA31A +#define mmCB_COLOR0_VIEW 0xA31B +#define mmCB_COLOR1_ATTRIB 0xA32C +#define mmCB_COLOR1_BASE 0xA327 +#define mmCB_COLOR1_CLEAR_WORD0 0xA332 +#define mmCB_COLOR1_CLEAR_WORD1 0xA333 +#define mmCB_COLOR1_CMASK 0xA32E +#define mmCB_COLOR1_CMASK_SLICE 0xA32F +#define mmCB_COLOR1_FMASK 0xA330 +#define mmCB_COLOR1_FMASK_SLICE 0xA331 +#define mmCB_COLOR1_INFO 0xA32B +#define mmCB_COLOR1_PITCH 0xA328 +#define mmCB_COLOR1_SLICE 0xA329 +#define mmCB_COLOR1_VIEW 0xA32A +#define mmCB_COLOR2_ATTRIB 0xA33B +#define mmCB_COLOR2_BASE 0xA336 +#define mmCB_COLOR2_CLEAR_WORD0 0xA341 +#define mmCB_COLOR2_CLEAR_WORD1 0xA342 +#define mmCB_COLOR2_CMASK 0xA33D +#define mmCB_COLOR2_CMASK_SLICE 0xA33E +#define mmCB_COLOR2_FMASK 0xA33F +#define mmCB_COLOR2_FMASK_SLICE 0xA340 +#define mmCB_COLOR2_INFO 0xA33A +#define mmCB_COLOR2_PITCH 0xA337 +#define mmCB_COLOR2_SLICE 0xA338 +#define mmCB_COLOR2_VIEW 0xA339 +#define mmCB_COLOR3_ATTRIB 0xA34A +#define mmCB_COLOR3_BASE 0xA345 +#define mmCB_COLOR3_CLEAR_WORD0 0xA350 +#define mmCB_COLOR3_CLEAR_WORD1 0xA351 +#define mmCB_COLOR3_CMASK 0xA34C +#define mmCB_COLOR3_CMASK_SLICE 0xA34D +#define mmCB_COLOR3_FMASK 0xA34E +#define mmCB_COLOR3_FMASK_SLICE 0xA34F +#define mmCB_COLOR3_INFO 0xA349 +#define mmCB_COLOR3_PITCH 0xA346 +#define mmCB_COLOR3_SLICE 0xA347 +#define mmCB_COLOR3_VIEW 0xA348 +#define mmCB_COLOR4_ATTRIB 0xA359 +#define mmCB_COLOR4_BASE 0xA354 +#define mmCB_COLOR4_CLEAR_WORD0 0xA35F +#define mmCB_COLOR4_CLEAR_WORD1 0xA360 +#define mmCB_COLOR4_CMASK 0xA35B +#define mmCB_COLOR4_CMASK_SLICE 0xA35C +#define mmCB_COLOR4_FMASK 0xA35D +#define mmCB_COLOR4_FMASK_SLICE 0xA35E +#define mmCB_COLOR4_INFO 0xA358 +#define mmCB_COLOR4_PITCH 0xA355 +#define mmCB_COLOR4_SLICE 0xA356 +#define mmCB_COLOR4_VIEW 0xA357 +#define mmCB_COLOR5_ATTRIB 0xA368 +#define mmCB_COLOR5_BASE 0xA363 +#define mmCB_COLOR5_CLEAR_WORD0 0xA36E +#define mmCB_COLOR5_CLEAR_WORD1 0xA36F +#define mmCB_COLOR5_CMASK 0xA36A +#define mmCB_COLOR5_CMASK_SLICE 0xA36B +#define mmCB_COLOR5_FMASK 0xA36C +#define mmCB_COLOR5_FMASK_SLICE 0xA36D +#define mmCB_COLOR5_INFO 0xA367 +#define mmCB_COLOR5_PITCH 0xA364 +#define mmCB_COLOR5_SLICE 0xA365 +#define mmCB_COLOR5_VIEW 0xA366 +#define mmCB_COLOR6_ATTRIB 0xA377 +#define mmCB_COLOR6_BASE 0xA372 +#define mmCB_COLOR6_CLEAR_WORD0 0xA37D +#define mmCB_COLOR6_CLEAR_WORD1 0xA37E +#define mmCB_COLOR6_CMASK 0xA379 +#define mmCB_COLOR6_CMASK_SLICE 0xA37A +#define mmCB_COLOR6_FMASK 0xA37B +#define mmCB_COLOR6_FMASK_SLICE 0xA37C +#define mmCB_COLOR6_INFO 0xA376 +#define mmCB_COLOR6_PITCH 0xA373 +#define mmCB_COLOR6_SLICE 0xA374 +#define mmCB_COLOR6_VIEW 0xA375 +#define mmCB_COLOR7_ATTRIB 0xA386 +#define mmCB_COLOR7_BASE 0xA381 +#define mmCB_COLOR7_CLEAR_WORD0 0xA38C +#define mmCB_COLOR7_CLEAR_WORD1 0xA38D +#define mmCB_COLOR7_CMASK 0xA388 +#define mmCB_COLOR7_CMASK_SLICE 0xA389 +#define mmCB_COLOR7_FMASK 0xA38A +#define mmCB_COLOR7_FMASK_SLICE 0xA38B +#define mmCB_COLOR7_INFO 0xA385 +#define mmCB_COLOR7_PITCH 0xA382 +#define mmCB_COLOR7_SLICE 0xA383 +#define mmCB_COLOR7_VIEW 0xA384 +#define mmCB_COLOR_CONTROL 0xA202 +#define mmCB_DEBUG_BUS_10 0x26A2 +#define mmCB_DEBUG_BUS_1 0x2699 +#define mmCB_DEBUG_BUS_11 0x26A3 +#define mmCB_DEBUG_BUS_12 0x26A4 +#define mmCB_DEBUG_BUS_13 0x26A5 +#define mmCB_DEBUG_BUS_14 0x26A6 +#define mmCB_DEBUG_BUS_15 0x26A7 +#define mmCB_DEBUG_BUS_16 0x26A8 +#define mmCB_DEBUG_BUS_17 0x26A9 +#define mmCB_DEBUG_BUS_18 0x26AA +#define mmCB_DEBUG_BUS_2 0x269A +#define mmCB_DEBUG_BUS_3 0x269B +#define mmCB_DEBUG_BUS_4 0x269C +#define mmCB_DEBUG_BUS_5 0x269D +#define mmCB_DEBUG_BUS_6 0x269E +#define mmCB_DEBUG_BUS_7 0x269F +#define mmCB_DEBUG_BUS_8 0x26A0 +#define mmCB_DEBUG_BUS_9 0x26A1 +#define mmCB_HW_CONTROL 0x2684 +#define mmCB_HW_CONTROL_1 0x2685 +#define mmCB_HW_CONTROL_2 0x2686 +#define mmCB_PERFCOUNTER0_HI 0x2691 +#define mmCB_PERFCOUNTER0_LO 0x2690 +#define mmCB_PERFCOUNTER0_SELECT1 0x2689 +#define mmCB_PERFCOUNTER1_HI 0x2693 +#define mmCB_PERFCOUNTER1_LO 0x2692 +#define mmCB_PERFCOUNTER2_HI 0x2695 +#define mmCB_PERFCOUNTER2_LO 0x2694 +#define mmCB_PERFCOUNTER3_HI 0x2697 +#define mmCB_PERFCOUNTER3_LO 0x2696 +#define mmCB_SHADER_MASK 0xA08F +#define mmCB_TARGET_MASK 0xA08E +#define mmCC_GC_SHADER_ARRAY_CONFIG 0x226F +#define mmCC_RB_BACKEND_DISABLE 0x263D +#define mmCC_RB_DAISY_CHAIN 0x2641 +#define mmCC_RB_REDUNDANCY 0x263C +#define mmCC_SQC_BANK_DISABLE 0x2307 +#define mmCGTS_RD_CTRL_REG 0x2455 +#define mmCGTS_RD_REG 0x2456 +#define mmCGTS_SM_CTRL_REG 0x2454 +#define mmCGTS_TCC_DISABLE 0x2452 +#define mmCGTS_USER_TCC_DISABLE 0x2453 +#define mmCGTT_BCI_CLK_CTRL 0x24A9 +#define mmCGTT_CP_CLK_CTRL 0x3059 +#define mmCGTT_GDS_CLK_CTRL 0x25DD +#define mmCGTT_IA_CLK_CTRL 0x2261 +#define mmCGTT_PA_CLK_CTRL 0x2286 +#define mmCGTT_PC_CLK_CTRL 0x24A8 +#define mmCGTT_RLC_CLK_CTRL 0x30E0 +#define mmCGTT_SC_CLK_CTRL 0x22CA +#define mmCGTT_SPI_CLK_CTRL 0x2451 +#define mmCGTT_SQ_CLK_CTRL 0x2362 +#define mmCGTT_SQG_CLK_CTRL 0x2363 +#define mmCGTT_SX_CLK_CTRL0 0x240C +#define mmCGTT_SX_CLK_CTRL1 0x240D +#define mmCGTT_SX_CLK_CTRL2 0x240E +#define mmCGTT_SX_CLK_CTRL3 0x240F +#define mmCGTT_SX_CLK_CTRL4 0x2410 +#define mmCGTT_TCI_CLK_CTRL 0x2B60 +#define mmCGTT_TCP_CLK_CTRL 0x2B15 +#define mmCGTT_VGT_CLK_CTRL 0x225F +#define mmCOHER_DEST_BASE_0 0xA092 +#define mmCOHER_DEST_BASE_1 0xA093 +#define mmCOHER_DEST_BASE_2 0xA07E +#define mmCOHER_DEST_BASE_3 0xA07F +#define mmCOMPUTE_DIM_X 0x2E01 +#define mmCOMPUTE_DIM_Y 0x2E02 +#define mmCOMPUTE_DIM_Z 0x2E03 +#define mmCOMPUTE_DISPATCH_INITIATOR 0x2E00 +#define mmCOMPUTE_NUM_THREAD_X 0x2E07 +#define mmCOMPUTE_NUM_THREAD_Y 0x2E08 +#define mmCOMPUTE_NUM_THREAD_Z 0x2E09 +#define mmCOMPUTE_PGM_HI 0x2E0D +#define mmCOMPUTE_PGM_LO 0x2E0C +#define mmCOMPUTE_PGM_RSRC1 0x2E12 +#define mmCOMPUTE_PGM_RSRC2 0x2E13 +#define mmCOMPUTE_RESOURCE_LIMITS 0x2E15 +#define mmCOMPUTE_START_X 0x2E04 +#define mmCOMPUTE_START_Y 0x2E05 +#define mmCOMPUTE_START_Z 0x2E06 +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0 0x2E16 +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1 0x2E17 +#define mmCOMPUTE_TBA_HI 0x2E0F +#define mmCOMPUTE_TBA_LO 0x2E0E +#define mmCOMPUTE_TMA_HI 0x2E11 +#define mmCOMPUTE_TMA_LO 0x2E10 +#define mmCOMPUTE_TMPRING_SIZE 0x2E18 +#define mmCOMPUTE_USER_DATA_0 0x2E40 +#define mmCOMPUTE_USER_DATA_10 0x2E4A +#define mmCOMPUTE_USER_DATA_1 0x2E41 +#define mmCOMPUTE_USER_DATA_11 0x2E4B +#define mmCOMPUTE_USER_DATA_12 0x2E4C +#define mmCOMPUTE_USER_DATA_13 0x2E4D +#define mmCOMPUTE_USER_DATA_14 0x2E4E +#define mmCOMPUTE_USER_DATA_15 0x2E4F +#define mmCOMPUTE_USER_DATA_2 0x2E42 +#define mmCOMPUTE_USER_DATA_3 0x2E43 +#define mmCOMPUTE_USER_DATA_4 0x2E44 +#define mmCOMPUTE_USER_DATA_5 0x2E45 +#define mmCOMPUTE_USER_DATA_6 0x2E46 +#define mmCOMPUTE_USER_DATA_7 0x2E47 +#define mmCOMPUTE_USER_DATA_8 0x2E48 +#define mmCOMPUTE_USER_DATA_9 0x2E49 +#define mmCOMPUTE_VMID 0x2E14 +#define mmCP_APPEND_ADDR_HI 0x2159 +#define mmCP_APPEND_ADDR_LO 0x2158 +#define mmCP_APPEND_DATA 0x215A +#define mmCP_APPEND_LAST_CS_FENCE 0x215B +#define mmCP_APPEND_LAST_PS_FENCE 0x215C +#define mmCP_ATOMIC_PREOP_HI 0x215E +#define mmCP_ATOMIC_PREOP_LO 0x215D +#define mmCP_BUSY_STAT 0x219F +#define mmCP_CE_HEADER_DUMP 0x21A4 +#define mmCP_CE_IB1_BASE_HI 0x21C7 +#define mmCP_CE_IB1_BASE_LO 0x21C6 +#define mmCP_CE_IB1_BUFSZ 0x21C8 +#define mmCP_CE_IB2_BASE_HI 0x21CA +#define mmCP_CE_IB2_BASE_LO 0x21C9 +#define mmCP_CE_IB2_BUFSZ 0x21CB +#define mmCP_CE_INIT_BASE_HI 0x21C4 +#define mmCP_CE_INIT_BASE_LO 0x21C3 +#define mmCP_CE_INIT_BUFSZ 0x21C5 +#define mmCP_CEQ1_AVAIL 0x21E6 +#define mmCP_CEQ2_AVAIL 0x21E7 +#define mmCP_CE_ROQ_IB1_STAT 0x21E9 +#define mmCP_CE_ROQ_IB2_STAT 0x21EA +#define mmCP_CE_ROQ_RB_STAT 0x21E8 +#define mmCP_CE_UCODE_ADDR 0x305A +#define mmCP_CE_UCODE_DATA 0x305B +#define mmCP_CMD_DATA 0x21DF +#define mmCP_CMD_INDEX 0x21DE +#define mmCP_CNTX_STAT 0x21B8 +#define mmCP_COHER_BASE 0x217E +#define mmCP_COHER_CNTL 0x217C +#define mmCP_COHER_SIZE 0x217D +#define mmCP_COHER_START_DELAY 0x217B +#define mmCP_COHER_STATUS 0x217F +#define mmCP_CSF_CNTL 0x21B5 +#define mmCP_CSF_STAT 0x21B4 +#define mmCP_DMA_CNTL 0x218A +#define mmCP_DMA_ME_COMMAND 0x2184 +#define mmCP_DMA_ME_DST_ADDR 0x2182 +#define mmCP_DMA_ME_DST_ADDR_HI 0x2183 +#define mmCP_DMA_ME_SRC_ADDR 0x2180 +#define mmCP_DMA_ME_SRC_ADDR_HI 0x2181 +#define mmCP_DMA_PFP_COMMAND 0x2189 +#define mmCP_DMA_PFP_DST_ADDR 0x2187 +#define mmCP_DMA_PFP_DST_ADDR_HI 0x2188 +#define mmCP_DMA_PFP_SRC_ADDR 0x2185 +#define mmCP_DMA_PFP_SRC_ADDR_HI 0x2186 +#define mmCP_DMA_READ_TAGS 0x218B +#define mmCP_ECC_FIRSTOCCURRENCE 0x307A +#define mmCP_ECC_FIRSTOCCURRENCE_RING0 0x307B +#define mmCP_ECC_FIRSTOCCURRENCE_RING1 0x307C +#define mmCP_ECC_FIRSTOCCURRENCE_RING2 0x307D +#define mmCP_EOP_DONE_ADDR_HI 0x2101 +#define mmCP_EOP_DONE_ADDR_LO 0x2100 +#define mmCP_EOP_DONE_DATA_HI 0x2103 +#define mmCP_EOP_DONE_DATA_LO 0x2102 +#define mmCP_EOP_LAST_FENCE_HI 0x2105 +#define mmCP_EOP_LAST_FENCE_LO 0x2104 +#define mmCP_GDS_ATOMIC0_PREOP_HI 0x2160 +#define mmCP_GDS_ATOMIC0_PREOP_LO 0x215F +#define mmCP_GDS_ATOMIC1_PREOP_HI 0x2162 +#define mmCP_GDS_ATOMIC1_PREOP_LO 0x2161 +#define mmCP_GRBM_FREE_COUNT 0x21A3 +#define mmCP_IB1_BASE_HI 0x21CD +#define mmCP_IB1_BASE_LO 0x21CC +#define mmCP_IB1_BUFSZ 0x21CE +#define mmCP_IB1_OFFSET 0x2192 +#define mmCP_IB1_PREAMBLE_BEGIN 0x2194 +#define mmCP_IB1_PREAMBLE_END 0x2195 +#define mmCP_IB2_BASE_HI 0x21D0 +#define mmCP_IB2_BASE_LO 0x21CF +#define mmCP_IB2_BUFSZ 0x21D1 +#define mmCP_IB2_OFFSET 0x2193 +#define mmCP_IB2_PREAMBLE_BEGIN 0x2196 +#define mmCP_IB2_PREAMBLE_END 0x2197 +#define mmCP_INT_CNTL 0x3049 +#define mmCP_INT_CNTL_RING0 0x306A +#define mmCP_INT_CNTL_RING1 0x306B +#define mmCP_INT_CNTL_RING2 0x306C +#define mmCP_INT_STAT_DEBUG 0x21F7 +#define mmCP_INT_STATUS 0x304A +#define mmCP_INT_STATUS_RING0 0x306D +#define mmCP_INT_STATUS_RING1 0x306E +#define mmCP_INT_STATUS_RING2 0x306F +#define mmCP_MC_PACK_DELAY_CNT 0x21A7 +#define mmCP_ME_CNTL 0x21B6 +#define mmCP_ME_HEADER_DUMP 0x21A1 +#define mmCP_ME_MC_RADDR_HI 0x216E +#define mmCP_ME_MC_RADDR_LO 0x216D +#define mmCP_ME_MC_WADDR_HI 0x216A +#define mmCP_ME_MC_WADDR_LO 0x2169 +#define mmCP_ME_MC_WDATA_HI 0x216C +#define mmCP_ME_MC_WDATA_LO 0x216B +#define mmCP_MEM_SLP_CNTL 0x3079 +#define mmCP_ME_PREEMPTION 0x21B9 +#define mmCP_MEQ_AVAIL 0x21DD +#define mmCP_MEQ_STAT 0x21E5 +#define mmCP_MEQ_THRESHOLDS 0x21D9 +#define mmCP_ME_RAM_DATA 0x3058 +#define mmCP_ME_RAM_RADDR 0x3056 +#define mmCP_ME_RAM_WADDR 0x3057 +#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI 0x210B +#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO 0x210A +#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI 0x210F +#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO 0x210E +#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI 0x2113 +#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO 0x2112 +#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI 0x2117 +#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO 0x2116 +#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI 0x2109 +#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO 0x2108 +#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI 0x210D +#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO 0x210C +#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI 0x2111 +#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO 0x2110 +#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI 0x2115 +#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO 0x2114 +#define mmCP_PA_CINVOC_COUNT_HI 0x2129 +#define mmCP_PA_CINVOC_COUNT_LO 0x2128 +#define mmCP_PA_CPRIM_COUNT_HI 0x212B +#define mmCP_PA_CPRIM_COUNT_LO 0x212A +#define mmCP_PERFMON_CNTL 0x21FF +#define mmCP_PERFMON_CNTX_CNTL 0xA0D8 +#define mmCP_PFP_HEADER_DUMP 0x21A2 +#define mmCP_PFP_IB_CONTROL 0x218D +#define mmCP_PFP_LOAD_CONTROL 0x218E +#define mmCP_PFP_UCODE_ADDR 0x3054 +#define mmCP_PFP_UCODE_DATA 0x3055 +#define mmCP_PIPE_STATS_ADDR_HI 0x2119 +#define mmCP_PIPE_STATS_ADDR_LO 0x2118 +#define mmCP_PWR_CNTL 0x3078 +#define mmCP_QUEUE_THRESHOLDS 0x21D8 +#define mmCP_RB0_BASE 0x3040 +#define mmCP_RB0_CNTL 0x3041 +#define mmCP_RB0_RPTR 0x21C0 +#define mmCP_RB0_RPTR_ADDR 0x3043 +#define mmCP_RB0_RPTR_ADDR_HI 0x3044 +#define mmCP_RB0_WPTR 0x3045 +#define mmCP_RB1_BASE 0x3060 +#define mmCP_RB1_CNTL 0x3061 +#define mmCP_RB1_RPTR 0x21BF +#define mmCP_RB1_RPTR_ADDR 0x3062 +#define mmCP_RB1_RPTR_ADDR_HI 0x3063 +#define mmCP_RB1_WPTR 0x3064 +#define mmCP_RB2_BASE 0x3065 +#define mmCP_RB2_CNTL 0x3066 +#define mmCP_RB2_RPTR 0x21BE +#define mmCP_RB2_RPTR_ADDR 0x3067 +#define mmCP_RB2_RPTR_ADDR_HI 0x3068 +#define mmCP_RB2_WPTR 0x3069 +#define mmCP_RB_BASE 0x3040 +#define mmCP_RB_CNTL 0x3041 +#define mmCP_RB_OFFSET 0x2191 +#define mmCP_RB_RPTR 0x21C0 +#define mmCP_RB_RPTR_ADDR 0x3043 +#define mmCP_RB_RPTR_ADDR_HI 0x3044 +#define mmCP_RB_RPTR_WR 0x3042 +#define mmCP_RB_VMID 0x3051 +#define mmCP_RB_WPTR 0x3045 +#define mmCP_RB_WPTR_DELAY 0x21C1 +#define mmCP_RB_WPTR_POLL_ADDR_HI 0x3047 +#define mmCP_RB_WPTR_POLL_ADDR_LO 0x3046 +#define mmCP_RB_WPTR_POLL_CNTL 0x21C2 +#define mmCP_RING0_PRIORITY 0x304D +#define mmCP_RING1_PRIORITY 0x304E +#define mmCP_RING2_PRIORITY 0x304F +#define mmCP_RINGID 0xA0D9 +#define mmCP_RING_PRIORITY_CNTS 0x304C +#define mmCP_ROQ1_THRESHOLDS 0x21D5 +#define mmCP_ROQ2_AVAIL 0x21DC +#define mmCP_ROQ2_THRESHOLDS 0x21D6 +#define mmCP_ROQ_AVAIL 0x21DA +#define mmCP_ROQ_IB1_STAT 0x21E1 +#define mmCP_ROQ_IB2_STAT 0x21E2 +#define mmCP_ROQ_RB_STAT 0x21E0 +#define mmCP_SC_PSINVOC_COUNT0_HI 0x212D +#define mmCP_SC_PSINVOC_COUNT0_LO 0x212C +#define mmCP_SC_PSINVOC_COUNT1_HI 0x212F +#define mmCP_SC_PSINVOC_COUNT1_LO 0x212E +#define mmCP_SCRATCH_DATA 0x2190 +#define mmCP_SCRATCH_INDEX 0x218F +#define mmCP_SEM_INCOMPLETE_TIMER_CNTL 0x2172 +#define mmCP_SEM_WAIT_TIMER 0x216F +#define mmCP_SIG_SEM_ADDR_HI 0x2171 +#define mmCP_SIG_SEM_ADDR_LO 0x2170 +#define mmCP_STALLED_STAT1 0x219D +#define mmCP_STALLED_STAT2 0x219E +#define mmCP_STALLED_STAT3 0x219C +#define mmCP_STAT 0x21A0 +#define mmCP_ST_BASE_HI 0x21D3 +#define mmCP_ST_BASE_LO 0x21D2 +#define mmCP_ST_BUFSZ 0x21D4 +#define mmCP_STQ_AVAIL 0x21DB +#define mmCP_STQ_STAT 0x21E3 +#define mmCP_STQ_THRESHOLDS 0x21D7 +#define mmCP_STREAM_OUT_ADDR_HI 0x2107 +#define mmCP_STREAM_OUT_ADDR_LO 0x2106 +#define mmCP_STRMOUT_CNTL 0x213F +#define mmCP_VGT_CSINVOC_COUNT_HI 0x2131 +#define mmCP_VGT_CSINVOC_COUNT_LO 0x2130 +#define mmCP_VGT_DSINVOC_COUNT_HI 0x2127 +#define mmCP_VGT_DSINVOC_COUNT_LO 0x2126 +#define mmCP_VGT_GSINVOC_COUNT_HI 0x2123 +#define mmCP_VGT_GSINVOC_COUNT_LO 0x2122 +#define mmCP_VGT_GSPRIM_COUNT_HI 0x211F +#define mmCP_VGT_GSPRIM_COUNT_LO 0x211E +#define mmCP_VGT_HSINVOC_COUNT_HI 0x2125 +#define mmCP_VGT_HSINVOC_COUNT_LO 0x2124 +#define mmCP_VGT_IAPRIM_COUNT_HI 0x211D +#define mmCP_VGT_IAPRIM_COUNT_LO 0x211C +#define mmCP_VGT_IAVERT_COUNT_HI 0x211B +#define mmCP_VGT_IAVERT_COUNT_LO 0x211A +#define mmCP_VGT_VSINVOC_COUNT_HI 0x2121 +#define mmCP_VGT_VSINVOC_COUNT_LO 0x2120 +#define mmCP_VMID 0xA0DA +#define mmCP_WAIT_REG_MEM_TIMEOUT 0x2174 +#define mmCP_WAIT_SEM_ADDR_HI 0x2176 +#define mmCP_WAIT_SEM_ADDR_LO 0x2175 +#define mmCS_COPY_STATE 0xA1F3 +#define mmDB_ALPHA_TO_MASK 0xA2DC +#define mmDB_CGTT_CLK_CTRL_0 0x261A +#define mmDB_COUNT_CONTROL 0xA001 +#define mmDB_CREDIT_LIMIT 0x2614 +#define mmDB_DEBUG 0x260C +#define mmDB_DEBUG2 0x260D +#define mmDB_DEBUG3 0x260E +#define mmDB_DEBUG4 0x260F +#define mmDB_DEPTH_BOUNDS_MAX 0xA009 +#define mmDB_DEPTH_BOUNDS_MIN 0xA008 +#define mmDB_DEPTH_CLEAR 0xA00B +#define mmDB_DEPTH_CONTROL 0xA200 +#define mmDB_DEPTH_INFO 0xA00F +#define mmDB_DEPTH_SIZE 0xA016 +#define mmDB_DEPTH_SLICE 0xA017 +#define mmDB_DEPTH_VIEW 0xA002 +#define mmDB_EQAA 0xA201 +#define mmDB_FIFO_DEPTH1 0x2618 +#define mmDB_FIFO_DEPTH2 0x2619 +#define mmDB_FREE_CACHELINES 0x2617 +#define mmDB_HTILE_DATA_BASE 0xA005 +#define mmDB_HTILE_SURFACE 0xA2AF +#define mmDB_PERFCOUNTER0_HI 0x2602 +#define mmDB_PERFCOUNTER0_LO 0x2601 +#define mmDB_PERFCOUNTER0_SELECT 0x2600 +#define mmDB_PERFCOUNTER1_HI 0x2605 +#define mmDB_PERFCOUNTER1_LO 0x2604 +#define mmDB_PERFCOUNTER1_SELECT 0x2603 +#define mmDB_PERFCOUNTER2_HI 0x2608 +#define mmDB_PERFCOUNTER2_LO 0x2607 +#define mmDB_PERFCOUNTER2_SELECT 0x2606 +#define mmDB_PERFCOUNTER3_HI 0x260B +#define mmDB_PERFCOUNTER3_LO 0x260A +#define mmDB_PERFCOUNTER3_SELECT 0x2609 +#define mmDB_PRELOAD_CONTROL 0xA2B2 +#define mmDB_READ_DEBUG_0 0x2620 +#define mmDB_READ_DEBUG_1 0x2621 +#define mmDB_READ_DEBUG_2 0x2622 +#define mmDB_READ_DEBUG_3 0x2623 +#define mmDB_READ_DEBUG_4 0x2624 +#define mmDB_READ_DEBUG_5 0x2625 +#define mmDB_READ_DEBUG_6 0x2626 +#define mmDB_READ_DEBUG_7 0x2627 +#define mmDB_READ_DEBUG_8 0x2628 +#define mmDB_READ_DEBUG_9 0x2629 +#define mmDB_READ_DEBUG_A 0x262A +#define mmDB_READ_DEBUG_B 0x262B +#define mmDB_READ_DEBUG_C 0x262C +#define mmDB_READ_DEBUG_D 0x262D +#define mmDB_READ_DEBUG_E 0x262E +#define mmDB_READ_DEBUG_F 0x262F +#define mmDB_RENDER_CONTROL 0xA000 +#define mmDB_RENDER_OVERRIDE 0xA003 +#define mmDB_RENDER_OVERRIDE2 0xA004 +#define mmDB_SHADER_CONTROL 0xA203 +#define mmDB_SRESULTS_COMPARE_STATE0 0xA2B0 +#define mmDB_SRESULTS_COMPARE_STATE1 0xA2B1 +#define mmDB_STENCIL_CLEAR 0xA00A +#define mmDB_STENCIL_CONTROL 0xA10B +#define mmDB_STENCIL_INFO 0xA011 +#define mmDB_STENCIL_READ_BASE 0xA013 +#define mmDB_STENCILREFMASK 0xA10C +#define mmDB_STENCILREFMASK_BF 0xA10D +#define mmDB_STENCIL_WRITE_BASE 0xA015 +#define mmDB_SUBTILE_CONTROL 0x2616 +#define mmDB_WATERMARKS 0x2615 +#define mmDB_Z_INFO 0xA010 +#define mmDB_ZPASS_COUNT_HI 0x261D +#define mmDB_ZPASS_COUNT_LOW 0x261C +#define mmDB_Z_READ_BASE 0xA012 +#define mmDB_Z_WRITE_BASE 0xA014 +#define mmDEBUG_DATA 0x203D +#define mmDEBUG_INDEX 0x203C +#define mmGB_ADDR_CONFIG 0x263E +#define mmGB_BACKEND_MAP 0x263F +#define mmGB_EDC_MODE 0x307E +#define mmGB_GPU_ID 0x2640 +#define mmGB_TILE_MODE0 0x2644 +#define mmGB_TILE_MODE10 0x264E +#define mmGB_TILE_MODE1 0x2645 +#define mmGB_TILE_MODE11 0x264F +#define mmGB_TILE_MODE12 0x2650 +#define mmGB_TILE_MODE13 0x2651 +#define mmGB_TILE_MODE14 0x2652 +#define mmGB_TILE_MODE15 0x2653 +#define mmGB_TILE_MODE16 0x2654 +#define mmGB_TILE_MODE17 0x2655 +#define mmGB_TILE_MODE18 0x2656 +#define mmGB_TILE_MODE19 0x2657 +#define mmGB_TILE_MODE20 0x2658 +#define mmGB_TILE_MODE2 0x2646 +#define mmGB_TILE_MODE21 0x2659 +#define mmGB_TILE_MODE22 0x265A +#define mmGB_TILE_MODE23 0x265B +#define mmGB_TILE_MODE24 0x265C +#define mmGB_TILE_MODE25 0x265D +#define mmGB_TILE_MODE26 0x265E +#define mmGB_TILE_MODE27 0x265F +#define mmGB_TILE_MODE28 0x2660 +#define mmGB_TILE_MODE29 0x2661 +#define mmGB_TILE_MODE30 0x2662 +#define mmGB_TILE_MODE3 0x2647 +#define mmGB_TILE_MODE31 0x2663 +#define mmGB_TILE_MODE4 0x2648 +#define mmGB_TILE_MODE5 0x2649 +#define mmGB_TILE_MODE6 0x264A +#define mmGB_TILE_MODE7 0x264B +#define mmGB_TILE_MODE8 0x264C +#define mmGB_TILE_MODE9 0x264D +#define mmGC_PRIV_MODE 0x3048 +#define mmGC_USER_RB_BACKEND_DISABLE 0x26DF +#define mmGC_USER_SHADER_ARRAY_CONFIG 0x2270 +#define mmGDS_ATOM_BASE 0x25CE +#define mmGDS_ATOM_CNTL 0x25CC +#define mmGDS_ATOM_COMPLETE 0x25CD +#define mmGDS_ATOM_DST 0x25D2 +#define mmGDS_ATOM_OFFSET0 0x25D0 +#define mmGDS_ATOM_OFFSET1 0x25D1 +#define mmGDS_ATOM_OP 0x25D3 +#define mmGDS_ATOM_READ0 0x25D8 +#define mmGDS_ATOM_READ0_U 0x25D9 +#define mmGDS_ATOM_READ1 0x25DA +#define mmGDS_ATOM_READ1_U 0x25DB +#define mmGDS_ATOM_SIZE 0x25CF +#define mmGDS_ATOM_SRC0 0x25D4 +#define mmGDS_ATOM_SRC0_U 0x25D5 +#define mmGDS_ATOM_SRC1 0x25D6 +#define mmGDS_ATOM_SRC1_U 0x25D7 +#define mmGDS_CNTL_STATUS 0x25C1 +#define mmGDS_CONFIG 0x25C0 +#define mmGDS_DEBUG_CNTL 0x25DE +#define mmGDS_DEBUG_DATA 0x25DF +#define mmGDS_ENHANCE 0x25DC +#define mmGDS_GRBM_SECDED_CNT 0x25E3 +#define mmGDS_GWS_RESOURCE 0x25E1 +#define mmGDS_GWS_RESOURCE_CNTL 0x25E0 +#define mmGDS_OA_DED 0x25E4 +#define mmGDS_PERFCOUNTER0_HI 0x25E7 +#define mmGDS_PERFCOUNTER0_LO 0x25E6 +#define mmGDS_PERFCOUNTER0_SELECT 0x25E5 +#define mmGDS_PERFCOUNTER1_HI 0x25EA +#define mmGDS_PERFCOUNTER1_LO 0x25E9 +#define mmGDS_PERFCOUNTER1_SELECT 0x25E8 +#define mmGDS_PERFCOUNTER2_HI 0x25ED +#define mmGDS_PERFCOUNTER2_LO 0x25EC +#define mmGDS_PERFCOUNTER2_SELECT 0x25EB +#define mmGDS_PERFCOUNTER3_HI 0x25F0 +#define mmGDS_PERFCOUNTER3_LO 0x25EF +#define mmGDS_PERFCOUNTER3_SELECT 0x25EE +#define mmGDS_RD_ADDR 0x25C2 +#define mmGDS_RD_BURST_ADDR 0x25C4 +#define mmGDS_RD_BURST_COUNT 0x25C5 +#define mmGDS_RD_BURST_DATA 0x25C6 +#define mmGDS_RD_DATA 0x25C3 +#define mmGDS_SECDED_CNT 0x25E2 +#define mmGDS_WR_ADDR 0x25C7 +#define mmGDS_WR_BURST_ADDR 0x25C9 +#define mmGDS_WR_BURST_DATA 0x25CA +#define mmGDS_WR_DATA 0x25C8 +#define mmGDS_WRITE_COMPLETE 0x25CB +#define mmGFX_COPY_STATE 0xA1F4 +#define mmGRBM_CAM_DATA 0x3001 +#define mmGRBM_CAM_INDEX 0x3000 +#define mmGRBM_CNTL 0x2000 +#define mmGRBM_DEBUG 0x2014 +#define mmGRBM_DEBUG_CNTL 0x2009 +#define mmGRBM_DEBUG_DATA 0x200A +#define mmGRBM_DEBUG_SNAPSHOT 0x2015 +#define mmGRBM_GFX_CLKEN_CNTL 0x200C +#define mmGRBM_GFX_INDEX 0x200B +#define mmGRBM_INT_CNTL 0x2018 +#define mmGRBM_NOWHERE 0x203F +#define mmGRBM_PERFCOUNTER0_HI 0x201F +#define mmGRBM_PERFCOUNTER0_LO 0x201E +#define mmGRBM_PERFCOUNTER0_SELECT 0x201C +#define mmGRBM_PERFCOUNTER1_HI 0x2021 +#define mmGRBM_PERFCOUNTER1_LO 0x2020 +#define mmGRBM_PERFCOUNTER1_SELECT 0x201D +#define mmGRBM_PWR_CNTL 0x2003 +#define mmGRBM_READ_ERROR 0x2016 +#define mmGRBM_SCRATCH_REG0 0x2040 +#define mmGRBM_SCRATCH_REG1 0x2041 +#define mmGRBM_SCRATCH_REG2 0x2042 +#define mmGRBM_SCRATCH_REG3 0x2043 +#define mmGRBM_SCRATCH_REG4 0x2044 +#define mmGRBM_SCRATCH_REG5 0x2045 +#define mmGRBM_SCRATCH_REG6 0x2046 +#define mmGRBM_SCRATCH_REG7 0x2047 +#define mmGRBM_SE0_PERFCOUNTER_HI 0x202B +#define mmGRBM_SE0_PERFCOUNTER_LO 0x202A +#define mmGRBM_SE0_PERFCOUNTER_SELECT 0x2026 +#define mmGRBM_SE1_PERFCOUNTER_HI 0x202D +#define mmGRBM_SE1_PERFCOUNTER_LO 0x202C +#define mmGRBM_SE1_PERFCOUNTER_SELECT 0x2027 +#define mmGRBM_SKEW_CNTL 0x2001 +#define mmGRBM_SOFT_RESET 0x2008 +#define mmGRBM_STATUS 0x2004 +#define mmGRBM_STATUS2 0x2002 +#define mmGRBM_STATUS_SE0 0x2005 +#define mmGRBM_STATUS_SE1 0x2006 +#define mmGRBM_WAIT_IDLE_CLOCKS 0x200D +#define mmIA_CNTL_STATUS 0x2237 +#define mmIA_DEBUG_CNTL 0x223A +#define mmIA_DEBUG_DATA 0x223B +#define mmIA_ENHANCE 0xA29C +#define mmIA_MULTI_VGT_PARAM 0xA2AA +#define mmIA_PERFCOUNTER0_HI 0x2225 +#define mmIA_PERFCOUNTER0_LO 0x2224 +#define mmIA_PERFCOUNTER0_SELECT 0x2220 +#define mmIA_PERFCOUNTER1_HI 0x2227 +#define mmIA_PERFCOUNTER1_LO 0x2226 +#define mmIA_PERFCOUNTER1_SELECT 0x2221 +#define mmIA_PERFCOUNTER2_HI 0x2229 +#define mmIA_PERFCOUNTER2_LO 0x2228 +#define mmIA_PERFCOUNTER2_SELECT 0x2222 +#define mmIA_PERFCOUNTER3_HI 0x222B +#define mmIA_PERFCOUNTER3_LO 0x222A +#define mmIA_PERFCOUNTER3_SELECT 0x2223 +#define mmIA_VMID_OVERRIDE 0x2260 +#define mmPA_CL_CLIP_CNTL 0xA204 +#define mmPA_CL_CNTL_STATUS 0x2284 +#define mmPA_CL_ENHANCE 0x2285 +#define mmPA_CL_GB_HORZ_CLIP_ADJ 0xA2FC +#define mmPA_CL_GB_HORZ_DISC_ADJ 0xA2FD +#define mmPA_CL_GB_VERT_CLIP_ADJ 0xA2FA +#define mmPA_CL_GB_VERT_DISC_ADJ 0xA2FB +#define mmPA_CL_NANINF_CNTL 0xA208 +#define mmPA_CL_POINT_CULL_RAD 0xA1F8 +#define mmPA_CL_POINT_SIZE 0xA1F7 +#define mmPA_CL_POINT_X_RAD 0xA1F5 +#define mmPA_CL_POINT_Y_RAD 0xA1F6 +#define mmPA_CL_UCP_0_W 0xA172 +#define mmPA_CL_UCP_0_X 0xA16F +#define mmPA_CL_UCP_0_Y 0xA170 +#define mmPA_CL_UCP_0_Z 0xA171 +#define mmPA_CL_UCP_1_W 0xA176 +#define mmPA_CL_UCP_1_X 0xA173 +#define mmPA_CL_UCP_1_Y 0xA174 +#define mmPA_CL_UCP_1_Z 0xA175 +#define mmPA_CL_UCP_2_W 0xA17A +#define mmPA_CL_UCP_2_X 0xA177 +#define mmPA_CL_UCP_2_Y 0xA178 +#define mmPA_CL_UCP_2_Z 0xA179 +#define mmPA_CL_UCP_3_W 0xA17E +#define mmPA_CL_UCP_3_X 0xA17B +#define mmPA_CL_UCP_3_Y 0xA17C +#define mmPA_CL_UCP_3_Z 0xA17D +#define mmPA_CL_UCP_4_W 0xA182 +#define mmPA_CL_UCP_4_X 0xA17F +#define mmPA_CL_UCP_4_Y 0xA180 +#define mmPA_CL_UCP_4_Z 0xA181 +#define mmPA_CL_UCP_5_W 0xA186 +#define mmPA_CL_UCP_5_X 0xA183 +#define mmPA_CL_UCP_5_Y 0xA184 +#define mmPA_CL_UCP_5_Z 0xA185 +#define mmPA_CL_VPORT_XOFFSET 0xA110 +#define mmPA_CL_VPORT_XOFFSET_10 0xA14C +#define mmPA_CL_VPORT_XOFFSET_1 0xA116 +#define mmPA_CL_VPORT_XOFFSET_11 0xA152 +#define mmPA_CL_VPORT_XOFFSET_12 0xA158 +#define mmPA_CL_VPORT_XOFFSET_13 0xA15E +#define mmPA_CL_VPORT_XOFFSET_14 0xA164 +#define mmPA_CL_VPORT_XOFFSET_15 0xA16A +#define mmPA_CL_VPORT_XOFFSET_2 0xA11C +#define mmPA_CL_VPORT_XOFFSET_3 0xA122 +#define mmPA_CL_VPORT_XOFFSET_4 0xA128 +#define mmPA_CL_VPORT_XOFFSET_5 0xA12E +#define mmPA_CL_VPORT_XOFFSET_6 0xA134 +#define mmPA_CL_VPORT_XOFFSET_7 0xA13A +#define mmPA_CL_VPORT_XOFFSET_8 0xA140 +#define mmPA_CL_VPORT_XOFFSET_9 0xA146 +#define mmPA_CL_VPORT_XSCALE 0xA10F +#define mmPA_CL_VPORT_XSCALE_10 0xA14B +#define mmPA_CL_VPORT_XSCALE_1 0xA115 +#define mmPA_CL_VPORT_XSCALE_11 0xA151 +#define mmPA_CL_VPORT_XSCALE_12 0xA157 +#define mmPA_CL_VPORT_XSCALE_13 0xA15D +#define mmPA_CL_VPORT_XSCALE_14 0xA163 +#define mmPA_CL_VPORT_XSCALE_15 0xA169 +#define mmPA_CL_VPORT_XSCALE_2 0xA11B +#define mmPA_CL_VPORT_XSCALE_3 0xA121 +#define mmPA_CL_VPORT_XSCALE_4 0xA127 +#define mmPA_CL_VPORT_XSCALE_5 0xA12D +#define mmPA_CL_VPORT_XSCALE_6 0xA133 +#define mmPA_CL_VPORT_XSCALE_7 0xA139 +#define mmPA_CL_VPORT_XSCALE_8 0xA13F +#define mmPA_CL_VPORT_XSCALE_9 0xA145 +#define mmPA_CL_VPORT_YOFFSET 0xA112 +#define mmPA_CL_VPORT_YOFFSET_10 0xA14E +#define mmPA_CL_VPORT_YOFFSET_1 0xA118 +#define mmPA_CL_VPORT_YOFFSET_11 0xA154 +#define mmPA_CL_VPORT_YOFFSET_12 0xA15A +#define mmPA_CL_VPORT_YOFFSET_13 0xA160 +#define mmPA_CL_VPORT_YOFFSET_14 0xA166 +#define mmPA_CL_VPORT_YOFFSET_15 0xA16C +#define mmPA_CL_VPORT_YOFFSET_2 0xA11E +#define mmPA_CL_VPORT_YOFFSET_3 0xA124 +#define mmPA_CL_VPORT_YOFFSET_4 0xA12A +#define mmPA_CL_VPORT_YOFFSET_5 0xA130 +#define mmPA_CL_VPORT_YOFFSET_6 0xA136 +#define mmPA_CL_VPORT_YOFFSET_7 0xA13C +#define mmPA_CL_VPORT_YOFFSET_8 0xA142 +#define mmPA_CL_VPORT_YOFFSET_9 0xA148 +#define mmPA_CL_VPORT_YSCALE 0xA111 +#define mmPA_CL_VPORT_YSCALE_10 0xA14D +#define mmPA_CL_VPORT_YSCALE_1 0xA117 +#define mmPA_CL_VPORT_YSCALE_11 0xA153 +#define mmPA_CL_VPORT_YSCALE_12 0xA159 +#define mmPA_CL_VPORT_YSCALE_13 0xA15F +#define mmPA_CL_VPORT_YSCALE_14 0xA165 +#define mmPA_CL_VPORT_YSCALE_15 0xA16B +#define mmPA_CL_VPORT_YSCALE_2 0xA11D +#define mmPA_CL_VPORT_YSCALE_3 0xA123 +#define mmPA_CL_VPORT_YSCALE_4 0xA129 +#define mmPA_CL_VPORT_YSCALE_5 0xA12F +#define mmPA_CL_VPORT_YSCALE_6 0xA135 +#define mmPA_CL_VPORT_YSCALE_7 0xA13B +#define mmPA_CL_VPORT_YSCALE_8 0xA141 +#define mmPA_CL_VPORT_YSCALE_9 0xA147 +#define mmPA_CL_VPORT_ZOFFSET 0xA114 +#define mmPA_CL_VPORT_ZOFFSET_10 0xA150 +#define mmPA_CL_VPORT_ZOFFSET_1 0xA11A +#define mmPA_CL_VPORT_ZOFFSET_11 0xA156 +#define mmPA_CL_VPORT_ZOFFSET_12 0xA15C +#define mmPA_CL_VPORT_ZOFFSET_13 0xA162 +#define mmPA_CL_VPORT_ZOFFSET_14 0xA168 +#define mmPA_CL_VPORT_ZOFFSET_15 0xA16E +#define mmPA_CL_VPORT_ZOFFSET_2 0xA120 +#define mmPA_CL_VPORT_ZOFFSET_3 0xA126 +#define mmPA_CL_VPORT_ZOFFSET_4 0xA12C +#define mmPA_CL_VPORT_ZOFFSET_5 0xA132 +#define mmPA_CL_VPORT_ZOFFSET_6 0xA138 +#define mmPA_CL_VPORT_ZOFFSET_7 0xA13E +#define mmPA_CL_VPORT_ZOFFSET_8 0xA144 +#define mmPA_CL_VPORT_ZOFFSET_9 0xA14A +#define mmPA_CL_VPORT_ZSCALE 0xA113 +#define mmPA_CL_VPORT_ZSCALE_10 0xA14F +#define mmPA_CL_VPORT_ZSCALE_1 0xA119 +#define mmPA_CL_VPORT_ZSCALE_11 0xA155 +#define mmPA_CL_VPORT_ZSCALE_12 0xA15B +#define mmPA_CL_VPORT_ZSCALE_13 0xA161 +#define mmPA_CL_VPORT_ZSCALE_14 0xA167 +#define mmPA_CL_VPORT_ZSCALE_15 0xA16D +#define mmPA_CL_VPORT_ZSCALE_2 0xA11F +#define mmPA_CL_VPORT_ZSCALE_3 0xA125 +#define mmPA_CL_VPORT_ZSCALE_4 0xA12B +#define mmPA_CL_VPORT_ZSCALE_5 0xA131 +#define mmPA_CL_VPORT_ZSCALE_6 0xA137 +#define mmPA_CL_VPORT_ZSCALE_7 0xA13D +#define mmPA_CL_VPORT_ZSCALE_8 0xA143 +#define mmPA_CL_VPORT_ZSCALE_9 0xA149 +#define mmPA_CL_VS_OUT_CNTL 0xA207 +#define mmPA_CL_VTE_CNTL 0xA206 +#define mmPA_SC_AA_CONFIG 0xA2F8 +#define mmPA_SC_AA_MASK_X0Y0_X1Y0 0xA30E +#define mmPA_SC_AA_MASK_X0Y1_X1Y1 0xA30F +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0xA2FE +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0xA2FF +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0xA300 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0xA301 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0xA306 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0xA307 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0xA308 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0xA309 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0xA302 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0xA303 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0xA304 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0xA305 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0xA30A +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0xA30B +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0xA30C +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0xA30D +#define mmPA_SC_CENTROID_PRIORITY_0 0xA2F5 +#define mmPA_SC_CENTROID_PRIORITY_1 0xA2F6 +#define mmPA_SC_CLIPRECT_0_BR 0xA085 +#define mmPA_SC_CLIPRECT_0_TL 0xA084 +#define mmPA_SC_CLIPRECT_1_BR 0xA087 +#define mmPA_SC_CLIPRECT_1_TL 0xA086 +#define mmPA_SC_CLIPRECT_2_BR 0xA089 +#define mmPA_SC_CLIPRECT_2_TL 0xA088 +#define mmPA_SC_CLIPRECT_3_BR 0xA08B +#define mmPA_SC_CLIPRECT_3_TL 0xA08A +#define mmPA_SC_CLIPRECT_RULE 0xA083 +#define mmPA_SC_DEBUG_CNTL 0x22F6 +#define mmPA_SC_DEBUG_DATA 0x22F7 +#define mmPA_SC_EDGERULE 0xA08C +#define mmPA_SC_ENHANCE 0x22FC +#define mmPA_SC_FIFO_DEPTH_CNTL 0x2295 +#define mmPA_SC_FIFO_SIZE 0x22F3 +#define mmPA_SC_FORCE_EOV_MAX_CNTS 0x22C9 +#define mmPA_SC_GENERIC_SCISSOR_BR 0xA091 +#define mmPA_SC_GENERIC_SCISSOR_TL 0xA090 +#define mmPA_SC_IF_FIFO_SIZE 0x22F5 +#define mmPA_SC_LINE_CNTL 0xA2F7 +#define mmPA_SC_LINE_STIPPLE 0xA283 +#define mmPA_SC_LINE_STIPPLE_STATE 0x22C4 +#define mmPA_SC_MODE_CNTL_0 0xA292 +#define mmPA_SC_MODE_CNTL_1 0xA293 +#define mmPA_SC_PERFCOUNTER0_HI 0x22A9 +#define mmPA_SC_PERFCOUNTER0_LO 0x22A8 +#define mmPA_SC_PERFCOUNTER0_SELECT 0x22A0 +#define mmPA_SC_PERFCOUNTER1_HI 0x22AB +#define mmPA_SC_PERFCOUNTER1_LO 0x22AA +#define mmPA_SC_PERFCOUNTER1_SELECT 0x22A1 +#define mmPA_SC_PERFCOUNTER2_HI 0x22AD +#define mmPA_SC_PERFCOUNTER2_LO 0x22AC +#define mmPA_SC_PERFCOUNTER2_SELECT 0x22A2 +#define mmPA_SC_PERFCOUNTER3_HI 0x22AF +#define mmPA_SC_PERFCOUNTER3_LO 0x22AE +#define mmPA_SC_PERFCOUNTER3_SELECT 0x22A3 +#define mmPA_SC_PERFCOUNTER4_HI 0x22B1 +#define mmPA_SC_PERFCOUNTER4_LO 0x22B0 +#define mmPA_SC_PERFCOUNTER4_SELECT 0x22A4 +#define mmPA_SC_PERFCOUNTER5_HI 0x22B3 +#define mmPA_SC_PERFCOUNTER5_LO 0x22B2 +#define mmPA_SC_PERFCOUNTER5_SELECT 0x22A5 +#define mmPA_SC_PERFCOUNTER6_HI 0x22B5 +#define mmPA_SC_PERFCOUNTER6_LO 0x22B4 +#define mmPA_SC_PERFCOUNTER6_SELECT 0x22A6 +#define mmPA_SC_PERFCOUNTER7_HI 0x22B7 +#define mmPA_SC_PERFCOUNTER7_LO 0x22B6 +#define mmPA_SC_PERFCOUNTER7_SELECT 0x22A7 +#define mmPA_SC_RASTER_CONFIG 0xA0D4 +#define mmPA_SC_SCREEN_SCISSOR_BR 0xA00D +#define mmPA_SC_SCREEN_SCISSOR_TL 0xA00C +#define mmPA_SC_VPORT_SCISSOR_0_BR 0xA095 +#define mmPA_SC_VPORT_SCISSOR_0_TL 0xA094 +#define mmPA_SC_VPORT_SCISSOR_10_BR 0xA0A9 +#define mmPA_SC_VPORT_SCISSOR_10_TL 0xA0A8 +#define mmPA_SC_VPORT_SCISSOR_11_BR 0xA0AB +#define mmPA_SC_VPORT_SCISSOR_11_TL 0xA0AA +#define mmPA_SC_VPORT_SCISSOR_12_BR 0xA0AD +#define mmPA_SC_VPORT_SCISSOR_12_TL 0xA0AC +#define mmPA_SC_VPORT_SCISSOR_13_BR 0xA0AF +#define mmPA_SC_VPORT_SCISSOR_13_TL 0xA0AE +#define mmPA_SC_VPORT_SCISSOR_14_BR 0xA0B1 +#define mmPA_SC_VPORT_SCISSOR_14_TL 0xA0B0 +#define mmPA_SC_VPORT_SCISSOR_15_BR 0xA0B3 +#define mmPA_SC_VPORT_SCISSOR_15_TL 0xA0B2 +#define mmPA_SC_VPORT_SCISSOR_1_BR 0xA097 +#define mmPA_SC_VPORT_SCISSOR_1_TL 0xA096 +#define mmPA_SC_VPORT_SCISSOR_2_BR 0xA099 +#define mmPA_SC_VPORT_SCISSOR_2_TL 0xA098 +#define mmPA_SC_VPORT_SCISSOR_3_BR 0xA09B +#define mmPA_SC_VPORT_SCISSOR_3_TL 0xA09A +#define mmPA_SC_VPORT_SCISSOR_4_BR 0xA09D +#define mmPA_SC_VPORT_SCISSOR_4_TL 0xA09C +#define mmPA_SC_VPORT_SCISSOR_5_BR 0xA09F +#define mmPA_SC_VPORT_SCISSOR_5_TL 0xA09E +#define mmPA_SC_VPORT_SCISSOR_6_BR 0xA0A1 +#define mmPA_SC_VPORT_SCISSOR_6_TL 0xA0A0 +#define mmPA_SC_VPORT_SCISSOR_7_BR 0xA0A3 +#define mmPA_SC_VPORT_SCISSOR_7_TL 0xA0A2 +#define mmPA_SC_VPORT_SCISSOR_8_BR 0xA0A5 +#define mmPA_SC_VPORT_SCISSOR_8_TL 0xA0A4 +#define mmPA_SC_VPORT_SCISSOR_9_BR 0xA0A7 +#define mmPA_SC_VPORT_SCISSOR_9_TL 0xA0A6 +#define mmPA_SC_VPORT_ZMAX_0 0xA0B5 +#define mmPA_SC_VPORT_ZMAX_10 0xA0C9 +#define mmPA_SC_VPORT_ZMAX_1 0xA0B7 +#define mmPA_SC_VPORT_ZMAX_11 0xA0CB +#define mmPA_SC_VPORT_ZMAX_12 0xA0CD +#define mmPA_SC_VPORT_ZMAX_13 0xA0CF +#define mmPA_SC_VPORT_ZMAX_14 0xA0D1 +#define mmPA_SC_VPORT_ZMAX_15 0xA0D3 +#define mmPA_SC_VPORT_ZMAX_2 0xA0B9 +#define mmPA_SC_VPORT_ZMAX_3 0xA0BB +#define mmPA_SC_VPORT_ZMAX_4 0xA0BD +#define mmPA_SC_VPORT_ZMAX_5 0xA0BF +#define mmPA_SC_VPORT_ZMAX_6 0xA0C1 +#define mmPA_SC_VPORT_ZMAX_7 0xA0C3 +#define mmPA_SC_VPORT_ZMAX_8 0xA0C5 +#define mmPA_SC_VPORT_ZMAX_9 0xA0C7 +#define mmPA_SC_VPORT_ZMIN_0 0xA0B4 +#define mmPA_SC_VPORT_ZMIN_10 0xA0C8 +#define mmPA_SC_VPORT_ZMIN_1 0xA0B6 +#define mmPA_SC_VPORT_ZMIN_11 0xA0CA +#define mmPA_SC_VPORT_ZMIN_12 0xA0CC +#define mmPA_SC_VPORT_ZMIN_13 0xA0CE +#define mmPA_SC_VPORT_ZMIN_14 0xA0D0 +#define mmPA_SC_VPORT_ZMIN_15 0xA0D2 +#define mmPA_SC_VPORT_ZMIN_2 0xA0B8 +#define mmPA_SC_VPORT_ZMIN_3 0xA0BA +#define mmPA_SC_VPORT_ZMIN_4 0xA0BC +#define mmPA_SC_VPORT_ZMIN_5 0xA0BE +#define mmPA_SC_VPORT_ZMIN_6 0xA0C0 +#define mmPA_SC_VPORT_ZMIN_7 0xA0C2 +#define mmPA_SC_VPORT_ZMIN_8 0xA0C4 +#define mmPA_SC_VPORT_ZMIN_9 0xA0C6 +#define mmPA_SC_WINDOW_OFFSET 0xA080 +#define mmPA_SC_WINDOW_SCISSOR_BR 0xA082 +#define mmPA_SC_WINDOW_SCISSOR_TL 0xA081 +#define mmPA_SU_CNTL_STATUS 0x2294 +#define mmPA_SU_DEBUG_CNTL 0x2280 +#define mmPA_SU_DEBUG_DATA 0x2281 +#define mmPA_SU_HARDWARE_SCREEN_OFFSET 0xA08D +#define mmPA_SU_LINE_CNTL 0xA282 +#define mmPA_SU_LINE_STIPPLE_CNTL 0xA209 +#define mmPA_SU_LINE_STIPPLE_SCALE 0xA20A +#define mmPA_SU_LINE_STIPPLE_VALUE 0x2298 +#define mmPA_SU_PERFCOUNTER0_HI 0x228D +#define mmPA_SU_PERFCOUNTER0_LO 0x228C +#define mmPA_SU_PERFCOUNTER0_SELECT 0x2288 +#define mmPA_SU_PERFCOUNTER1_HI 0x228F +#define mmPA_SU_PERFCOUNTER1_LO 0x228E +#define mmPA_SU_PERFCOUNTER1_SELECT 0x2289 +#define mmPA_SU_PERFCOUNTER2_HI 0x2291 +#define mmPA_SU_PERFCOUNTER2_LO 0x2290 +#define mmPA_SU_PERFCOUNTER2_SELECT 0x228A +#define mmPA_SU_PERFCOUNTER3_HI 0x2293 +#define mmPA_SU_PERFCOUNTER3_LO 0x2292 +#define mmPA_SU_PERFCOUNTER3_SELECT 0x228B +#define mmPA_SU_POINT_MINMAX 0xA281 +#define mmPA_SU_POINT_SIZE 0xA280 +#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0xA2E3 +#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0xA2E2 +#define mmPA_SU_POLY_OFFSET_CLAMP 0xA2DF +#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0xA2DE +#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0xA2E1 +#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0xA2E0 +#define mmPA_SU_PRIM_FILTER_CNTL 0xA20B +#define mmPA_SU_SC_MODE_CNTL 0xA205 +#define mmPA_SU_VTX_CNTL 0xA2F9 +#define mmRAS_BCI_SIGNATURE0 0x339E +#define mmRAS_BCI_SIGNATURE1 0x339F +#define mmRAS_CB_SIGNATURE0 0x339D +#define mmRAS_DB_SIGNATURE0 0x338B +#define mmRAS_IA_SIGNATURE0 0x3397 +#define mmRAS_IA_SIGNATURE1 0x3398 +#define mmRAS_PA_SIGNATURE0 0x338C +#define mmRAS_SC_SIGNATURE0 0x338F +#define mmRAS_SC_SIGNATURE1 0x3390 +#define mmRAS_SC_SIGNATURE2 0x3391 +#define mmRAS_SC_SIGNATURE3 0x3392 +#define mmRAS_SC_SIGNATURE4 0x3393 +#define mmRAS_SC_SIGNATURE5 0x3394 +#define mmRAS_SC_SIGNATURE6 0x3395 +#define mmRAS_SC_SIGNATURE7 0x3396 +#define mmRAS_SIGNATURE_CONTROL 0x3380 +#define mmRAS_SIGNATURE_MASK 0x3381 +#define mmRAS_SPI_SIGNATURE0 0x3399 +#define mmRAS_SPI_SIGNATURE1 0x339A +#define mmRAS_SQ_SIGNATURE0 0x338E +#define mmRAS_SX_SIGNATURE0 0x3382 +#define mmRAS_SX_SIGNATURE1 0x3383 +#define mmRAS_SX_SIGNATURE2 0x3384 +#define mmRAS_SX_SIGNATURE3 0x3385 +#define mmRAS_TA_SIGNATURE0 0x339B +#define mmRAS_TD_SIGNATURE0 0x339C +#define mmRAS_VGT_SIGNATURE0 0x338D +#define mmRLC_AUTO_PG_CTRL 0x310D +#define mmRLC_CAPTURE_GPU_CLOCK_COUNT 0x30D0 +#define mmRLC_CGCG_CGLS_CTRL 0x3101 +#define mmRLC_CGCG_RAMP_CTRL 0x3102 +#define mmRLC_CGTT_MGCG_OVERRIDE 0x3100 +#define mmRLC_CNTL 0x30C0 +#define mmRLC_CU_STATUS 0x3106 +#define mmRLC_DEBUG 0x30CA +#define mmRLC_DEBUG_SELECT 0x30C9 +#define mmRLC_DRIVER_CPDMA_STATUS 0x30C7 +#define mmRLC_DYN_PG_REQUEST 0x3104 +#define mmRLC_DYN_PG_STATUS 0x3103 +#define mmRLC_GPU_CLOCK_32 0x30D5 +#define mmRLC_GPU_CLOCK_32_RES_SEL 0x30D4 +#define mmRLC_GPU_CLOCK_COUNT_LSB 0x30CE +#define mmRLC_GPU_CLOCK_COUNT_MSB 0x30CF +#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK 0x3108 +#define mmRLC_LB_CNTL 0x30C3 +#define mmRLC_LB_CNTR_INIT 0x30C6 +#define mmRLC_LB_CNTR_MAX 0x30C5 +#define mmRLC_LB_INIT_CU_MASK 0x3107 +#define mmRLC_LB_PARAMS 0x3109 +#define mmRLC_LOAD_BALANCE_CNTR 0x30F6 +#define mmRLC_MAX_PG_CU 0x310C +#define mmRLC_MC_CNTL 0x30D1 +#define mmRLC_MEM_SLP_CNTL 0x30D8 +#define mmRLC_PERFCOUNTER0_HI 0x30DC +#define mmRLC_PERFCOUNTER0_LO 0x30DB +#define mmRLC_PERFCOUNTER0_SELECT 0x30DA +#define mmRLC_PERFCOUNTER1_HI 0x30DF +#define mmRLC_PERFCOUNTER1_LO 0x30DE +#define mmRLC_PERFCOUNTER1_SELECT 0x30DD +#define mmRLC_PERFMON_CNTL 0x30D9 +#define mmRLC_PG_ALWAYS_ON_CU_MASK 0x310B +#define mmRLC_PG_CNTL 0x30D7 +#define mmRLC_SAVE_AND_RESTORE_BASE 0x30C4 +#define mmRLC_SERDES_RD_DATA_0 0x3112 +#define mmRLC_SERDES_RD_DATA_1 0x3113 +#define mmRLC_SERDES_RD_DATA_2 0x3114 +#define mmRLC_SERDES_RD_MASTER_INDEX 0x3111 +#define mmRLC_SERDES_WR_CTRL 0x3117 +#define mmRLC_SERDES_WR_DATA 0x3118 +#define mmRLC_SMU_GRBM_REG_SAVE_CTRL 0x310E +#define mmRLC_SMU_PG_CTRL 0x310F +#define mmRLC_SMU_PG_WAKE_UP_CTRL 0x3110 +#define mmRLC_SOFT_RESET_GPU 0x30D6 +#define mmRLC_STAT 0x30D3 +#define mmRLC_THREAD1_DELAY 0x310A +#define mmRLC_UCODE_CNTL 0x30D2 +#define mmSCRATCH_ADDR 0x2151 +#define mmSCRATCH_REG0 0x2140 +#define mmSCRATCH_REG1 0x2141 +#define mmSCRATCH_REG2 0x2142 +#define mmSCRATCH_REG3 0x2143 +#define mmSCRATCH_REG4 0x2144 +#define mmSCRATCH_REG5 0x2145 +#define mmSCRATCH_REG6 0x2146 +#define mmSCRATCH_REG7 0x2147 +#define mmSCRATCH_UMSK 0x2150 +#define mmSPI_ARB_CYCLES_0 0x243D +#define mmSPI_ARB_CYCLES_1 0x243E +#define mmSPI_ARB_PRIORITY 0x243C +#define mmSPI_BARYC_CNTL 0xA1B8 +#define mmSPI_CONFIG_CNTL 0x2440 +#define mmSPI_CONFIG_CNTL_1 0x244F +#define mmSPI_DEBUG_BUSY 0x2450 +#define mmSPI_DEBUG_CNTL 0x2441 +#define mmSPI_DEBUG_READ 0x2442 +#define mmSPI_GDS_CREDITS 0x24D8 +#define mmSPI_INTERP_CONTROL_0 0xA1B5 +#define mmSPI_LB_CTR_CTRL 0x24D4 +#define mmSPI_LB_CU_MASK 0x24D5 +#define mmSPI_LB_DATA_REG 0x24D6 +#define mmSPI_PERFCOUNTER0_HI 0x2447 +#define mmSPI_PERFCOUNTER0_LO 0x2448 +#define mmSPI_PERFCOUNTER0_SELECT 0x2443 +#define mmSPI_PERFCOUNTER1_HI 0x2449 +#define mmSPI_PERFCOUNTER1_LO 0x244A +#define mmSPI_PERFCOUNTER1_SELECT 0x2444 +#define mmSPI_PERFCOUNTER2_HI 0x244B +#define mmSPI_PERFCOUNTER2_LO 0x244C +#define mmSPI_PERFCOUNTER2_SELECT 0x2445 +#define mmSPI_PERFCOUNTER3_HI 0x244D +#define mmSPI_PERFCOUNTER3_LO 0x244E +#define mmSPI_PERFCOUNTER3_SELECT 0x2446 +#define mmSPI_PERFCOUNTER_BINS 0x243F +#define mmSPI_PG_ENABLE_STATIC_CU_MASK 0x24D7 +#define mmSPI_PS_IN_CONTROL 0xA1B6 +#define mmSPI_PS_INPUT_ADDR 0xA1B4 +#define mmSPI_PS_INPUT_CNTL_0 0xA191 +#define mmSPI_PS_INPUT_CNTL_10 0xA19B +#define mmSPI_PS_INPUT_CNTL_1 0xA192 +#define mmSPI_PS_INPUT_CNTL_11 0xA19C +#define mmSPI_PS_INPUT_CNTL_12 0xA19D +#define mmSPI_PS_INPUT_CNTL_13 0xA19E +#define mmSPI_PS_INPUT_CNTL_14 0xA19F +#define mmSPI_PS_INPUT_CNTL_15 0xA1A0 +#define mmSPI_PS_INPUT_CNTL_16 0xA1A1 +#define mmSPI_PS_INPUT_CNTL_17 0xA1A2 +#define mmSPI_PS_INPUT_CNTL_18 0xA1A3 +#define mmSPI_PS_INPUT_CNTL_19 0xA1A4 +#define mmSPI_PS_INPUT_CNTL_20 0xA1A5 +#define mmSPI_PS_INPUT_CNTL_2 0xA193 +#define mmSPI_PS_INPUT_CNTL_21 0xA1A6 +#define mmSPI_PS_INPUT_CNTL_22 0xA1A7 +#define mmSPI_PS_INPUT_CNTL_23 0xA1A8 +#define mmSPI_PS_INPUT_CNTL_24 0xA1A9 +#define mmSPI_PS_INPUT_CNTL_25 0xA1AA +#define mmSPI_PS_INPUT_CNTL_26 0xA1AB +#define mmSPI_PS_INPUT_CNTL_27 0xA1AC +#define mmSPI_PS_INPUT_CNTL_28 0xA1AD +#define mmSPI_PS_INPUT_CNTL_29 0xA1AE +#define mmSPI_PS_INPUT_CNTL_30 0xA1AF +#define mmSPI_PS_INPUT_CNTL_3 0xA194 +#define mmSPI_PS_INPUT_CNTL_31 0xA1B0 +#define mmSPI_PS_INPUT_CNTL_4 0xA195 +#define mmSPI_PS_INPUT_CNTL_5 0xA196 +#define mmSPI_PS_INPUT_CNTL_6 0xA197 +#define mmSPI_PS_INPUT_CNTL_7 0xA198 +#define mmSPI_PS_INPUT_CNTL_8 0xA199 +#define mmSPI_PS_INPUT_CNTL_9 0xA19A +#define mmSPI_PS_INPUT_ENA 0xA1B3 +#define mmSPI_PS_MAX_WAVE_ID 0x243B +#define mmSPI_SHADER_COL_FORMAT 0xA1C5 +#define mmSPI_SHADER_PGM_HI_ES 0x2CC9 +#define mmSPI_SHADER_PGM_HI_GS 0x2C89 +#define mmSPI_SHADER_PGM_HI_HS 0x2D09 +#define mmSPI_SHADER_PGM_HI_LS 0x2D49 +#define mmSPI_SHADER_PGM_HI_PS 0x2C09 +#define mmSPI_SHADER_PGM_HI_VS 0x2C49 +#define mmSPI_SHADER_PGM_LO_ES 0x2CC8 +#define mmSPI_SHADER_PGM_LO_GS 0x2C88 +#define mmSPI_SHADER_PGM_LO_HS 0x2D08 +#define mmSPI_SHADER_PGM_LO_LS 0x2D48 +#define mmSPI_SHADER_PGM_LO_PS 0x2C08 +#define mmSPI_SHADER_PGM_LO_VS 0x2C48 +#define mmSPI_SHADER_PGM_RSRC1_ES 0x2CCA +#define mmSPI_SHADER_PGM_RSRC1_GS 0x2C8A +#define mmSPI_SHADER_PGM_RSRC1_HS 0x2D0A +#define mmSPI_SHADER_PGM_RSRC1_LS 0x2D4A +#define mmSPI_SHADER_PGM_RSRC1_PS 0x2C0A +#define mmSPI_SHADER_PGM_RSRC1_VS 0x2C4A +#define mmSPI_SHADER_PGM_RSRC2_ES 0x2CCB +#define mmSPI_SHADER_PGM_RSRC2_GS 0x2C8B +#define mmSPI_SHADER_PGM_RSRC2_HS 0x2D0B +#define mmSPI_SHADER_PGM_RSRC2_LS 0x2D4B +#define mmSPI_SHADER_PGM_RSRC2_PS 0x2C0B +#define mmSPI_SHADER_PGM_RSRC2_VS 0x2C4B +#define mmSPI_SHADER_POS_FORMAT 0xA1C3 +#define mmSPI_SHADER_TBA_HI_ES 0x2CC1 +#define mmSPI_SHADER_TBA_HI_GS 0x2C81 +#define mmSPI_SHADER_TBA_HI_HS 0x2D01 +#define mmSPI_SHADER_TBA_HI_LS 0x2D41 +#define mmSPI_SHADER_TBA_HI_PS 0x2C01 +#define mmSPI_SHADER_TBA_HI_VS 0x2C41 +#define mmSPI_SHADER_TBA_LO_ES 0x2CC0 +#define mmSPI_SHADER_TBA_LO_GS 0x2C80 +#define mmSPI_SHADER_TBA_LO_HS 0x2D00 +#define mmSPI_SHADER_TBA_LO_LS 0x2D40 +#define mmSPI_SHADER_TBA_LO_PS 0x2C00 +#define mmSPI_SHADER_TBA_LO_VS 0x2C40 +#define mmSPI_SHADER_TMA_HI_ES 0x2CC3 +#define mmSPI_SHADER_TMA_HI_GS 0x2C83 +#define mmSPI_SHADER_TMA_HI_HS 0x2D03 +#define mmSPI_SHADER_TMA_HI_LS 0x2D43 +#define mmSPI_SHADER_TMA_HI_PS 0x2C03 +#define mmSPI_SHADER_TMA_HI_VS 0x2C43 +#define mmSPI_SHADER_TMA_LO_ES 0x2CC2 +#define mmSPI_SHADER_TMA_LO_GS 0x2C82 +#define mmSPI_SHADER_TMA_LO_HS 0x2D02 +#define mmSPI_SHADER_TMA_LO_LS 0x2D42 +#define mmSPI_SHADER_TMA_LO_PS 0x2C02 +#define mmSPI_SHADER_TMA_LO_VS 0x2C42 +#define mmSPI_SHADER_USER_DATA_ES_0 0x2CCC +#define mmSPI_SHADER_USER_DATA_ES_10 0x2CD6 +#define mmSPI_SHADER_USER_DATA_ES_1 0x2CCD +#define mmSPI_SHADER_USER_DATA_ES_11 0x2CD7 +#define mmSPI_SHADER_USER_DATA_ES_12 0x2CD8 +#define mmSPI_SHADER_USER_DATA_ES_13 0x2CD9 +#define mmSPI_SHADER_USER_DATA_ES_14 0x2CDA +#define mmSPI_SHADER_USER_DATA_ES_15 0x2CDB +#define mmSPI_SHADER_USER_DATA_ES_2 0x2CCE +#define mmSPI_SHADER_USER_DATA_ES_3 0x2CCF +#define mmSPI_SHADER_USER_DATA_ES_4 0x2CD0 +#define mmSPI_SHADER_USER_DATA_ES_5 0x2CD1 +#define mmSPI_SHADER_USER_DATA_ES_6 0x2CD2 +#define mmSPI_SHADER_USER_DATA_ES_7 0x2CD3 +#define mmSPI_SHADER_USER_DATA_ES_8 0x2CD4 +#define mmSPI_SHADER_USER_DATA_ES_9 0x2CD5 +#define mmSPI_SHADER_USER_DATA_GS_0 0x2C8C +#define mmSPI_SHADER_USER_DATA_GS_10 0x2C96 +#define mmSPI_SHADER_USER_DATA_GS_1 0x2C8D +#define mmSPI_SHADER_USER_DATA_GS_11 0x2C97 +#define mmSPI_SHADER_USER_DATA_GS_12 0x2C98 +#define mmSPI_SHADER_USER_DATA_GS_13 0x2C99 +#define mmSPI_SHADER_USER_DATA_GS_14 0x2C9A +#define mmSPI_SHADER_USER_DATA_GS_15 0x2C9B +#define mmSPI_SHADER_USER_DATA_GS_2 0x2C8E +#define mmSPI_SHADER_USER_DATA_GS_3 0x2C8F +#define mmSPI_SHADER_USER_DATA_GS_4 0x2C90 +#define mmSPI_SHADER_USER_DATA_GS_5 0x2C91 +#define mmSPI_SHADER_USER_DATA_GS_6 0x2C92 +#define mmSPI_SHADER_USER_DATA_GS_7 0x2C93 +#define mmSPI_SHADER_USER_DATA_GS_8 0x2C94 +#define mmSPI_SHADER_USER_DATA_GS_9 0x2C95 +#define mmSPI_SHADER_USER_DATA_HS_0 0x2D0C +#define mmSPI_SHADER_USER_DATA_HS_10 0x2D16 +#define mmSPI_SHADER_USER_DATA_HS_1 0x2D0D +#define mmSPI_SHADER_USER_DATA_HS_11 0x2D17 +#define mmSPI_SHADER_USER_DATA_HS_12 0x2D18 +#define mmSPI_SHADER_USER_DATA_HS_13 0x2D19 +#define mmSPI_SHADER_USER_DATA_HS_14 0x2D1A +#define mmSPI_SHADER_USER_DATA_HS_15 0x2D1B +#define mmSPI_SHADER_USER_DATA_HS_2 0x2D0E +#define mmSPI_SHADER_USER_DATA_HS_3 0x2D0F +#define mmSPI_SHADER_USER_DATA_HS_4 0x2D10 +#define mmSPI_SHADER_USER_DATA_HS_5 0x2D11 +#define mmSPI_SHADER_USER_DATA_HS_6 0x2D12 +#define mmSPI_SHADER_USER_DATA_HS_7 0x2D13 +#define mmSPI_SHADER_USER_DATA_HS_8 0x2D14 +#define mmSPI_SHADER_USER_DATA_HS_9 0x2D15 +#define mmSPI_SHADER_USER_DATA_LS_0 0x2D4C +#define mmSPI_SHADER_USER_DATA_LS_10 0x2D56 +#define mmSPI_SHADER_USER_DATA_LS_1 0x2D4D +#define mmSPI_SHADER_USER_DATA_LS_11 0x2D57 +#define mmSPI_SHADER_USER_DATA_LS_12 0x2D58 +#define mmSPI_SHADER_USER_DATA_LS_13 0x2D59 +#define mmSPI_SHADER_USER_DATA_LS_14 0x2D5A +#define mmSPI_SHADER_USER_DATA_LS_15 0x2D5B +#define mmSPI_SHADER_USER_DATA_LS_2 0x2D4E +#define mmSPI_SHADER_USER_DATA_LS_3 0x2D4F +#define mmSPI_SHADER_USER_DATA_LS_4 0x2D50 +#define mmSPI_SHADER_USER_DATA_LS_5 0x2D51 +#define mmSPI_SHADER_USER_DATA_LS_6 0x2D52 +#define mmSPI_SHADER_USER_DATA_LS_7 0x2D53 +#define mmSPI_SHADER_USER_DATA_LS_8 0x2D54 +#define mmSPI_SHADER_USER_DATA_LS_9 0x2D55 +#define mmSPI_SHADER_USER_DATA_PS_0 0x2C0C +#define mmSPI_SHADER_USER_DATA_PS_10 0x2C16 +#define mmSPI_SHADER_USER_DATA_PS_1 0x2C0D +#define mmSPI_SHADER_USER_DATA_PS_11 0x2C17 +#define mmSPI_SHADER_USER_DATA_PS_12 0x2C18 +#define mmSPI_SHADER_USER_DATA_PS_13 0x2C19 +#define mmSPI_SHADER_USER_DATA_PS_14 0x2C1A +#define mmSPI_SHADER_USER_DATA_PS_15 0x2C1B +#define mmSPI_SHADER_USER_DATA_PS_2 0x2C0E +#define mmSPI_SHADER_USER_DATA_PS_3 0x2C0F +#define mmSPI_SHADER_USER_DATA_PS_4 0x2C10 +#define mmSPI_SHADER_USER_DATA_PS_5 0x2C11 +#define mmSPI_SHADER_USER_DATA_PS_6 0x2C12 +#define mmSPI_SHADER_USER_DATA_PS_7 0x2C13 +#define mmSPI_SHADER_USER_DATA_PS_8 0x2C14 +#define mmSPI_SHADER_USER_DATA_PS_9 0x2C15 +#define mmSPI_SHADER_USER_DATA_VS_0 0x2C4C +#define mmSPI_SHADER_USER_DATA_VS_10 0x2C56 +#define mmSPI_SHADER_USER_DATA_VS_1 0x2C4D +#define mmSPI_SHADER_USER_DATA_VS_11 0x2C57 +#define mmSPI_SHADER_USER_DATA_VS_12 0x2C58 +#define mmSPI_SHADER_USER_DATA_VS_13 0x2C59 +#define mmSPI_SHADER_USER_DATA_VS_14 0x2C5A +#define mmSPI_SHADER_USER_DATA_VS_15 0x2C5B +#define mmSPI_SHADER_USER_DATA_VS_2 0x2C4E +#define mmSPI_SHADER_USER_DATA_VS_3 0x2C4F +#define mmSPI_SHADER_USER_DATA_VS_4 0x2C50 +#define mmSPI_SHADER_USER_DATA_VS_5 0x2C51 +#define mmSPI_SHADER_USER_DATA_VS_6 0x2C52 +#define mmSPI_SHADER_USER_DATA_VS_7 0x2C53 +#define mmSPI_SHADER_USER_DATA_VS_8 0x2C54 +#define mmSPI_SHADER_USER_DATA_VS_9 0x2C55 +#define mmSPI_SHADER_Z_FORMAT 0xA1C4 +#define mmSPI_SLAVE_DEBUG_BUSY 0x24D3 +#define mmSPI_SX_EXPORT_BUFFER_SIZES 0x24D9 +#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES 0x24DA +#define mmSPI_TMPRING_SIZE 0xA1BA +#define mmSPI_VS_OUT_CONFIG 0xA1B1 +#define mmSQ_ALU_CLK_CTRL 0x2360 +#define mmSQ_BUF_RSRC_WORD0 0x23C0 +#define mmSQ_BUF_RSRC_WORD1 0x23C1 +#define mmSQ_BUF_RSRC_WORD2 0x23C2 +#define mmSQ_BUF_RSRC_WORD3 0x23C3 +#define mmSQC_CACHES 0x2302 +#define mmSQC_CONFIG 0x2301 +#define mmSQ_CONFIG 0x2300 +#define mmSQC_SECDED_CNT 0x23A0 +#define mmSQ_DEBUG_STS_GLOBAL 0x2309 +#define mmSQ_DED_CNT 0x23A2 +#define mmSQ_DED_INFO 0x23A3 +#define mmSQ_DS_0 0x237F +#define mmSQ_DS_1 0x237F +#define mmSQ_EXP_0 0x237F +#define mmSQ_EXP_1 0x237F +#define mmSQ_FIFO_SIZES 0x2305 +#define mmSQ_IMG_RSRC_WORD0 0x23C4 +#define mmSQ_IMG_RSRC_WORD1 0x23C5 +#define mmSQ_IMG_RSRC_WORD2 0x23C6 +#define mmSQ_IMG_RSRC_WORD3 0x23C7 +#define mmSQ_IMG_RSRC_WORD4 0x23C8 +#define mmSQ_IMG_RSRC_WORD5 0x23C9 +#define mmSQ_IMG_RSRC_WORD6 0x23CA +#define mmSQ_IMG_RSRC_WORD7 0x23CB +#define mmSQ_IMG_SAMP_WORD0 0x23CC +#define mmSQ_IMG_SAMP_WORD1 0x23CD +#define mmSQ_IMG_SAMP_WORD2 0x23CE +#define mmSQ_IMG_SAMP_WORD3 0x23CF +#define mmSQ_IND_CMD 0x237A +#define mmSQ_IND_DATA 0x2379 +#define mmSQ_IND_INDEX 0x2378 +#define mmSQ_INST 0x237F +#define mmSQ_LB_CTR_CTRL 0x2398 +#define mmSQ_LB_DATA_ALU_CYCLES 0x2399 +#define mmSQ_LB_DATA_ALU_STALLS 0x239B +#define mmSQ_LB_DATA_TEX_CYCLES 0x239A +#define mmSQ_LB_DATA_TEX_STALLS 0x239C +#define mmSQ_MIMG_0 0x237F +#define mmSQ_MIMG_1 0x237F +#define mmSQ_MTBUF_0 0x237F +#define mmSQ_MTBUF_1 0x237F +#define mmSQ_MUBUF_0 0x237F +#define mmSQ_MUBUF_1 0x237F +#define mmSQ_PERFCOUNTER0_HI 0x2321 +#define mmSQ_PERFCOUNTER0_LO 0x2320 +#define mmSQ_PERFCOUNTER0_SELECT 0x2340 +#define mmSQ_PERFCOUNTER10_HI 0x2335 +#define mmSQ_PERFCOUNTER10_LO 0x2334 +#define mmSQ_PERFCOUNTER10_SELECT 0x234A +#define mmSQ_PERFCOUNTER11_HI 0x2337 +#define mmSQ_PERFCOUNTER11_LO 0x2336 +#define mmSQ_PERFCOUNTER11_SELECT 0x234B +#define mmSQ_PERFCOUNTER12_HI 0x2339 +#define mmSQ_PERFCOUNTER12_LO 0x2338 +#define mmSQ_PERFCOUNTER12_SELECT 0x234C +#define mmSQ_PERFCOUNTER13_HI 0x233B +#define mmSQ_PERFCOUNTER13_LO 0x233A +#define mmSQ_PERFCOUNTER13_SELECT 0x234D +#define mmSQ_PERFCOUNTER14_HI 0x233D +#define mmSQ_PERFCOUNTER14_LO 0x233C +#define mmSQ_PERFCOUNTER14_SELECT 0x234E +#define mmSQ_PERFCOUNTER15_HI 0x233F +#define mmSQ_PERFCOUNTER15_LO 0x233E +#define mmSQ_PERFCOUNTER15_SELECT 0x234F +#define mmSQ_PERFCOUNTER1_HI 0x2323 +#define mmSQ_PERFCOUNTER1_LO 0x2322 +#define mmSQ_PERFCOUNTER1_SELECT 0x2341 +#define mmSQ_PERFCOUNTER2_HI 0x2325 +#define mmSQ_PERFCOUNTER2_LO 0x2324 +#define mmSQ_PERFCOUNTER2_SELECT 0x2342 +#define mmSQ_PERFCOUNTER3_HI 0x2327 +#define mmSQ_PERFCOUNTER3_LO 0x2326 +#define mmSQ_PERFCOUNTER3_SELECT 0x2343 +#define mmSQ_PERFCOUNTER4_HI 0x2329 +#define mmSQ_PERFCOUNTER4_LO 0x2328 +#define mmSQ_PERFCOUNTER4_SELECT 0x2344 +#define mmSQ_PERFCOUNTER5_HI 0x232B +#define mmSQ_PERFCOUNTER5_LO 0x232A +#define mmSQ_PERFCOUNTER5_SELECT 0x2345 +#define mmSQ_PERFCOUNTER6_HI 0x232D +#define mmSQ_PERFCOUNTER6_LO 0x232C +#define mmSQ_PERFCOUNTER6_SELECT 0x2346 +#define mmSQ_PERFCOUNTER7_HI 0x232F +#define mmSQ_PERFCOUNTER7_LO 0x232E +#define mmSQ_PERFCOUNTER7_SELECT 0x2347 +#define mmSQ_PERFCOUNTER8_HI 0x2331 +#define mmSQ_PERFCOUNTER8_LO 0x2330 +#define mmSQ_PERFCOUNTER8_SELECT 0x2348 +#define mmSQ_PERFCOUNTER9_HI 0x2333 +#define mmSQ_PERFCOUNTER9_LO 0x2332 +#define mmSQ_PERFCOUNTER9_SELECT 0x2349 +#define mmSQ_PERFCOUNTER_CTRL 0x2306 +#define mmSQ_POWER_THROTTLE 0x2396 +#define mmSQ_POWER_THROTTLE2 0x2397 +#define mmSQ_RANDOM_WAVE_PRI 0x2303 +#define mmSQ_REG_CREDITS 0x2304 +#define mmSQ_SEC_CNT 0x23A1 +#define mmSQ_SMRD 0x237F +#define mmSQ_SOP1 0x237F +#define mmSQ_SOP2 0x237F +#define mmSQ_SOPC 0x237F +#define mmSQ_SOPK 0x237F +#define mmSQ_SOPP 0x237F +#define mmSQ_TEX_CLK_CTRL 0x2361 +#define mmSQ_THREAD_TRACE_BASE 0x2380 +#define mmSQ_THREAD_TRACE_CNTR 0x2390 +#define mmSQ_THREAD_TRACE_CTRL 0x238F +#define mmSQ_THREAD_TRACE_HIWATER 0x2392 +#define mmSQ_THREAD_TRACE_MASK 0x2382 +#define mmSQ_THREAD_TRACE_MODE 0x238E +#define mmSQ_THREAD_TRACE_PERF_MASK 0x2384 +#define mmSQ_THREAD_TRACE_SIZE 0x2381 +#define mmSQ_THREAD_TRACE_STATUS 0x238D +#define mmSQ_THREAD_TRACE_TOKEN_MASK 0x2383 +#define mmSQ_THREAD_TRACE_USERDATA_0 0x2388 +#define mmSQ_THREAD_TRACE_USERDATA_1 0x2389 +#define mmSQ_THREAD_TRACE_USERDATA_2 0x238A +#define mmSQ_THREAD_TRACE_USERDATA_3 0x238B +#define mmSQ_THREAD_TRACE_WORD_CMN 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_EVENT 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_INST 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x23B1 +#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x23B1 +#define mmSQ_THREAD_TRACE_WORD_ISSUE 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_MISC 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x23B1 +#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_TIME 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x23B1 +#define mmSQ_THREAD_TRACE_WORD_WAVE 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_WAVE_START 0x23B0 +#define mmSQ_THREAD_TRACE_WPTR 0x238C +#define mmSQ_TIME_HI 0x237C +#define mmSQ_TIME_LO 0x237D +#define mmSQ_VINTRP 0x237F +#define mmSQ_VOP1 0x237F +#define mmSQ_VOP2 0x237F +#define mmSQ_VOP3_0 0x237F +#define mmSQ_VOP3_0_SDST_ENC 0x237F +#define mmSQ_VOP3_1 0x237F +#define mmSQ_VOPC 0x237F +#define mmSX_DEBUG_1 0x2418 +#define mmSX_DEBUG_BUSY 0x2414 +#define mmSX_DEBUG_BUSY_2 0x2415 +#define mmSX_DEBUG_BUSY_3 0x2416 +#define mmSX_DEBUG_BUSY_4 0x2417 +#define mmSX_PERFCOUNTER0_HI 0x2421 +#define mmSX_PERFCOUNTER0_LO 0x2420 +#define mmSX_PERFCOUNTER0_SELECT 0x241C +#define mmSX_PERFCOUNTER1_HI 0x2423 +#define mmSX_PERFCOUNTER1_LO 0x2422 +#define mmSX_PERFCOUNTER1_SELECT 0x241D +#define mmSX_PERFCOUNTER2_HI 0x2425 +#define mmSX_PERFCOUNTER2_LO 0x2424 +#define mmSX_PERFCOUNTER2_SELECT 0x241E +#define mmSX_PERFCOUNTER3_HI 0x2427 +#define mmSX_PERFCOUNTER3_LO 0x2426 +#define mmSX_PERFCOUNTER3_SELECT 0x241F +#define mmTA_BC_BASE_ADDR 0xA020 +#define mmTA_CGTT_CTRL 0x2544 +#define mmTA_CNTL 0x2541 +#define mmTA_CNTL_AUX 0x2542 +#define mmTA_CS_BC_BASE_ADDR 0x2543 +#define mmTA_DEBUG_DATA 0x254D +#define mmTA_DEBUG_INDEX 0x254C +#define mmTA_PERFCOUNTER0_HI 0x2556 +#define mmTA_PERFCOUNTER0_LO 0x2555 +#define mmTA_PERFCOUNTER0_SELECT 0x2554 +#define mmTA_PERFCOUNTER1_HI 0x2562 +#define mmTA_PERFCOUNTER1_LO 0x2561 +#define mmTA_PERFCOUNTER1_SELECT 0x2560 +#define mmTA_SCRATCH 0x2564 +#define mmTA_STATUS 0x2548 +#define mmTCA_CGTT_SCLK_CTRL 0x2BC1 +#define mmTCA_CTRL 0x2BC0 +#define mmTCA_PERFCOUNTER0_HI 0x2BD2 +#define mmTCA_PERFCOUNTER0_LO 0x2BD1 +#define mmTCA_PERFCOUNTER0_SELECT 0x2BD0 +#define mmTCA_PERFCOUNTER1_HI 0x2BD5 +#define mmTCA_PERFCOUNTER1_LO 0x2BD4 +#define mmTCA_PERFCOUNTER1_SELECT 0x2BD3 +#define mmTCA_PERFCOUNTER2_HI 0x2BD8 +#define mmTCA_PERFCOUNTER2_LO 0x2BD7 +#define mmTCA_PERFCOUNTER2_SELECT 0x2BD6 +#define mmTCA_PERFCOUNTER3_HI 0x2BDB +#define mmTCA_PERFCOUNTER3_LO 0x2BDA +#define mmTCA_PERFCOUNTER3_SELECT 0x2BD9 +#define mmTCC_CGTT_SCLK_CTRL 0x2B81 +#define mmTCC_CTRL 0x2B80 +#define mmTCC_EDC_COUNTER 0x2B82 +#define mmTCC_PERFCOUNTER0_HI 0x2B92 +#define mmTCC_PERFCOUNTER0_LO 0x2B91 +#define mmTCC_PERFCOUNTER0_SELECT 0x2B90 +#define mmTCC_PERFCOUNTER1_HI 0x2B95 +#define mmTCC_PERFCOUNTER1_LO 0x2B94 +#define mmTCC_PERFCOUNTER1_SELECT 0x2B93 +#define mmTCC_PERFCOUNTER2_HI 0x2B98 +#define mmTCC_PERFCOUNTER2_LO 0x2B97 +#define mmTCC_PERFCOUNTER2_SELECT 0x2B96 +#define mmTCC_PERFCOUNTER3_HI 0x2B9B +#define mmTCC_PERFCOUNTER3_LO 0x2B9A +#define mmTCC_PERFCOUNTER3_SELECT 0x2B99 +#define mmTCI_CNTL_1 0x2B62 +#define mmTCI_CNTL_2 0x2B63 +#define mmTCI_STATUS 0x2B61 +#define mmTCP_ADDR_CONFIG 0x2B05 +#define mmTCP_BUFFER_ADDR_HASH_CNTL 0x2B16 +#define mmTCP_CHAN_STEER_HI 0x2B04 +#define mmTCP_CHAN_STEER_LO 0x2B03 +#define mmTCP_CNTL 0x2B02 +#define mmTCP_CREDIT 0x2B06 +#define mmTCP_EDC_COUNTER 0x2B17 +#define mmTCP_INVALIDATE 0x2B00 +#define mmTCP_PERFCOUNTER0_HI 0x2B0A +#define mmTCP_PERFCOUNTER0_LO 0x2B0B +#define mmTCP_PERFCOUNTER0_SELECT 0x2B09 +#define mmTCP_PERFCOUNTER1_HI 0x2B0D +#define mmTCP_PERFCOUNTER1_LO 0x2B0E +#define mmTCP_PERFCOUNTER1_SELECT 0x2B0C +#define mmTCP_PERFCOUNTER2_HI 0x2B10 +#define mmTCP_PERFCOUNTER2_LO 0x2B11 +#define mmTCP_PERFCOUNTER2_SELECT 0x2B0F +#define mmTCP_PERFCOUNTER3_HI 0x2B13 +#define mmTCP_PERFCOUNTER3_LO 0x2B14 +#define mmTCP_PERFCOUNTER3_SELECT 0x2B12 +#define mmTCP_STATUS 0x2B01 +#define mmTD_CGTT_CTRL 0x2527 +#define mmTD_CNTL 0x2525 +#define mmTD_DEBUG_DATA 0x2529 +#define mmTD_DEBUG_INDEX 0x2528 +#define mmTD_PERFCOUNTER0_HI 0x252E +#define mmTD_PERFCOUNTER0_LO 0x252D +#define mmTD_PERFCOUNTER0_SELECT 0x252C +#define mmTD_SCRATCH 0x2530 +#define mmTD_STATUS 0x2526 +#define mmUSER_SQC_BANK_DISABLE 0x2308 +#define mmVGT_CACHE_INVALIDATION 0x2231 +#define mmVGT_CNTL_STATUS 0x223C +#define mmVGT_DEBUG_CNTL 0x2238 +#define mmVGT_DEBUG_DATA 0x2239 +#define mmVGT_DMA_BASE 0xA1FA +#define mmVGT_DMA_BASE_HI 0xA1F9 +#define mmVGT_DMA_DATA_FIFO_DEPTH 0x222D +#define mmVGT_DMA_INDEX_TYPE 0xA29F +#define mmVGT_DMA_MAX_SIZE 0xA29E +#define mmVGT_DMA_NUM_INSTANCES 0xA2A2 +#define mmVGT_DMA_REQ_FIFO_DEPTH 0x222E +#define mmVGT_DMA_SIZE 0xA29D +#define mmVGT_DRAW_INIT_FIFO_DEPTH 0x222F +#define mmVGT_DRAW_INITIATOR 0xA1FC +#define mmVGT_ENHANCE 0xA294 +#define mmVGT_ESGS_RING_ITEMSIZE 0xA2AB +#define mmVGT_ESGS_RING_SIZE 0x2232 +#define mmVGT_ES_PER_GS 0xA296 +#define mmVGT_EVENT_ADDRESS_REG 0xA1FE +#define mmVGT_EVENT_INITIATOR 0xA2A4 +#define mmVGT_FIFO_DEPTHS 0x2234 +#define mmVGT_GROUP_DECR 0xA28B +#define mmVGT_GROUP_FIRST_DECR 0xA28A +#define mmVGT_GROUP_PRIM_TYPE 0xA289 +#define mmVGT_GROUP_VECT_0_CNTL 0xA28C +#define mmVGT_GROUP_VECT_0_FMT_CNTL 0xA28E +#define mmVGT_GROUP_VECT_1_CNTL 0xA28D +#define mmVGT_GROUP_VECT_1_FMT_CNTL 0xA28F +#define mmVGT_GS_INSTANCE_CNT 0xA2E4 +#define mmVGT_GS_MAX_VERT_OUT 0xA2CE +#define mmVGT_GS_MODE 0xA290 +#define mmVGT_GS_OUT_PRIM_TYPE 0xA29B +#define mmVGT_GS_PER_ES 0xA295 +#define mmVGT_GS_PER_VS 0xA297 +#define mmVGT_GS_VERTEX_REUSE 0x2235 +#define mmVGT_GS_VERT_ITEMSIZE 0xA2D7 +#define mmVGT_GS_VERT_ITEMSIZE_1 0xA2D8 +#define mmVGT_GS_VERT_ITEMSIZE_2 0xA2D9 +#define mmVGT_GS_VERT_ITEMSIZE_3 0xA2DA +#define mmVGT_GSVS_RING_ITEMSIZE 0xA2AC +#define mmVGT_GSVS_RING_OFFSET_1 0xA298 +#define mmVGT_GSVS_RING_OFFSET_2 0xA299 +#define mmVGT_GSVS_RING_OFFSET_3 0xA29A +#define mmVGT_GSVS_RING_SIZE 0x2233 +#define mmVGT_HOS_CNTL 0xA285 +#define mmVGT_HOS_MAX_TESS_LEVEL 0xA286 +#define mmVGT_HOS_MIN_TESS_LEVEL 0xA287 +#define mmVGT_HOS_REUSE_DEPTH 0xA288 +#define mmVGT_HS_OFFCHIP_PARAM 0x226C +#define mmVGT_IMMED_DATA 0xA1FD +#define mmVGT_INDEX_TYPE 0x2257 +#define mmVGT_INDX_OFFSET 0xA102 +#define mmVGT_INSTANCE_STEP_RATE_0 0xA2A8 +#define mmVGT_INSTANCE_STEP_RATE_1 0xA2A9 +#define mmVGT_LAST_COPY_STATE 0x2230 +#define mmVGT_LS_HS_CONFIG 0xA2D6 +#define mmVGT_MAX_VTX_INDX 0xA100 +#define mmVGT_MC_LAT_CNTL 0x2236 +#define mmVGT_MIN_VTX_INDX 0xA101 +#define mmVGT_MULTI_PRIM_IB_RESET_EN 0xA2A5 +#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0xA103 +#define mmVGT_NUM_INDICES 0x225C +#define mmVGT_NUM_INSTANCES 0x225D +#define mmVGT_OUT_DEALLOC_CNTL 0xA317 +#define mmVGT_OUTPUT_PATH_CNTL 0xA284 +#define mmVGT_PERFCOUNTER0_HI 0x224D +#define mmVGT_PERFCOUNTER0_LO 0x224C +#define mmVGT_PERFCOUNTER0_SELECT 0x2248 +#define mmVGT_PERFCOUNTER1_HI 0x224F +#define mmVGT_PERFCOUNTER1_LO 0x224E +#define mmVGT_PERFCOUNTER1_SELECT 0x2249 +#define mmVGT_PERFCOUNTER2_HI 0x2251 +#define mmVGT_PERFCOUNTER2_LO 0x2250 +#define mmVGT_PERFCOUNTER2_SELECT 0x224A +#define mmVGT_PERFCOUNTER3_HI 0x2253 +#define mmVGT_PERFCOUNTER3_LO 0x2252 +#define mmVGT_PERFCOUNTER3_SELECT 0x224B +#define mmVGT_PERFCOUNTER_SEID_MASK 0x2247 +#define mmVGT_PRIMITIVEID_EN 0xA2A1 +#define mmVGT_PRIMITIVEID_RESET 0xA2A3 +#define mmVGT_PRIMITIVE_TYPE 0x2256 +#define mmVGT_REUSE_OFF 0xA2AD +#define mmVGT_SHADER_STAGES_EN 0xA2D5 +#define mmVGT_STRMOUT_BUFFER_CONFIG 0xA2E6 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x2258 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x2259 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x225A +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0x225B +#define mmVGT_STRMOUT_BUFFER_OFFSET_0 0xA2B7 +#define mmVGT_STRMOUT_BUFFER_OFFSET_1 0xA2BB +#define mmVGT_STRMOUT_BUFFER_OFFSET_2 0xA2BF +#define mmVGT_STRMOUT_BUFFER_OFFSET_3 0xA2C3 +#define mmVGT_STRMOUT_BUFFER_SIZE_0 0xA2B4 +#define mmVGT_STRMOUT_BUFFER_SIZE_1 0xA2B8 +#define mmVGT_STRMOUT_BUFFER_SIZE_2 0xA2BC +#define mmVGT_STRMOUT_BUFFER_SIZE_3 0xA2C0 +#define mmVGT_STRMOUT_CONFIG 0xA2E5 +#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0xA2CB +#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0xA2CA +#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0xA2CC +#define mmVGT_STRMOUT_VTX_STRIDE_0 0xA2B5 +#define mmVGT_STRMOUT_VTX_STRIDE_1 0xA2B9 +#define mmVGT_STRMOUT_VTX_STRIDE_2 0xA2BD +#define mmVGT_STRMOUT_VTX_STRIDE_3 0xA2C1 +#define mmVGT_SYS_CONFIG 0x2263 +#define mmVGT_TF_MEMORY_BASE 0x226E +#define mmVGT_TF_PARAM 0xA2DB +#define mmVGT_TF_RING_SIZE 0x2262 +#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0xA316 +#define mmVGT_VTX_CNT_EN 0xA2AE +#define mmVGT_VTX_VECT_EJECT_REG 0x222C + +/* manually added from old sid.h */ +#define mmCB_PERFCOUNTER0_SELECT0 0x2688 +#define mmCB_PERFCOUNTER1_SELECT0 0x268A +#define mmCB_PERFCOUNTER1_SELECT1 0x268B +#define mmCB_PERFCOUNTER2_SELECT0 0x268C +#define mmCB_PERFCOUNTER2_SELECT1 0x268D +#define mmCB_PERFCOUNTER3_SELECT0 0x268E +#define mmCB_PERFCOUNTER3_SELECT1 0x268F +#define mmCP_COHER_CNTL2 0x217A +#define mmCP_DEBUG 0x307F +#define mmRLC_SERDES_MASTER_BUSY_0 0x3119 +#define mmRLC_SERDES_MASTER_BUSY_1 0x311A +#define mmRLC_RL_BASE 0x30C1 +#define mmRLC_RL_SIZE 0x30C2 +#define mmRLC_UCODE_ADDR 0x30CB +#define mmRLC_UCODE_DATA 0x30CC +#define mmRLC_GCPM_GENERAL_3 0x311E +#define mmRLC_SERDES_WR_MASTER_MASK_0 0x3115 +#define mmRLC_SERDES_WR_MASTER_MASK_1 0x3116 +#define mmRLC_TTOP_D 0x3105 +#define mmRLC_CLEAR_STATE_RESTORE_BASE 0x30C8 +#define mmRLC_PG_AO_CU_MASK 0x310B +#define mmSPI_STATIC_THREAD_MGMT_3 0x243A + +#endif |