diff options
Diffstat (limited to 'drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_offset.h')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_offset.h | 14663 |
1 files changed, 14663 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_offset.h new file mode 100644 index 000000000000..944e1548f638 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_offset.h @@ -0,0 +1,14663 @@ +/* + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _nbio_2_3_OFFSET_HEADER +#define _nbio_2_3_OFFSET_HEADER + + + +// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC +// base address: 0x0 +#define mmBIF_BX_PF_MM_INDEX 0x0000 +#define mmBIF_BX_PF_MM_INDEX_BASE_IDX 0 +#define mmBIF_BX_PF_MM_DATA 0x0001 +#define mmBIF_BX_PF_MM_DATA_BASE_IDX 0 +#define mmBIF_BX_PF_MM_INDEX_HI 0x0006 +#define mmBIF_BX_PF_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_bif_bx_SYSDEC +// base address: 0x0 +#define mmSYSHUB_INDEX_OVLP 0x0008 +#define mmSYSHUB_INDEX_OVLP_BASE_IDX 0 +#define mmSYSHUB_DATA_OVLP 0x0009 +#define mmSYSHUB_DATA_OVLP_BASE_IDX 0 +#define mmPCIE_INDEX 0x000c +#define mmPCIE_INDEX_BASE_IDX 0 +#define mmPCIE_DATA 0x000d +#define mmPCIE_DATA_BASE_IDX 0 +#define mmPCIE_INDEX2 0x000e +#define mmPCIE_INDEX2_BASE_IDX 0 +#define mmPCIE_DATA2 0x000f +#define mmPCIE_DATA2_BASE_IDX 0 +#define mmSBIOS_SCRATCH_0 0x0034 +#define mmSBIOS_SCRATCH_0_BASE_IDX 1 +#define mmSBIOS_SCRATCH_1 0x0035 +#define mmSBIOS_SCRATCH_1_BASE_IDX 1 +#define mmSBIOS_SCRATCH_2 0x0036 +#define mmSBIOS_SCRATCH_2_BASE_IDX 1 +#define mmSBIOS_SCRATCH_3 0x0037 +#define mmSBIOS_SCRATCH_3_BASE_IDX 1 +#define mmBIOS_SCRATCH_0 0x0038 +#define mmBIOS_SCRATCH_0_BASE_IDX 1 +#define mmBIOS_SCRATCH_1 0x0039 +#define mmBIOS_SCRATCH_1_BASE_IDX 1 +#define mmBIOS_SCRATCH_2 0x003a +#define mmBIOS_SCRATCH_2_BASE_IDX 1 +#define mmBIOS_SCRATCH_3 0x003b +#define mmBIOS_SCRATCH_3_BASE_IDX 1 +#define mmBIOS_SCRATCH_4 0x003c +#define mmBIOS_SCRATCH_4_BASE_IDX 1 +#define mmBIOS_SCRATCH_5 0x003d +#define mmBIOS_SCRATCH_5_BASE_IDX 1 +#define mmBIOS_SCRATCH_6 0x003e +#define mmBIOS_SCRATCH_6_BASE_IDX 1 +#define mmBIOS_SCRATCH_7 0x003f +#define mmBIOS_SCRATCH_7_BASE_IDX 1 +#define mmBIOS_SCRATCH_8 0x0040 +#define mmBIOS_SCRATCH_8_BASE_IDX 1 +#define mmBIOS_SCRATCH_9 0x0041 +#define mmBIOS_SCRATCH_9_BASE_IDX 1 +#define mmBIOS_SCRATCH_10 0x0042 +#define mmBIOS_SCRATCH_10_BASE_IDX 1 +#define mmBIOS_SCRATCH_11 0x0043 +#define mmBIOS_SCRATCH_11_BASE_IDX 1 +#define mmBIOS_SCRATCH_12 0x0044 +#define mmBIOS_SCRATCH_12_BASE_IDX 1 +#define mmBIOS_SCRATCH_13 0x0045 +#define mmBIOS_SCRATCH_13_BASE_IDX 1 +#define mmBIOS_SCRATCH_14 0x0046 +#define mmBIOS_SCRATCH_14_BASE_IDX 1 +#define mmBIOS_SCRATCH_15 0x0047 +#define mmBIOS_SCRATCH_15_BASE_IDX 1 +#define mmBIF_RLC_INTR_CNTL 0x004c +#define mmBIF_RLC_INTR_CNTL_BASE_IDX 1 +#define mmBIF_VCE_INTR_CNTL 0x004d +#define mmBIF_VCE_INTR_CNTL_BASE_IDX 1 +#define mmBIF_UVD_INTR_CNTL 0x004e +#define mmBIF_UVD_INTR_CNTL_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_ADDR0 0x006c +#define mmGFX_MMIOREG_CAM_ADDR0_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR0 0x006d +#define mmGFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_ADDR1 0x006e +#define mmGFX_MMIOREG_CAM_ADDR1_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR1 0x006f +#define mmGFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_ADDR2 0x0070 +#define mmGFX_MMIOREG_CAM_ADDR2_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR2 0x0071 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_ADDR3 0x0072 +#define mmGFX_MMIOREG_CAM_ADDR3_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR3 0x0073 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_ADDR4 0x0074 +#define mmGFX_MMIOREG_CAM_ADDR4_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR4 0x0075 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_ADDR5 0x0076 +#define mmGFX_MMIOREG_CAM_ADDR5_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR5 0x0077 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_ADDR6 0x0078 +#define mmGFX_MMIOREG_CAM_ADDR6_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR6 0x0079 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_ADDR7 0x007a +#define mmGFX_MMIOREG_CAM_ADDR7_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_REMAP_ADDR7 0x007b +#define mmGFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_CNTL 0x007c +#define mmGFX_MMIOREG_CAM_CNTL_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_ZERO_CPL 0x007d +#define mmGFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_ONE_CPL 0x007e +#define mmGFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 1 +#define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x007f +#define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 1 + + +// addressBlock: nbio_nbif0_syshub_mmreg_syshubdec +// base address: 0x0 +#define mmSYSHUB_INDEX 0x0008 +#define mmSYSHUB_INDEX_BASE_IDX 0 +#define mmSYSHUB_DATA 0x0009 +#define mmSYSHUB_DATA_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 +// base address: 0x0 +#define mmRCC_BIF_STRAP0 0x0000 +#define mmRCC_BIF_STRAP0_BASE_IDX 2 +#define mmRCC_BIF_STRAP1 0x0001 +#define mmRCC_BIF_STRAP1_BASE_IDX 2 +#define mmRCC_BIF_STRAP2 0x0002 +#define mmRCC_BIF_STRAP2_BASE_IDX 2 +#define mmRCC_BIF_STRAP3 0x0003 +#define mmRCC_BIF_STRAP3_BASE_IDX 2 +#define mmRCC_BIF_STRAP4 0x0004 +#define mmRCC_BIF_STRAP4_BASE_IDX 2 +#define mmRCC_BIF_STRAP5 0x0005 +#define mmRCC_BIF_STRAP5_BASE_IDX 2 +#define mmRCC_BIF_STRAP6 0x0006 +#define mmRCC_BIF_STRAP6_BASE_IDX 2 +#define mmRCC_DEV0_PORT_STRAP0 0x0007 +#define mmRCC_DEV0_PORT_STRAP0_BASE_IDX 2 +#define mmRCC_DEV0_PORT_STRAP1 0x0008 +#define mmRCC_DEV0_PORT_STRAP1_BASE_IDX 2 +#define mmRCC_DEV0_PORT_STRAP2 0x0009 +#define mmRCC_DEV0_PORT_STRAP2_BASE_IDX 2 +#define mmRCC_DEV0_PORT_STRAP3 0x000a +#define mmRCC_DEV0_PORT_STRAP3_BASE_IDX 2 +#define mmRCC_DEV0_PORT_STRAP4 0x000b +#define mmRCC_DEV0_PORT_STRAP4_BASE_IDX 2 +#define mmRCC_DEV0_PORT_STRAP5 0x000c +#define mmRCC_DEV0_PORT_STRAP5_BASE_IDX 2 +#define mmRCC_DEV0_PORT_STRAP6 0x000d +#define mmRCC_DEV0_PORT_STRAP6_BASE_IDX 2 +#define mmRCC_DEV0_PORT_STRAP7 0x000e +#define mmRCC_DEV0_PORT_STRAP7_BASE_IDX 2 +#define mmRCC_DEV0_PORT_STRAP8 0x000f +#define mmRCC_DEV0_PORT_STRAP8_BASE_IDX 2 +#define mmRCC_DEV0_PORT_STRAP9 0x0010 +#define mmRCC_DEV0_PORT_STRAP9_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_STRAP0 0x0011 +#define mmRCC_DEV0_EPF0_STRAP0_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_STRAP1 0x0012 +#define mmRCC_DEV0_EPF0_STRAP1_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_STRAP13 0x0013 +#define mmRCC_DEV0_EPF0_STRAP13_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_STRAP2 0x0014 +#define mmRCC_DEV0_EPF0_STRAP2_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_STRAP3 0x0015 +#define mmRCC_DEV0_EPF0_STRAP3_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_STRAP4 0x0016 +#define mmRCC_DEV0_EPF0_STRAP4_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_STRAP5 0x0017 +#define mmRCC_DEV0_EPF0_STRAP5_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_STRAP8 0x0018 +#define mmRCC_DEV0_EPF0_STRAP8_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_STRAP9 0x0019 +#define mmRCC_DEV0_EPF0_STRAP9_BASE_IDX 2 +#define mmRCC_DEV0_EPF1_STRAP0 0x001a +#define mmRCC_DEV0_EPF1_STRAP0_BASE_IDX 2 +#define mmRCC_DEV0_EPF1_STRAP10 0x001b +#define mmRCC_DEV0_EPF1_STRAP10_BASE_IDX 2 +#define mmRCC_DEV0_EPF1_STRAP11 0x001c +#define mmRCC_DEV0_EPF1_STRAP11_BASE_IDX 2 +#define mmRCC_DEV0_EPF1_STRAP12 0x001d +#define mmRCC_DEV0_EPF1_STRAP12_BASE_IDX 2 +#define mmRCC_DEV0_EPF1_STRAP13 0x001e +#define mmRCC_DEV0_EPF1_STRAP13_BASE_IDX 2 +#define mmRCC_DEV0_EPF1_STRAP2 0x001f +#define mmRCC_DEV0_EPF1_STRAP2_BASE_IDX 2 +#define mmRCC_DEV0_EPF1_STRAP3 0x0020 +#define mmRCC_DEV0_EPF1_STRAP3_BASE_IDX 2 +#define mmRCC_DEV0_EPF1_STRAP4 0x0021 +#define mmRCC_DEV0_EPF1_STRAP4_BASE_IDX 2 +#define mmRCC_DEV0_EPF1_STRAP5 0x0022 +#define mmRCC_DEV0_EPF1_STRAP5_BASE_IDX 2 +#define mmRCC_DEV0_EPF1_STRAP6 0x0023 +#define mmRCC_DEV0_EPF1_STRAP6_BASE_IDX 2 +#define mmRCC_DEV0_EPF1_STRAP7 0x0024 +#define mmRCC_DEV0_EPF1_STRAP7_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 +// base address: 0x0 +#define mmEP_PCIE_SCRATCH 0x0025 +#define mmEP_PCIE_SCRATCH_BASE_IDX 2 +#define mmEP_PCIE_CNTL 0x0027 +#define mmEP_PCIE_CNTL_BASE_IDX 2 +#define mmEP_PCIE_INT_CNTL 0x0028 +#define mmEP_PCIE_INT_CNTL_BASE_IDX 2 +#define mmEP_PCIE_INT_STATUS 0x0029 +#define mmEP_PCIE_INT_STATUS_BASE_IDX 2 +#define mmEP_PCIE_RX_CNTL2 0x002a +#define mmEP_PCIE_RX_CNTL2_BASE_IDX 2 +#define mmEP_PCIE_BUS_CNTL 0x002b +#define mmEP_PCIE_BUS_CNTL_BASE_IDX 2 +#define mmEP_PCIE_CFG_CNTL 0x002c +#define mmEP_PCIE_CFG_CNTL_BASE_IDX 2 +#define mmEP_PCIE_TX_LTR_CNTL 0x002e +#define mmEP_PCIE_TX_LTR_CNTL_BASE_IDX 2 +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x002f +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x002f +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x002f +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x002f +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x0030 +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x0030 +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x0030 +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x0030 +#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 +#define mmEP_PCIE_STRAP_MISC 0x0031 +#define mmEP_PCIE_STRAP_MISC_BASE_IDX 2 +#define mmEP_PCIE_STRAP_MISC2 0x0032 +#define mmEP_PCIE_STRAP_MISC2_BASE_IDX 2 +#define mmEP_PCIE_F0_DPA_CAP 0x0034 +#define mmEP_PCIE_F0_DPA_CAP_BASE_IDX 2 +#define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR 0x0035 +#define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 2 +#define mmEP_PCIE_F0_DPA_CNTL 0x0035 +#define mmEP_PCIE_F0_DPA_CNTL_BASE_IDX 2 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x0035 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x0036 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x0036 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x0036 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x0036 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x0037 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x0037 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x0037 +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 +#define mmEP_PCIE_PME_CONTROL 0x0037 +#define mmEP_PCIE_PME_CONTROL_BASE_IDX 2 +#define mmEP_PCIEP_RESERVED 0x0038 +#define mmEP_PCIEP_RESERVED_BASE_IDX 2 +#define mmEP_PCIE_TX_CNTL 0x003a +#define mmEP_PCIE_TX_CNTL_BASE_IDX 2 +#define mmEP_PCIE_TX_REQUESTER_ID 0x003b +#define mmEP_PCIE_TX_REQUESTER_ID_BASE_IDX 2 +#define mmEP_PCIE_ERR_CNTL 0x003c +#define mmEP_PCIE_ERR_CNTL_BASE_IDX 2 +#define mmEP_PCIE_RX_CNTL 0x003d +#define mmEP_PCIE_RX_CNTL_BASE_IDX 2 +#define mmEP_PCIE_LC_SPEED_CNTL 0x003e +#define mmEP_PCIE_LC_SPEED_CNTL_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 +// base address: 0x0 +#define mmDN_PCIE_RESERVED 0x0040 +#define mmDN_PCIE_RESERVED_BASE_IDX 2 +#define mmDN_PCIE_SCRATCH 0x0041 +#define mmDN_PCIE_SCRATCH_BASE_IDX 2 +#define mmDN_PCIE_CNTL 0x0043 +#define mmDN_PCIE_CNTL_BASE_IDX 2 +#define mmDN_PCIE_CONFIG_CNTL 0x0044 +#define mmDN_PCIE_CONFIG_CNTL_BASE_IDX 2 +#define mmDN_PCIE_RX_CNTL2 0x0045 +#define mmDN_PCIE_RX_CNTL2_BASE_IDX 2 +#define mmDN_PCIE_BUS_CNTL 0x0046 +#define mmDN_PCIE_BUS_CNTL_BASE_IDX 2 +#define mmDN_PCIE_CFG_CNTL 0x0047 +#define mmDN_PCIE_CFG_CNTL_BASE_IDX 2 +#define mmDN_PCIE_STRAP_F0 0x0048 +#define mmDN_PCIE_STRAP_F0_BASE_IDX 2 +#define mmDN_PCIE_STRAP_MISC 0x0049 +#define mmDN_PCIE_STRAP_MISC_BASE_IDX 2 +#define mmDN_PCIE_STRAP_MISC2 0x004a +#define mmDN_PCIE_STRAP_MISC2_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 +// base address: 0x0 +#define mmPCIE_ERR_CNTL 0x004f +#define mmPCIE_ERR_CNTL_BASE_IDX 2 +#define mmPCIE_RX_CNTL 0x0050 +#define mmPCIE_RX_CNTL_BASE_IDX 2 +#define mmPCIE_LC_SPEED_CNTL 0x0051 +#define mmPCIE_LC_SPEED_CNTL_BASE_IDX 2 +#define mmPCIE_LC_CNTL2 0x0052 +#define mmPCIE_LC_CNTL2_BASE_IDX 2 +#define mmPCIEP_STRAP_MISC 0x0053 +#define mmPCIEP_STRAP_MISC_BASE_IDX 2 +#define mmLTR_MSG_INFO_FROM_EP 0x0054 +#define mmLTR_MSG_INFO_FROM_EP_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975] +// base address: 0x3480 +#define mmRCC_DEV0_EPF0_RCC_ERR_LOG 0x0085 +#define mmRCC_DEV0_EPF0_RCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_RCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_DEV0_EPF0_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1 +// base address: 0x0 +#define mmRCC_ERR_INT_CNTL 0x0086 +#define mmRCC_ERR_INT_CNTL_BASE_IDX 2 +#define mmRCC_BACO_CNTL_MISC 0x0087 +#define mmRCC_BACO_CNTL_MISC_BASE_IDX 2 +#define mmRCC_RESET_EN 0x0088 +#define mmRCC_RESET_EN_BASE_IDX 2 +#define mmRCC_VDM_SUPPORT 0x0089 +#define mmRCC_VDM_SUPPORT_BASE_IDX 2 +#define mmRCC_MARGIN_PARAM_CNTL0 0x008a +#define mmRCC_MARGIN_PARAM_CNTL0_BASE_IDX 2 +#define mmRCC_MARGIN_PARAM_CNTL1 0x008b +#define mmRCC_MARGIN_PARAM_CNTL1_BASE_IDX 2 +#define mmRCC_GPUIOV_REGION 0x008c +#define mmRCC_GPUIOV_REGION_BASE_IDX 2 +#define mmRCC_PEER_REG_RANGE0 0x00be +#define mmRCC_PEER_REG_RANGE0_BASE_IDX 2 +#define mmRCC_PEER_REG_RANGE1 0x00bf +#define mmRCC_PEER_REG_RANGE1_BASE_IDX 2 +#define mmRCC_BUS_CNTL 0x00c1 +#define mmRCC_BUS_CNTL_BASE_IDX 2 +#define mmRCC_CONFIG_CNTL 0x00c2 +#define mmRCC_CONFIG_CNTL_BASE_IDX 2 +#define mmRCC_CONFIG_F0_BASE 0x00c6 +#define mmRCC_CONFIG_F0_BASE_BASE_IDX 2 +#define mmRCC_CONFIG_APER_SIZE 0x00c7 +#define mmRCC_CONFIG_APER_SIZE_BASE_IDX 2 +#define mmRCC_CONFIG_REG_APER_SIZE 0x00c8 +#define mmRCC_CONFIG_REG_APER_SIZE_BASE_IDX 2 +#define mmRCC_XDMA_LO 0x00c9 +#define mmRCC_XDMA_LO_BASE_IDX 2 +#define mmRCC_XDMA_HI 0x00ca +#define mmRCC_XDMA_HI_BASE_IDX 2 +#define mmRCC_FEATURES_CONTROL_MISC 0x00cb +#define mmRCC_FEATURES_CONTROL_MISC_BASE_IDX 2 +#define mmRCC_BUSNUM_CNTL1 0x00cc +#define mmRCC_BUSNUM_CNTL1_BASE_IDX 2 +#define mmRCC_BUSNUM_LIST0 0x00cd +#define mmRCC_BUSNUM_LIST0_BASE_IDX 2 +#define mmRCC_BUSNUM_LIST1 0x00ce +#define mmRCC_BUSNUM_LIST1_BASE_IDX 2 +#define mmRCC_BUSNUM_CNTL2 0x00cf +#define mmRCC_BUSNUM_CNTL2_BASE_IDX 2 +#define mmRCC_CAPTURE_HOST_BUSNUM 0x00d0 +#define mmRCC_CAPTURE_HOST_BUSNUM_BASE_IDX 2 +#define mmRCC_HOST_BUSNUM 0x00d1 +#define mmRCC_HOST_BUSNUM_BASE_IDX 2 +#define mmRCC_PEER0_FB_OFFSET_HI 0x00d2 +#define mmRCC_PEER0_FB_OFFSET_HI_BASE_IDX 2 +#define mmRCC_PEER0_FB_OFFSET_LO 0x00d3 +#define mmRCC_PEER0_FB_OFFSET_LO_BASE_IDX 2 +#define mmRCC_PEER1_FB_OFFSET_HI 0x00d4 +#define mmRCC_PEER1_FB_OFFSET_HI_BASE_IDX 2 +#define mmRCC_PEER1_FB_OFFSET_LO 0x00d5 +#define mmRCC_PEER1_FB_OFFSET_LO_BASE_IDX 2 +#define mmRCC_PEER2_FB_OFFSET_HI 0x00d6 +#define mmRCC_PEER2_FB_OFFSET_HI_BASE_IDX 2 +#define mmRCC_PEER2_FB_OFFSET_LO 0x00d7 +#define mmRCC_PEER2_FB_OFFSET_LO_BASE_IDX 2 +#define mmRCC_PEER3_FB_OFFSET_HI 0x00d8 +#define mmRCC_PEER3_FB_OFFSET_HI_BASE_IDX 2 +#define mmRCC_PEER3_FB_OFFSET_LO 0x00d9 +#define mmRCC_PEER3_FB_OFFSET_LO_BASE_IDX 2 +#define mmRCC_DEVFUNCNUM_LIST0 0x00da +#define mmRCC_DEVFUNCNUM_LIST0_BASE_IDX 2 +#define mmRCC_DEVFUNCNUM_LIST1 0x00db +#define mmRCC_DEVFUNCNUM_LIST1_BASE_IDX 2 +#define mmRCC_DEV0_LINK_CNTL 0x00dd +#define mmRCC_DEV0_LINK_CNTL_BASE_IDX 2 +#define mmRCC_CMN_LINK_CNTL 0x00de +#define mmRCC_CMN_LINK_CNTL_BASE_IDX 2 +#define mmRCC_EP_REQUESTERID_RESTORE 0x00df +#define mmRCC_EP_REQUESTERID_RESTORE_BASE_IDX 2 +#define mmRCC_LTR_LSWITCH_CNTL 0x00e0 +#define mmRCC_LTR_LSWITCH_CNTL_BASE_IDX 2 +#define mmRCC_MH_ARB_CNTL 0x00e1 +#define mmRCC_MH_ARB_CNTL_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_BIFDEC1 +// base address: 0x0 +#define mmCC_BIF_BX_STRAP0 0x00e2 +#define mmCC_BIF_BX_STRAP0_BASE_IDX 2 +#define mmCC_BIF_BX_PINSTRAP0 0x00e4 +#define mmCC_BIF_BX_PINSTRAP0_BASE_IDX 2 +#define mmBIF_MM_INDACCESS_CNTL 0x00e6 +#define mmBIF_MM_INDACCESS_CNTL_BASE_IDX 2 +#define mmBUS_CNTL 0x00e7 +#define mmBUS_CNTL_BASE_IDX 2 +#define mmBIF_SCRATCH0 0x00e8 +#define mmBIF_SCRATCH0_BASE_IDX 2 +#define mmBIF_SCRATCH1 0x00e9 +#define mmBIF_SCRATCH1_BASE_IDX 2 +#define mmBX_RESET_EN 0x00ed +#define mmBX_RESET_EN_BASE_IDX 2 +#define mmMM_CFGREGS_CNTL 0x00ee +#define mmMM_CFGREGS_CNTL_BASE_IDX 2 +#define mmBX_RESET_CNTL 0x00f0 +#define mmBX_RESET_CNTL_BASE_IDX 2 +#define mmINTERRUPT_CNTL 0x00f1 +#define mmINTERRUPT_CNTL_BASE_IDX 2 +#define mmINTERRUPT_CNTL2 0x00f2 +#define mmINTERRUPT_CNTL2_BASE_IDX 2 +#define mmCLKREQB_PAD_CNTL 0x00f8 +#define mmCLKREQB_PAD_CNTL_BASE_IDX 2 +#define mmBIF_FEATURES_CONTROL_MISC 0x00fb +#define mmBIF_FEATURES_CONTROL_MISC_BASE_IDX 2 +#define mmBIF_DOORBELL_CNTL 0x00fc +#define mmBIF_DOORBELL_CNTL_BASE_IDX 2 +#define mmBIF_DOORBELL_INT_CNTL 0x00fd +#define mmBIF_DOORBELL_INT_CNTL_BASE_IDX 2 +#define mmBIF_FB_EN 0x00ff +#define mmBIF_FB_EN_BASE_IDX 2 +#define mmBIF_INTR_CNTL 0x0100 +#define mmBIF_INTR_CNTL_BASE_IDX 2 +#define mmBIF_MST_TRANS_PENDING_VF 0x0109 +#define mmBIF_MST_TRANS_PENDING_VF_BASE_IDX 2 +#define mmBIF_SLV_TRANS_PENDING_VF 0x010a +#define mmBIF_SLV_TRANS_PENDING_VF_BASE_IDX 2 +#define mmBACO_CNTL 0x010b +#define mmBACO_CNTL_BASE_IDX 2 +#define mmBIF_BACO_EXIT_TIME0 0x010c +#define mmBIF_BACO_EXIT_TIME0_BASE_IDX 2 +#define mmBIF_BACO_EXIT_TIMER1 0x010d +#define mmBIF_BACO_EXIT_TIMER1_BASE_IDX 2 +#define mmBIF_BACO_EXIT_TIMER2 0x010e +#define mmBIF_BACO_EXIT_TIMER2_BASE_IDX 2 +#define mmBIF_BACO_EXIT_TIMER3 0x010f +#define mmBIF_BACO_EXIT_TIMER3_BASE_IDX 2 +#define mmBIF_BACO_EXIT_TIMER4 0x0110 +#define mmBIF_BACO_EXIT_TIMER4_BASE_IDX 2 +#define mmMEM_TYPE_CNTL 0x0111 +#define mmMEM_TYPE_CNTL_BASE_IDX 2 +#define mmNBIF_GFX_ADDR_LUT_CNTL 0x0113 +#define mmNBIF_GFX_ADDR_LUT_CNTL_BASE_IDX 2 +#define mmNBIF_GFX_ADDR_LUT_0 0x0114 +#define mmNBIF_GFX_ADDR_LUT_0_BASE_IDX 2 +#define mmNBIF_GFX_ADDR_LUT_1 0x0115 +#define mmNBIF_GFX_ADDR_LUT_1_BASE_IDX 2 +#define mmNBIF_GFX_ADDR_LUT_2 0x0116 +#define mmNBIF_GFX_ADDR_LUT_2_BASE_IDX 2 +#define mmNBIF_GFX_ADDR_LUT_3 0x0117 +#define mmNBIF_GFX_ADDR_LUT_3_BASE_IDX 2 +#define mmNBIF_GFX_ADDR_LUT_4 0x0118 +#define mmNBIF_GFX_ADDR_LUT_4_BASE_IDX 2 +#define mmNBIF_GFX_ADDR_LUT_5 0x0119 +#define mmNBIF_GFX_ADDR_LUT_5_BASE_IDX 2 +#define mmNBIF_GFX_ADDR_LUT_6 0x011a +#define mmNBIF_GFX_ADDR_LUT_6_BASE_IDX 2 +#define mmNBIF_GFX_ADDR_LUT_7 0x011b +#define mmNBIF_GFX_ADDR_LUT_7_BASE_IDX 2 +#define mmNBIF_GFX_ADDR_LUT_8 0x011c +#define mmNBIF_GFX_ADDR_LUT_8_BASE_IDX 2 +#define mmNBIF_GFX_ADDR_LUT_9 0x011d +#define mmNBIF_GFX_ADDR_LUT_9_BASE_IDX 2 +#define mmNBIF_GFX_ADDR_LUT_10 0x011e +#define mmNBIF_GFX_ADDR_LUT_10_BASE_IDX 2 +#define mmNBIF_GFX_ADDR_LUT_11 0x011f +#define mmNBIF_GFX_ADDR_LUT_11_BASE_IDX 2 +#define mmNBIF_GFX_ADDR_LUT_12 0x0120 +#define mmNBIF_GFX_ADDR_LUT_12_BASE_IDX 2 +#define mmNBIF_GFX_ADDR_LUT_13 0x0121 +#define mmNBIF_GFX_ADDR_LUT_13_BASE_IDX 2 +#define mmNBIF_GFX_ADDR_LUT_14 0x0122 +#define mmNBIF_GFX_ADDR_LUT_14_BASE_IDX 2 +#define mmNBIF_GFX_ADDR_LUT_15 0x0123 +#define mmNBIF_GFX_ADDR_LUT_15_BASE_IDX 2 +#define mmREMAP_HDP_MEM_FLUSH_CNTL 0x012d +#define mmREMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 2 +#define mmREMAP_HDP_REG_FLUSH_CNTL 0x012e +#define mmREMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_RB_CNTL 0x012f +#define mmBIF_RB_CNTL_BASE_IDX 2 +#define mmBIF_RB_BASE 0x0130 +#define mmBIF_RB_BASE_BASE_IDX 2 +#define mmBIF_RB_RPTR 0x0131 +#define mmBIF_RB_RPTR_BASE_IDX 2 +#define mmBIF_RB_WPTR 0x0132 +#define mmBIF_RB_WPTR_BASE_IDX 2 +#define mmBIF_RB_WPTR_ADDR_HI 0x0133 +#define mmBIF_RB_WPTR_ADDR_HI_BASE_IDX 2 +#define mmBIF_RB_WPTR_ADDR_LO 0x0134 +#define mmBIF_RB_WPTR_ADDR_LO_BASE_IDX 2 +#define mmMAILBOX_INDEX 0x0135 +#define mmMAILBOX_INDEX_BASE_IDX 2 +#define mmBIF_MP1_INTR_CTRL 0x0142 +#define mmBIF_MP1_INTR_CTRL_BASE_IDX 2 +#define mmBIF_UVD_GPUIOV_CFG_SIZE 0x0143 +#define mmBIF_UVD_GPUIOV_CFG_SIZE_BASE_IDX 2 +#define mmBIF_VCE_GPUIOV_CFG_SIZE 0x0144 +#define mmBIF_VCE_GPUIOV_CFG_SIZE_BASE_IDX 2 +#define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE 0x0145 +#define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_BASE_IDX 2 +#define mmBIF_PERSTB_PAD_CNTL 0x0148 +#define mmBIF_PERSTB_PAD_CNTL_BASE_IDX 2 +#define mmBIF_PX_EN_PAD_CNTL 0x0149 +#define mmBIF_PX_EN_PAD_CNTL_BASE_IDX 2 +#define mmBIF_REFPADKIN_PAD_CNTL 0x014a +#define mmBIF_REFPADKIN_PAD_CNTL_BASE_IDX 2 +#define mmBIF_CLKREQB_PAD_CNTL 0x014b +#define mmBIF_CLKREQB_PAD_CNTL_BASE_IDX 2 +#define mmBIF_PWRBRK_PAD_CNTL 0x014c +#define mmBIF_PWRBRK_PAD_CNTL_BASE_IDX 2 +#define mmBIF_WAKEB_PAD_CNTL 0x014d +#define mmBIF_WAKEB_PAD_CNTL_BASE_IDX 2 +#define mmBIF_VAUX_PRESENT_PAD_CNTL 0x014e +#define mmBIF_VAUX_PRESENT_PAD_CNTL_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BX_PF_BIF_BME_STATUS 0x00eb +#define mmBIF_BX_PF_BIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_BX_PF_BIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_BX_PF_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmBIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmBIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_PF_GPU_HDP_FLUSH_REQ 0x0106 +#define mmBIF_BX_PF_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmBIF_BX_PF_GPU_HDP_FLUSH_DONE 0x0107 +#define mmBIF_BX_PF_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_BX_PF_BIF_TRANS_PENDING 0x0108 +#define mmBIF_BX_PF_BIF_TRANS_PENDING_BASE_IDX 2 +#define mmBIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define mmBIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmBIF_BX_PF_MAILBOX_CONTROL 0x013e +#define mmBIF_BX_PF_MAILBOX_CONTROL_BASE_IDX 2 +#define mmBIF_BX_PF_MAILBOX_INT_CNTL 0x013f +#define mmBIF_BX_PF_MAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_BX_PF_BIF_VMHV_MAILBOX 0x0140 +#define mmBIF_BX_PF_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_gdc_GDCDEC +// base address: 0x0 +#define mmA2S_CNTL_CL0 0x0190 +#define mmA2S_CNTL_CL0_BASE_IDX 2 +#define mmA2S_CNTL_CL1 0x0191 +#define mmA2S_CNTL_CL1_BASE_IDX 2 +#define mmA2S_CNTL3_CL0 0x01a0 +#define mmA2S_CNTL3_CL0_BASE_IDX 2 +#define mmA2S_CNTL3_CL1 0x01a1 +#define mmA2S_CNTL3_CL1_BASE_IDX 2 +#define mmA2S_CNTL_SW0 0x01b0 +#define mmA2S_CNTL_SW0_BASE_IDX 2 +#define mmA2S_CNTL_SW1 0x01b1 +#define mmA2S_CNTL_SW1_BASE_IDX 2 +#define mmA2S_CNTL_SW2 0x01b2 +#define mmA2S_CNTL_SW2_BASE_IDX 2 +#define mmA2S_CPLBUF_ALLOC_CNTL 0x01bc +#define mmA2S_CPLBUF_ALLOC_CNTL_BASE_IDX 2 +#define mmA2S_TAG_ALLOC_0 0x01bd +#define mmA2S_TAG_ALLOC_0_BASE_IDX 2 +#define mmA2S_TAG_ALLOC_1 0x01be +#define mmA2S_TAG_ALLOC_1_BASE_IDX 2 +#define mmA2S_MISC_CNTL 0x01c1 +#define mmA2S_MISC_CNTL_BASE_IDX 2 +#define mmNGDC_SDP_PORT_CTRL 0x01c2 +#define mmNGDC_SDP_PORT_CTRL_BASE_IDX 2 +#define mmSHUB_REGS_IF_CTL 0x01c3 +#define mmSHUB_REGS_IF_CTL_BASE_IDX 2 +#define mmNGDC_MGCG_CTRL 0x01ca +#define mmNGDC_MGCG_CTRL_BASE_IDX 2 +#define mmNGDC_RESERVED_0 0x01cb +#define mmNGDC_RESERVED_0_BASE_IDX 2 +#define mmNGDC_RESERVED_1 0x01cc +#define mmNGDC_RESERVED_1_BASE_IDX 2 +#define mmNGDC_SDP_PORT_CTRL_SOCCLK 0x01cd +#define mmNGDC_SDP_PORT_CTRL_SOCCLK_BASE_IDX 2 +#define mmBIF_SDMA0_DOORBELL_RANGE 0x01d0 +#define mmBIF_SDMA0_DOORBELL_RANGE_BASE_IDX 2 +#define mmBIF_SDMA1_DOORBELL_RANGE 0x01d1 +#define mmBIF_SDMA1_DOORBELL_RANGE_BASE_IDX 2 +#define mmBIF_IH_DOORBELL_RANGE 0x01d2 +#define mmBIF_IH_DOORBELL_RANGE_BASE_IDX 2 +#define mmBIF_MMSCH0_DOORBELL_RANGE 0x01d3 +#define mmBIF_MMSCH0_DOORBELL_RANGE_BASE_IDX 2 +#define mmBIF_ACV_DOORBELL_RANGE 0x01d4 +#define mmBIF_ACV_DOORBELL_RANGE_BASE_IDX 2 +#define mmBIF_DOORBELL_FENCE_CNTL 0x01de +#define mmBIF_DOORBELL_FENCE_CNTL_BASE_IDX 2 +#define mmS2A_MISC_CNTL 0x01df +#define mmS2A_MISC_CNTL_BASE_IDX 2 +#define mmNGDC_PG_MISC_CTRL 0x01f0 +#define mmNGDC_PG_MISC_CTRL_BASE_IDX 2 +#define mmNGDC_PGMST_CTRL 0x01f1 +#define mmNGDC_PGMST_CTRL_BASE_IDX 2 +#define mmNGDC_PGSLV_CTRL 0x01f2 +#define mmNGDC_PGSLV_CTRL_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL 0x0403 +#define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL 0x0407 +#define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA 0x040a +#define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL 0x040b +#define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO 0x040c +#define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI 0x040d +#define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA 0x040e +#define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL 0x040f +#define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_GFXMSIX_PBA 0x0800 +#define mmRCC_DEV0_EPF0_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_pcie0_pswuscfg0_cfgdecp +// base address: 0x0 +#define cfgPSWUSCFG0_0_VENDOR_ID 0x0000 +#define cfgPSWUSCFG0_0_DEVICE_ID 0x0002 +#define cfgPSWUSCFG0_0_COMMAND 0x0004 +#define cfgPSWUSCFG0_0_STATUS 0x0006 +#define cfgPSWUSCFG0_0_REVISION_ID 0x0008 +#define cfgPSWUSCFG0_0_PROG_INTERFACE 0x0009 +#define cfgPSWUSCFG0_0_SUB_CLASS 0x000a +#define cfgPSWUSCFG0_0_BASE_CLASS 0x000b +#define cfgPSWUSCFG0_0_CACHE_LINE 0x000c +#define cfgPSWUSCFG0_0_LATENCY 0x000d +#define cfgPSWUSCFG0_0_HEADER 0x000e +#define cfgPSWUSCFG0_0_BIST 0x000f +#define cfgPSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY 0x0018 +#define cfgPSWUSCFG0_0_IO_BASE_LIMIT 0x001c +#define cfgPSWUSCFG0_0_SECONDARY_STATUS 0x001e +#define cfgPSWUSCFG0_0_MEM_BASE_LIMIT 0x0020 +#define cfgPSWUSCFG0_0_PREF_BASE_LIMIT 0x0024 +#define cfgPSWUSCFG0_0_PREF_BASE_UPPER 0x0028 +#define cfgPSWUSCFG0_0_PREF_LIMIT_UPPER 0x002c +#define cfgPSWUSCFG0_0_IO_BASE_LIMIT_HI 0x0030 +#define cfgPSWUSCFG0_0_CAP_PTR 0x0034 +#define cfgPSWUSCFG0_0_ROM_BASE_ADDR 0x0038 +#define cfgPSWUSCFG0_0_INTERRUPT_LINE 0x003c +#define cfgPSWUSCFG0_0_INTERRUPT_PIN 0x003d +#define cfgPSWUSCFG0_0_IRQ_BRIDGE_CNTL 0x003e +#define cfgPSWUSCFG0_0_EXT_BRIDGE_CNTL 0x0040 +#define cfgPSWUSCFG0_0_VENDOR_CAP_LIST 0x0048 +#define cfgPSWUSCFG0_0_ADAPTER_ID_W 0x004c +#define cfgPSWUSCFG0_0_PMI_CAP_LIST 0x0050 +#define cfgPSWUSCFG0_0_PMI_CAP 0x0052 +#define cfgPSWUSCFG0_0_PMI_STATUS_CNTL 0x0054 +#define cfgPSWUSCFG0_0_PCIE_CAP_LIST 0x0058 +#define cfgPSWUSCFG0_0_PCIE_CAP 0x005a +#define cfgPSWUSCFG0_0_DEVICE_CAP 0x005c +#define cfgPSWUSCFG0_0_DEVICE_CNTL 0x0060 +#define cfgPSWUSCFG0_0_DEVICE_STATUS 0x0062 +#define cfgPSWUSCFG0_0_LINK_CAP 0x0064 +#define cfgPSWUSCFG0_0_LINK_CNTL 0x0068 +#define cfgPSWUSCFG0_0_LINK_STATUS 0x006a +#define cfgPSWUSCFG0_0_DEVICE_CAP2 0x007c +#define cfgPSWUSCFG0_0_DEVICE_CNTL2 0x0080 +#define cfgPSWUSCFG0_0_DEVICE_STATUS2 0x0082 +#define cfgPSWUSCFG0_0_LINK_CAP2 0x0084 +#define cfgPSWUSCFG0_0_LINK_CNTL2 0x0088 +#define cfgPSWUSCFG0_0_LINK_STATUS2 0x008a +#define cfgPSWUSCFG0_0_MSI_CAP_LIST 0x00a0 +#define cfgPSWUSCFG0_0_MSI_MSG_CNTL 0x00a2 +#define cfgPSWUSCFG0_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgPSWUSCFG0_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgPSWUSCFG0_0_MSI_MSG_DATA 0x00a8 +#define cfgPSWUSCFG0_0_MSI_MSG_DATA_64 0x00ac +#define cfgPSWUSCFG0_0_SSID_CAP_LIST 0x00c0 +#define cfgPSWUSCFG0_0_SSID_CAP 0x00c4 +#define cfgPSWUSCFG0_0_MSI_MAP_CAP_LIST 0x00c8 +#define cfgPSWUSCFG0_0_MSI_MAP_CAP 0x00ca +#define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgPSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST 0x0110 +#define cfgPSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1 0x0114 +#define cfgPSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2 0x0118 +#define cfgPSWUSCFG0_0_PCIE_PORT_VC_CNTL 0x011c +#define cfgPSWUSCFG0_0_PCIE_PORT_VC_STATUS 0x011e +#define cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP 0x0120 +#define cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL 0x0124 +#define cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS 0x012a +#define cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP 0x012c +#define cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL 0x0130 +#define cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS 0x0136 +#define cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 +#define cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 +#define cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 +#define cfgPSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgPSWUSCFG0_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgPSWUSCFG0_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgPSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgPSWUSCFG0_0_PCIE_HDR_LOG0 0x016c +#define cfgPSWUSCFG0_0_PCIE_HDR_LOG1 0x0170 +#define cfgPSWUSCFG0_0_PCIE_HDR_LOG2 0x0174 +#define cfgPSWUSCFG0_0_PCIE_HDR_LOG3 0x0178 +#define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgPSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 +#define cfgPSWUSCFG0_0_PCIE_LINK_CNTL3 0x0274 +#define cfgPSWUSCFG0_0_PCIE_LANE_ERROR_STATUS 0x0278 +#define cfgPSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c +#define cfgPSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e +#define cfgPSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 +#define cfgPSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 +#define cfgPSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 +#define cfgPSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 +#define cfgPSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 +#define cfgPSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a +#define cfgPSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c +#define cfgPSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e +#define cfgPSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 +#define cfgPSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 +#define cfgPSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 +#define cfgPSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 +#define cfgPSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 +#define cfgPSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a +#define cfgPSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgPSWUSCFG0_0_PCIE_ACS_CAP 0x02a4 +#define cfgPSWUSCFG0_0_PCIE_ACS_CNTL 0x02a6 +#define cfgPSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST 0x02f0 +#define cfgPSWUSCFG0_0_PCIE_MC_CAP 0x02f4 +#define cfgPSWUSCFG0_0_PCIE_MC_CNTL 0x02f6 +#define cfgPSWUSCFG0_0_PCIE_MC_ADDR0 0x02f8 +#define cfgPSWUSCFG0_0_PCIE_MC_ADDR1 0x02fc +#define cfgPSWUSCFG0_0_PCIE_MC_RCV0 0x0300 +#define cfgPSWUSCFG0_0_PCIE_MC_RCV1 0x0304 +#define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_ALL0 0x0308 +#define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_ALL1 0x030c +#define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 +#define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 +#define cfgPSWUSCFG0_0_PCIE_MC_OVERLAY_BAR0 0x0318 +#define cfgPSWUSCFG0_0_PCIE_MC_OVERLAY_BAR1 0x031c +#define cfgPSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST 0x0320 +#define cfgPSWUSCFG0_0_PCIE_LTR_CAP 0x0324 +#define cfgPSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgPSWUSCFG0_0_PCIE_ARI_CAP 0x032c +#define cfgPSWUSCFG0_0_PCIE_ARI_CNTL 0x032e +#define cfgPSWUSCFG0_0_PCIE_L1_PM_SUB_CAP_LIST 0x0370 +#define cfgPSWUSCFG0_0_PCIE_L1_PM_SUB_CAP 0x0374 +#define cfgPSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL 0x0378 +#define cfgPSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL2 0x037c +#define cfgPSWUSCFG0_0_PCIE_ESM_CAP_LIST 0x03c4 +#define cfgPSWUSCFG0_0_PCIE_ESM_HEADER_1 0x03c8 +#define cfgPSWUSCFG0_0_PCIE_ESM_HEADER_2 0x03cc +#define cfgPSWUSCFG0_0_PCIE_ESM_STATUS 0x03ce +#define cfgPSWUSCFG0_0_PCIE_ESM_CTRL 0x03d0 +#define cfgPSWUSCFG0_0_PCIE_ESM_CAP_1 0x03d4 +#define cfgPSWUSCFG0_0_PCIE_ESM_CAP_2 0x03d8 +#define cfgPSWUSCFG0_0_PCIE_ESM_CAP_3 0x03dc +#define cfgPSWUSCFG0_0_PCIE_ESM_CAP_4 0x03e0 +#define cfgPSWUSCFG0_0_PCIE_ESM_CAP_5 0x03e4 +#define cfgPSWUSCFG0_0_PCIE_ESM_CAP_6 0x03e8 +#define cfgPSWUSCFG0_0_PCIE_ESM_CAP_7 0x03ec +#define cfgPSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST 0x0400 +#define cfgPSWUSCFG0_0_DATA_LINK_FEATURE_CAP 0x0404 +#define cfgPSWUSCFG0_0_DATA_LINK_FEATURE_STATUS 0x0408 +#define cfgPSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 +#define cfgPSWUSCFG0_0_LINK_CAP_16GT 0x0414 +#define cfgPSWUSCFG0_0_LINK_CNTL_16GT 0x0418 +#define cfgPSWUSCFG0_0_LINK_STATUS_16GT 0x041c +#define cfgPSWUSCFG0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 +#define cfgPSWUSCFG0_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 +#define cfgPSWUSCFG0_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 +#define cfgPSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 +#define cfgPSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 +#define cfgPSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 +#define cfgPSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 +#define cfgPSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 +#define cfgPSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 +#define cfgPSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 +#define cfgPSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 +#define cfgPSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 +#define cfgPSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 +#define cfgPSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT 0x043a +#define cfgPSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT 0x043b +#define cfgPSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT 0x043c +#define cfgPSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT 0x043d +#define cfgPSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT 0x043e +#define cfgPSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT 0x043f +#define cfgPSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST 0x0440 +#define cfgPSWUSCFG0_0_MARGINING_PORT_CAP 0x0444 +#define cfgPSWUSCFG0_0_MARGINING_PORT_STATUS 0x0446 +#define cfgPSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL 0x0448 +#define cfgPSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS 0x044a +#define cfgPSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL 0x044c +#define cfgPSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS 0x044e +#define cfgPSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL 0x0450 +#define cfgPSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS 0x0452 +#define cfgPSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL 0x0454 +#define cfgPSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS 0x0456 +#define cfgPSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL 0x0458 +#define cfgPSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS 0x045a +#define cfgPSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL 0x045c +#define cfgPSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS 0x045e +#define cfgPSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL 0x0460 +#define cfgPSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS 0x0462 +#define cfgPSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL 0x0464 +#define cfgPSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS 0x0466 +#define cfgPSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL 0x0468 +#define cfgPSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS 0x046a +#define cfgPSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL 0x046c +#define cfgPSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS 0x046e +#define cfgPSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL 0x0470 +#define cfgPSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS 0x0472 +#define cfgPSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL 0x0474 +#define cfgPSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS 0x0476 +#define cfgPSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL 0x0478 +#define cfgPSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS 0x047a +#define cfgPSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL 0x047c +#define cfgPSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS 0x047e +#define cfgPSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL 0x0480 +#define cfgPSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS 0x0482 +#define cfgPSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL 0x0484 +#define cfgPSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS 0x0486 +#define cfgPSWUSCFG0_0_PCIE_CCIX_CAP_LIST 0x0488 +#define cfgPSWUSCFG0_0_PCIE_CCIX_HEADER_1 0x048c +#define cfgPSWUSCFG0_0_PCIE_CCIX_HEADER_2 0x0490 +#define cfgPSWUSCFG0_0_PCIE_CCIX_CAP 0x0492 +#define cfgPSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP 0x0494 +#define cfgPSWUSCFG0_0_PCIE_CCIX_ESM_OPTL_CAP 0x0498 +#define cfgPSWUSCFG0_0_PCIE_CCIX_ESM_STATUS 0x049c +#define cfgPSWUSCFG0_0_PCIE_CCIX_ESM_CNTL 0x04a0 +#define cfgPSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0x04a4 +#define cfgPSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0x04a5 +#define cfgPSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0x04a6 +#define cfgPSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0x04a7 +#define cfgPSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0x04a8 +#define cfgPSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0x04a9 +#define cfgPSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0x04aa +#define cfgPSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0x04ab +#define cfgPSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0x04ac +#define cfgPSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0x04ad +#define cfgPSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0x04ae +#define cfgPSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0x04af +#define cfgPSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0x04b0 +#define cfgPSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0x04b1 +#define cfgPSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0x04b2 +#define cfgPSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0x04b3 +#define cfgPSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0x04b4 +#define cfgPSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0x04b5 +#define cfgPSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0x04b6 +#define cfgPSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0x04b7 +#define cfgPSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0x04b8 +#define cfgPSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0x04b9 +#define cfgPSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0x04ba +#define cfgPSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0x04bb +#define cfgPSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0x04bc +#define cfgPSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0x04bd +#define cfgPSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0x04be +#define cfgPSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0x04bf +#define cfgPSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0x04c0 +#define cfgPSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0x04c1 +#define cfgPSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0x04c2 +#define cfgPSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0x04c3 +#define cfgPSWUSCFG0_0_PCIE_CCIX_TRANS_CAP 0x04c4 +#define cfgPSWUSCFG0_0_PCIE_CCIX_TRANS_CNTL 0x04c8 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST 0x0048 +#define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W 0x004c +#define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST 0x0110 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 0x0114 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 0x0118 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL 0x011c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS 0x011e +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP 0x0120 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL 0x0124 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS 0x012a +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP 0x012c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL 0x0130 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS 0x0136 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST 0x0200 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP 0x0204 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL 0x0208 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP 0x020c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL 0x0210 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP 0x0214 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL 0x0218 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP 0x021c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL 0x0220 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP 0x0224 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL 0x0228 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP 0x022c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL 0x0230 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA 0x0248 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP 0x024c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST 0x0250 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP 0x0254 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS 0x025c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL 0x025e +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 0x0274 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS 0x0278 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP 0x02a4 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL 0x02a6 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL 0x02c4 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS 0x02c6 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST 0x02d0 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP 0x02d4 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL 0x02d6 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST 0x02f0 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP 0x02f4 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL 0x02f6 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0 0x02f8 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1 0x02fc +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0 0x0300 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1 0x0304 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0 0x0308 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1 0x030c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST 0x0320 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP 0x0324 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL 0x032e +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST 0x0330 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP 0x0334 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL 0x0338 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS 0x033a +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS 0x033c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS 0x033e +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS 0x0340 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK 0x0342 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE 0x0346 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID 0x034a +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST 0x0370 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP 0x0374 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL 0x0378 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP 0x0404 +#define cfgBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS 0x0408 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 +#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT 0x0414 +#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT 0x0418 +#define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT 0x041c +#define cfgBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 +#define cfgBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 +#define cfgBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT 0x043a +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT 0x043b +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT 0x043c +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT 0x043d +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT 0x043e +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT 0x043f +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST 0x0440 +#define cfgBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP 0x0444 +#define cfgBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS 0x0446 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL 0x0448 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS 0x044a +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL 0x044c +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS 0x044e +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL 0x0450 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS 0x0452 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL 0x0454 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS 0x0456 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL 0x0458 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS 0x045a +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL 0x045c +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS 0x045e +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL 0x0460 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS 0x0462 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL 0x0464 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS 0x0466 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL 0x0468 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS 0x046a +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL 0x046c +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS 0x046e +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL 0x0470 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS 0x0472 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL 0x0474 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS 0x0476 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL 0x0478 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS 0x047a +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL 0x047c +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS 0x047e +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL 0x0480 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS 0x0482 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL 0x0484 +#define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS 0x0486 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x04c0 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP 0x04c4 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL 0x04c8 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP 0x04cc +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL 0x04d0 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP 0x04d4 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL 0x04d8 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP 0x04dc +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL 0x04e0 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP 0x04e4 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL 0x04e8 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP 0x04ec +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL 0x04f0 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0500 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0504 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0508 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x050c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0510 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0514 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0518 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x051c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0520 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0524 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0528 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x052c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0x0530 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0x0534 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0538 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x053c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0540 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x0544 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0548 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x054c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0550 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x0554 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0558 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x055c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0560 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x0564 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0568 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x056c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0570 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x0574 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0x0578 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0x057c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0x0580 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0x0584 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0x0588 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0x058c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0x0590 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0x0594 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0x0598 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0x059c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0x05a0 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0x05a4 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0x05a8 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0x05ac +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0x05b0 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x05c0 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x05c4 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x05c8 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x05cc +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x05d0 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x05d4 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x05d8 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x05dc +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0x05e0 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x05f0 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x05f4 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x05f8 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x05fc +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x0600 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x0604 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x0608 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x060c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0x0610 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x0620 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x0624 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x0628 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x062c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x0630 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x0634 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x0638 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x063c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0x0640 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 0x0650 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 0x0654 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 0x0658 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 0x065c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 0x0660 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 0x0664 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 0x0668 +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 0x066c +#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 0x0670 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF1_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF1_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF1_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF1_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF1_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF1_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF1_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF1_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF1_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF1_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF1_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF1_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST 0x0048 +#define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W 0x004c +#define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST 0x0110 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1 0x0114 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2 0x0118 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL 0x011c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS 0x011e +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP 0x0120 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL 0x0124 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS 0x012a +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP 0x012c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL 0x0130 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS 0x0136 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST 0x0200 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP 0x0204 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL 0x0208 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP 0x020c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL 0x0210 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP 0x0214 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL 0x0218 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP 0x021c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL 0x0220 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP 0x0224 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL 0x0228 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP 0x022c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL 0x0230 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA 0x0248 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP 0x024c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST 0x0250 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP 0x0254 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS 0x025c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL 0x025e +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3 0x0274 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS 0x0278 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP 0x02a4 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL 0x02a6 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL 0x02c4 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS 0x02c6 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST 0x02d0 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP 0x02d4 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL 0x02d6 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST 0x02f0 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP 0x02f4 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL 0x02f6 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0 0x02f8 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1 0x02fc +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0 0x0300 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1 0x0304 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0 0x0308 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1 0x030c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST 0x0320 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP 0x0324 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL 0x032e +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST 0x0330 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP 0x0334 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL 0x0338 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS 0x033a +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS 0x033c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS 0x033e +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS 0x0340 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK 0x0342 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE 0x0346 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID 0x034a +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST 0x0370 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP 0x0374 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL 0x0378 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP 0x0404 +#define cfgBIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS 0x0408 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 +#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT 0x0414 +#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT 0x0418 +#define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT 0x041c +#define cfgBIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 +#define cfgBIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 +#define cfgBIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT 0x043a +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT 0x043b +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT 0x043c +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT 0x043d +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT 0x043e +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT 0x043f +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST 0x0440 +#define cfgBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP 0x0444 +#define cfgBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS 0x0446 +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL 0x0448 +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS 0x044a +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL 0x044c +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS 0x044e +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL 0x0450 +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS 0x0452 +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL 0x0454 +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS 0x0456 +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL 0x0458 +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS 0x045a +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL 0x045c +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS 0x045e +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL 0x0460 +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS 0x0462 +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL 0x0464 +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS 0x0466 +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL 0x0468 +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS 0x046a +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL 0x046c +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS 0x046e +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL 0x0470 +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS 0x0472 +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL 0x0474 +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS 0x0476 +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL 0x0478 +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS 0x047a +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL 0x047c +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS 0x047e +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL 0x0480 +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS 0x0482 +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL 0x0484 +#define cfgBIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS 0x0486 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x04c0 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP 0x04c4 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL 0x04c8 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP 0x04cc +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL 0x04d0 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP 0x04d4 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL 0x04d8 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP 0x04dc +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL 0x04e0 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP 0x04e4 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL 0x04e8 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP 0x04ec +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL 0x04f0 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0500 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0504 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0508 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x050c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0510 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0514 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0518 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x051c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0520 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0524 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0528 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x052c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0x0530 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0x0534 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0538 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x053c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0540 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x0544 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0548 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x054c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0550 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x0554 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0558 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x055c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0560 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x0564 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0568 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x056c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0570 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x0574 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0x0578 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0x057c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0x0580 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0x0584 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0x0588 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0x058c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0x0590 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0x0594 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0x0598 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0x059c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0x05a0 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0x05a4 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0x05a8 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0x05ac +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0x05b0 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x05c0 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x05c4 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x05c8 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x05cc +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x05d0 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x05d4 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x05d8 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x05dc +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0x05e0 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x05f0 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x05f4 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x05f8 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x05fc +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x0600 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x0604 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x0608 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x060c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0x0610 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x0620 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x0624 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x0628 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x062c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x0630 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x0634 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x0638 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x063c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0x0640 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 0x0650 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 0x0654 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 0x0658 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 0x065c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 0x0660 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 0x0664 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 0x0668 +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 0x066c +#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 0x0670 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF2_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF2_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF2_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF2_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF2_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF2_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF2_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF2_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF2_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF2_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF2_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF2_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF2_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF2_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST 0x0048 +#define cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W 0x004c +#define cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV0_EPF2_0_SBRN 0x0060 +#define cfgBIF_CFG_DEV0_EPF2_0_FLADJ 0x0061 +#define cfgBIF_CFG_DEV0_EPF2_0_DBESL_DBESLD 0x0062 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF2_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF2_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF2_0_SATA_CAP_0 0x00d0 +#define cfgBIF_CFG_DEV0_EPF2_0_SATA_CAP_1 0x00d4 +#define cfgBIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX 0x00d8 +#define cfgBIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA 0x00dc +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST 0x0200 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP 0x0204 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL 0x0208 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP 0x020c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL 0x0210 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP 0x0214 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL 0x0218 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP 0x021c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL 0x0220 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP 0x0224 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL 0x0228 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP 0x022c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL 0x0230 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA 0x0248 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP 0x024c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST 0x0250 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP 0x0254 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS 0x025c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL 0x025e +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP 0x02a4 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL 0x02a6 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST 0x02d0 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP 0x02d4 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL 0x02d6 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL 0x032e +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST 0x0370 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP 0x0374 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL 0x0378 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0 0x037c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1 0x037e +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2 0x0380 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3 0x0382 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4 0x0384 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5 0x0386 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6 0x0388 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7 0x038a +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8 0x038c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9 0x038e +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10 0x0390 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11 0x0392 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12 0x0394 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13 0x0396 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14 0x0398 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15 0x039a +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16 0x039c +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17 0x039e +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18 0x03a0 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19 0x03a2 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20 0x03a4 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21 0x03a6 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22 0x03a8 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23 0x03aa +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24 0x03ac +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25 0x03ae +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26 0x03b0 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27 0x03b2 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28 0x03b4 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29 0x03b6 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30 0x03b8 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31 0x03ba +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32 0x03bc +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33 0x03be +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34 0x03c0 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35 0x03c2 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36 0x03c4 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37 0x03c6 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38 0x03c8 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39 0x03ca +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40 0x03cc +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41 0x03ce +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42 0x03d0 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43 0x03d2 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44 0x03d4 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45 0x03d6 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46 0x03d8 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47 0x03da +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48 0x03dc +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49 0x03de +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50 0x03e0 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51 0x03e2 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52 0x03e4 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53 0x03e6 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54 0x03e8 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55 0x03ea +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56 0x03ec +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57 0x03ee +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58 0x03f0 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59 0x03f2 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60 0x03f4 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61 0x03f6 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62 0x03f8 +#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63 0x03fa + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF3_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF3_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF3_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF3_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF3_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF3_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF3_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF3_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF3_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF3_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF3_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF3_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF3_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF3_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST 0x0048 +#define cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W 0x004c +#define cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV0_EPF3_0_SBRN 0x0060 +#define cfgBIF_CFG_DEV0_EPF3_0_FLADJ 0x0061 +#define cfgBIF_CFG_DEV0_EPF3_0_DBESL_DBESLD 0x0062 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF3_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF3_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF3_0_SATA_CAP_0 0x00d0 +#define cfgBIF_CFG_DEV0_EPF3_0_SATA_CAP_1 0x00d4 +#define cfgBIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX 0x00d8 +#define cfgBIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA 0x00dc +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST 0x0200 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP 0x0204 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL 0x0208 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP 0x020c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL 0x0210 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP 0x0214 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL 0x0218 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP 0x021c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL 0x0220 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP 0x0224 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL 0x0228 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP 0x022c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL 0x0230 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA 0x0248 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP 0x024c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST 0x0250 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP 0x0254 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS 0x025c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL 0x025e +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP 0x02a4 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL 0x02a6 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST 0x02d0 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP 0x02d4 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL 0x02d6 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL 0x032e +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST 0x0370 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP 0x0374 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL 0x0378 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0 0x037c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1 0x037e +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2 0x0380 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3 0x0382 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4 0x0384 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5 0x0386 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6 0x0388 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7 0x038a +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8 0x038c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9 0x038e +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10 0x0390 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11 0x0392 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12 0x0394 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13 0x0396 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14 0x0398 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15 0x039a +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16 0x039c +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17 0x039e +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18 0x03a0 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19 0x03a2 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20 0x03a4 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21 0x03a6 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22 0x03a8 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23 0x03aa +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24 0x03ac +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25 0x03ae +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26 0x03b0 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27 0x03b2 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28 0x03b4 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29 0x03b6 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30 0x03b8 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31 0x03ba +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32 0x03bc +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33 0x03be +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34 0x03c0 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35 0x03c2 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36 0x03c4 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37 0x03c6 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38 0x03c8 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39 0x03ca +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40 0x03cc +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41 0x03ce +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42 0x03d0 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43 0x03d2 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44 0x03d4 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45 0x03d6 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46 0x03d8 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47 0x03da +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48 0x03dc +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49 0x03de +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50 0x03e0 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51 0x03e2 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52 0x03e4 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53 0x03e6 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54 0x03e8 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55 0x03ea +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56 0x03ec +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57 0x03ee +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58 0x03f0 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59 0x03f2 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60 0x03f4 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61 0x03f6 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62 0x03f8 +#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63 0x03fa + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_swds_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_SWDS0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_SWDS0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_SWDS0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_SWDS0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_SWDS0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_SWDS0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_SWDS0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_SWDS0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_SWDS0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_SWDS0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_SWDS0_BIST 0x000f +#define cfgBIF_CFG_DEV0_SWDS0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_SWDS0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY 0x0018 +#define cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT 0x001c +#define cfgBIF_CFG_DEV0_SWDS0_SECONDARY_STATUS 0x001e +#define cfgBIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT 0x0020 +#define cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT 0x0024 +#define cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_UPPER 0x0028 +#define cfgBIF_CFG_DEV0_SWDS0_PREF_LIMIT_UPPER 0x002c +#define cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI 0x0030 +#define cfgBIF_CFG_DEV0_SWDS0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_SWDS0_ROM_BASE_ADDR 0x0038 +#define cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL 0x003e +#define cfgBIF_CFG_DEV0_SWDS0_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV0_SWDS0_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST 0x0058 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP 0x005a +#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP 0x005c +#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL 0x0060 +#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS 0x0062 +#define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP 0x0064 +#define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL 0x0068 +#define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS 0x006a +#define cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP 0x006c +#define cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL 0x0070 +#define cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS 0x0072 +#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP2 0x007c +#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL2 0x0080 +#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS2 0x0082 +#define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP2 0x0084 +#define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL2 0x0088 +#define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS2 0x008a +#define cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP2 0x008c +#define cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL2 0x0090 +#define cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS2 0x0092 +#define cfgBIF_CFG_DEV0_SWDS0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_SWDS0_SSID_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_SWDS0_SSID_CAP 0x00c4 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST 0x0110 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1 0x0114 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2 0x0118 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL 0x011c +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_STATUS 0x011e +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP 0x0120 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL 0x0124 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS 0x012a +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP 0x012c +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL 0x0130 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS 0x0136 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3 0x0274 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS 0x0278 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP 0x02a4 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL 0x02a6 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_DLF_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_CAP 0x0404 +#define cfgBIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_STATUS 0x0408 +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 +#define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP_16GT 0x0414 +#define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL_16GT 0x0418 +#define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT 0x041c +#define cfgBIF_CFG_DEV0_SWDS0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 +#define cfgBIF_CFG_DEV0_SWDS0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 +#define cfgBIF_CFG_DEV0_SWDS0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 +#define cfgBIF_CFG_DEV0_SWDS0_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 +#define cfgBIF_CFG_DEV0_SWDS0_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 +#define cfgBIF_CFG_DEV0_SWDS0_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 +#define cfgBIF_CFG_DEV0_SWDS0_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 +#define cfgBIF_CFG_DEV0_SWDS0_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 +#define cfgBIF_CFG_DEV0_SWDS0_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 +#define cfgBIF_CFG_DEV0_SWDS0_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 +#define cfgBIF_CFG_DEV0_SWDS0_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 +#define cfgBIF_CFG_DEV0_SWDS0_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 +#define cfgBIF_CFG_DEV0_SWDS0_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 +#define cfgBIF_CFG_DEV0_SWDS0_LANE_10_EQUALIZATION_CNTL_16GT 0x043a +#define cfgBIF_CFG_DEV0_SWDS0_LANE_11_EQUALIZATION_CNTL_16GT 0x043b +#define cfgBIF_CFG_DEV0_SWDS0_LANE_12_EQUALIZATION_CNTL_16GT 0x043c +#define cfgBIF_CFG_DEV0_SWDS0_LANE_13_EQUALIZATION_CNTL_16GT 0x043d +#define cfgBIF_CFG_DEV0_SWDS0_LANE_14_EQUALIZATION_CNTL_16GT 0x043e +#define cfgBIF_CFG_DEV0_SWDS0_LANE_15_EQUALIZATION_CNTL_16GT 0x043f +#define cfgBIF_CFG_DEV0_SWDS0_PCIE_MARGINING_ENH_CAP_LIST 0x0440 +#define cfgBIF_CFG_DEV0_SWDS0_MARGINING_PORT_CAP 0x0444 +#define cfgBIF_CFG_DEV0_SWDS0_MARGINING_PORT_STATUS 0x0446 +#define cfgBIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL 0x0448 +#define cfgBIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS 0x044a +#define cfgBIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL 0x044c +#define cfgBIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS 0x044e +#define cfgBIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL 0x0450 +#define cfgBIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS 0x0452 +#define cfgBIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL 0x0454 +#define cfgBIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS 0x0456 +#define cfgBIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL 0x0458 +#define cfgBIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS 0x045a +#define cfgBIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL 0x045c +#define cfgBIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS 0x045e +#define cfgBIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL 0x0460 +#define cfgBIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS 0x0462 +#define cfgBIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL 0x0464 +#define cfgBIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS 0x0466 +#define cfgBIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL 0x0468 +#define cfgBIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS 0x046a +#define cfgBIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL 0x046c +#define cfgBIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS 0x046e +#define cfgBIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL 0x0470 +#define cfgBIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS 0x0472 +#define cfgBIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL 0x0474 +#define cfgBIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS 0x0476 +#define cfgBIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL 0x0478 +#define cfgBIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS 0x047a +#define cfgBIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL 0x047c +#define cfgBIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS 0x047e +#define cfgBIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL 0x0480 +#define cfgBIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS 0x0482 +#define cfgBIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL 0x0484 +#define cfgBIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS 0x0486 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf16_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf17_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf18_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf19_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf20_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf21_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf22_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf23_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf24_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf25_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf26_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf27_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf28_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf29_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf30_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX 0x0000 +#define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF0_MM_DATA 0x0001 +#define mmBIF_BX_DEV0_EPF0_VF0_MM_DATA_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI 0x0006 +#define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF0_RCC_ERR_LOG 0x0085 +#define mmRCC_DEV0_EPF0_VF0_RCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS 0x00eb +#define mmBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ 0x0106 +#define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE 0x0107 +#define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING 0x0108 +#define mmBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define mmBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL 0x013e +#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL 0x013f +#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX 0x0140 +#define mmBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFDEC2 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL 0x0403 +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL 0x0407 +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA 0x040a +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL 0x040b +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO 0x040c +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI 0x040d +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA 0x040e +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL 0x040f +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_PBA 0x0800 +#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX 0x0000 +#define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF1_MM_DATA 0x0001 +#define mmBIF_BX_DEV0_EPF0_VF1_MM_DATA_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI 0x0006 +#define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF1_RCC_ERR_LOG 0x0085 +#define mmRCC_DEV0_EPF0_VF1_RCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS 0x00eb +#define mmBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ 0x0106 +#define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE 0x0107 +#define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING 0x0108 +#define mmBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define mmBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL 0x013e +#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL 0x013f +#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX 0x0140 +#define mmBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFDEC2 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL 0x0403 +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL 0x0407 +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA 0x040a +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL 0x040b +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO 0x040c +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI 0x040d +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA 0x040e +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL 0x040f +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_PBA 0x0800 +#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX 0x0000 +#define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF2_MM_DATA 0x0001 +#define mmBIF_BX_DEV0_EPF0_VF2_MM_DATA_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI 0x0006 +#define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF2_RCC_ERR_LOG 0x0085 +#define mmRCC_DEV0_EPF0_VF2_RCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS 0x00eb +#define mmBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ 0x0106 +#define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE 0x0107 +#define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING 0x0108 +#define mmBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define mmBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL 0x013e +#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL 0x013f +#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX 0x0140 +#define mmBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFDEC2 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL 0x0403 +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL 0x0407 +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA 0x040a +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL 0x040b +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO 0x040c +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI 0x040d +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA 0x040e +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL 0x040f +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_PBA 0x0800 +#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX 0x0000 +#define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF3_MM_DATA 0x0001 +#define mmBIF_BX_DEV0_EPF0_VF3_MM_DATA_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI 0x0006 +#define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF3_RCC_ERR_LOG 0x0085 +#define mmRCC_DEV0_EPF0_VF3_RCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS 0x00eb +#define mmBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ 0x0106 +#define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE 0x0107 +#define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING 0x0108 +#define mmBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define mmBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL 0x013e +#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL 0x013f +#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX 0x0140 +#define mmBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFDEC2 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL 0x0403 +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL 0x0407 +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA 0x040a +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL 0x040b +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO 0x040c +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI 0x040d +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA 0x040e +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL 0x040f +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_PBA 0x0800 +#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX 0x0000 +#define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF4_MM_DATA 0x0001 +#define mmBIF_BX_DEV0_EPF0_VF4_MM_DATA_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI 0x0006 +#define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF4_RCC_ERR_LOG 0x0085 +#define mmRCC_DEV0_EPF0_VF4_RCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS 0x00eb +#define mmBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ 0x0106 +#define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE 0x0107 +#define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING 0x0108 +#define mmBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define mmBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL 0x013e +#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL 0x013f +#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX 0x0140 +#define mmBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFDEC2 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL 0x0403 +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL 0x0407 +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA 0x040a +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL 0x040b +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO 0x040c +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI 0x040d +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA 0x040e +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL 0x040f +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_PBA 0x0800 +#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX 0x0000 +#define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF5_MM_DATA 0x0001 +#define mmBIF_BX_DEV0_EPF0_VF5_MM_DATA_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI 0x0006 +#define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF5_RCC_ERR_LOG 0x0085 +#define mmRCC_DEV0_EPF0_VF5_RCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS 0x00eb +#define mmBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ 0x0106 +#define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE 0x0107 +#define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING 0x0108 +#define mmBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define mmBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL 0x013e +#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL 0x013f +#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX 0x0140 +#define mmBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFDEC2 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL 0x0403 +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL 0x0407 +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA 0x040a +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL 0x040b +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO 0x040c +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI 0x040d +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA 0x040e +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL 0x040f +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_PBA 0x0800 +#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX 0x0000 +#define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF6_MM_DATA 0x0001 +#define mmBIF_BX_DEV0_EPF0_VF6_MM_DATA_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI 0x0006 +#define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF6_RCC_ERR_LOG 0x0085 +#define mmRCC_DEV0_EPF0_VF6_RCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS 0x00eb +#define mmBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ 0x0106 +#define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE 0x0107 +#define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING 0x0108 +#define mmBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define mmBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL 0x013e +#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL 0x013f +#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX 0x0140 +#define mmBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFDEC2 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL 0x0403 +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL 0x0407 +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA 0x040a +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL 0x040b +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO 0x040c +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI 0x040d +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA 0x040e +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL 0x040f +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_PBA 0x0800 +#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX 0x0000 +#define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF7_MM_DATA 0x0001 +#define mmBIF_BX_DEV0_EPF0_VF7_MM_DATA_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI 0x0006 +#define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF7_RCC_ERR_LOG 0x0085 +#define mmRCC_DEV0_EPF0_VF7_RCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS 0x00eb +#define mmBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ 0x0106 +#define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE 0x0107 +#define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING 0x0108 +#define mmBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define mmBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL 0x013e +#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL 0x013f +#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX 0x0140 +#define mmBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFDEC2 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL 0x0403 +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL 0x0407 +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA 0x040a +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL 0x040b +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO 0x040c +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI 0x040d +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA 0x040e +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL 0x040f +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_PBA 0x0800 +#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_SYSPFVFDEC +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX 0x0000 +#define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF8_MM_DATA 0x0001 +#define mmBIF_BX_DEV0_EPF0_VF8_MM_DATA_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI 0x0006 +#define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF8_RCC_ERR_LOG 0x0085 +#define mmRCC_DEV0_EPF0_VF8_RCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS 0x00eb +#define mmBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ 0x0106 +#define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE 0x0107 +#define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING 0x0108 +#define mmBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define mmBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL 0x013e +#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL 0x013f +#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX 0x0140 +#define mmBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFDEC2 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL 0x0403 +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL 0x0407 +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA 0x040a +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL 0x040b +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO 0x040c +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI 0x040d +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA 0x040e +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL 0x040f +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_PBA 0x0800 +#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_SYSPFVFDEC +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX 0x0000 +#define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF9_MM_DATA 0x0001 +#define mmBIF_BX_DEV0_EPF0_VF9_MM_DATA_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI 0x0006 +#define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF9_RCC_ERR_LOG 0x0085 +#define mmRCC_DEV0_EPF0_VF9_RCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS 0x00eb +#define mmBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ 0x0106 +#define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE 0x0107 +#define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING 0x0108 +#define mmBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define mmBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL 0x013e +#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL 0x013f +#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX 0x0140 +#define mmBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFDEC2 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL 0x0403 +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL 0x0407 +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA 0x040a +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL 0x040b +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO 0x040c +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI 0x040d +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA 0x040e +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL 0x040f +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_PBA 0x0800 +#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_SYSPFVFDEC +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX 0x0000 +#define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF10_MM_DATA 0x0001 +#define mmBIF_BX_DEV0_EPF0_VF10_MM_DATA_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI 0x0006 +#define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF10_RCC_ERR_LOG 0x0085 +#define mmRCC_DEV0_EPF0_VF10_RCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS 0x00eb +#define mmBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ 0x0106 +#define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE 0x0107 +#define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING 0x0108 +#define mmBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define mmBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL 0x013e +#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL 0x013f +#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX 0x0140 +#define mmBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFDEC2 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL 0x0403 +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL 0x0407 +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA 0x040a +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL 0x040b +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO 0x040c +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI 0x040d +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA 0x040e +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL 0x040f +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_PBA 0x0800 +#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_SYSPFVFDEC +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX 0x0000 +#define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF11_MM_DATA 0x0001 +#define mmBIF_BX_DEV0_EPF0_VF11_MM_DATA_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI 0x0006 +#define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF11_RCC_ERR_LOG 0x0085 +#define mmRCC_DEV0_EPF0_VF11_RCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS 0x00eb +#define mmBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ 0x0106 +#define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE 0x0107 +#define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING 0x0108 +#define mmBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define mmBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL 0x013e +#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL 0x013f +#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX 0x0140 +#define mmBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFDEC2 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL 0x0403 +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL 0x0407 +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA 0x040a +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL 0x040b +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO 0x040c +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI 0x040d +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA 0x040e +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL 0x040f +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_PBA 0x0800 +#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_SYSPFVFDEC +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX 0x0000 +#define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF12_MM_DATA 0x0001 +#define mmBIF_BX_DEV0_EPF0_VF12_MM_DATA_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI 0x0006 +#define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF12_RCC_ERR_LOG 0x0085 +#define mmRCC_DEV0_EPF0_VF12_RCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS 0x00eb +#define mmBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ 0x0106 +#define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE 0x0107 +#define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING 0x0108 +#define mmBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define mmBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL 0x013e +#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL 0x013f +#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX 0x0140 +#define mmBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFDEC2 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL 0x0403 +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL 0x0407 +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA 0x040a +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL 0x040b +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO 0x040c +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI 0x040d +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA 0x040e +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL 0x040f +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_PBA 0x0800 +#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_SYSPFVFDEC +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX 0x0000 +#define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF13_MM_DATA 0x0001 +#define mmBIF_BX_DEV0_EPF0_VF13_MM_DATA_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI 0x0006 +#define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF13_RCC_ERR_LOG 0x0085 +#define mmRCC_DEV0_EPF0_VF13_RCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS 0x00eb +#define mmBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ 0x0106 +#define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE 0x0107 +#define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING 0x0108 +#define mmBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define mmBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL 0x013e +#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL 0x013f +#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX 0x0140 +#define mmBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFDEC2 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL 0x0403 +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL 0x0407 +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA 0x040a +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL 0x040b +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO 0x040c +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI 0x040d +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA 0x040e +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL 0x040f +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_PBA 0x0800 +#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_SYSPFVFDEC +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX 0x0000 +#define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF14_MM_DATA 0x0001 +#define mmBIF_BX_DEV0_EPF0_VF14_MM_DATA_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI 0x0006 +#define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF14_RCC_ERR_LOG 0x0085 +#define mmRCC_DEV0_EPF0_VF14_RCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS 0x00eb +#define mmBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ 0x0106 +#define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE 0x0107 +#define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING 0x0108 +#define mmBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define mmBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL 0x013e +#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL 0x013f +#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX 0x0140 +#define mmBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFDEC2 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL 0x0403 +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL 0x0407 +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA 0x040a +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL 0x040b +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO 0x040c +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI 0x040d +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA 0x040e +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL 0x040f +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_PBA 0x0800 +#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_SYSPFVFDEC +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX 0x0000 +#define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF15_MM_DATA 0x0001 +#define mmBIF_BX_DEV0_EPF0_VF15_MM_DATA_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI 0x0006 +#define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF15_RCC_ERR_LOG 0x0085 +#define mmRCC_DEV0_EPF0_VF15_RCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS 0x00eb +#define mmBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ 0x0106 +#define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE 0x0107 +#define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING 0x0108 +#define mmBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define mmBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL 0x013e +#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL 0x013f +#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX 0x0140 +#define mmBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFDEC2 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL 0x0403 +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL 0x0407 +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA 0x040a +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL 0x040b +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO 0x040c +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI 0x040d +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA 0x040e +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL 0x040f +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_PBA 0x0800 +#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf16_SYSPFVFDEC +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF16_MM_INDEX 0x0000 +#define mmBIF_BX_DEV0_EPF0_VF16_MM_INDEX_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF16_MM_DATA 0x0001 +#define mmBIF_BX_DEV0_EPF0_VF16_MM_DATA_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF16_MM_INDEX_HI 0x0006 +#define mmBIF_BX_DEV0_EPF0_VF16_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf16_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF16_RCC_ERR_LOG 0x0085 +#define mmRCC_DEV0_EPF0_VF16_RCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF16_RCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DEV0_EPF0_VF16_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF16_RCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_DEV0_EPF0_VF16_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF16_RCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_DEV0_EPF0_VF16_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf16_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS 0x00eb +#define mmBIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF16_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmBIF_BX_DEV0_EPF0_VF16_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF16_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmBIF_BX_DEV0_EPF0_VF16_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ 0x0106 +#define mmBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE 0x0107 +#define mmBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING 0x0108 +#define mmBIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF16_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define mmBIF_BX_DEV0_EPF0_VF16_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL 0x013e +#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL 0x013f +#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX 0x0140 +#define mmBIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf16_BIFDEC2 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_CONTROL 0x0403 +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_CONTROL 0x0407 +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_MSG_DATA 0x040a +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_CONTROL 0x040b +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_LO 0x040c +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_HI 0x040d +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_MSG_DATA 0x040e +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_CONTROL 0x040f +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_PBA 0x0800 +#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf17_SYSPFVFDEC +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF17_MM_INDEX 0x0000 +#define mmBIF_BX_DEV0_EPF0_VF17_MM_INDEX_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF17_MM_DATA 0x0001 +#define mmBIF_BX_DEV0_EPF0_VF17_MM_DATA_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF17_MM_INDEX_HI 0x0006 +#define mmBIF_BX_DEV0_EPF0_VF17_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf17_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF17_RCC_ERR_LOG 0x0085 +#define mmRCC_DEV0_EPF0_VF17_RCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF17_RCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DEV0_EPF0_VF17_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF17_RCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_DEV0_EPF0_VF17_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF17_RCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_DEV0_EPF0_VF17_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf17_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS 0x00eb +#define mmBIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF17_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmBIF_BX_DEV0_EPF0_VF17_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF17_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmBIF_BX_DEV0_EPF0_VF17_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ 0x0106 +#define mmBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE 0x0107 +#define mmBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING 0x0108 +#define mmBIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF17_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define mmBIF_BX_DEV0_EPF0_VF17_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL 0x013e +#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL 0x013f +#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX 0x0140 +#define mmBIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf17_BIFDEC2 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_CONTROL 0x0403 +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_CONTROL 0x0407 +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_MSG_DATA 0x040a +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_CONTROL 0x040b +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_LO 0x040c +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_HI 0x040d +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_MSG_DATA 0x040e +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_CONTROL 0x040f +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_PBA 0x0800 +#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf18_SYSPFVFDEC +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF18_MM_INDEX 0x0000 +#define mmBIF_BX_DEV0_EPF0_VF18_MM_INDEX_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF18_MM_DATA 0x0001 +#define mmBIF_BX_DEV0_EPF0_VF18_MM_DATA_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF18_MM_INDEX_HI 0x0006 +#define mmBIF_BX_DEV0_EPF0_VF18_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf18_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF18_RCC_ERR_LOG 0x0085 +#define mmRCC_DEV0_EPF0_VF18_RCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF18_RCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DEV0_EPF0_VF18_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF18_RCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_DEV0_EPF0_VF18_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF18_RCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_DEV0_EPF0_VF18_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf18_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS 0x00eb +#define mmBIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF18_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmBIF_BX_DEV0_EPF0_VF18_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF18_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmBIF_BX_DEV0_EPF0_VF18_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ 0x0106 +#define mmBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE 0x0107 +#define mmBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING 0x0108 +#define mmBIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF18_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define mmBIF_BX_DEV0_EPF0_VF18_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL 0x013e +#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL 0x013f +#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX 0x0140 +#define mmBIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf18_BIFDEC2 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_CONTROL 0x0403 +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_CONTROL 0x0407 +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_MSG_DATA 0x040a +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_CONTROL 0x040b +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_LO 0x040c +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_HI 0x040d +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_MSG_DATA 0x040e +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_CONTROL 0x040f +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_PBA 0x0800 +#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf19_SYSPFVFDEC +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF19_MM_INDEX 0x0000 +#define mmBIF_BX_DEV0_EPF0_VF19_MM_INDEX_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF19_MM_DATA 0x0001 +#define mmBIF_BX_DEV0_EPF0_VF19_MM_DATA_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF19_MM_INDEX_HI 0x0006 +#define mmBIF_BX_DEV0_EPF0_VF19_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf19_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF19_RCC_ERR_LOG 0x0085 +#define mmRCC_DEV0_EPF0_VF19_RCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF19_RCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DEV0_EPF0_VF19_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF19_RCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_DEV0_EPF0_VF19_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF19_RCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_DEV0_EPF0_VF19_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf19_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS 0x00eb +#define mmBIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF19_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmBIF_BX_DEV0_EPF0_VF19_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF19_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmBIF_BX_DEV0_EPF0_VF19_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ 0x0106 +#define mmBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE 0x0107 +#define mmBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING 0x0108 +#define mmBIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF19_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define mmBIF_BX_DEV0_EPF0_VF19_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL 0x013e +#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL 0x013f +#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX 0x0140 +#define mmBIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf19_BIFDEC2 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_CONTROL 0x0403 +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_CONTROL 0x0407 +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_MSG_DATA 0x040a +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_CONTROL 0x040b +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_LO 0x040c +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_HI 0x040d +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_MSG_DATA 0x040e +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_CONTROL 0x040f +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_PBA 0x0800 +#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf20_SYSPFVFDEC +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF20_MM_INDEX 0x0000 +#define mmBIF_BX_DEV0_EPF0_VF20_MM_INDEX_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF20_MM_DATA 0x0001 +#define mmBIF_BX_DEV0_EPF0_VF20_MM_DATA_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF20_MM_INDEX_HI 0x0006 +#define mmBIF_BX_DEV0_EPF0_VF20_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf20_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF20_RCC_ERR_LOG 0x0085 +#define mmRCC_DEV0_EPF0_VF20_RCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF20_RCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DEV0_EPF0_VF20_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF20_RCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_DEV0_EPF0_VF20_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF20_RCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_DEV0_EPF0_VF20_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf20_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS 0x00eb +#define mmBIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF20_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmBIF_BX_DEV0_EPF0_VF20_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF20_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmBIF_BX_DEV0_EPF0_VF20_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ 0x0106 +#define mmBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE 0x0107 +#define mmBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING 0x0108 +#define mmBIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF20_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define mmBIF_BX_DEV0_EPF0_VF20_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL 0x013e +#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL 0x013f +#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX 0x0140 +#define mmBIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf20_BIFDEC2 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_CONTROL 0x0403 +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_CONTROL 0x0407 +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_MSG_DATA 0x040a +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_CONTROL 0x040b +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_LO 0x040c +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_HI 0x040d +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_MSG_DATA 0x040e +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_CONTROL 0x040f +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_PBA 0x0800 +#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf21_SYSPFVFDEC +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF21_MM_INDEX 0x0000 +#define mmBIF_BX_DEV0_EPF0_VF21_MM_INDEX_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF21_MM_DATA 0x0001 +#define mmBIF_BX_DEV0_EPF0_VF21_MM_DATA_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF21_MM_INDEX_HI 0x0006 +#define mmBIF_BX_DEV0_EPF0_VF21_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf21_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF21_RCC_ERR_LOG 0x0085 +#define mmRCC_DEV0_EPF0_VF21_RCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF21_RCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DEV0_EPF0_VF21_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF21_RCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_DEV0_EPF0_VF21_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF21_RCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_DEV0_EPF0_VF21_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf21_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS 0x00eb +#define mmBIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF21_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmBIF_BX_DEV0_EPF0_VF21_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF21_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmBIF_BX_DEV0_EPF0_VF21_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ 0x0106 +#define mmBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE 0x0107 +#define mmBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING 0x0108 +#define mmBIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF21_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define mmBIF_BX_DEV0_EPF0_VF21_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL 0x013e +#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL 0x013f +#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX 0x0140 +#define mmBIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf21_BIFDEC2 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_CONTROL 0x0403 +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_CONTROL 0x0407 +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_MSG_DATA 0x040a +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_CONTROL 0x040b +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_LO 0x040c +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_HI 0x040d +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_MSG_DATA 0x040e +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_CONTROL 0x040f +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_PBA 0x0800 +#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf22_SYSPFVFDEC +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF22_MM_INDEX 0x0000 +#define mmBIF_BX_DEV0_EPF0_VF22_MM_INDEX_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF22_MM_DATA 0x0001 +#define mmBIF_BX_DEV0_EPF0_VF22_MM_DATA_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF22_MM_INDEX_HI 0x0006 +#define mmBIF_BX_DEV0_EPF0_VF22_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf22_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF22_RCC_ERR_LOG 0x0085 +#define mmRCC_DEV0_EPF0_VF22_RCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF22_RCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DEV0_EPF0_VF22_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF22_RCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_DEV0_EPF0_VF22_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF22_RCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_DEV0_EPF0_VF22_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf22_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS 0x00eb +#define mmBIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF22_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmBIF_BX_DEV0_EPF0_VF22_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF22_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmBIF_BX_DEV0_EPF0_VF22_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ 0x0106 +#define mmBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE 0x0107 +#define mmBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING 0x0108 +#define mmBIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF22_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define mmBIF_BX_DEV0_EPF0_VF22_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL 0x013e +#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL 0x013f +#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX 0x0140 +#define mmBIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf22_BIFDEC2 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_CONTROL 0x0403 +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_CONTROL 0x0407 +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_MSG_DATA 0x040a +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_CONTROL 0x040b +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_LO 0x040c +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_HI 0x040d +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_MSG_DATA 0x040e +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_CONTROL 0x040f +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_PBA 0x0800 +#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf23_SYSPFVFDEC +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF23_MM_INDEX 0x0000 +#define mmBIF_BX_DEV0_EPF0_VF23_MM_INDEX_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF23_MM_DATA 0x0001 +#define mmBIF_BX_DEV0_EPF0_VF23_MM_DATA_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF23_MM_INDEX_HI 0x0006 +#define mmBIF_BX_DEV0_EPF0_VF23_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf23_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF23_RCC_ERR_LOG 0x0085 +#define mmRCC_DEV0_EPF0_VF23_RCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF23_RCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DEV0_EPF0_VF23_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF23_RCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_DEV0_EPF0_VF23_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF23_RCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_DEV0_EPF0_VF23_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf23_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS 0x00eb +#define mmBIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF23_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmBIF_BX_DEV0_EPF0_VF23_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF23_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmBIF_BX_DEV0_EPF0_VF23_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ 0x0106 +#define mmBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE 0x0107 +#define mmBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING 0x0108 +#define mmBIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF23_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define mmBIF_BX_DEV0_EPF0_VF23_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL 0x013e +#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL 0x013f +#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX 0x0140 +#define mmBIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf23_BIFDEC2 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_CONTROL 0x0403 +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_CONTROL 0x0407 +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_MSG_DATA 0x040a +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_CONTROL 0x040b +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_LO 0x040c +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_HI 0x040d +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_MSG_DATA 0x040e +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_CONTROL 0x040f +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_PBA 0x0800 +#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf24_SYSPFVFDEC +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF24_MM_INDEX 0x0000 +#define mmBIF_BX_DEV0_EPF0_VF24_MM_INDEX_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF24_MM_DATA 0x0001 +#define mmBIF_BX_DEV0_EPF0_VF24_MM_DATA_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF24_MM_INDEX_HI 0x0006 +#define mmBIF_BX_DEV0_EPF0_VF24_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf24_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF24_RCC_ERR_LOG 0x0085 +#define mmRCC_DEV0_EPF0_VF24_RCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF24_RCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DEV0_EPF0_VF24_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF24_RCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_DEV0_EPF0_VF24_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF24_RCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_DEV0_EPF0_VF24_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF24_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_DEV0_EPF0_VF24_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf24_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF24_BIF_BME_STATUS 0x00eb +#define mmBIF_BX_DEV0_EPF0_VF24_BIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF24_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmBIF_BX_DEV0_EPF0_VF24_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF24_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmBIF_BX_DEV0_EPF0_VF24_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ 0x0106 +#define mmBIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE 0x0107 +#define mmBIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF24_BIF_TRANS_PENDING 0x0108 +#define mmBIF_BX_DEV0_EPF0_VF24_BIF_TRANS_PENDING_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF24_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define mmBIF_BX_DEV0_EPF0_VF24_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL 0x013e +#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_INT_CNTL 0x013f +#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX 0x0140 +#define mmBIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf24_BIFDEC2 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_CONTROL 0x0403 +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_CONTROL 0x0407 +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_MSG_DATA 0x040a +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_CONTROL 0x040b +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_LO 0x040c +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_HI 0x040d +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_MSG_DATA 0x040e +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_CONTROL 0x040f +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_PBA 0x0800 +#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf25_SYSPFVFDEC +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF25_MM_INDEX 0x0000 +#define mmBIF_BX_DEV0_EPF0_VF25_MM_INDEX_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF25_MM_DATA 0x0001 +#define mmBIF_BX_DEV0_EPF0_VF25_MM_DATA_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF25_MM_INDEX_HI 0x0006 +#define mmBIF_BX_DEV0_EPF0_VF25_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf25_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF25_RCC_ERR_LOG 0x0085 +#define mmRCC_DEV0_EPF0_VF25_RCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF25_RCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DEV0_EPF0_VF25_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF25_RCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_DEV0_EPF0_VF25_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF25_RCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_DEV0_EPF0_VF25_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF25_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_DEV0_EPF0_VF25_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf25_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF25_BIF_BME_STATUS 0x00eb +#define mmBIF_BX_DEV0_EPF0_VF25_BIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF25_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmBIF_BX_DEV0_EPF0_VF25_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF25_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmBIF_BX_DEV0_EPF0_VF25_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ 0x0106 +#define mmBIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE 0x0107 +#define mmBIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF25_BIF_TRANS_PENDING 0x0108 +#define mmBIF_BX_DEV0_EPF0_VF25_BIF_TRANS_PENDING_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF25_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define mmBIF_BX_DEV0_EPF0_VF25_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL 0x013e +#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_INT_CNTL 0x013f +#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX 0x0140 +#define mmBIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf25_BIFDEC2 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_CONTROL 0x0403 +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_CONTROL 0x0407 +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_MSG_DATA 0x040a +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_CONTROL 0x040b +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_LO 0x040c +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_HI 0x040d +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_MSG_DATA 0x040e +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_CONTROL 0x040f +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_PBA 0x0800 +#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf26_SYSPFVFDEC +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF26_MM_INDEX 0x0000 +#define mmBIF_BX_DEV0_EPF0_VF26_MM_INDEX_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF26_MM_DATA 0x0001 +#define mmBIF_BX_DEV0_EPF0_VF26_MM_DATA_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF26_MM_INDEX_HI 0x0006 +#define mmBIF_BX_DEV0_EPF0_VF26_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf26_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF26_RCC_ERR_LOG 0x0085 +#define mmRCC_DEV0_EPF0_VF26_RCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF26_RCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DEV0_EPF0_VF26_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF26_RCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_DEV0_EPF0_VF26_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF26_RCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_DEV0_EPF0_VF26_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF26_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_DEV0_EPF0_VF26_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf26_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF26_BIF_BME_STATUS 0x00eb +#define mmBIF_BX_DEV0_EPF0_VF26_BIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF26_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmBIF_BX_DEV0_EPF0_VF26_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF26_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmBIF_BX_DEV0_EPF0_VF26_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ 0x0106 +#define mmBIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE 0x0107 +#define mmBIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF26_BIF_TRANS_PENDING 0x0108 +#define mmBIF_BX_DEV0_EPF0_VF26_BIF_TRANS_PENDING_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF26_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define mmBIF_BX_DEV0_EPF0_VF26_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL 0x013e +#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_INT_CNTL 0x013f +#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX 0x0140 +#define mmBIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf26_BIFDEC2 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_CONTROL 0x0403 +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_CONTROL 0x0407 +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_MSG_DATA 0x040a +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_CONTROL 0x040b +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_LO 0x040c +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_HI 0x040d +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_MSG_DATA 0x040e +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_CONTROL 0x040f +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_PBA 0x0800 +#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf27_SYSPFVFDEC +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF27_MM_INDEX 0x0000 +#define mmBIF_BX_DEV0_EPF0_VF27_MM_INDEX_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF27_MM_DATA 0x0001 +#define mmBIF_BX_DEV0_EPF0_VF27_MM_DATA_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF27_MM_INDEX_HI 0x0006 +#define mmBIF_BX_DEV0_EPF0_VF27_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf27_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF27_RCC_ERR_LOG 0x0085 +#define mmRCC_DEV0_EPF0_VF27_RCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF27_RCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DEV0_EPF0_VF27_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF27_RCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_DEV0_EPF0_VF27_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF27_RCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_DEV0_EPF0_VF27_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF27_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_DEV0_EPF0_VF27_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf27_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF27_BIF_BME_STATUS 0x00eb +#define mmBIF_BX_DEV0_EPF0_VF27_BIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF27_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmBIF_BX_DEV0_EPF0_VF27_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF27_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmBIF_BX_DEV0_EPF0_VF27_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ 0x0106 +#define mmBIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE 0x0107 +#define mmBIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF27_BIF_TRANS_PENDING 0x0108 +#define mmBIF_BX_DEV0_EPF0_VF27_BIF_TRANS_PENDING_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF27_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define mmBIF_BX_DEV0_EPF0_VF27_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL 0x013e +#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_INT_CNTL 0x013f +#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX 0x0140 +#define mmBIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf27_BIFDEC2 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_CONTROL 0x0403 +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_CONTROL 0x0407 +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_MSG_DATA 0x040a +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_CONTROL 0x040b +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_LO 0x040c +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_HI 0x040d +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_MSG_DATA 0x040e +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_CONTROL 0x040f +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_PBA 0x0800 +#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf28_SYSPFVFDEC +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF28_MM_INDEX 0x0000 +#define mmBIF_BX_DEV0_EPF0_VF28_MM_INDEX_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF28_MM_DATA 0x0001 +#define mmBIF_BX_DEV0_EPF0_VF28_MM_DATA_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF28_MM_INDEX_HI 0x0006 +#define mmBIF_BX_DEV0_EPF0_VF28_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf28_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF28_RCC_ERR_LOG 0x0085 +#define mmRCC_DEV0_EPF0_VF28_RCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF28_RCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DEV0_EPF0_VF28_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF28_RCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_DEV0_EPF0_VF28_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF28_RCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_DEV0_EPF0_VF28_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF28_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_DEV0_EPF0_VF28_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf28_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF28_BIF_BME_STATUS 0x00eb +#define mmBIF_BX_DEV0_EPF0_VF28_BIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF28_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmBIF_BX_DEV0_EPF0_VF28_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF28_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmBIF_BX_DEV0_EPF0_VF28_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ 0x0106 +#define mmBIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE 0x0107 +#define mmBIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF28_BIF_TRANS_PENDING 0x0108 +#define mmBIF_BX_DEV0_EPF0_VF28_BIF_TRANS_PENDING_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF28_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define mmBIF_BX_DEV0_EPF0_VF28_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL 0x013e +#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_INT_CNTL 0x013f +#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX 0x0140 +#define mmBIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf28_BIFDEC2 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_CONTROL 0x0403 +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_CONTROL 0x0407 +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_MSG_DATA 0x040a +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_CONTROL 0x040b +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_LO 0x040c +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_HI 0x040d +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_MSG_DATA 0x040e +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_CONTROL 0x040f +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_PBA 0x0800 +#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf29_SYSPFVFDEC +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF29_MM_INDEX 0x0000 +#define mmBIF_BX_DEV0_EPF0_VF29_MM_INDEX_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF29_MM_DATA 0x0001 +#define mmBIF_BX_DEV0_EPF0_VF29_MM_DATA_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF29_MM_INDEX_HI 0x0006 +#define mmBIF_BX_DEV0_EPF0_VF29_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf29_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF29_RCC_ERR_LOG 0x0085 +#define mmRCC_DEV0_EPF0_VF29_RCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF29_RCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DEV0_EPF0_VF29_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF29_RCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_DEV0_EPF0_VF29_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF29_RCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_DEV0_EPF0_VF29_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF29_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_DEV0_EPF0_VF29_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf29_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF29_BIF_BME_STATUS 0x00eb +#define mmBIF_BX_DEV0_EPF0_VF29_BIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF29_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmBIF_BX_DEV0_EPF0_VF29_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF29_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmBIF_BX_DEV0_EPF0_VF29_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ 0x0106 +#define mmBIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE 0x0107 +#define mmBIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF29_BIF_TRANS_PENDING 0x0108 +#define mmBIF_BX_DEV0_EPF0_VF29_BIF_TRANS_PENDING_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF29_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define mmBIF_BX_DEV0_EPF0_VF29_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL 0x013e +#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_INT_CNTL 0x013f +#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX 0x0140 +#define mmBIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf29_BIFDEC2 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_CONTROL 0x0403 +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_CONTROL 0x0407 +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_MSG_DATA 0x040a +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_CONTROL 0x040b +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_LO 0x040c +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_HI 0x040d +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_MSG_DATA 0x040e +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_CONTROL 0x040f +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_PBA 0x0800 +#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf30_SYSPFVFDEC +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF30_MM_INDEX 0x0000 +#define mmBIF_BX_DEV0_EPF0_VF30_MM_INDEX_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF30_MM_DATA 0x0001 +#define mmBIF_BX_DEV0_EPF0_VF30_MM_DATA_BASE_IDX 0 +#define mmBIF_BX_DEV0_EPF0_VF30_MM_INDEX_HI 0x0006 +#define mmBIF_BX_DEV0_EPF0_VF30_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf30_BIFPFVFDEC1 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF30_RCC_ERR_LOG 0x0085 +#define mmRCC_DEV0_EPF0_VF30_RCC_ERR_LOG_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF30_RCC_DOORBELL_APER_EN 0x00c0 +#define mmRCC_DEV0_EPF0_VF30_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF30_RCC_CONFIG_MEMSIZE 0x00c3 +#define mmRCC_DEV0_EPF0_VF30_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF30_RCC_CONFIG_RESERVED 0x00c4 +#define mmRCC_DEV0_EPF0_VF30_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define mmRCC_DEV0_EPF0_VF30_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define mmRCC_DEV0_EPF0_VF30_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf30_BIFPFVFDEC1 +// base address: 0x0 +#define mmBIF_BX_DEV0_EPF0_VF30_BIF_BME_STATUS 0x00eb +#define mmBIF_BX_DEV0_EPF0_VF30_BIF_BME_STATUS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG 0x00ec +#define mmBIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define mmBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define mmBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define mmBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF30_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define mmBIF_BX_DEV0_EPF0_VF30_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF30_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define mmBIF_BX_DEV0_EPF0_VF30_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ 0x0106 +#define mmBIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE 0x0107 +#define mmBIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF30_BIF_TRANS_PENDING 0x0108 +#define mmBIF_BX_DEV0_EPF0_VF30_BIF_TRANS_PENDING_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF30_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define mmBIF_BX_DEV0_EPF0_VF30_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL 0x013e +#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_INT_CNTL 0x013f +#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_INT_CNTL_BASE_IDX 2 +#define mmBIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX 0x0140 +#define mmBIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf30_BIFDEC2 +// base address: 0x0 +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_CONTROL 0x0403 +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_CONTROL 0x0407 +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_MSG_DATA 0x040a +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_CONTROL 0x040b +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_LO 0x040c +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_HI 0x040d +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_MSG_DATA 0x040e +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_CONTROL 0x040f +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_PBA 0x0800 +#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_PBA_BASE_IDX 3 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC +// base address: 0xd0000000 +#define cfgBIF_BX_DEV0_EPF0_VF0_MM_INDEX 0xd0000000 +#define cfgBIF_BX_DEV0_EPF0_VF0_MM_DATA 0xd0000004 +#define cfgBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI 0xd0000018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1 +// base address: 0xd0000000 +#define cfgRCC_DEV0_EPF0_VF0_RCC_ERR_LOG 0xd0003694 +#define cfgRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN 0xd0003780 +#define cfgRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE 0xd000378c +#define cfgRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED 0xd0003790 +#define cfgRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER 0xd0003794 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1 +// base address: 0xd0000000 +#define cfgBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS 0xd000382c +#define cfgBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG 0xd0003830 +#define cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd000384c +#define cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0003850 +#define cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0003854 +#define cfgBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0003858 +#define cfgBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd000385c +#define cfgBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ 0xd0003898 +#define cfgBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE 0xd000389c +#define cfgBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING 0xd00038a0 +#define cfgBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS 0xd00038c8 +#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 0xd0003958 +#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 0xd000395c +#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 0xd0003960 +#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 0xd0003964 +#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 0xd0003968 +#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 0xd000396c +#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 0xd0003970 +#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 0xd0003974 +#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL 0xd0003978 +#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL 0xd000397c +#define cfgBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX 0xd0003980 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFDEC2 +// base address: 0xd0000000 +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO 0xd0042000 +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI 0xd0042004 +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA 0xd0042008 +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL 0xd004200c +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO 0xd0042010 +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI 0xd0042014 +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA 0xd0042018 +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL 0xd004201c +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO 0xd0042020 +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI 0xd0042024 +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA 0xd0042028 +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL 0xd004202c +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO 0xd0042030 +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI 0xd0042034 +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA 0xd0042038 +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL 0xd004203c +#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_PBA 0xd0043000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC +// base address: 0xd0080000 +#define cfgBIF_BX_DEV0_EPF0_VF1_MM_INDEX 0xd0080000 +#define cfgBIF_BX_DEV0_EPF0_VF1_MM_DATA 0xd0080004 +#define cfgBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI 0xd0080018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1 +// base address: 0xd0080000 +#define cfgRCC_DEV0_EPF0_VF1_RCC_ERR_LOG 0xd0083694 +#define cfgRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN 0xd0083780 +#define cfgRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE 0xd008378c +#define cfgRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED 0xd0083790 +#define cfgRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER 0xd0083794 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1 +// base address: 0xd0080000 +#define cfgBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS 0xd008382c +#define cfgBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG 0xd0083830 +#define cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd008384c +#define cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0083850 +#define cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0083854 +#define cfgBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0083858 +#define cfgBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd008385c +#define cfgBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ 0xd0083898 +#define cfgBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE 0xd008389c +#define cfgBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING 0xd00838a0 +#define cfgBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS 0xd00838c8 +#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 0xd0083958 +#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 0xd008395c +#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 0xd0083960 +#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 0xd0083964 +#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 0xd0083968 +#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 0xd008396c +#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 0xd0083970 +#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 0xd0083974 +#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL 0xd0083978 +#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL 0xd008397c +#define cfgBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX 0xd0083980 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFDEC2 +// base address: 0xd0080000 +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO 0xd00c2000 +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI 0xd00c2004 +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA 0xd00c2008 +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL 0xd00c200c +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO 0xd00c2010 +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI 0xd00c2014 +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA 0xd00c2018 +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL 0xd00c201c +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO 0xd00c2020 +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI 0xd00c2024 +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA 0xd00c2028 +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL 0xd00c202c +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO 0xd00c2030 +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI 0xd00c2034 +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA 0xd00c2038 +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL 0xd00c203c +#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_PBA 0xd00c3000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC +// base address: 0xd0100000 +#define cfgBIF_BX_DEV0_EPF0_VF2_MM_INDEX 0xd0100000 +#define cfgBIF_BX_DEV0_EPF0_VF2_MM_DATA 0xd0100004 +#define cfgBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI 0xd0100018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1 +// base address: 0xd0100000 +#define cfgRCC_DEV0_EPF0_VF2_RCC_ERR_LOG 0xd0103694 +#define cfgRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN 0xd0103780 +#define cfgRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE 0xd010378c +#define cfgRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED 0xd0103790 +#define cfgRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER 0xd0103794 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1 +// base address: 0xd0100000 +#define cfgBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS 0xd010382c +#define cfgBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG 0xd0103830 +#define cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd010384c +#define cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0103850 +#define cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0103854 +#define cfgBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0103858 +#define cfgBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd010385c +#define cfgBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ 0xd0103898 +#define cfgBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE 0xd010389c +#define cfgBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING 0xd01038a0 +#define cfgBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS 0xd01038c8 +#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 0xd0103958 +#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 0xd010395c +#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 0xd0103960 +#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 0xd0103964 +#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 0xd0103968 +#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 0xd010396c +#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 0xd0103970 +#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 0xd0103974 +#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL 0xd0103978 +#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL 0xd010397c +#define cfgBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX 0xd0103980 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFDEC2 +// base address: 0xd0100000 +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO 0xd0142000 +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI 0xd0142004 +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA 0xd0142008 +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL 0xd014200c +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO 0xd0142010 +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI 0xd0142014 +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA 0xd0142018 +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL 0xd014201c +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO 0xd0142020 +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI 0xd0142024 +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA 0xd0142028 +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL 0xd014202c +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO 0xd0142030 +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI 0xd0142034 +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA 0xd0142038 +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL 0xd014203c +#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_PBA 0xd0143000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC +// base address: 0xd0180000 +#define cfgBIF_BX_DEV0_EPF0_VF3_MM_INDEX 0xd0180000 +#define cfgBIF_BX_DEV0_EPF0_VF3_MM_DATA 0xd0180004 +#define cfgBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI 0xd0180018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1 +// base address: 0xd0180000 +#define cfgRCC_DEV0_EPF0_VF3_RCC_ERR_LOG 0xd0183694 +#define cfgRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN 0xd0183780 +#define cfgRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE 0xd018378c +#define cfgRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED 0xd0183790 +#define cfgRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER 0xd0183794 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1 +// base address: 0xd0180000 +#define cfgBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS 0xd018382c +#define cfgBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG 0xd0183830 +#define cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd018384c +#define cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0183850 +#define cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0183854 +#define cfgBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0183858 +#define cfgBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd018385c +#define cfgBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ 0xd0183898 +#define cfgBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE 0xd018389c +#define cfgBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING 0xd01838a0 +#define cfgBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS 0xd01838c8 +#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 0xd0183958 +#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 0xd018395c +#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 0xd0183960 +#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 0xd0183964 +#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 0xd0183968 +#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 0xd018396c +#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 0xd0183970 +#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 0xd0183974 +#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL 0xd0183978 +#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL 0xd018397c +#define cfgBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX 0xd0183980 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFDEC2 +// base address: 0xd0180000 +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO 0xd01c2000 +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI 0xd01c2004 +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA 0xd01c2008 +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL 0xd01c200c +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO 0xd01c2010 +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI 0xd01c2014 +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA 0xd01c2018 +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL 0xd01c201c +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO 0xd01c2020 +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI 0xd01c2024 +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA 0xd01c2028 +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL 0xd01c202c +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO 0xd01c2030 +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI 0xd01c2034 +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA 0xd01c2038 +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL 0xd01c203c +#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_PBA 0xd01c3000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC +// base address: 0xd0200000 +#define cfgBIF_BX_DEV0_EPF0_VF4_MM_INDEX 0xd0200000 +#define cfgBIF_BX_DEV0_EPF0_VF4_MM_DATA 0xd0200004 +#define cfgBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI 0xd0200018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1 +// base address: 0xd0200000 +#define cfgRCC_DEV0_EPF0_VF4_RCC_ERR_LOG 0xd0203694 +#define cfgRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN 0xd0203780 +#define cfgRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE 0xd020378c +#define cfgRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED 0xd0203790 +#define cfgRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER 0xd0203794 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1 +// base address: 0xd0200000 +#define cfgBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS 0xd020382c +#define cfgBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG 0xd0203830 +#define cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd020384c +#define cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0203850 +#define cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0203854 +#define cfgBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0203858 +#define cfgBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd020385c +#define cfgBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ 0xd0203898 +#define cfgBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE 0xd020389c +#define cfgBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING 0xd02038a0 +#define cfgBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS 0xd02038c8 +#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 0xd0203958 +#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 0xd020395c +#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 0xd0203960 +#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 0xd0203964 +#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 0xd0203968 +#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 0xd020396c +#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 0xd0203970 +#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 0xd0203974 +#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL 0xd0203978 +#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL 0xd020397c +#define cfgBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX 0xd0203980 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFDEC2 +// base address: 0xd0200000 +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO 0xd0242000 +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI 0xd0242004 +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA 0xd0242008 +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL 0xd024200c +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO 0xd0242010 +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI 0xd0242014 +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA 0xd0242018 +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL 0xd024201c +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO 0xd0242020 +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI 0xd0242024 +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA 0xd0242028 +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL 0xd024202c +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO 0xd0242030 +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI 0xd0242034 +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA 0xd0242038 +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL 0xd024203c +#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_PBA 0xd0243000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC +// base address: 0xd0280000 +#define cfgBIF_BX_DEV0_EPF0_VF5_MM_INDEX 0xd0280000 +#define cfgBIF_BX_DEV0_EPF0_VF5_MM_DATA 0xd0280004 +#define cfgBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI 0xd0280018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1 +// base address: 0xd0280000 +#define cfgRCC_DEV0_EPF0_VF5_RCC_ERR_LOG 0xd0283694 +#define cfgRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN 0xd0283780 +#define cfgRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE 0xd028378c +#define cfgRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED 0xd0283790 +#define cfgRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER 0xd0283794 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1 +// base address: 0xd0280000 +#define cfgBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS 0xd028382c +#define cfgBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG 0xd0283830 +#define cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd028384c +#define cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0283850 +#define cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0283854 +#define cfgBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0283858 +#define cfgBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd028385c +#define cfgBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ 0xd0283898 +#define cfgBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE 0xd028389c +#define cfgBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING 0xd02838a0 +#define cfgBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS 0xd02838c8 +#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 0xd0283958 +#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 0xd028395c +#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 0xd0283960 +#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 0xd0283964 +#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 0xd0283968 +#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 0xd028396c +#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 0xd0283970 +#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 0xd0283974 +#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL 0xd0283978 +#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL 0xd028397c +#define cfgBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX 0xd0283980 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFDEC2 +// base address: 0xd0280000 +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO 0xd02c2000 +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI 0xd02c2004 +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA 0xd02c2008 +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL 0xd02c200c +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO 0xd02c2010 +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI 0xd02c2014 +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA 0xd02c2018 +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL 0xd02c201c +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO 0xd02c2020 +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI 0xd02c2024 +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA 0xd02c2028 +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL 0xd02c202c +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO 0xd02c2030 +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI 0xd02c2034 +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA 0xd02c2038 +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL 0xd02c203c +#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_PBA 0xd02c3000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC +// base address: 0xd0300000 +#define cfgBIF_BX_DEV0_EPF0_VF6_MM_INDEX 0xd0300000 +#define cfgBIF_BX_DEV0_EPF0_VF6_MM_DATA 0xd0300004 +#define cfgBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI 0xd0300018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1 +// base address: 0xd0300000 +#define cfgRCC_DEV0_EPF0_VF6_RCC_ERR_LOG 0xd0303694 +#define cfgRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN 0xd0303780 +#define cfgRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE 0xd030378c +#define cfgRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED 0xd0303790 +#define cfgRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER 0xd0303794 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1 +// base address: 0xd0300000 +#define cfgBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS 0xd030382c +#define cfgBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG 0xd0303830 +#define cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd030384c +#define cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0303850 +#define cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0303854 +#define cfgBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0303858 +#define cfgBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd030385c +#define cfgBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ 0xd0303898 +#define cfgBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE 0xd030389c +#define cfgBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING 0xd03038a0 +#define cfgBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS 0xd03038c8 +#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 0xd0303958 +#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 0xd030395c +#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 0xd0303960 +#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 0xd0303964 +#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 0xd0303968 +#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 0xd030396c +#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 0xd0303970 +#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 0xd0303974 +#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL 0xd0303978 +#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL 0xd030397c +#define cfgBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX 0xd0303980 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFDEC2 +// base address: 0xd0300000 +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO 0xd0342000 +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI 0xd0342004 +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA 0xd0342008 +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL 0xd034200c +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO 0xd0342010 +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI 0xd0342014 +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA 0xd0342018 +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL 0xd034201c +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO 0xd0342020 +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI 0xd0342024 +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA 0xd0342028 +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL 0xd034202c +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO 0xd0342030 +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI 0xd0342034 +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA 0xd0342038 +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL 0xd034203c +#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_PBA 0xd0343000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC +// base address: 0xd0380000 +#define cfgBIF_BX_DEV0_EPF0_VF7_MM_INDEX 0xd0380000 +#define cfgBIF_BX_DEV0_EPF0_VF7_MM_DATA 0xd0380004 +#define cfgBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI 0xd0380018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1 +// base address: 0xd0380000 +#define cfgRCC_DEV0_EPF0_VF7_RCC_ERR_LOG 0xd0383694 +#define cfgRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN 0xd0383780 +#define cfgRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE 0xd038378c +#define cfgRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED 0xd0383790 +#define cfgRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER 0xd0383794 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1 +// base address: 0xd0380000 +#define cfgBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS 0xd038382c +#define cfgBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG 0xd0383830 +#define cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd038384c +#define cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0383850 +#define cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0383854 +#define cfgBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0383858 +#define cfgBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd038385c +#define cfgBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ 0xd0383898 +#define cfgBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE 0xd038389c +#define cfgBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING 0xd03838a0 +#define cfgBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS 0xd03838c8 +#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 0xd0383958 +#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 0xd038395c +#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 0xd0383960 +#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 0xd0383964 +#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 0xd0383968 +#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 0xd038396c +#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 0xd0383970 +#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 0xd0383974 +#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL 0xd0383978 +#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL 0xd038397c +#define cfgBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX 0xd0383980 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFDEC2 +// base address: 0xd0380000 +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO 0xd03c2000 +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI 0xd03c2004 +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA 0xd03c2008 +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL 0xd03c200c +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO 0xd03c2010 +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI 0xd03c2014 +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA 0xd03c2018 +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL 0xd03c201c +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO 0xd03c2020 +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI 0xd03c2024 +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA 0xd03c2028 +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL 0xd03c202c +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO 0xd03c2030 +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI 0xd03c2034 +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA 0xd03c2038 +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL 0xd03c203c +#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_PBA 0xd03c3000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_SYSPFVFDEC +// base address: 0xd0400000 +#define cfgBIF_BX_DEV0_EPF0_VF8_MM_INDEX 0xd0400000 +#define cfgBIF_BX_DEV0_EPF0_VF8_MM_DATA 0xd0400004 +#define cfgBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI 0xd0400018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFPFVFDEC1 +// base address: 0xd0400000 +#define cfgRCC_DEV0_EPF0_VF8_RCC_ERR_LOG 0xd0403694 +#define cfgRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN 0xd0403780 +#define cfgRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE 0xd040378c +#define cfgRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED 0xd0403790 +#define cfgRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER 0xd0403794 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1 +// base address: 0xd0400000 +#define cfgBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS 0xd040382c +#define cfgBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG 0xd0403830 +#define cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd040384c +#define cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0403850 +#define cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0403854 +#define cfgBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0403858 +#define cfgBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd040385c +#define cfgBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ 0xd0403898 +#define cfgBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE 0xd040389c +#define cfgBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING 0xd04038a0 +#define cfgBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS 0xd04038c8 +#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0 0xd0403958 +#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1 0xd040395c +#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2 0xd0403960 +#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3 0xd0403964 +#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0 0xd0403968 +#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1 0xd040396c +#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2 0xd0403970 +#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3 0xd0403974 +#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL 0xd0403978 +#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL 0xd040397c +#define cfgBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX 0xd0403980 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFDEC2 +// base address: 0xd0400000 +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO 0xd0442000 +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI 0xd0442004 +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA 0xd0442008 +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL 0xd044200c +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO 0xd0442010 +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI 0xd0442014 +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA 0xd0442018 +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL 0xd044201c +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO 0xd0442020 +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI 0xd0442024 +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA 0xd0442028 +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL 0xd044202c +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO 0xd0442030 +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI 0xd0442034 +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA 0xd0442038 +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL 0xd044203c +#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_PBA 0xd0443000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_SYSPFVFDEC +// base address: 0xd0480000 +#define cfgBIF_BX_DEV0_EPF0_VF9_MM_INDEX 0xd0480000 +#define cfgBIF_BX_DEV0_EPF0_VF9_MM_DATA 0xd0480004 +#define cfgBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI 0xd0480018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFPFVFDEC1 +// base address: 0xd0480000 +#define cfgRCC_DEV0_EPF0_VF9_RCC_ERR_LOG 0xd0483694 +#define cfgRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN 0xd0483780 +#define cfgRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE 0xd048378c +#define cfgRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED 0xd0483790 +#define cfgRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER 0xd0483794 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1 +// base address: 0xd0480000 +#define cfgBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS 0xd048382c +#define cfgBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG 0xd0483830 +#define cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd048384c +#define cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0483850 +#define cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0483854 +#define cfgBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0483858 +#define cfgBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd048385c +#define cfgBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ 0xd0483898 +#define cfgBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE 0xd048389c +#define cfgBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING 0xd04838a0 +#define cfgBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS 0xd04838c8 +#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0 0xd0483958 +#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1 0xd048395c +#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2 0xd0483960 +#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3 0xd0483964 +#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0 0xd0483968 +#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1 0xd048396c +#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2 0xd0483970 +#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3 0xd0483974 +#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL 0xd0483978 +#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL 0xd048397c +#define cfgBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX 0xd0483980 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFDEC2 +// base address: 0xd0480000 +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO 0xd04c2000 +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI 0xd04c2004 +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA 0xd04c2008 +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL 0xd04c200c +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO 0xd04c2010 +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI 0xd04c2014 +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA 0xd04c2018 +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL 0xd04c201c +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO 0xd04c2020 +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI 0xd04c2024 +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA 0xd04c2028 +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL 0xd04c202c +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO 0xd04c2030 +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI 0xd04c2034 +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA 0xd04c2038 +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL 0xd04c203c +#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_PBA 0xd04c3000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_SYSPFVFDEC +// base address: 0xd0500000 +#define cfgBIF_BX_DEV0_EPF0_VF10_MM_INDEX 0xd0500000 +#define cfgBIF_BX_DEV0_EPF0_VF10_MM_DATA 0xd0500004 +#define cfgBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI 0xd0500018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFPFVFDEC1 +// base address: 0xd0500000 +#define cfgRCC_DEV0_EPF0_VF10_RCC_ERR_LOG 0xd0503694 +#define cfgRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN 0xd0503780 +#define cfgRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE 0xd050378c +#define cfgRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED 0xd0503790 +#define cfgRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER 0xd0503794 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1 +// base address: 0xd0500000 +#define cfgBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS 0xd050382c +#define cfgBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG 0xd0503830 +#define cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd050384c +#define cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0503850 +#define cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0503854 +#define cfgBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0503858 +#define cfgBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd050385c +#define cfgBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ 0xd0503898 +#define cfgBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE 0xd050389c +#define cfgBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING 0xd05038a0 +#define cfgBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS 0xd05038c8 +#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0 0xd0503958 +#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1 0xd050395c +#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2 0xd0503960 +#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3 0xd0503964 +#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0 0xd0503968 +#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1 0xd050396c +#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2 0xd0503970 +#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3 0xd0503974 +#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL 0xd0503978 +#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL 0xd050397c +#define cfgBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX 0xd0503980 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFDEC2 +// base address: 0xd0500000 +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO 0xd0542000 +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI 0xd0542004 +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA 0xd0542008 +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL 0xd054200c +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO 0xd0542010 +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI 0xd0542014 +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA 0xd0542018 +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL 0xd054201c +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO 0xd0542020 +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI 0xd0542024 +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA 0xd0542028 +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL 0xd054202c +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO 0xd0542030 +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI 0xd0542034 +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA 0xd0542038 +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL 0xd054203c +#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_PBA 0xd0543000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_SYSPFVFDEC +// base address: 0xd0580000 +#define cfgBIF_BX_DEV0_EPF0_VF11_MM_INDEX 0xd0580000 +#define cfgBIF_BX_DEV0_EPF0_VF11_MM_DATA 0xd0580004 +#define cfgBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI 0xd0580018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFPFVFDEC1 +// base address: 0xd0580000 +#define cfgRCC_DEV0_EPF0_VF11_RCC_ERR_LOG 0xd0583694 +#define cfgRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN 0xd0583780 +#define cfgRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE 0xd058378c +#define cfgRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED 0xd0583790 +#define cfgRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER 0xd0583794 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1 +// base address: 0xd0580000 +#define cfgBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS 0xd058382c +#define cfgBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG 0xd0583830 +#define cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd058384c +#define cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0583850 +#define cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0583854 +#define cfgBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0583858 +#define cfgBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd058385c +#define cfgBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ 0xd0583898 +#define cfgBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE 0xd058389c +#define cfgBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING 0xd05838a0 +#define cfgBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS 0xd05838c8 +#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0 0xd0583958 +#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1 0xd058395c +#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2 0xd0583960 +#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3 0xd0583964 +#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0 0xd0583968 +#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1 0xd058396c +#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2 0xd0583970 +#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3 0xd0583974 +#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL 0xd0583978 +#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL 0xd058397c +#define cfgBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX 0xd0583980 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFDEC2 +// base address: 0xd0580000 +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO 0xd05c2000 +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI 0xd05c2004 +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA 0xd05c2008 +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL 0xd05c200c +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO 0xd05c2010 +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI 0xd05c2014 +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA 0xd05c2018 +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL 0xd05c201c +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO 0xd05c2020 +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI 0xd05c2024 +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA 0xd05c2028 +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL 0xd05c202c +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO 0xd05c2030 +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI 0xd05c2034 +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA 0xd05c2038 +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL 0xd05c203c +#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_PBA 0xd05c3000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_SYSPFVFDEC +// base address: 0xd0600000 +#define cfgBIF_BX_DEV0_EPF0_VF12_MM_INDEX 0xd0600000 +#define cfgBIF_BX_DEV0_EPF0_VF12_MM_DATA 0xd0600004 +#define cfgBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI 0xd0600018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFPFVFDEC1 +// base address: 0xd0600000 +#define cfgRCC_DEV0_EPF0_VF12_RCC_ERR_LOG 0xd0603694 +#define cfgRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN 0xd0603780 +#define cfgRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE 0xd060378c +#define cfgRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED 0xd0603790 +#define cfgRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER 0xd0603794 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1 +// base address: 0xd0600000 +#define cfgBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS 0xd060382c +#define cfgBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG 0xd0603830 +#define cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd060384c +#define cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0603850 +#define cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0603854 +#define cfgBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0603858 +#define cfgBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd060385c +#define cfgBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ 0xd0603898 +#define cfgBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE 0xd060389c +#define cfgBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING 0xd06038a0 +#define cfgBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS 0xd06038c8 +#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0 0xd0603958 +#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1 0xd060395c +#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2 0xd0603960 +#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3 0xd0603964 +#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0 0xd0603968 +#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1 0xd060396c +#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2 0xd0603970 +#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3 0xd0603974 +#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL 0xd0603978 +#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL 0xd060397c +#define cfgBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX 0xd0603980 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFDEC2 +// base address: 0xd0600000 +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO 0xd0642000 +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI 0xd0642004 +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA 0xd0642008 +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL 0xd064200c +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO 0xd0642010 +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI 0xd0642014 +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA 0xd0642018 +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL 0xd064201c +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO 0xd0642020 +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI 0xd0642024 +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA 0xd0642028 +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL 0xd064202c +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO 0xd0642030 +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI 0xd0642034 +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA 0xd0642038 +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL 0xd064203c +#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_PBA 0xd0643000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_SYSPFVFDEC +// base address: 0xd0680000 +#define cfgBIF_BX_DEV0_EPF0_VF13_MM_INDEX 0xd0680000 +#define cfgBIF_BX_DEV0_EPF0_VF13_MM_DATA 0xd0680004 +#define cfgBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI 0xd0680018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFPFVFDEC1 +// base address: 0xd0680000 +#define cfgRCC_DEV0_EPF0_VF13_RCC_ERR_LOG 0xd0683694 +#define cfgRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN 0xd0683780 +#define cfgRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE 0xd068378c +#define cfgRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED 0xd0683790 +#define cfgRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER 0xd0683794 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1 +// base address: 0xd0680000 +#define cfgBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS 0xd068382c +#define cfgBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG 0xd0683830 +#define cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd068384c +#define cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0683850 +#define cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0683854 +#define cfgBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0683858 +#define cfgBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd068385c +#define cfgBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ 0xd0683898 +#define cfgBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE 0xd068389c +#define cfgBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING 0xd06838a0 +#define cfgBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS 0xd06838c8 +#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0 0xd0683958 +#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1 0xd068395c +#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2 0xd0683960 +#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3 0xd0683964 +#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0 0xd0683968 +#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1 0xd068396c +#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2 0xd0683970 +#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3 0xd0683974 +#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL 0xd0683978 +#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL 0xd068397c +#define cfgBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX 0xd0683980 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFDEC2 +// base address: 0xd0680000 +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO 0xd06c2000 +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI 0xd06c2004 +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA 0xd06c2008 +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL 0xd06c200c +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO 0xd06c2010 +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI 0xd06c2014 +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA 0xd06c2018 +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL 0xd06c201c +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO 0xd06c2020 +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI 0xd06c2024 +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA 0xd06c2028 +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL 0xd06c202c +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO 0xd06c2030 +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI 0xd06c2034 +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA 0xd06c2038 +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL 0xd06c203c +#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_PBA 0xd06c3000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_SYSPFVFDEC +// base address: 0xd0700000 +#define cfgBIF_BX_DEV0_EPF0_VF14_MM_INDEX 0xd0700000 +#define cfgBIF_BX_DEV0_EPF0_VF14_MM_DATA 0xd0700004 +#define cfgBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI 0xd0700018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFPFVFDEC1 +// base address: 0xd0700000 +#define cfgRCC_DEV0_EPF0_VF14_RCC_ERR_LOG 0xd0703694 +#define cfgRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN 0xd0703780 +#define cfgRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE 0xd070378c +#define cfgRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED 0xd0703790 +#define cfgRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER 0xd0703794 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1 +// base address: 0xd0700000 +#define cfgBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS 0xd070382c +#define cfgBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG 0xd0703830 +#define cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd070384c +#define cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0703850 +#define cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0703854 +#define cfgBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0703858 +#define cfgBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd070385c +#define cfgBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ 0xd0703898 +#define cfgBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE 0xd070389c +#define cfgBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING 0xd07038a0 +#define cfgBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS 0xd07038c8 +#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0 0xd0703958 +#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1 0xd070395c +#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2 0xd0703960 +#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3 0xd0703964 +#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0 0xd0703968 +#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1 0xd070396c +#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2 0xd0703970 +#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3 0xd0703974 +#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL 0xd0703978 +#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL 0xd070397c +#define cfgBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX 0xd0703980 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFDEC2 +// base address: 0xd0700000 +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO 0xd0742000 +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI 0xd0742004 +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA 0xd0742008 +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL 0xd074200c +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO 0xd0742010 +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI 0xd0742014 +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA 0xd0742018 +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL 0xd074201c +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO 0xd0742020 +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI 0xd0742024 +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA 0xd0742028 +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL 0xd074202c +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO 0xd0742030 +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI 0xd0742034 +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA 0xd0742038 +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL 0xd074203c +#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_PBA 0xd0743000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_SYSPFVFDEC +// base address: 0xd0780000 +#define cfgBIF_BX_DEV0_EPF0_VF15_MM_INDEX 0xd0780000 +#define cfgBIF_BX_DEV0_EPF0_VF15_MM_DATA 0xd0780004 +#define cfgBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI 0xd0780018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFPFVFDEC1 +// base address: 0xd0780000 +#define cfgRCC_DEV0_EPF0_VF15_RCC_ERR_LOG 0xd0783694 +#define cfgRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN 0xd0783780 +#define cfgRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE 0xd078378c +#define cfgRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED 0xd0783790 +#define cfgRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER 0xd0783794 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1 +// base address: 0xd0780000 +#define cfgBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS 0xd078382c +#define cfgBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG 0xd0783830 +#define cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd078384c +#define cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0783850 +#define cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0783854 +#define cfgBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0783858 +#define cfgBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd078385c +#define cfgBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ 0xd0783898 +#define cfgBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE 0xd078389c +#define cfgBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING 0xd07838a0 +#define cfgBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS 0xd07838c8 +#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0 0xd0783958 +#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1 0xd078395c +#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2 0xd0783960 +#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3 0xd0783964 +#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0 0xd0783968 +#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1 0xd078396c +#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2 0xd0783970 +#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3 0xd0783974 +#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL 0xd0783978 +#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL 0xd078397c +#define cfgBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX 0xd0783980 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFDEC2 +// base address: 0xd0780000 +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO 0xd07c2000 +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI 0xd07c2004 +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA 0xd07c2008 +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL 0xd07c200c +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO 0xd07c2010 +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI 0xd07c2014 +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA 0xd07c2018 +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL 0xd07c201c +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO 0xd07c2020 +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI 0xd07c2024 +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA 0xd07c2028 +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL 0xd07c202c +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO 0xd07c2030 +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI 0xd07c2034 +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA 0xd07c2038 +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL 0xd07c203c +#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_PBA 0xd07c3000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf16_SYSPFVFDEC +// base address: 0xd0800000 +#define cfgBIF_BX_DEV0_EPF0_VF16_MM_INDEX 0xd0800000 +#define cfgBIF_BX_DEV0_EPF0_VF16_MM_DATA 0xd0800004 +#define cfgBIF_BX_DEV0_EPF0_VF16_MM_INDEX_HI 0xd0800018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf16_BIFPFVFDEC1 +// base address: 0xd0800000 +#define cfgRCC_DEV0_EPF0_VF16_RCC_ERR_LOG 0xd0803694 +#define cfgRCC_DEV0_EPF0_VF16_RCC_DOORBELL_APER_EN 0xd0803780 +#define cfgRCC_DEV0_EPF0_VF16_RCC_CONFIG_MEMSIZE 0xd080378c +#define cfgRCC_DEV0_EPF0_VF16_RCC_CONFIG_RESERVED 0xd0803790 +#define cfgRCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER 0xd0803794 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf16_BIFPFVFDEC1 +// base address: 0xd0800000 +#define cfgBIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS 0xd080382c +#define cfgBIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG 0xd0803830 +#define cfgBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd080384c +#define cfgBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0803850 +#define cfgBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0803854 +#define cfgBIF_BX_DEV0_EPF0_VF16_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0803858 +#define cfgBIF_BX_DEV0_EPF0_VF16_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd080385c +#define cfgBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ 0xd0803898 +#define cfgBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE 0xd080389c +#define cfgBIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING 0xd08038a0 +#define cfgBIF_BX_DEV0_EPF0_VF16_NBIF_GFX_ADDR_LUT_BYPASS 0xd08038c8 +#define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW0 0xd0803958 +#define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW1 0xd080395c +#define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW2 0xd0803960 +#define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW3 0xd0803964 +#define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW0 0xd0803968 +#define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW1 0xd080396c +#define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW2 0xd0803970 +#define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW3 0xd0803974 +#define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL 0xd0803978 +#define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL 0xd080397c +#define cfgBIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX 0xd0803980 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf16_BIFDEC2 +// base address: 0xd0800000 +#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_LO 0xd0842000 +#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_HI 0xd0842004 +#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_MSG_DATA 0xd0842008 +#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_CONTROL 0xd084200c +#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_LO 0xd0842010 +#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_HI 0xd0842014 +#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_MSG_DATA 0xd0842018 +#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_CONTROL 0xd084201c +#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_LO 0xd0842020 +#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_HI 0xd0842024 +#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_MSG_DATA 0xd0842028 +#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_CONTROL 0xd084202c +#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_LO 0xd0842030 +#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_HI 0xd0842034 +#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_MSG_DATA 0xd0842038 +#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_CONTROL 0xd084203c +#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_PBA 0xd0843000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf17_SYSPFVFDEC +// base address: 0xd0880000 +#define cfgBIF_BX_DEV0_EPF0_VF17_MM_INDEX 0xd0880000 +#define cfgBIF_BX_DEV0_EPF0_VF17_MM_DATA 0xd0880004 +#define cfgBIF_BX_DEV0_EPF0_VF17_MM_INDEX_HI 0xd0880018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf17_BIFPFVFDEC1 +// base address: 0xd0880000 +#define cfgRCC_DEV0_EPF0_VF17_RCC_ERR_LOG 0xd0883694 +#define cfgRCC_DEV0_EPF0_VF17_RCC_DOORBELL_APER_EN 0xd0883780 +#define cfgRCC_DEV0_EPF0_VF17_RCC_CONFIG_MEMSIZE 0xd088378c +#define cfgRCC_DEV0_EPF0_VF17_RCC_CONFIG_RESERVED 0xd0883790 +#define cfgRCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER 0xd0883794 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf17_BIFPFVFDEC1 +// base address: 0xd0880000 +#define cfgBIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS 0xd088382c +#define cfgBIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG 0xd0883830 +#define cfgBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd088384c +#define cfgBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0883850 +#define cfgBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0883854 +#define cfgBIF_BX_DEV0_EPF0_VF17_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0883858 +#define cfgBIF_BX_DEV0_EPF0_VF17_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd088385c +#define cfgBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ 0xd0883898 +#define cfgBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE 0xd088389c +#define cfgBIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING 0xd08838a0 +#define cfgBIF_BX_DEV0_EPF0_VF17_NBIF_GFX_ADDR_LUT_BYPASS 0xd08838c8 +#define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW0 0xd0883958 +#define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW1 0xd088395c +#define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW2 0xd0883960 +#define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW3 0xd0883964 +#define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW0 0xd0883968 +#define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW1 0xd088396c +#define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW2 0xd0883970 +#define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW3 0xd0883974 +#define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL 0xd0883978 +#define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL 0xd088397c +#define cfgBIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX 0xd0883980 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf17_BIFDEC2 +// base address: 0xd0880000 +#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_LO 0xd08c2000 +#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_HI 0xd08c2004 +#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_MSG_DATA 0xd08c2008 +#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_CONTROL 0xd08c200c +#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_LO 0xd08c2010 +#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_HI 0xd08c2014 +#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_MSG_DATA 0xd08c2018 +#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_CONTROL 0xd08c201c +#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_LO 0xd08c2020 +#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_HI 0xd08c2024 +#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_MSG_DATA 0xd08c2028 +#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_CONTROL 0xd08c202c +#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_LO 0xd08c2030 +#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_HI 0xd08c2034 +#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_MSG_DATA 0xd08c2038 +#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_CONTROL 0xd08c203c +#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_PBA 0xd08c3000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf18_SYSPFVFDEC +// base address: 0xd0900000 +#define cfgBIF_BX_DEV0_EPF0_VF18_MM_INDEX 0xd0900000 +#define cfgBIF_BX_DEV0_EPF0_VF18_MM_DATA 0xd0900004 +#define cfgBIF_BX_DEV0_EPF0_VF18_MM_INDEX_HI 0xd0900018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf18_BIFPFVFDEC1 +// base address: 0xd0900000 +#define cfgRCC_DEV0_EPF0_VF18_RCC_ERR_LOG 0xd0903694 +#define cfgRCC_DEV0_EPF0_VF18_RCC_DOORBELL_APER_EN 0xd0903780 +#define cfgRCC_DEV0_EPF0_VF18_RCC_CONFIG_MEMSIZE 0xd090378c +#define cfgRCC_DEV0_EPF0_VF18_RCC_CONFIG_RESERVED 0xd0903790 +#define cfgRCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER 0xd0903794 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf18_BIFPFVFDEC1 +// base address: 0xd0900000 +#define cfgBIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS 0xd090382c +#define cfgBIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG 0xd0903830 +#define cfgBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd090384c +#define cfgBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0903850 +#define cfgBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0903854 +#define cfgBIF_BX_DEV0_EPF0_VF18_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0903858 +#define cfgBIF_BX_DEV0_EPF0_VF18_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd090385c +#define cfgBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ 0xd0903898 +#define cfgBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE 0xd090389c +#define cfgBIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING 0xd09038a0 +#define cfgBIF_BX_DEV0_EPF0_VF18_NBIF_GFX_ADDR_LUT_BYPASS 0xd09038c8 +#define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW0 0xd0903958 +#define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW1 0xd090395c +#define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW2 0xd0903960 +#define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW3 0xd0903964 +#define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW0 0xd0903968 +#define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW1 0xd090396c +#define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW2 0xd0903970 +#define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW3 0xd0903974 +#define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL 0xd0903978 +#define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL 0xd090397c +#define cfgBIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX 0xd0903980 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf18_BIFDEC2 +// base address: 0xd0900000 +#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_LO 0xd0942000 +#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_HI 0xd0942004 +#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_MSG_DATA 0xd0942008 +#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_CONTROL 0xd094200c +#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_LO 0xd0942010 +#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_HI 0xd0942014 +#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_MSG_DATA 0xd0942018 +#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_CONTROL 0xd094201c +#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_LO 0xd0942020 +#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_HI 0xd0942024 +#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_MSG_DATA 0xd0942028 +#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_CONTROL 0xd094202c +#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_LO 0xd0942030 +#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_HI 0xd0942034 +#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_MSG_DATA 0xd0942038 +#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_CONTROL 0xd094203c +#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_PBA 0xd0943000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf19_SYSPFVFDEC +// base address: 0xd0980000 +#define cfgBIF_BX_DEV0_EPF0_VF19_MM_INDEX 0xd0980000 +#define cfgBIF_BX_DEV0_EPF0_VF19_MM_DATA 0xd0980004 +#define cfgBIF_BX_DEV0_EPF0_VF19_MM_INDEX_HI 0xd0980018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf19_BIFPFVFDEC1 +// base address: 0xd0980000 +#define cfgRCC_DEV0_EPF0_VF19_RCC_ERR_LOG 0xd0983694 +#define cfgRCC_DEV0_EPF0_VF19_RCC_DOORBELL_APER_EN 0xd0983780 +#define cfgRCC_DEV0_EPF0_VF19_RCC_CONFIG_MEMSIZE 0xd098378c +#define cfgRCC_DEV0_EPF0_VF19_RCC_CONFIG_RESERVED 0xd0983790 +#define cfgRCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER 0xd0983794 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf19_BIFPFVFDEC1 +// base address: 0xd0980000 +#define cfgBIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS 0xd098382c +#define cfgBIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG 0xd0983830 +#define cfgBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd098384c +#define cfgBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0983850 +#define cfgBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0983854 +#define cfgBIF_BX_DEV0_EPF0_VF19_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0983858 +#define cfgBIF_BX_DEV0_EPF0_VF19_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd098385c +#define cfgBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ 0xd0983898 +#define cfgBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE 0xd098389c +#define cfgBIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING 0xd09838a0 +#define cfgBIF_BX_DEV0_EPF0_VF19_NBIF_GFX_ADDR_LUT_BYPASS 0xd09838c8 +#define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW0 0xd0983958 +#define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW1 0xd098395c +#define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW2 0xd0983960 +#define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW3 0xd0983964 +#define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW0 0xd0983968 +#define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW1 0xd098396c +#define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW2 0xd0983970 +#define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW3 0xd0983974 +#define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL 0xd0983978 +#define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL 0xd098397c +#define cfgBIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX 0xd0983980 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf19_BIFDEC2 +// base address: 0xd0980000 +#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_LO 0xd09c2000 +#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_HI 0xd09c2004 +#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_MSG_DATA 0xd09c2008 +#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_CONTROL 0xd09c200c +#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_LO 0xd09c2010 +#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_HI 0xd09c2014 +#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_MSG_DATA 0xd09c2018 +#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_CONTROL 0xd09c201c +#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_LO 0xd09c2020 +#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_HI 0xd09c2024 +#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_MSG_DATA 0xd09c2028 +#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_CONTROL 0xd09c202c +#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_LO 0xd09c2030 +#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_HI 0xd09c2034 +#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_MSG_DATA 0xd09c2038 +#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_CONTROL 0xd09c203c +#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_PBA 0xd09c3000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf20_SYSPFVFDEC +// base address: 0xd0a00000 +#define cfgBIF_BX_DEV0_EPF0_VF20_MM_INDEX 0xd0a00000 +#define cfgBIF_BX_DEV0_EPF0_VF20_MM_DATA 0xd0a00004 +#define cfgBIF_BX_DEV0_EPF0_VF20_MM_INDEX_HI 0xd0a00018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf20_BIFPFVFDEC1 +// base address: 0xd0a00000 +#define cfgRCC_DEV0_EPF0_VF20_RCC_ERR_LOG 0xd0a03694 +#define cfgRCC_DEV0_EPF0_VF20_RCC_DOORBELL_APER_EN 0xd0a03780 +#define cfgRCC_DEV0_EPF0_VF20_RCC_CONFIG_MEMSIZE 0xd0a0378c +#define cfgRCC_DEV0_EPF0_VF20_RCC_CONFIG_RESERVED 0xd0a03790 +#define cfgRCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER 0xd0a03794 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf20_BIFPFVFDEC1 +// base address: 0xd0a00000 +#define cfgBIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS 0xd0a0382c +#define cfgBIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG 0xd0a03830 +#define cfgBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0a0384c +#define cfgBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0a03850 +#define cfgBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0a03854 +#define cfgBIF_BX_DEV0_EPF0_VF20_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0a03858 +#define cfgBIF_BX_DEV0_EPF0_VF20_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0a0385c +#define cfgBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ 0xd0a03898 +#define cfgBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE 0xd0a0389c +#define cfgBIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING 0xd0a038a0 +#define cfgBIF_BX_DEV0_EPF0_VF20_NBIF_GFX_ADDR_LUT_BYPASS 0xd0a038c8 +#define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW0 0xd0a03958 +#define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW1 0xd0a0395c +#define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW2 0xd0a03960 +#define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW3 0xd0a03964 +#define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW0 0xd0a03968 +#define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW1 0xd0a0396c +#define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW2 0xd0a03970 +#define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW3 0xd0a03974 +#define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL 0xd0a03978 +#define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL 0xd0a0397c +#define cfgBIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX 0xd0a03980 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf20_BIFDEC2 +// base address: 0xd0a00000 +#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_LO 0xd0a42000 +#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_HI 0xd0a42004 +#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_MSG_DATA 0xd0a42008 +#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_CONTROL 0xd0a4200c +#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_LO 0xd0a42010 +#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_HI 0xd0a42014 +#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_MSG_DATA 0xd0a42018 +#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_CONTROL 0xd0a4201c +#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_LO 0xd0a42020 +#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_HI 0xd0a42024 +#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_MSG_DATA 0xd0a42028 +#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_CONTROL 0xd0a4202c +#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_LO 0xd0a42030 +#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_HI 0xd0a42034 +#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_MSG_DATA 0xd0a42038 +#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_CONTROL 0xd0a4203c +#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_PBA 0xd0a43000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf21_SYSPFVFDEC +// base address: 0xd0a80000 +#define cfgBIF_BX_DEV0_EPF0_VF21_MM_INDEX 0xd0a80000 +#define cfgBIF_BX_DEV0_EPF0_VF21_MM_DATA 0xd0a80004 +#define cfgBIF_BX_DEV0_EPF0_VF21_MM_INDEX_HI 0xd0a80018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf21_BIFPFVFDEC1 +// base address: 0xd0a80000 +#define cfgRCC_DEV0_EPF0_VF21_RCC_ERR_LOG 0xd0a83694 +#define cfgRCC_DEV0_EPF0_VF21_RCC_DOORBELL_APER_EN 0xd0a83780 +#define cfgRCC_DEV0_EPF0_VF21_RCC_CONFIG_MEMSIZE 0xd0a8378c +#define cfgRCC_DEV0_EPF0_VF21_RCC_CONFIG_RESERVED 0xd0a83790 +#define cfgRCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER 0xd0a83794 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf21_BIFPFVFDEC1 +// base address: 0xd0a80000 +#define cfgBIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS 0xd0a8382c +#define cfgBIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG 0xd0a83830 +#define cfgBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0a8384c +#define cfgBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0a83850 +#define cfgBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0a83854 +#define cfgBIF_BX_DEV0_EPF0_VF21_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0a83858 +#define cfgBIF_BX_DEV0_EPF0_VF21_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0a8385c +#define cfgBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ 0xd0a83898 +#define cfgBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE 0xd0a8389c +#define cfgBIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING 0xd0a838a0 +#define cfgBIF_BX_DEV0_EPF0_VF21_NBIF_GFX_ADDR_LUT_BYPASS 0xd0a838c8 +#define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW0 0xd0a83958 +#define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW1 0xd0a8395c +#define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW2 0xd0a83960 +#define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW3 0xd0a83964 +#define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW0 0xd0a83968 +#define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW1 0xd0a8396c +#define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW2 0xd0a83970 +#define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW3 0xd0a83974 +#define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL 0xd0a83978 +#define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL 0xd0a8397c +#define cfgBIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX 0xd0a83980 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf21_BIFDEC2 +// base address: 0xd0a80000 +#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_LO 0xd0ac2000 +#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_HI 0xd0ac2004 +#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_MSG_DATA 0xd0ac2008 +#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_CONTROL 0xd0ac200c +#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_LO 0xd0ac2010 +#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_HI 0xd0ac2014 +#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_MSG_DATA 0xd0ac2018 +#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_CONTROL 0xd0ac201c +#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_LO 0xd0ac2020 +#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_HI 0xd0ac2024 +#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_MSG_DATA 0xd0ac2028 +#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_CONTROL 0xd0ac202c +#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_LO 0xd0ac2030 +#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_HI 0xd0ac2034 +#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_MSG_DATA 0xd0ac2038 +#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_CONTROL 0xd0ac203c +#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_PBA 0xd0ac3000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf22_SYSPFVFDEC +// base address: 0xd0b00000 +#define cfgBIF_BX_DEV0_EPF0_VF22_MM_INDEX 0xd0b00000 +#define cfgBIF_BX_DEV0_EPF0_VF22_MM_DATA 0xd0b00004 +#define cfgBIF_BX_DEV0_EPF0_VF22_MM_INDEX_HI 0xd0b00018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf22_BIFPFVFDEC1 +// base address: 0xd0b00000 +#define cfgRCC_DEV0_EPF0_VF22_RCC_ERR_LOG 0xd0b03694 +#define cfgRCC_DEV0_EPF0_VF22_RCC_DOORBELL_APER_EN 0xd0b03780 +#define cfgRCC_DEV0_EPF0_VF22_RCC_CONFIG_MEMSIZE 0xd0b0378c +#define cfgRCC_DEV0_EPF0_VF22_RCC_CONFIG_RESERVED 0xd0b03790 +#define cfgRCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER 0xd0b03794 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf22_BIFPFVFDEC1 +// base address: 0xd0b00000 +#define cfgBIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS 0xd0b0382c +#define cfgBIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG 0xd0b03830 +#define cfgBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0b0384c +#define cfgBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0b03850 +#define cfgBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0b03854 +#define cfgBIF_BX_DEV0_EPF0_VF22_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0b03858 +#define cfgBIF_BX_DEV0_EPF0_VF22_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0b0385c +#define cfgBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ 0xd0b03898 +#define cfgBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE 0xd0b0389c +#define cfgBIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING 0xd0b038a0 +#define cfgBIF_BX_DEV0_EPF0_VF22_NBIF_GFX_ADDR_LUT_BYPASS 0xd0b038c8 +#define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW0 0xd0b03958 +#define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW1 0xd0b0395c +#define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW2 0xd0b03960 +#define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW3 0xd0b03964 +#define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW0 0xd0b03968 +#define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW1 0xd0b0396c +#define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW2 0xd0b03970 +#define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW3 0xd0b03974 +#define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL 0xd0b03978 +#define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL 0xd0b0397c +#define cfgBIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX 0xd0b03980 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf22_BIFDEC2 +// base address: 0xd0b00000 +#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_LO 0xd0b42000 +#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_HI 0xd0b42004 +#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_MSG_DATA 0xd0b42008 +#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_CONTROL 0xd0b4200c +#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_LO 0xd0b42010 +#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_HI 0xd0b42014 +#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_MSG_DATA 0xd0b42018 +#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_CONTROL 0xd0b4201c +#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_LO 0xd0b42020 +#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_HI 0xd0b42024 +#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_MSG_DATA 0xd0b42028 +#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_CONTROL 0xd0b4202c +#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_LO 0xd0b42030 +#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_HI 0xd0b42034 +#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_MSG_DATA 0xd0b42038 +#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_CONTROL 0xd0b4203c +#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_PBA 0xd0b43000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf23_SYSPFVFDEC +// base address: 0xd0b80000 +#define cfgBIF_BX_DEV0_EPF0_VF23_MM_INDEX 0xd0b80000 +#define cfgBIF_BX_DEV0_EPF0_VF23_MM_DATA 0xd0b80004 +#define cfgBIF_BX_DEV0_EPF0_VF23_MM_INDEX_HI 0xd0b80018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf23_BIFPFVFDEC1 +// base address: 0xd0b80000 +#define cfgRCC_DEV0_EPF0_VF23_RCC_ERR_LOG 0xd0b83694 +#define cfgRCC_DEV0_EPF0_VF23_RCC_DOORBELL_APER_EN 0xd0b83780 +#define cfgRCC_DEV0_EPF0_VF23_RCC_CONFIG_MEMSIZE 0xd0b8378c +#define cfgRCC_DEV0_EPF0_VF23_RCC_CONFIG_RESERVED 0xd0b83790 +#define cfgRCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER 0xd0b83794 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf23_BIFPFVFDEC1 +// base address: 0xd0b80000 +#define cfgBIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS 0xd0b8382c +#define cfgBIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG 0xd0b83830 +#define cfgBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0b8384c +#define cfgBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0b83850 +#define cfgBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0b83854 +#define cfgBIF_BX_DEV0_EPF0_VF23_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0b83858 +#define cfgBIF_BX_DEV0_EPF0_VF23_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0b8385c +#define cfgBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ 0xd0b83898 +#define cfgBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE 0xd0b8389c +#define cfgBIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING 0xd0b838a0 +#define cfgBIF_BX_DEV0_EPF0_VF23_NBIF_GFX_ADDR_LUT_BYPASS 0xd0b838c8 +#define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW0 0xd0b83958 +#define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW1 0xd0b8395c +#define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW2 0xd0b83960 +#define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW3 0xd0b83964 +#define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW0 0xd0b83968 +#define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW1 0xd0b8396c +#define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW2 0xd0b83970 +#define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW3 0xd0b83974 +#define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL 0xd0b83978 +#define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL 0xd0b8397c +#define cfgBIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX 0xd0b83980 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf23_BIFDEC2 +// base address: 0xd0b80000 +#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_LO 0xd0bc2000 +#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_HI 0xd0bc2004 +#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_MSG_DATA 0xd0bc2008 +#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_CONTROL 0xd0bc200c +#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_LO 0xd0bc2010 +#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_HI 0xd0bc2014 +#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_MSG_DATA 0xd0bc2018 +#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_CONTROL 0xd0bc201c +#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_LO 0xd0bc2020 +#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_HI 0xd0bc2024 +#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_MSG_DATA 0xd0bc2028 +#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_CONTROL 0xd0bc202c +#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_LO 0xd0bc2030 +#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_HI 0xd0bc2034 +#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_MSG_DATA 0xd0bc2038 +#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_CONTROL 0xd0bc203c +#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_PBA 0xd0bc3000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf24_SYSPFVFDEC +// base address: 0xd0c00000 +#define cfgBIF_BX_DEV0_EPF0_VF24_MM_INDEX 0xd0c00000 +#define cfgBIF_BX_DEV0_EPF0_VF24_MM_DATA 0xd0c00004 +#define cfgBIF_BX_DEV0_EPF0_VF24_MM_INDEX_HI 0xd0c00018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf24_BIFPFVFDEC1 +// base address: 0xd0c00000 +#define cfgRCC_DEV0_EPF0_VF24_RCC_ERR_LOG 0xd0c03694 +#define cfgRCC_DEV0_EPF0_VF24_RCC_DOORBELL_APER_EN 0xd0c03780 +#define cfgRCC_DEV0_EPF0_VF24_RCC_CONFIG_MEMSIZE 0xd0c0378c +#define cfgRCC_DEV0_EPF0_VF24_RCC_CONFIG_RESERVED 0xd0c03790 +#define cfgRCC_DEV0_EPF0_VF24_RCC_IOV_FUNC_IDENTIFIER 0xd0c03794 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf24_BIFPFVFDEC1 +// base address: 0xd0c00000 +#define cfgBIF_BX_DEV0_EPF0_VF24_BIF_BME_STATUS 0xd0c0382c +#define cfgBIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG 0xd0c03830 +#define cfgBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0c0384c +#define cfgBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0c03850 +#define cfgBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0c03854 +#define cfgBIF_BX_DEV0_EPF0_VF24_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0c03858 +#define cfgBIF_BX_DEV0_EPF0_VF24_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0c0385c +#define cfgBIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ 0xd0c03898 +#define cfgBIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE 0xd0c0389c +#define cfgBIF_BX_DEV0_EPF0_VF24_BIF_TRANS_PENDING 0xd0c038a0 +#define cfgBIF_BX_DEV0_EPF0_VF24_NBIF_GFX_ADDR_LUT_BYPASS 0xd0c038c8 +#define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW0 0xd0c03958 +#define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW1 0xd0c0395c +#define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW2 0xd0c03960 +#define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW3 0xd0c03964 +#define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW0 0xd0c03968 +#define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW1 0xd0c0396c +#define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW2 0xd0c03970 +#define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW3 0xd0c03974 +#define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL 0xd0c03978 +#define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_INT_CNTL 0xd0c0397c +#define cfgBIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX 0xd0c03980 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf24_BIFDEC2 +// base address: 0xd0c00000 +#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_LO 0xd0c42000 +#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_HI 0xd0c42004 +#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_MSG_DATA 0xd0c42008 +#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_CONTROL 0xd0c4200c +#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_LO 0xd0c42010 +#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_HI 0xd0c42014 +#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_MSG_DATA 0xd0c42018 +#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_CONTROL 0xd0c4201c +#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_LO 0xd0c42020 +#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_HI 0xd0c42024 +#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_MSG_DATA 0xd0c42028 +#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_CONTROL 0xd0c4202c +#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_LO 0xd0c42030 +#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_HI 0xd0c42034 +#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_MSG_DATA 0xd0c42038 +#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_CONTROL 0xd0c4203c +#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_PBA 0xd0c43000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf25_SYSPFVFDEC +// base address: 0xd0c80000 +#define cfgBIF_BX_DEV0_EPF0_VF25_MM_INDEX 0xd0c80000 +#define cfgBIF_BX_DEV0_EPF0_VF25_MM_DATA 0xd0c80004 +#define cfgBIF_BX_DEV0_EPF0_VF25_MM_INDEX_HI 0xd0c80018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf25_BIFPFVFDEC1 +// base address: 0xd0c80000 +#define cfgRCC_DEV0_EPF0_VF25_RCC_ERR_LOG 0xd0c83694 +#define cfgRCC_DEV0_EPF0_VF25_RCC_DOORBELL_APER_EN 0xd0c83780 +#define cfgRCC_DEV0_EPF0_VF25_RCC_CONFIG_MEMSIZE 0xd0c8378c +#define cfgRCC_DEV0_EPF0_VF25_RCC_CONFIG_RESERVED 0xd0c83790 +#define cfgRCC_DEV0_EPF0_VF25_RCC_IOV_FUNC_IDENTIFIER 0xd0c83794 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf25_BIFPFVFDEC1 +// base address: 0xd0c80000 +#define cfgBIF_BX_DEV0_EPF0_VF25_BIF_BME_STATUS 0xd0c8382c +#define cfgBIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG 0xd0c83830 +#define cfgBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0c8384c +#define cfgBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0c83850 +#define cfgBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0c83854 +#define cfgBIF_BX_DEV0_EPF0_VF25_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0c83858 +#define cfgBIF_BX_DEV0_EPF0_VF25_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0c8385c +#define cfgBIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ 0xd0c83898 +#define cfgBIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE 0xd0c8389c +#define cfgBIF_BX_DEV0_EPF0_VF25_BIF_TRANS_PENDING 0xd0c838a0 +#define cfgBIF_BX_DEV0_EPF0_VF25_NBIF_GFX_ADDR_LUT_BYPASS 0xd0c838c8 +#define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW0 0xd0c83958 +#define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW1 0xd0c8395c +#define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW2 0xd0c83960 +#define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW3 0xd0c83964 +#define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW0 0xd0c83968 +#define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW1 0xd0c8396c +#define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW2 0xd0c83970 +#define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW3 0xd0c83974 +#define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL 0xd0c83978 +#define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_INT_CNTL 0xd0c8397c +#define cfgBIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX 0xd0c83980 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf25_BIFDEC2 +// base address: 0xd0c80000 +#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_LO 0xd0cc2000 +#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_HI 0xd0cc2004 +#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_MSG_DATA 0xd0cc2008 +#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_CONTROL 0xd0cc200c +#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_LO 0xd0cc2010 +#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_HI 0xd0cc2014 +#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_MSG_DATA 0xd0cc2018 +#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_CONTROL 0xd0cc201c +#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_LO 0xd0cc2020 +#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_HI 0xd0cc2024 +#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_MSG_DATA 0xd0cc2028 +#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_CONTROL 0xd0cc202c +#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_LO 0xd0cc2030 +#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_HI 0xd0cc2034 +#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_MSG_DATA 0xd0cc2038 +#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_CONTROL 0xd0cc203c +#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_PBA 0xd0cc3000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf26_SYSPFVFDEC +// base address: 0xd0d00000 +#define cfgBIF_BX_DEV0_EPF0_VF26_MM_INDEX 0xd0d00000 +#define cfgBIF_BX_DEV0_EPF0_VF26_MM_DATA 0xd0d00004 +#define cfgBIF_BX_DEV0_EPF0_VF26_MM_INDEX_HI 0xd0d00018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf26_BIFPFVFDEC1 +// base address: 0xd0d00000 +#define cfgRCC_DEV0_EPF0_VF26_RCC_ERR_LOG 0xd0d03694 +#define cfgRCC_DEV0_EPF0_VF26_RCC_DOORBELL_APER_EN 0xd0d03780 +#define cfgRCC_DEV0_EPF0_VF26_RCC_CONFIG_MEMSIZE 0xd0d0378c +#define cfgRCC_DEV0_EPF0_VF26_RCC_CONFIG_RESERVED 0xd0d03790 +#define cfgRCC_DEV0_EPF0_VF26_RCC_IOV_FUNC_IDENTIFIER 0xd0d03794 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf26_BIFPFVFDEC1 +// base address: 0xd0d00000 +#define cfgBIF_BX_DEV0_EPF0_VF26_BIF_BME_STATUS 0xd0d0382c +#define cfgBIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG 0xd0d03830 +#define cfgBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0d0384c +#define cfgBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0d03850 +#define cfgBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0d03854 +#define cfgBIF_BX_DEV0_EPF0_VF26_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0d03858 +#define cfgBIF_BX_DEV0_EPF0_VF26_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0d0385c +#define cfgBIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ 0xd0d03898 +#define cfgBIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE 0xd0d0389c +#define cfgBIF_BX_DEV0_EPF0_VF26_BIF_TRANS_PENDING 0xd0d038a0 +#define cfgBIF_BX_DEV0_EPF0_VF26_NBIF_GFX_ADDR_LUT_BYPASS 0xd0d038c8 +#define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW0 0xd0d03958 +#define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW1 0xd0d0395c +#define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW2 0xd0d03960 +#define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW3 0xd0d03964 +#define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW0 0xd0d03968 +#define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW1 0xd0d0396c +#define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW2 0xd0d03970 +#define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW3 0xd0d03974 +#define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL 0xd0d03978 +#define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_INT_CNTL 0xd0d0397c +#define cfgBIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX 0xd0d03980 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf26_BIFDEC2 +// base address: 0xd0d00000 +#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_LO 0xd0d42000 +#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_HI 0xd0d42004 +#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_MSG_DATA 0xd0d42008 +#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_CONTROL 0xd0d4200c +#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_LO 0xd0d42010 +#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_HI 0xd0d42014 +#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_MSG_DATA 0xd0d42018 +#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_CONTROL 0xd0d4201c +#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_LO 0xd0d42020 +#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_HI 0xd0d42024 +#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_MSG_DATA 0xd0d42028 +#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_CONTROL 0xd0d4202c +#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_LO 0xd0d42030 +#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_HI 0xd0d42034 +#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_MSG_DATA 0xd0d42038 +#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_CONTROL 0xd0d4203c +#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_PBA 0xd0d43000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf27_SYSPFVFDEC +// base address: 0xd0d80000 +#define cfgBIF_BX_DEV0_EPF0_VF27_MM_INDEX 0xd0d80000 +#define cfgBIF_BX_DEV0_EPF0_VF27_MM_DATA 0xd0d80004 +#define cfgBIF_BX_DEV0_EPF0_VF27_MM_INDEX_HI 0xd0d80018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf27_BIFPFVFDEC1 +// base address: 0xd0d80000 +#define cfgRCC_DEV0_EPF0_VF27_RCC_ERR_LOG 0xd0d83694 +#define cfgRCC_DEV0_EPF0_VF27_RCC_DOORBELL_APER_EN 0xd0d83780 +#define cfgRCC_DEV0_EPF0_VF27_RCC_CONFIG_MEMSIZE 0xd0d8378c +#define cfgRCC_DEV0_EPF0_VF27_RCC_CONFIG_RESERVED 0xd0d83790 +#define cfgRCC_DEV0_EPF0_VF27_RCC_IOV_FUNC_IDENTIFIER 0xd0d83794 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf27_BIFPFVFDEC1 +// base address: 0xd0d80000 +#define cfgBIF_BX_DEV0_EPF0_VF27_BIF_BME_STATUS 0xd0d8382c +#define cfgBIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG 0xd0d83830 +#define cfgBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0d8384c +#define cfgBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0d83850 +#define cfgBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0d83854 +#define cfgBIF_BX_DEV0_EPF0_VF27_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0d83858 +#define cfgBIF_BX_DEV0_EPF0_VF27_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0d8385c +#define cfgBIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ 0xd0d83898 +#define cfgBIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE 0xd0d8389c +#define cfgBIF_BX_DEV0_EPF0_VF27_BIF_TRANS_PENDING 0xd0d838a0 +#define cfgBIF_BX_DEV0_EPF0_VF27_NBIF_GFX_ADDR_LUT_BYPASS 0xd0d838c8 +#define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW0 0xd0d83958 +#define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW1 0xd0d8395c +#define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW2 0xd0d83960 +#define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW3 0xd0d83964 +#define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW0 0xd0d83968 +#define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW1 0xd0d8396c +#define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW2 0xd0d83970 +#define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW3 0xd0d83974 +#define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL 0xd0d83978 +#define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_INT_CNTL 0xd0d8397c +#define cfgBIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX 0xd0d83980 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf27_BIFDEC2 +// base address: 0xd0d80000 +#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_LO 0xd0dc2000 +#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_HI 0xd0dc2004 +#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_MSG_DATA 0xd0dc2008 +#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_CONTROL 0xd0dc200c +#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_LO 0xd0dc2010 +#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_HI 0xd0dc2014 +#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_MSG_DATA 0xd0dc2018 +#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_CONTROL 0xd0dc201c +#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_LO 0xd0dc2020 +#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_HI 0xd0dc2024 +#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_MSG_DATA 0xd0dc2028 +#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_CONTROL 0xd0dc202c +#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_LO 0xd0dc2030 +#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_HI 0xd0dc2034 +#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_MSG_DATA 0xd0dc2038 +#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_CONTROL 0xd0dc203c +#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_PBA 0xd0dc3000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf28_SYSPFVFDEC +// base address: 0xd0e00000 +#define cfgBIF_BX_DEV0_EPF0_VF28_MM_INDEX 0xd0e00000 +#define cfgBIF_BX_DEV0_EPF0_VF28_MM_DATA 0xd0e00004 +#define cfgBIF_BX_DEV0_EPF0_VF28_MM_INDEX_HI 0xd0e00018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf28_BIFPFVFDEC1 +// base address: 0xd0e00000 +#define cfgRCC_DEV0_EPF0_VF28_RCC_ERR_LOG 0xd0e03694 +#define cfgRCC_DEV0_EPF0_VF28_RCC_DOORBELL_APER_EN 0xd0e03780 +#define cfgRCC_DEV0_EPF0_VF28_RCC_CONFIG_MEMSIZE 0xd0e0378c +#define cfgRCC_DEV0_EPF0_VF28_RCC_CONFIG_RESERVED 0xd0e03790 +#define cfgRCC_DEV0_EPF0_VF28_RCC_IOV_FUNC_IDENTIFIER 0xd0e03794 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf28_BIFPFVFDEC1 +// base address: 0xd0e00000 +#define cfgBIF_BX_DEV0_EPF0_VF28_BIF_BME_STATUS 0xd0e0382c +#define cfgBIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG 0xd0e03830 +#define cfgBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0e0384c +#define cfgBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0e03850 +#define cfgBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0e03854 +#define cfgBIF_BX_DEV0_EPF0_VF28_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0e03858 +#define cfgBIF_BX_DEV0_EPF0_VF28_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0e0385c +#define cfgBIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ 0xd0e03898 +#define cfgBIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE 0xd0e0389c +#define cfgBIF_BX_DEV0_EPF0_VF28_BIF_TRANS_PENDING 0xd0e038a0 +#define cfgBIF_BX_DEV0_EPF0_VF28_NBIF_GFX_ADDR_LUT_BYPASS 0xd0e038c8 +#define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW0 0xd0e03958 +#define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW1 0xd0e0395c +#define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW2 0xd0e03960 +#define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW3 0xd0e03964 +#define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW0 0xd0e03968 +#define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW1 0xd0e0396c +#define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW2 0xd0e03970 +#define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW3 0xd0e03974 +#define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL 0xd0e03978 +#define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_INT_CNTL 0xd0e0397c +#define cfgBIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX 0xd0e03980 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf28_BIFDEC2 +// base address: 0xd0e00000 +#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_LO 0xd0e42000 +#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_HI 0xd0e42004 +#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_MSG_DATA 0xd0e42008 +#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_CONTROL 0xd0e4200c +#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_LO 0xd0e42010 +#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_HI 0xd0e42014 +#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_MSG_DATA 0xd0e42018 +#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_CONTROL 0xd0e4201c +#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_LO 0xd0e42020 +#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_HI 0xd0e42024 +#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_MSG_DATA 0xd0e42028 +#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_CONTROL 0xd0e4202c +#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_LO 0xd0e42030 +#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_HI 0xd0e42034 +#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_MSG_DATA 0xd0e42038 +#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_CONTROL 0xd0e4203c +#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_PBA 0xd0e43000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf29_SYSPFVFDEC +// base address: 0xd0e80000 +#define cfgBIF_BX_DEV0_EPF0_VF29_MM_INDEX 0xd0e80000 +#define cfgBIF_BX_DEV0_EPF0_VF29_MM_DATA 0xd0e80004 +#define cfgBIF_BX_DEV0_EPF0_VF29_MM_INDEX_HI 0xd0e80018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf29_BIFPFVFDEC1 +// base address: 0xd0e80000 +#define cfgRCC_DEV0_EPF0_VF29_RCC_ERR_LOG 0xd0e83694 +#define cfgRCC_DEV0_EPF0_VF29_RCC_DOORBELL_APER_EN 0xd0e83780 +#define cfgRCC_DEV0_EPF0_VF29_RCC_CONFIG_MEMSIZE 0xd0e8378c +#define cfgRCC_DEV0_EPF0_VF29_RCC_CONFIG_RESERVED 0xd0e83790 +#define cfgRCC_DEV0_EPF0_VF29_RCC_IOV_FUNC_IDENTIFIER 0xd0e83794 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf29_BIFPFVFDEC1 +// base address: 0xd0e80000 +#define cfgBIF_BX_DEV0_EPF0_VF29_BIF_BME_STATUS 0xd0e8382c +#define cfgBIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG 0xd0e83830 +#define cfgBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0e8384c +#define cfgBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0e83850 +#define cfgBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0e83854 +#define cfgBIF_BX_DEV0_EPF0_VF29_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0e83858 +#define cfgBIF_BX_DEV0_EPF0_VF29_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0e8385c +#define cfgBIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ 0xd0e83898 +#define cfgBIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE 0xd0e8389c +#define cfgBIF_BX_DEV0_EPF0_VF29_BIF_TRANS_PENDING 0xd0e838a0 +#define cfgBIF_BX_DEV0_EPF0_VF29_NBIF_GFX_ADDR_LUT_BYPASS 0xd0e838c8 +#define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW0 0xd0e83958 +#define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW1 0xd0e8395c +#define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW2 0xd0e83960 +#define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW3 0xd0e83964 +#define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW0 0xd0e83968 +#define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW1 0xd0e8396c +#define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW2 0xd0e83970 +#define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW3 0xd0e83974 +#define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL 0xd0e83978 +#define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_INT_CNTL 0xd0e8397c +#define cfgBIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX 0xd0e83980 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf29_BIFDEC2 +// base address: 0xd0e80000 +#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_LO 0xd0ec2000 +#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_HI 0xd0ec2004 +#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_MSG_DATA 0xd0ec2008 +#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_CONTROL 0xd0ec200c +#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_LO 0xd0ec2010 +#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_HI 0xd0ec2014 +#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_MSG_DATA 0xd0ec2018 +#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_CONTROL 0xd0ec201c +#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_LO 0xd0ec2020 +#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_HI 0xd0ec2024 +#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_MSG_DATA 0xd0ec2028 +#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_CONTROL 0xd0ec202c +#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_LO 0xd0ec2030 +#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_HI 0xd0ec2034 +#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_MSG_DATA 0xd0ec2038 +#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_CONTROL 0xd0ec203c +#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_PBA 0xd0ec3000 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf30_SYSPFVFDEC +// base address: 0xd0f00000 +#define cfgBIF_BX_DEV0_EPF0_VF30_MM_INDEX 0xd0f00000 +#define cfgBIF_BX_DEV0_EPF0_VF30_MM_DATA 0xd0f00004 +#define cfgBIF_BX_DEV0_EPF0_VF30_MM_INDEX_HI 0xd0f00018 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf30_BIFPFVFDEC1 +// base address: 0xd0f00000 +#define cfgRCC_DEV0_EPF0_VF30_RCC_ERR_LOG 0xd0f03694 +#define cfgRCC_DEV0_EPF0_VF30_RCC_DOORBELL_APER_EN 0xd0f03780 +#define cfgRCC_DEV0_EPF0_VF30_RCC_CONFIG_MEMSIZE 0xd0f0378c +#define cfgRCC_DEV0_EPF0_VF30_RCC_CONFIG_RESERVED 0xd0f03790 +#define cfgRCC_DEV0_EPF0_VF30_RCC_IOV_FUNC_IDENTIFIER 0xd0f03794 + + +// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf30_BIFPFVFDEC1 +// base address: 0xd0f00000 +#define cfgBIF_BX_DEV0_EPF0_VF30_BIF_BME_STATUS 0xd0f0382c +#define cfgBIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG 0xd0f03830 +#define cfgBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0f0384c +#define cfgBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0f03850 +#define cfgBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0f03854 +#define cfgBIF_BX_DEV0_EPF0_VF30_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0f03858 +#define cfgBIF_BX_DEV0_EPF0_VF30_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0f0385c +#define cfgBIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ 0xd0f03898 +#define cfgBIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE 0xd0f0389c +#define cfgBIF_BX_DEV0_EPF0_VF30_BIF_TRANS_PENDING 0xd0f038a0 +#define cfgBIF_BX_DEV0_EPF0_VF30_NBIF_GFX_ADDR_LUT_BYPASS 0xd0f038c8 +#define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW0 0xd0f03958 +#define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW1 0xd0f0395c +#define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW2 0xd0f03960 +#define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW3 0xd0f03964 +#define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW0 0xd0f03968 +#define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW1 0xd0f0396c +#define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW2 0xd0f03970 +#define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW3 0xd0f03974 +#define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL 0xd0f03978 +#define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_INT_CNTL 0xd0f0397c +#define cfgBIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX 0xd0f03980 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf30_BIFDEC2 +// base address: 0xd0f00000 +#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_LO 0xd0f42000 +#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_HI 0xd0f42004 +#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_MSG_DATA 0xd0f42008 +#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_CONTROL 0xd0f4200c +#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_LO 0xd0f42010 +#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_HI 0xd0f42014 +#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_MSG_DATA 0xd0f42018 +#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_CONTROL 0xd0f4201c +#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_LO 0xd0f42020 +#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_HI 0xd0f42024 +#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_MSG_DATA 0xd0f42028 +#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_CONTROL 0xd0f4202c +#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_LO 0xd0f42030 +#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_HI 0xd0f42034 +#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_MSG_DATA 0xd0f42038 +#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_CONTROL 0xd0f4203c +#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_PBA 0xd0f43000 + + +// addressBlock: nbio_pcie0_pswuscfg0_cfgdecp +// base address: 0xfffe00000000 +#define cfgPSWUSCFG0_1_VENDOR_ID 0xfffe00000000 +#define cfgPSWUSCFG0_1_DEVICE_ID 0xfffe00000002 +#define cfgPSWUSCFG0_1_COMMAND 0xfffe00000004 +#define cfgPSWUSCFG0_1_STATUS 0xfffe00000006 +#define cfgPSWUSCFG0_1_REVISION_ID 0xfffe00000008 +#define cfgPSWUSCFG0_1_PROG_INTERFACE 0xfffe00000009 +#define cfgPSWUSCFG0_1_SUB_CLASS 0xfffe0000000a +#define cfgPSWUSCFG0_1_BASE_CLASS 0xfffe0000000b +#define cfgPSWUSCFG0_1_CACHE_LINE 0xfffe0000000c +#define cfgPSWUSCFG0_1_LATENCY 0xfffe0000000d +#define cfgPSWUSCFG0_1_HEADER 0xfffe0000000e +#define cfgPSWUSCFG0_1_BIST 0xfffe0000000f +#define cfgPSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY 0xfffe00000018 +#define cfgPSWUSCFG0_1_IO_BASE_LIMIT 0xfffe0000001c +#define cfgPSWUSCFG0_1_SECONDARY_STATUS 0xfffe0000001e +#define cfgPSWUSCFG0_1_MEM_BASE_LIMIT 0xfffe00000020 +#define cfgPSWUSCFG0_1_PREF_BASE_LIMIT 0xfffe00000024 +#define cfgPSWUSCFG0_1_PREF_BASE_UPPER 0xfffe00000028 +#define cfgPSWUSCFG0_1_PREF_LIMIT_UPPER 0xfffe0000002c +#define cfgPSWUSCFG0_1_IO_BASE_LIMIT_HI 0xfffe00000030 +#define cfgPSWUSCFG0_1_CAP_PTR 0xfffe00000034 +#define cfgPSWUSCFG0_1_ROM_BASE_ADDR 0xfffe00000038 +#define cfgPSWUSCFG0_1_INTERRUPT_LINE 0xfffe0000003c +#define cfgPSWUSCFG0_1_INTERRUPT_PIN 0xfffe0000003d +#define cfgPSWUSCFG0_1_IRQ_BRIDGE_CNTL 0xfffe0000003e +#define cfgPSWUSCFG0_1_EXT_BRIDGE_CNTL 0xfffe00000040 +#define cfgPSWUSCFG0_1_VENDOR_CAP_LIST 0xfffe00000048 +#define cfgPSWUSCFG0_1_ADAPTER_ID_W 0xfffe0000004c +#define cfgPSWUSCFG0_1_PMI_CAP_LIST 0xfffe00000050 +#define cfgPSWUSCFG0_1_PMI_CAP 0xfffe00000052 +#define cfgPSWUSCFG0_1_PMI_STATUS_CNTL 0xfffe00000054 +#define cfgPSWUSCFG0_1_PCIE_CAP_LIST 0xfffe00000058 +#define cfgPSWUSCFG0_1_PCIE_CAP 0xfffe0000005a +#define cfgPSWUSCFG0_1_DEVICE_CAP 0xfffe0000005c +#define cfgPSWUSCFG0_1_DEVICE_CNTL 0xfffe00000060 +#define cfgPSWUSCFG0_1_DEVICE_STATUS 0xfffe00000062 +#define cfgPSWUSCFG0_1_LINK_CAP 0xfffe00000064 +#define cfgPSWUSCFG0_1_LINK_CNTL 0xfffe00000068 +#define cfgPSWUSCFG0_1_LINK_STATUS 0xfffe0000006a +#define cfgPSWUSCFG0_1_DEVICE_CAP2 0xfffe0000007c +#define cfgPSWUSCFG0_1_DEVICE_CNTL2 0xfffe00000080 +#define cfgPSWUSCFG0_1_DEVICE_STATUS2 0xfffe00000082 +#define cfgPSWUSCFG0_1_LINK_CAP2 0xfffe00000084 +#define cfgPSWUSCFG0_1_LINK_CNTL2 0xfffe00000088 +#define cfgPSWUSCFG0_1_LINK_STATUS2 0xfffe0000008a +#define cfgPSWUSCFG0_1_MSI_CAP_LIST 0xfffe000000a0 +#define cfgPSWUSCFG0_1_MSI_MSG_CNTL 0xfffe000000a2 +#define cfgPSWUSCFG0_1_MSI_MSG_ADDR_LO 0xfffe000000a4 +#define cfgPSWUSCFG0_1_MSI_MSG_ADDR_HI 0xfffe000000a8 +#define cfgPSWUSCFG0_1_MSI_MSG_DATA 0xfffe000000a8 +#define cfgPSWUSCFG0_1_MSI_MSG_DATA_64 0xfffe000000ac +#define cfgPSWUSCFG0_1_SSID_CAP_LIST 0xfffe000000c0 +#define cfgPSWUSCFG0_1_SSID_CAP 0xfffe000000c4 +#define cfgPSWUSCFG0_1_MSI_MAP_CAP_LIST 0xfffe000000c8 +#define cfgPSWUSCFG0_1_MSI_MAP_CAP 0xfffe000000ca +#define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe00000100 +#define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe00000104 +#define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC1 0xfffe00000108 +#define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC2 0xfffe0000010c +#define cfgPSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST 0xfffe00000110 +#define cfgPSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1 0xfffe00000114 +#define cfgPSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2 0xfffe00000118 +#define cfgPSWUSCFG0_1_PCIE_PORT_VC_CNTL 0xfffe0000011c +#define cfgPSWUSCFG0_1_PCIE_PORT_VC_STATUS 0xfffe0000011e +#define cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP 0xfffe00000120 +#define cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL 0xfffe00000124 +#define cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS 0xfffe0000012a +#define cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP 0xfffe0000012c +#define cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL 0xfffe00000130 +#define cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS 0xfffe00000136 +#define cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xfffe00000140 +#define cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW1 0xfffe00000144 +#define cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW2 0xfffe00000148 +#define cfgPSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe00000150 +#define cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS 0xfffe00000154 +#define cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_MASK 0xfffe00000158 +#define cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe0000015c +#define cfgPSWUSCFG0_1_PCIE_CORR_ERR_STATUS 0xfffe00000160 +#define cfgPSWUSCFG0_1_PCIE_CORR_ERR_MASK 0xfffe00000164 +#define cfgPSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe00000168 +#define cfgPSWUSCFG0_1_PCIE_HDR_LOG0 0xfffe0000016c +#define cfgPSWUSCFG0_1_PCIE_HDR_LOG1 0xfffe00000170 +#define cfgPSWUSCFG0_1_PCIE_HDR_LOG2 0xfffe00000174 +#define cfgPSWUSCFG0_1_PCIE_HDR_LOG3 0xfffe00000178 +#define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG0 0xfffe00000188 +#define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG1 0xfffe0000018c +#define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG2 0xfffe00000190 +#define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG3 0xfffe00000194 +#define cfgPSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST 0xfffe00000270 +#define cfgPSWUSCFG0_1_PCIE_LINK_CNTL3 0xfffe00000274 +#define cfgPSWUSCFG0_1_PCIE_LANE_ERROR_STATUS 0xfffe00000278 +#define cfgPSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL 0xfffe0000027c +#define cfgPSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL 0xfffe0000027e +#define cfgPSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL 0xfffe00000280 +#define cfgPSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL 0xfffe00000282 +#define cfgPSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL 0xfffe00000284 +#define cfgPSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL 0xfffe00000286 +#define cfgPSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL 0xfffe00000288 +#define cfgPSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL 0xfffe0000028a +#define cfgPSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL 0xfffe0000028c +#define cfgPSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL 0xfffe0000028e +#define cfgPSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL 0xfffe00000290 +#define cfgPSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL 0xfffe00000292 +#define cfgPSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL 0xfffe00000294 +#define cfgPSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL 0xfffe00000296 +#define cfgPSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL 0xfffe00000298 +#define cfgPSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL 0xfffe0000029a +#define cfgPSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST 0xfffe000002a0 +#define cfgPSWUSCFG0_1_PCIE_ACS_CAP 0xfffe000002a4 +#define cfgPSWUSCFG0_1_PCIE_ACS_CNTL 0xfffe000002a6 +#define cfgPSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST 0xfffe000002f0 +#define cfgPSWUSCFG0_1_PCIE_MC_CAP 0xfffe000002f4 +#define cfgPSWUSCFG0_1_PCIE_MC_CNTL 0xfffe000002f6 +#define cfgPSWUSCFG0_1_PCIE_MC_ADDR0 0xfffe000002f8 +#define cfgPSWUSCFG0_1_PCIE_MC_ADDR1 0xfffe000002fc +#define cfgPSWUSCFG0_1_PCIE_MC_RCV0 0xfffe00000300 +#define cfgPSWUSCFG0_1_PCIE_MC_RCV1 0xfffe00000304 +#define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_ALL0 0xfffe00000308 +#define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_ALL1 0xfffe0000030c +#define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0xfffe00000310 +#define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0xfffe00000314 +#define cfgPSWUSCFG0_1_PCIE_MC_OVERLAY_BAR0 0xfffe00000318 +#define cfgPSWUSCFG0_1_PCIE_MC_OVERLAY_BAR1 0xfffe0000031c +#define cfgPSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST 0xfffe00000320 +#define cfgPSWUSCFG0_1_PCIE_LTR_CAP 0xfffe00000324 +#define cfgPSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST 0xfffe00000328 +#define cfgPSWUSCFG0_1_PCIE_ARI_CAP 0xfffe0000032c +#define cfgPSWUSCFG0_1_PCIE_ARI_CNTL 0xfffe0000032e +#define cfgPSWUSCFG0_1_PCIE_L1_PM_SUB_CAP_LIST 0xfffe00000370 +#define cfgPSWUSCFG0_1_PCIE_L1_PM_SUB_CAP 0xfffe00000374 +#define cfgPSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL 0xfffe00000378 +#define cfgPSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL2 0xfffe0000037c +#define cfgPSWUSCFG0_1_PCIE_ESM_CAP_LIST 0xfffe000003c4 +#define cfgPSWUSCFG0_1_PCIE_ESM_HEADER_1 0xfffe000003c8 +#define cfgPSWUSCFG0_1_PCIE_ESM_HEADER_2 0xfffe000003cc +#define cfgPSWUSCFG0_1_PCIE_ESM_STATUS 0xfffe000003ce +#define cfgPSWUSCFG0_1_PCIE_ESM_CTRL 0xfffe000003d0 +#define cfgPSWUSCFG0_1_PCIE_ESM_CAP_1 0xfffe000003d4 +#define cfgPSWUSCFG0_1_PCIE_ESM_CAP_2 0xfffe000003d8 +#define cfgPSWUSCFG0_1_PCIE_ESM_CAP_3 0xfffe000003dc +#define cfgPSWUSCFG0_1_PCIE_ESM_CAP_4 0xfffe000003e0 +#define cfgPSWUSCFG0_1_PCIE_ESM_CAP_5 0xfffe000003e4 +#define cfgPSWUSCFG0_1_PCIE_ESM_CAP_6 0xfffe000003e8 +#define cfgPSWUSCFG0_1_PCIE_ESM_CAP_7 0xfffe000003ec +#define cfgPSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST 0xfffe00000400 +#define cfgPSWUSCFG0_1_DATA_LINK_FEATURE_CAP 0xfffe00000404 +#define cfgPSWUSCFG0_1_DATA_LINK_FEATURE_STATUS 0xfffe00000408 +#define cfgPSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST 0xfffe00000410 +#define cfgPSWUSCFG0_1_LINK_CAP_16GT 0xfffe00000414 +#define cfgPSWUSCFG0_1_LINK_CNTL_16GT 0xfffe00000418 +#define cfgPSWUSCFG0_1_LINK_STATUS_16GT 0xfffe0000041c +#define cfgPSWUSCFG0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0xfffe00000420 +#define cfgPSWUSCFG0_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0xfffe00000424 +#define cfgPSWUSCFG0_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0xfffe00000428 +#define cfgPSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT 0xfffe00000430 +#define cfgPSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT 0xfffe00000431 +#define cfgPSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT 0xfffe00000432 +#define cfgPSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT 0xfffe00000433 +#define cfgPSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT 0xfffe00000434 +#define cfgPSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT 0xfffe00000435 +#define cfgPSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT 0xfffe00000436 +#define cfgPSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT 0xfffe00000437 +#define cfgPSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT 0xfffe00000438 +#define cfgPSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT 0xfffe00000439 +#define cfgPSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT 0xfffe0000043a +#define cfgPSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT 0xfffe0000043b +#define cfgPSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT 0xfffe0000043c +#define cfgPSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT 0xfffe0000043d +#define cfgPSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT 0xfffe0000043e +#define cfgPSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT 0xfffe0000043f +#define cfgPSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST 0xfffe00000440 +#define cfgPSWUSCFG0_1_MARGINING_PORT_CAP 0xfffe00000444 +#define cfgPSWUSCFG0_1_MARGINING_PORT_STATUS 0xfffe00000446 +#define cfgPSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL 0xfffe00000448 +#define cfgPSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS 0xfffe0000044a +#define cfgPSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL 0xfffe0000044c +#define cfgPSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS 0xfffe0000044e +#define cfgPSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL 0xfffe00000450 +#define cfgPSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS 0xfffe00000452 +#define cfgPSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL 0xfffe00000454 +#define cfgPSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS 0xfffe00000456 +#define cfgPSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL 0xfffe00000458 +#define cfgPSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS 0xfffe0000045a +#define cfgPSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL 0xfffe0000045c +#define cfgPSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS 0xfffe0000045e +#define cfgPSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL 0xfffe00000460 +#define cfgPSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS 0xfffe00000462 +#define cfgPSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL 0xfffe00000464 +#define cfgPSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS 0xfffe00000466 +#define cfgPSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL 0xfffe00000468 +#define cfgPSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS 0xfffe0000046a +#define cfgPSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL 0xfffe0000046c +#define cfgPSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS 0xfffe0000046e +#define cfgPSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL 0xfffe00000470 +#define cfgPSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS 0xfffe00000472 +#define cfgPSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL 0xfffe00000474 +#define cfgPSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS 0xfffe00000476 +#define cfgPSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL 0xfffe00000478 +#define cfgPSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS 0xfffe0000047a +#define cfgPSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL 0xfffe0000047c +#define cfgPSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS 0xfffe0000047e +#define cfgPSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL 0xfffe00000480 +#define cfgPSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS 0xfffe00000482 +#define cfgPSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL 0xfffe00000484 +#define cfgPSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS 0xfffe00000486 +#define cfgPSWUSCFG0_1_PCIE_CCIX_CAP_LIST 0xfffe00000488 +#define cfgPSWUSCFG0_1_PCIE_CCIX_HEADER_1 0xfffe0000048c +#define cfgPSWUSCFG0_1_PCIE_CCIX_HEADER_2 0xfffe00000490 +#define cfgPSWUSCFG0_1_PCIE_CCIX_CAP 0xfffe00000492 +#define cfgPSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP 0xfffe00000494 +#define cfgPSWUSCFG0_1_PCIE_CCIX_ESM_OPTL_CAP 0xfffe00000498 +#define cfgPSWUSCFG0_1_PCIE_CCIX_ESM_STATUS 0xfffe0000049c +#define cfgPSWUSCFG0_1_PCIE_CCIX_ESM_CNTL 0xfffe000004a0 +#define cfgPSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0xfffe000004a4 +#define cfgPSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0xfffe000004a5 +#define cfgPSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0xfffe000004a6 +#define cfgPSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0xfffe000004a7 +#define cfgPSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0xfffe000004a8 +#define cfgPSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0xfffe000004a9 +#define cfgPSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0xfffe000004aa +#define cfgPSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0xfffe000004ab +#define cfgPSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0xfffe000004ac +#define cfgPSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0xfffe000004ad +#define cfgPSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0xfffe000004ae +#define cfgPSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0xfffe000004af +#define cfgPSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0xfffe000004b0 +#define cfgPSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0xfffe000004b1 +#define cfgPSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0xfffe000004b2 +#define cfgPSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0xfffe000004b3 +#define cfgPSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0xfffe000004b4 +#define cfgPSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0xfffe000004b5 +#define cfgPSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0xfffe000004b6 +#define cfgPSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0xfffe000004b7 +#define cfgPSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0xfffe000004b8 +#define cfgPSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0xfffe000004b9 +#define cfgPSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0xfffe000004ba +#define cfgPSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0xfffe000004bb +#define cfgPSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0xfffe000004bc +#define cfgPSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0xfffe000004bd +#define cfgPSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0xfffe000004be +#define cfgPSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0xfffe000004bf +#define cfgPSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0xfffe000004c0 +#define cfgPSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0xfffe000004c1 +#define cfgPSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0xfffe000004c2 +#define cfgPSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0xfffe000004c3 +#define cfgPSWUSCFG0_1_PCIE_CCIX_TRANS_CAP 0xfffe000004c4 +#define cfgPSWUSCFG0_1_PCIE_CCIX_TRANS_CNTL 0xfffe000004c8 + + +// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC:1 +// base address: 0x0 +#define cfgBIF_BX_PF0_MM_INDEX 0x0000 +#define cfgBIF_BX_PF0_MM_DATA 0x0004 +#define cfgBIF_BX_PF0_MM_INDEX_HI 0x0018 + + +// addressBlock: nbio_nbif0_bif_swus_SUMDEC +// base address: 0x100000 +#define cfgSUM_INDEX 0x1000e0 +#define cfgSUM_DATA 0x1000e4 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_swds_bifcfgdecp +// base address: 0xfffe10100000 +#define cfgBIF_CFG_DEV0_SWDS1_VENDOR_ID 0xfffe10100000 +#define cfgBIF_CFG_DEV0_SWDS1_DEVICE_ID 0xfffe10100002 +#define cfgBIF_CFG_DEV0_SWDS1_COMMAND 0xfffe10100004 +#define cfgBIF_CFG_DEV0_SWDS1_STATUS 0xfffe10100006 +#define cfgBIF_CFG_DEV0_SWDS1_REVISION_ID 0xfffe10100008 +#define cfgBIF_CFG_DEV0_SWDS1_PROG_INTERFACE 0xfffe10100009 +#define cfgBIF_CFG_DEV0_SWDS1_SUB_CLASS 0xfffe1010000a +#define cfgBIF_CFG_DEV0_SWDS1_BASE_CLASS 0xfffe1010000b +#define cfgBIF_CFG_DEV0_SWDS1_CACHE_LINE 0xfffe1010000c +#define cfgBIF_CFG_DEV0_SWDS1_LATENCY 0xfffe1010000d +#define cfgBIF_CFG_DEV0_SWDS1_HEADER 0xfffe1010000e +#define cfgBIF_CFG_DEV0_SWDS1_BIST 0xfffe1010000f +#define cfgBIF_CFG_DEV0_SWDS1_BASE_ADDR_1 0xfffe10100010 +#define cfgBIF_CFG_DEV0_SWDS1_BASE_ADDR_2 0xfffe10100014 +#define cfgBIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY 0xfffe10100018 +#define cfgBIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT 0xfffe1010001c +#define cfgBIF_CFG_DEV0_SWDS1_SECONDARY_STATUS 0xfffe1010001e +#define cfgBIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT 0xfffe10100020 +#define cfgBIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT 0xfffe10100024 +#define cfgBIF_CFG_DEV0_SWDS1_PREF_BASE_UPPER 0xfffe10100028 +#define cfgBIF_CFG_DEV0_SWDS1_PREF_LIMIT_UPPER 0xfffe1010002c +#define cfgBIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI 0xfffe10100030 +#define cfgBIF_CFG_DEV0_SWDS1_CAP_PTR 0xfffe10100034 +#define cfgBIF_CFG_DEV0_SWDS1_ROM_BASE_ADDR 0xfffe10100038 +#define cfgBIF_CFG_DEV0_SWDS1_INTERRUPT_LINE 0xfffe1010003c +#define cfgBIF_CFG_DEV0_SWDS1_INTERRUPT_PIN 0xfffe1010003d +#define cfgBIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL 0xfffe1010003e +#define cfgBIF_CFG_DEV0_SWDS1_PMI_CAP_LIST 0xfffe10100050 +#define cfgBIF_CFG_DEV0_SWDS1_PMI_CAP 0xfffe10100052 +#define cfgBIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL 0xfffe10100054 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST 0xfffe10100058 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_CAP 0xfffe1010005a +#define cfgBIF_CFG_DEV0_SWDS1_DEVICE_CAP 0xfffe1010005c +#define cfgBIF_CFG_DEV0_SWDS1_DEVICE_CNTL 0xfffe10100060 +#define cfgBIF_CFG_DEV0_SWDS1_DEVICE_STATUS 0xfffe10100062 +#define cfgBIF_CFG_DEV0_SWDS1_LINK_CAP 0xfffe10100064 +#define cfgBIF_CFG_DEV0_SWDS1_LINK_CNTL 0xfffe10100068 +#define cfgBIF_CFG_DEV0_SWDS1_LINK_STATUS 0xfffe1010006a +#define cfgBIF_CFG_DEV0_SWDS1_SLOT_CAP 0xfffe1010006c +#define cfgBIF_CFG_DEV0_SWDS1_SLOT_CNTL 0xfffe10100070 +#define cfgBIF_CFG_DEV0_SWDS1_SLOT_STATUS 0xfffe10100072 +#define cfgBIF_CFG_DEV0_SWDS1_DEVICE_CAP2 0xfffe1010007c +#define cfgBIF_CFG_DEV0_SWDS1_DEVICE_CNTL2 0xfffe10100080 +#define cfgBIF_CFG_DEV0_SWDS1_DEVICE_STATUS2 0xfffe10100082 +#define cfgBIF_CFG_DEV0_SWDS1_LINK_CAP2 0xfffe10100084 +#define cfgBIF_CFG_DEV0_SWDS1_LINK_CNTL2 0xfffe10100088 +#define cfgBIF_CFG_DEV0_SWDS1_LINK_STATUS2 0xfffe1010008a +#define cfgBIF_CFG_DEV0_SWDS1_SLOT_CAP2 0xfffe1010008c +#define cfgBIF_CFG_DEV0_SWDS1_SLOT_CNTL2 0xfffe10100090 +#define cfgBIF_CFG_DEV0_SWDS1_SLOT_STATUS2 0xfffe10100092 +#define cfgBIF_CFG_DEV0_SWDS1_MSI_CAP_LIST 0xfffe101000a0 +#define cfgBIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL 0xfffe101000a2 +#define cfgBIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_LO 0xfffe101000a4 +#define cfgBIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_HI 0xfffe101000a8 +#define cfgBIF_CFG_DEV0_SWDS1_MSI_MSG_DATA 0xfffe101000a8 +#define cfgBIF_CFG_DEV0_SWDS1_MSI_MSG_DATA_64 0xfffe101000ac +#define cfgBIF_CFG_DEV0_SWDS1_SSID_CAP_LIST 0xfffe101000c0 +#define cfgBIF_CFG_DEV0_SWDS1_SSID_CAP 0xfffe101000c4 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10100100 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10100104 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC1 0xfffe10100108 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC2 0xfffe1010010c +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST 0xfffe10100110 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1 0xfffe10100114 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2 0xfffe10100118 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL 0xfffe1010011c +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_STATUS 0xfffe1010011e +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP 0xfffe10100120 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL 0xfffe10100124 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS 0xfffe1010012a +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP 0xfffe1010012c +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL 0xfffe10100130 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS 0xfffe10100136 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xfffe10100140 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW1 0xfffe10100144 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW2 0xfffe10100148 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10100150 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS 0xfffe10100154 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK 0xfffe10100158 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1010015c +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS 0xfffe10100160 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK 0xfffe10100164 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10100168 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG0 0xfffe1010016c +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG1 0xfffe10100170 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG2 0xfffe10100174 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG3 0xfffe10100178 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG0 0xfffe10100188 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG1 0xfffe1010018c +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG2 0xfffe10100190 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG3 0xfffe10100194 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST 0xfffe10100270 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3 0xfffe10100274 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS 0xfffe10100278 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL 0xfffe1010027c +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL 0xfffe1010027e +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL 0xfffe10100280 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL 0xfffe10100282 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL 0xfffe10100284 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL 0xfffe10100286 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL 0xfffe10100288 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL 0xfffe1010028a +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL 0xfffe1010028c +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL 0xfffe1010028e +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL 0xfffe10100290 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL 0xfffe10100292 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL 0xfffe10100294 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL 0xfffe10100296 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL 0xfffe10100298 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL 0xfffe1010029a +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST 0xfffe101002a0 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP 0xfffe101002a4 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL 0xfffe101002a6 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_DLF_ENH_CAP_LIST 0xfffe10100400 +#define cfgBIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_CAP 0xfffe10100404 +#define cfgBIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_STATUS 0xfffe10100408 +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_PHY_16GT_ENH_CAP_LIST 0xfffe10100410 +#define cfgBIF_CFG_DEV0_SWDS1_LINK_CAP_16GT 0xfffe10100414 +#define cfgBIF_CFG_DEV0_SWDS1_LINK_CNTL_16GT 0xfffe10100418 +#define cfgBIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT 0xfffe1010041c +#define cfgBIF_CFG_DEV0_SWDS1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0xfffe10100420 +#define cfgBIF_CFG_DEV0_SWDS1_RTM1_PARITY_MISMATCH_STATUS_16GT 0xfffe10100424 +#define cfgBIF_CFG_DEV0_SWDS1_RTM2_PARITY_MISMATCH_STATUS_16GT 0xfffe10100428 +#define cfgBIF_CFG_DEV0_SWDS1_LANE_0_EQUALIZATION_CNTL_16GT 0xfffe10100430 +#define cfgBIF_CFG_DEV0_SWDS1_LANE_1_EQUALIZATION_CNTL_16GT 0xfffe10100431 +#define cfgBIF_CFG_DEV0_SWDS1_LANE_2_EQUALIZATION_CNTL_16GT 0xfffe10100432 +#define cfgBIF_CFG_DEV0_SWDS1_LANE_3_EQUALIZATION_CNTL_16GT 0xfffe10100433 +#define cfgBIF_CFG_DEV0_SWDS1_LANE_4_EQUALIZATION_CNTL_16GT 0xfffe10100434 +#define cfgBIF_CFG_DEV0_SWDS1_LANE_5_EQUALIZATION_CNTL_16GT 0xfffe10100435 +#define cfgBIF_CFG_DEV0_SWDS1_LANE_6_EQUALIZATION_CNTL_16GT 0xfffe10100436 +#define cfgBIF_CFG_DEV0_SWDS1_LANE_7_EQUALIZATION_CNTL_16GT 0xfffe10100437 +#define cfgBIF_CFG_DEV0_SWDS1_LANE_8_EQUALIZATION_CNTL_16GT 0xfffe10100438 +#define cfgBIF_CFG_DEV0_SWDS1_LANE_9_EQUALIZATION_CNTL_16GT 0xfffe10100439 +#define cfgBIF_CFG_DEV0_SWDS1_LANE_10_EQUALIZATION_CNTL_16GT 0xfffe1010043a +#define cfgBIF_CFG_DEV0_SWDS1_LANE_11_EQUALIZATION_CNTL_16GT 0xfffe1010043b +#define cfgBIF_CFG_DEV0_SWDS1_LANE_12_EQUALIZATION_CNTL_16GT 0xfffe1010043c +#define cfgBIF_CFG_DEV0_SWDS1_LANE_13_EQUALIZATION_CNTL_16GT 0xfffe1010043d +#define cfgBIF_CFG_DEV0_SWDS1_LANE_14_EQUALIZATION_CNTL_16GT 0xfffe1010043e +#define cfgBIF_CFG_DEV0_SWDS1_LANE_15_EQUALIZATION_CNTL_16GT 0xfffe1010043f +#define cfgBIF_CFG_DEV0_SWDS1_PCIE_MARGINING_ENH_CAP_LIST 0xfffe10100440 +#define cfgBIF_CFG_DEV0_SWDS1_MARGINING_PORT_CAP 0xfffe10100444 +#define cfgBIF_CFG_DEV0_SWDS1_MARGINING_PORT_STATUS 0xfffe10100446 +#define cfgBIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_CNTL 0xfffe10100448 +#define cfgBIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_STATUS 0xfffe1010044a +#define cfgBIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_CNTL 0xfffe1010044c +#define cfgBIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_STATUS 0xfffe1010044e +#define cfgBIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_CNTL 0xfffe10100450 +#define cfgBIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_STATUS 0xfffe10100452 +#define cfgBIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_CNTL 0xfffe10100454 +#define cfgBIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_STATUS 0xfffe10100456 +#define cfgBIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_CNTL 0xfffe10100458 +#define cfgBIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_STATUS 0xfffe1010045a +#define cfgBIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_CNTL 0xfffe1010045c +#define cfgBIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_STATUS 0xfffe1010045e +#define cfgBIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_CNTL 0xfffe10100460 +#define cfgBIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_STATUS 0xfffe10100462 +#define cfgBIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_CNTL 0xfffe10100464 +#define cfgBIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_STATUS 0xfffe10100466 +#define cfgBIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_CNTL 0xfffe10100468 +#define cfgBIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_STATUS 0xfffe1010046a +#define cfgBIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_CNTL 0xfffe1010046c +#define cfgBIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_STATUS 0xfffe1010046e +#define cfgBIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_CNTL 0xfffe10100470 +#define cfgBIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_STATUS 0xfffe10100472 +#define cfgBIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_CNTL 0xfffe10100474 +#define cfgBIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_STATUS 0xfffe10100476 +#define cfgBIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_CNTL 0xfffe10100478 +#define cfgBIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_STATUS 0xfffe1010047a +#define cfgBIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_CNTL 0xfffe1010047c +#define cfgBIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_STATUS 0xfffe1010047e +#define cfgBIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_CNTL 0xfffe10100480 +#define cfgBIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_STATUS 0xfffe10100482 +#define cfgBIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_CNTL 0xfffe10100484 +#define cfgBIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_STATUS 0xfffe10100486 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +// base address: 0xfffe10200000 +#define cfgBIF_CFG_DEV0_EPF0_1_VENDOR_ID 0xfffe10200000 +#define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_ID 0xfffe10200002 +#define cfgBIF_CFG_DEV0_EPF0_1_COMMAND 0xfffe10200004 +#define cfgBIF_CFG_DEV0_EPF0_1_STATUS 0xfffe10200006 +#define cfgBIF_CFG_DEV0_EPF0_1_REVISION_ID 0xfffe10200008 +#define cfgBIF_CFG_DEV0_EPF0_1_PROG_INTERFACE 0xfffe10200009 +#define cfgBIF_CFG_DEV0_EPF0_1_SUB_CLASS 0xfffe1020000a +#define cfgBIF_CFG_DEV0_EPF0_1_BASE_CLASS 0xfffe1020000b +#define cfgBIF_CFG_DEV0_EPF0_1_CACHE_LINE 0xfffe1020000c +#define cfgBIF_CFG_DEV0_EPF0_1_LATENCY 0xfffe1020000d +#define cfgBIF_CFG_DEV0_EPF0_1_HEADER 0xfffe1020000e +#define cfgBIF_CFG_DEV0_EPF0_1_BIST 0xfffe1020000f +#define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_1 0xfffe10200010 +#define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_2 0xfffe10200014 +#define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_3 0xfffe10200018 +#define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_4 0xfffe1020001c +#define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_5 0xfffe10200020 +#define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_6 0xfffe10200024 +#define cfgBIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR 0xfffe10200028 +#define cfgBIF_CFG_DEV0_EPF0_1_ADAPTER_ID 0xfffe1020002c +#define cfgBIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR 0xfffe10200030 +#define cfgBIF_CFG_DEV0_EPF0_1_CAP_PTR 0xfffe10200034 +#define cfgBIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE 0xfffe1020003c +#define cfgBIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN 0xfffe1020003d +#define cfgBIF_CFG_DEV0_EPF0_1_MIN_GRANT 0xfffe1020003e +#define cfgBIF_CFG_DEV0_EPF0_1_MAX_LATENCY 0xfffe1020003f +#define cfgBIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST 0xfffe10200048 +#define cfgBIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W 0xfffe1020004c +#define cfgBIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST 0xfffe10200050 +#define cfgBIF_CFG_DEV0_EPF0_1_PMI_CAP 0xfffe10200052 +#define cfgBIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL 0xfffe10200054 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST 0xfffe10200064 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CAP 0xfffe10200066 +#define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CAP 0xfffe10200068 +#define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL 0xfffe1020006c +#define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS 0xfffe1020006e +#define cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP 0xfffe10200070 +#define cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL 0xfffe10200074 +#define cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS 0xfffe10200076 +#define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CAP2 0xfffe10200088 +#define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2 0xfffe1020008c +#define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2 0xfffe1020008e +#define cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP2 0xfffe10200090 +#define cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL2 0xfffe10200094 +#define cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS2 0xfffe10200096 +#define cfgBIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST 0xfffe102000a0 +#define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL 0xfffe102000a2 +#define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO 0xfffe102000a4 +#define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI 0xfffe102000a8 +#define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA 0xfffe102000a8 +#define cfgBIF_CFG_DEV0_EPF0_1_MSI_MASK 0xfffe102000ac +#define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64 0xfffe102000ac +#define cfgBIF_CFG_DEV0_EPF0_1_MSI_MASK_64 0xfffe102000b0 +#define cfgBIF_CFG_DEV0_EPF0_1_MSI_PENDING 0xfffe102000b0 +#define cfgBIF_CFG_DEV0_EPF0_1_MSI_PENDING_64 0xfffe102000b4 +#define cfgBIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST 0xfffe102000c0 +#define cfgBIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL 0xfffe102000c2 +#define cfgBIF_CFG_DEV0_EPF0_1_MSIX_TABLE 0xfffe102000c4 +#define cfgBIF_CFG_DEV0_EPF0_1_MSIX_PBA 0xfffe102000c8 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10200100 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10200104 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1 0xfffe10200108 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2 0xfffe1020010c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST 0xfffe10200110 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1 0xfffe10200114 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2 0xfffe10200118 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL 0xfffe1020011c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS 0xfffe1020011e +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP 0xfffe10200120 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL 0xfffe10200124 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS 0xfffe1020012a +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP 0xfffe1020012c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL 0xfffe10200130 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS 0xfffe10200136 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xfffe10200140 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1 0xfffe10200144 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2 0xfffe10200148 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10200150 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS 0xfffe10200154 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK 0xfffe10200158 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1020015c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS 0xfffe10200160 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK 0xfffe10200164 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10200168 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0 0xfffe1020016c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1 0xfffe10200170 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2 0xfffe10200174 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3 0xfffe10200178 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0 0xfffe10200188 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1 0xfffe1020018c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2 0xfffe10200190 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3 0xfffe10200194 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST 0xfffe10200200 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP 0xfffe10200204 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL 0xfffe10200208 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP 0xfffe1020020c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL 0xfffe10200210 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP 0xfffe10200214 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL 0xfffe10200218 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP 0xfffe1020021c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL 0xfffe10200220 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP 0xfffe10200224 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL 0xfffe10200228 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP 0xfffe1020022c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL 0xfffe10200230 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0xfffe10200240 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT 0xfffe10200244 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA 0xfffe10200248 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP 0xfffe1020024c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST 0xfffe10200250 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP 0xfffe10200254 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR 0xfffe10200258 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS 0xfffe1020025c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL 0xfffe1020025e +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0xfffe10200260 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0xfffe10200261 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0xfffe10200262 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0xfffe10200263 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0xfffe10200264 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0xfffe10200265 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0xfffe10200266 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0xfffe10200267 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST 0xfffe10200270 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3 0xfffe10200274 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS 0xfffe10200278 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL 0xfffe1020027c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL 0xfffe1020027e +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL 0xfffe10200280 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL 0xfffe10200282 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL 0xfffe10200284 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL 0xfffe10200286 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL 0xfffe10200288 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL 0xfffe1020028a +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL 0xfffe1020028c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL 0xfffe1020028e +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL 0xfffe10200290 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL 0xfffe10200292 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL 0xfffe10200294 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL 0xfffe10200296 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL 0xfffe10200298 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL 0xfffe1020029a +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST 0xfffe102002a0 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP 0xfffe102002a4 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL 0xfffe102002a6 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST 0xfffe102002b0 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP 0xfffe102002b4 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL 0xfffe102002b6 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST 0xfffe102002c0 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL 0xfffe102002c4 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS 0xfffe102002c6 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0xfffe102002c8 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0xfffe102002cc +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST 0xfffe102002d0 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP 0xfffe102002d4 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL 0xfffe102002d6 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST 0xfffe102002f0 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP 0xfffe102002f4 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL 0xfffe102002f6 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0 0xfffe102002f8 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1 0xfffe102002fc +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0 0xfffe10200300 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1 0xfffe10200304 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0 0xfffe10200308 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1 0xfffe1020030c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0xfffe10200310 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0xfffe10200314 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST 0xfffe10200320 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP 0xfffe10200324 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10200328 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP 0xfffe1020032c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL 0xfffe1020032e +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST 0xfffe10200330 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP 0xfffe10200334 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL 0xfffe10200338 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS 0xfffe1020033a +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS 0xfffe1020033c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS 0xfffe1020033e +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS 0xfffe10200340 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK 0xfffe10200342 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET 0xfffe10200344 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE 0xfffe10200346 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID 0xfffe1020034a +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0xfffe1020034c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0xfffe10200350 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0 0xfffe10200354 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1 0xfffe10200358 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2 0xfffe1020035c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3 0xfffe10200360 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4 0xfffe10200364 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5 0xfffe10200368 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0xfffe1020036c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST 0xfffe10200370 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP 0xfffe10200374 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL 0xfffe10200378 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST 0xfffe10200400 +#define cfgBIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP 0xfffe10200404 +#define cfgBIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS 0xfffe10200408 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST 0xfffe10200410 +#define cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT 0xfffe10200414 +#define cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT 0xfffe10200418 +#define cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT 0xfffe1020041c +#define cfgBIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0xfffe10200420 +#define cfgBIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0xfffe10200424 +#define cfgBIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0xfffe10200428 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT 0xfffe10200430 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT 0xfffe10200431 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT 0xfffe10200432 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT 0xfffe10200433 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT 0xfffe10200434 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT 0xfffe10200435 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT 0xfffe10200436 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT 0xfffe10200437 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT 0xfffe10200438 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT 0xfffe10200439 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT 0xfffe1020043a +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT 0xfffe1020043b +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT 0xfffe1020043c +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT 0xfffe1020043d +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT 0xfffe1020043e +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT 0xfffe1020043f +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST 0xfffe10200440 +#define cfgBIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP 0xfffe10200444 +#define cfgBIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS 0xfffe10200446 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL 0xfffe10200448 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS 0xfffe1020044a +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL 0xfffe1020044c +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS 0xfffe1020044e +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL 0xfffe10200450 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS 0xfffe10200452 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL 0xfffe10200454 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS 0xfffe10200456 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL 0xfffe10200458 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS 0xfffe1020045a +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL 0xfffe1020045c +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS 0xfffe1020045e +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL 0xfffe10200460 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS 0xfffe10200462 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL 0xfffe10200464 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS 0xfffe10200466 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL 0xfffe10200468 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS 0xfffe1020046a +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL 0xfffe1020046c +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS 0xfffe1020046e +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL 0xfffe10200470 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS 0xfffe10200472 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL 0xfffe10200474 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS 0xfffe10200476 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL 0xfffe10200478 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS 0xfffe1020047a +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL 0xfffe1020047c +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS 0xfffe1020047e +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL 0xfffe10200480 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS 0xfffe10200482 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL 0xfffe10200484 +#define cfgBIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS 0xfffe10200486 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0xfffe102004c0 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP 0xfffe102004c4 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL 0xfffe102004c8 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP 0xfffe102004cc +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL 0xfffe102004d0 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP 0xfffe102004d4 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL 0xfffe102004d8 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP 0xfffe102004dc +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL 0xfffe102004e0 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP 0xfffe102004e4 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL 0xfffe102004e8 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP 0xfffe102004ec +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL 0xfffe102004f0 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0xfffe10200500 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0xfffe10200504 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0xfffe10200508 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0xfffe1020050c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0xfffe10200510 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0xfffe10200514 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0xfffe10200518 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0xfffe1020051c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0xfffe10200520 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0xfffe10200524 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0xfffe10200528 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0xfffe1020052c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0xfffe10200530 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0xfffe10200534 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0xfffe10200538 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0xfffe1020053c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0xfffe10200540 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0xfffe10200544 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0xfffe10200548 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0xfffe1020054c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0xfffe10200550 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0xfffe10200554 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0xfffe10200558 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0xfffe1020055c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0xfffe10200560 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0xfffe10200564 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0xfffe10200568 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0xfffe1020056c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0xfffe10200570 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0xfffe10200574 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0xfffe10200578 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0xfffe1020057c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0xfffe10200580 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0xfffe10200584 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0xfffe10200588 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0xfffe1020058c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0xfffe10200590 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0xfffe10200594 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0xfffe10200598 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0xfffe1020059c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0xfffe102005a0 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0xfffe102005a4 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0xfffe102005a8 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0xfffe102005ac +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0xfffe102005b0 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0xfffe102005c0 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0xfffe102005c4 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0xfffe102005c8 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0xfffe102005cc +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0xfffe102005d0 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0xfffe102005d4 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0xfffe102005d8 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0xfffe102005dc +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0xfffe102005e0 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0xfffe102005f0 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0xfffe102005f4 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0xfffe102005f8 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0xfffe102005fc +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0xfffe10200600 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0xfffe10200604 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0xfffe10200608 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0xfffe1020060c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0xfffe10200610 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0xfffe10200620 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0xfffe10200624 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0xfffe10200628 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0xfffe1020062c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0xfffe10200630 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0xfffe10200634 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0xfffe10200638 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0xfffe1020063c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0xfffe10200640 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 0xfffe10200650 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 0xfffe10200654 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 0xfffe10200658 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 0xfffe1020065c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 0xfffe10200660 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 0xfffe10200664 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 0xfffe10200668 +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 0xfffe1020066c +#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 0xfffe10200670 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp +// base address: 0xfffe10201000 +#define cfgBIF_CFG_DEV0_EPF1_1_VENDOR_ID 0xfffe10201000 +#define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_ID 0xfffe10201002 +#define cfgBIF_CFG_DEV0_EPF1_1_COMMAND 0xfffe10201004 +#define cfgBIF_CFG_DEV0_EPF1_1_STATUS 0xfffe10201006 +#define cfgBIF_CFG_DEV0_EPF1_1_REVISION_ID 0xfffe10201008 +#define cfgBIF_CFG_DEV0_EPF1_1_PROG_INTERFACE 0xfffe10201009 +#define cfgBIF_CFG_DEV0_EPF1_1_SUB_CLASS 0xfffe1020100a +#define cfgBIF_CFG_DEV0_EPF1_1_BASE_CLASS 0xfffe1020100b +#define cfgBIF_CFG_DEV0_EPF1_1_CACHE_LINE 0xfffe1020100c +#define cfgBIF_CFG_DEV0_EPF1_1_LATENCY 0xfffe1020100d +#define cfgBIF_CFG_DEV0_EPF1_1_HEADER 0xfffe1020100e +#define cfgBIF_CFG_DEV0_EPF1_1_BIST 0xfffe1020100f +#define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_1 0xfffe10201010 +#define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_2 0xfffe10201014 +#define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_3 0xfffe10201018 +#define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_4 0xfffe1020101c +#define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_5 0xfffe10201020 +#define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_6 0xfffe10201024 +#define cfgBIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR 0xfffe10201028 +#define cfgBIF_CFG_DEV0_EPF1_1_ADAPTER_ID 0xfffe1020102c +#define cfgBIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR 0xfffe10201030 +#define cfgBIF_CFG_DEV0_EPF1_1_CAP_PTR 0xfffe10201034 +#define cfgBIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE 0xfffe1020103c +#define cfgBIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN 0xfffe1020103d +#define cfgBIF_CFG_DEV0_EPF1_1_MIN_GRANT 0xfffe1020103e +#define cfgBIF_CFG_DEV0_EPF1_1_MAX_LATENCY 0xfffe1020103f +#define cfgBIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST 0xfffe10201048 +#define cfgBIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W 0xfffe1020104c +#define cfgBIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST 0xfffe10201050 +#define cfgBIF_CFG_DEV0_EPF1_1_PMI_CAP 0xfffe10201052 +#define cfgBIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL 0xfffe10201054 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST 0xfffe10201064 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CAP 0xfffe10201066 +#define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CAP 0xfffe10201068 +#define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL 0xfffe1020106c +#define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS 0xfffe1020106e +#define cfgBIF_CFG_DEV0_EPF1_1_LINK_CAP 0xfffe10201070 +#define cfgBIF_CFG_DEV0_EPF1_1_LINK_CNTL 0xfffe10201074 +#define cfgBIF_CFG_DEV0_EPF1_1_LINK_STATUS 0xfffe10201076 +#define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CAP2 0xfffe10201088 +#define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2 0xfffe1020108c +#define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2 0xfffe1020108e +#define cfgBIF_CFG_DEV0_EPF1_1_LINK_CAP2 0xfffe10201090 +#define cfgBIF_CFG_DEV0_EPF1_1_LINK_CNTL2 0xfffe10201094 +#define cfgBIF_CFG_DEV0_EPF1_1_LINK_STATUS2 0xfffe10201096 +#define cfgBIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST 0xfffe102010a0 +#define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL 0xfffe102010a2 +#define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO 0xfffe102010a4 +#define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI 0xfffe102010a8 +#define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA 0xfffe102010a8 +#define cfgBIF_CFG_DEV0_EPF1_1_MSI_MASK 0xfffe102010ac +#define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64 0xfffe102010ac +#define cfgBIF_CFG_DEV0_EPF1_1_MSI_MASK_64 0xfffe102010b0 +#define cfgBIF_CFG_DEV0_EPF1_1_MSI_PENDING 0xfffe102010b0 +#define cfgBIF_CFG_DEV0_EPF1_1_MSI_PENDING_64 0xfffe102010b4 +#define cfgBIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST 0xfffe102010c0 +#define cfgBIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL 0xfffe102010c2 +#define cfgBIF_CFG_DEV0_EPF1_1_MSIX_TABLE 0xfffe102010c4 +#define cfgBIF_CFG_DEV0_EPF1_1_MSIX_PBA 0xfffe102010c8 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10201100 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10201104 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1 0xfffe10201108 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2 0xfffe1020110c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST 0xfffe10201110 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1 0xfffe10201114 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2 0xfffe10201118 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL 0xfffe1020111c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS 0xfffe1020111e +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP 0xfffe10201120 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL 0xfffe10201124 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS 0xfffe1020112a +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP 0xfffe1020112c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL 0xfffe10201130 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS 0xfffe10201136 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xfffe10201140 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1 0xfffe10201144 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2 0xfffe10201148 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10201150 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS 0xfffe10201154 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK 0xfffe10201158 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1020115c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS 0xfffe10201160 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK 0xfffe10201164 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10201168 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0 0xfffe1020116c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1 0xfffe10201170 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2 0xfffe10201174 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3 0xfffe10201178 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0 0xfffe10201188 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1 0xfffe1020118c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2 0xfffe10201190 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3 0xfffe10201194 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST 0xfffe10201200 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP 0xfffe10201204 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL 0xfffe10201208 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP 0xfffe1020120c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL 0xfffe10201210 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP 0xfffe10201214 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL 0xfffe10201218 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP 0xfffe1020121c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL 0xfffe10201220 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP 0xfffe10201224 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL 0xfffe10201228 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP 0xfffe1020122c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL 0xfffe10201230 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0xfffe10201240 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT 0xfffe10201244 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA 0xfffe10201248 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP 0xfffe1020124c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST 0xfffe10201250 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP 0xfffe10201254 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR 0xfffe10201258 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS 0xfffe1020125c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL 0xfffe1020125e +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0xfffe10201260 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0xfffe10201261 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0xfffe10201262 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0xfffe10201263 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0xfffe10201264 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0xfffe10201265 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0xfffe10201266 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0xfffe10201267 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST 0xfffe10201270 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3 0xfffe10201274 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS 0xfffe10201278 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL 0xfffe1020127c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL 0xfffe1020127e +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL 0xfffe10201280 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL 0xfffe10201282 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL 0xfffe10201284 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL 0xfffe10201286 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL 0xfffe10201288 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL 0xfffe1020128a +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL 0xfffe1020128c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL 0xfffe1020128e +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL 0xfffe10201290 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL 0xfffe10201292 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL 0xfffe10201294 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL 0xfffe10201296 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL 0xfffe10201298 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL 0xfffe1020129a +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST 0xfffe102012a0 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP 0xfffe102012a4 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL 0xfffe102012a6 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST 0xfffe102012b0 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP 0xfffe102012b4 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL 0xfffe102012b6 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST 0xfffe102012c0 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL 0xfffe102012c4 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS 0xfffe102012c6 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0xfffe102012c8 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0xfffe102012cc +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST 0xfffe102012d0 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP 0xfffe102012d4 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL 0xfffe102012d6 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST 0xfffe102012f0 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP 0xfffe102012f4 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL 0xfffe102012f6 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0 0xfffe102012f8 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1 0xfffe102012fc +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0 0xfffe10201300 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1 0xfffe10201304 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0 0xfffe10201308 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1 0xfffe1020130c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0xfffe10201310 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0xfffe10201314 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST 0xfffe10201320 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP 0xfffe10201324 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10201328 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP 0xfffe1020132c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL 0xfffe1020132e +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST 0xfffe10201330 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP 0xfffe10201334 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL 0xfffe10201338 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS 0xfffe1020133a +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS 0xfffe1020133c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS 0xfffe1020133e +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS 0xfffe10201340 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK 0xfffe10201342 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET 0xfffe10201344 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE 0xfffe10201346 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID 0xfffe1020134a +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0xfffe1020134c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0xfffe10201350 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0 0xfffe10201354 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1 0xfffe10201358 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2 0xfffe1020135c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3 0xfffe10201360 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4 0xfffe10201364 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5 0xfffe10201368 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0xfffe1020136c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST 0xfffe10201370 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP 0xfffe10201374 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL 0xfffe10201378 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST 0xfffe10201400 +#define cfgBIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP 0xfffe10201404 +#define cfgBIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS 0xfffe10201408 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST 0xfffe10201410 +#define cfgBIF_CFG_DEV0_EPF1_1_LINK_CAP_16GT 0xfffe10201414 +#define cfgBIF_CFG_DEV0_EPF1_1_LINK_CNTL_16GT 0xfffe10201418 +#define cfgBIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT 0xfffe1020141c +#define cfgBIF_CFG_DEV0_EPF1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0xfffe10201420 +#define cfgBIF_CFG_DEV0_EPF1_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0xfffe10201424 +#define cfgBIF_CFG_DEV0_EPF1_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0xfffe10201428 +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT 0xfffe10201430 +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT 0xfffe10201431 +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT 0xfffe10201432 +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT 0xfffe10201433 +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT 0xfffe10201434 +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT 0xfffe10201435 +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT 0xfffe10201436 +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT 0xfffe10201437 +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT 0xfffe10201438 +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT 0xfffe10201439 +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT 0xfffe1020143a +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT 0xfffe1020143b +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT 0xfffe1020143c +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT 0xfffe1020143d +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT 0xfffe1020143e +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT 0xfffe1020143f +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST 0xfffe10201440 +#define cfgBIF_CFG_DEV0_EPF1_1_MARGINING_PORT_CAP 0xfffe10201444 +#define cfgBIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS 0xfffe10201446 +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL 0xfffe10201448 +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS 0xfffe1020144a +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL 0xfffe1020144c +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS 0xfffe1020144e +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL 0xfffe10201450 +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS 0xfffe10201452 +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL 0xfffe10201454 +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS 0xfffe10201456 +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL 0xfffe10201458 +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS 0xfffe1020145a +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL 0xfffe1020145c +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS 0xfffe1020145e +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL 0xfffe10201460 +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS 0xfffe10201462 +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL 0xfffe10201464 +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS 0xfffe10201466 +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL 0xfffe10201468 +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS 0xfffe1020146a +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL 0xfffe1020146c +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS 0xfffe1020146e +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL 0xfffe10201470 +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS 0xfffe10201472 +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL 0xfffe10201474 +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS 0xfffe10201476 +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL 0xfffe10201478 +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS 0xfffe1020147a +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL 0xfffe1020147c +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS 0xfffe1020147e +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL 0xfffe10201480 +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS 0xfffe10201482 +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL 0xfffe10201484 +#define cfgBIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS 0xfffe10201486 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0xfffe102014c0 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP 0xfffe102014c4 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL 0xfffe102014c8 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP 0xfffe102014cc +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL 0xfffe102014d0 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP 0xfffe102014d4 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL 0xfffe102014d8 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP 0xfffe102014dc +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL 0xfffe102014e0 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP 0xfffe102014e4 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL 0xfffe102014e8 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP 0xfffe102014ec +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL 0xfffe102014f0 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0xfffe10201500 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0xfffe10201504 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0xfffe10201508 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0xfffe1020150c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0xfffe10201510 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0xfffe10201514 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0xfffe10201518 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0xfffe1020151c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0xfffe10201520 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0xfffe10201524 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0xfffe10201528 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0xfffe1020152c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0xfffe10201530 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0xfffe10201534 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0xfffe10201538 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0xfffe1020153c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0xfffe10201540 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0xfffe10201544 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0xfffe10201548 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0xfffe1020154c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0xfffe10201550 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0xfffe10201554 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0xfffe10201558 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0xfffe1020155c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0xfffe10201560 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0xfffe10201564 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0xfffe10201568 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0xfffe1020156c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0xfffe10201570 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0xfffe10201574 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0xfffe10201578 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0xfffe1020157c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0xfffe10201580 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0xfffe10201584 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0xfffe10201588 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0xfffe1020158c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0xfffe10201590 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0xfffe10201594 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0xfffe10201598 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0xfffe1020159c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0xfffe102015a0 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0xfffe102015a4 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0xfffe102015a8 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0xfffe102015ac +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0xfffe102015b0 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0xfffe102015c0 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0xfffe102015c4 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0xfffe102015c8 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0xfffe102015cc +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0xfffe102015d0 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0xfffe102015d4 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0xfffe102015d8 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0xfffe102015dc +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0xfffe102015e0 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0xfffe102015f0 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0xfffe102015f4 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0xfffe102015f8 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0xfffe102015fc +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0xfffe10201600 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0xfffe10201604 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0xfffe10201608 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0xfffe1020160c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0xfffe10201610 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0xfffe10201620 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0xfffe10201624 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0xfffe10201628 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0xfffe1020162c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0xfffe10201630 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0xfffe10201634 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0xfffe10201638 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0xfffe1020163c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0xfffe10201640 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 0xfffe10201650 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 0xfffe10201654 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 0xfffe10201658 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 0xfffe1020165c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 0xfffe10201660 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 0xfffe10201664 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 0xfffe10201668 +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 0xfffe1020166c +#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 0xfffe10201670 + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp +// base address: 0xfffe10202000 +#define cfgBIF_CFG_DEV0_EPF2_1_VENDOR_ID 0xfffe10202000 +#define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_ID 0xfffe10202002 +#define cfgBIF_CFG_DEV0_EPF2_1_COMMAND 0xfffe10202004 +#define cfgBIF_CFG_DEV0_EPF2_1_STATUS 0xfffe10202006 +#define cfgBIF_CFG_DEV0_EPF2_1_REVISION_ID 0xfffe10202008 +#define cfgBIF_CFG_DEV0_EPF2_1_PROG_INTERFACE 0xfffe10202009 +#define cfgBIF_CFG_DEV0_EPF2_1_SUB_CLASS 0xfffe1020200a +#define cfgBIF_CFG_DEV0_EPF2_1_BASE_CLASS 0xfffe1020200b +#define cfgBIF_CFG_DEV0_EPF2_1_CACHE_LINE 0xfffe1020200c +#define cfgBIF_CFG_DEV0_EPF2_1_LATENCY 0xfffe1020200d +#define cfgBIF_CFG_DEV0_EPF2_1_HEADER 0xfffe1020200e +#define cfgBIF_CFG_DEV0_EPF2_1_BIST 0xfffe1020200f +#define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_1 0xfffe10202010 +#define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_2 0xfffe10202014 +#define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_3 0xfffe10202018 +#define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_4 0xfffe1020201c +#define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_5 0xfffe10202020 +#define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_6 0xfffe10202024 +#define cfgBIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR 0xfffe10202028 +#define cfgBIF_CFG_DEV0_EPF2_1_ADAPTER_ID 0xfffe1020202c +#define cfgBIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR 0xfffe10202030 +#define cfgBIF_CFG_DEV0_EPF2_1_CAP_PTR 0xfffe10202034 +#define cfgBIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE 0xfffe1020203c +#define cfgBIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN 0xfffe1020203d +#define cfgBIF_CFG_DEV0_EPF2_1_MIN_GRANT 0xfffe1020203e +#define cfgBIF_CFG_DEV0_EPF2_1_MAX_LATENCY 0xfffe1020203f +#define cfgBIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST 0xfffe10202048 +#define cfgBIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W 0xfffe1020204c +#define cfgBIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST 0xfffe10202050 +#define cfgBIF_CFG_DEV0_EPF2_1_PMI_CAP 0xfffe10202052 +#define cfgBIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL 0xfffe10202054 +#define cfgBIF_CFG_DEV0_EPF2_1_SBRN 0xfffe10202060 +#define cfgBIF_CFG_DEV0_EPF2_1_FLADJ 0xfffe10202061 +#define cfgBIF_CFG_DEV0_EPF2_1_DBESL_DBESLD 0xfffe10202062 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST 0xfffe10202064 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CAP 0xfffe10202066 +#define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CAP 0xfffe10202068 +#define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL 0xfffe1020206c +#define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS 0xfffe1020206e +#define cfgBIF_CFG_DEV0_EPF2_1_LINK_CAP 0xfffe10202070 +#define cfgBIF_CFG_DEV0_EPF2_1_LINK_CNTL 0xfffe10202074 +#define cfgBIF_CFG_DEV0_EPF2_1_LINK_STATUS 0xfffe10202076 +#define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CAP2 0xfffe10202088 +#define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2 0xfffe1020208c +#define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2 0xfffe1020208e +#define cfgBIF_CFG_DEV0_EPF2_1_LINK_CAP2 0xfffe10202090 +#define cfgBIF_CFG_DEV0_EPF2_1_LINK_CNTL2 0xfffe10202094 +#define cfgBIF_CFG_DEV0_EPF2_1_LINK_STATUS2 0xfffe10202096 +#define cfgBIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST 0xfffe102020a0 +#define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL 0xfffe102020a2 +#define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO 0xfffe102020a4 +#define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI 0xfffe102020a8 +#define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA 0xfffe102020a8 +#define cfgBIF_CFG_DEV0_EPF2_1_MSI_MASK 0xfffe102020ac +#define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64 0xfffe102020ac +#define cfgBIF_CFG_DEV0_EPF2_1_MSI_MASK_64 0xfffe102020b0 +#define cfgBIF_CFG_DEV0_EPF2_1_MSI_PENDING 0xfffe102020b0 +#define cfgBIF_CFG_DEV0_EPF2_1_MSI_PENDING_64 0xfffe102020b4 +#define cfgBIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST 0xfffe102020c0 +#define cfgBIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL 0xfffe102020c2 +#define cfgBIF_CFG_DEV0_EPF2_1_MSIX_TABLE 0xfffe102020c4 +#define cfgBIF_CFG_DEV0_EPF2_1_MSIX_PBA 0xfffe102020c8 +#define cfgBIF_CFG_DEV0_EPF2_1_SATA_CAP_0 0xfffe102020d0 +#define cfgBIF_CFG_DEV0_EPF2_1_SATA_CAP_1 0xfffe102020d4 +#define cfgBIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX 0xfffe102020d8 +#define cfgBIF_CFG_DEV0_EPF2_1_SATA_IDP_DATA 0xfffe102020dc +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10202100 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10202104 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1 0xfffe10202108 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2 0xfffe1020210c +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10202150 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS 0xfffe10202154 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK 0xfffe10202158 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1020215c +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS 0xfffe10202160 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK 0xfffe10202164 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10202168 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0 0xfffe1020216c +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1 0xfffe10202170 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2 0xfffe10202174 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3 0xfffe10202178 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0 0xfffe10202188 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1 0xfffe1020218c +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2 0xfffe10202190 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3 0xfffe10202194 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST 0xfffe10202200 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP 0xfffe10202204 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL 0xfffe10202208 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP 0xfffe1020220c +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL 0xfffe10202210 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP 0xfffe10202214 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL 0xfffe10202218 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP 0xfffe1020221c +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL 0xfffe10202220 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP 0xfffe10202224 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL 0xfffe10202228 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP 0xfffe1020222c +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL 0xfffe10202230 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0xfffe10202240 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT 0xfffe10202244 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA 0xfffe10202248 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP 0xfffe1020224c +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST 0xfffe10202250 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP 0xfffe10202254 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR 0xfffe10202258 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS 0xfffe1020225c +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL 0xfffe1020225e +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0xfffe10202260 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0xfffe10202261 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0xfffe10202262 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0xfffe10202263 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0xfffe10202264 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0xfffe10202265 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0xfffe10202266 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0xfffe10202267 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST 0xfffe102022a0 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP 0xfffe102022a4 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL 0xfffe102022a6 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST 0xfffe102022d0 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP 0xfffe102022d4 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL 0xfffe102022d6 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10202328 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP 0xfffe1020232c +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL 0xfffe1020232e +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST 0xfffe10202370 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP 0xfffe10202374 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL 0xfffe10202378 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0 0xfffe1020237c +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1 0xfffe1020237e +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2 0xfffe10202380 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3 0xfffe10202382 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4 0xfffe10202384 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5 0xfffe10202386 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6 0xfffe10202388 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7 0xfffe1020238a +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8 0xfffe1020238c +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9 0xfffe1020238e +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10 0xfffe10202390 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11 0xfffe10202392 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12 0xfffe10202394 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13 0xfffe10202396 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14 0xfffe10202398 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15 0xfffe1020239a +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16 0xfffe1020239c +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17 0xfffe1020239e +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18 0xfffe102023a0 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19 0xfffe102023a2 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20 0xfffe102023a4 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21 0xfffe102023a6 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22 0xfffe102023a8 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23 0xfffe102023aa +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24 0xfffe102023ac +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25 0xfffe102023ae +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26 0xfffe102023b0 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27 0xfffe102023b2 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28 0xfffe102023b4 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29 0xfffe102023b6 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30 0xfffe102023b8 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31 0xfffe102023ba +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32 0xfffe102023bc +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33 0xfffe102023be +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34 0xfffe102023c0 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35 0xfffe102023c2 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36 0xfffe102023c4 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37 0xfffe102023c6 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38 0xfffe102023c8 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39 0xfffe102023ca +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40 0xfffe102023cc +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41 0xfffe102023ce +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42 0xfffe102023d0 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43 0xfffe102023d2 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44 0xfffe102023d4 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45 0xfffe102023d6 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46 0xfffe102023d8 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47 0xfffe102023da +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48 0xfffe102023dc +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49 0xfffe102023de +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50 0xfffe102023e0 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51 0xfffe102023e2 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52 0xfffe102023e4 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53 0xfffe102023e6 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54 0xfffe102023e8 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55 0xfffe102023ea +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56 0xfffe102023ec +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57 0xfffe102023ee +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58 0xfffe102023f0 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59 0xfffe102023f2 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60 0xfffe102023f4 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61 0xfffe102023f6 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62 0xfffe102023f8 +#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63 0xfffe102023fa + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp +// base address: 0xfffe10203000 +#define cfgBIF_CFG_DEV0_EPF3_1_VENDOR_ID 0xfffe10203000 +#define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_ID 0xfffe10203002 +#define cfgBIF_CFG_DEV0_EPF3_1_COMMAND 0xfffe10203004 +#define cfgBIF_CFG_DEV0_EPF3_1_STATUS 0xfffe10203006 +#define cfgBIF_CFG_DEV0_EPF3_1_REVISION_ID 0xfffe10203008 +#define cfgBIF_CFG_DEV0_EPF3_1_PROG_INTERFACE 0xfffe10203009 +#define cfgBIF_CFG_DEV0_EPF3_1_SUB_CLASS 0xfffe1020300a +#define cfgBIF_CFG_DEV0_EPF3_1_BASE_CLASS 0xfffe1020300b +#define cfgBIF_CFG_DEV0_EPF3_1_CACHE_LINE 0xfffe1020300c +#define cfgBIF_CFG_DEV0_EPF3_1_LATENCY 0xfffe1020300d +#define cfgBIF_CFG_DEV0_EPF3_1_HEADER 0xfffe1020300e +#define cfgBIF_CFG_DEV0_EPF3_1_BIST 0xfffe1020300f +#define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_1 0xfffe10203010 +#define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_2 0xfffe10203014 +#define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_3 0xfffe10203018 +#define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_4 0xfffe1020301c +#define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_5 0xfffe10203020 +#define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_6 0xfffe10203024 +#define cfgBIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR 0xfffe10203028 +#define cfgBIF_CFG_DEV0_EPF3_1_ADAPTER_ID 0xfffe1020302c +#define cfgBIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR 0xfffe10203030 +#define cfgBIF_CFG_DEV0_EPF3_1_CAP_PTR 0xfffe10203034 +#define cfgBIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE 0xfffe1020303c +#define cfgBIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN 0xfffe1020303d +#define cfgBIF_CFG_DEV0_EPF3_1_MIN_GRANT 0xfffe1020303e +#define cfgBIF_CFG_DEV0_EPF3_1_MAX_LATENCY 0xfffe1020303f +#define cfgBIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST 0xfffe10203048 +#define cfgBIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W 0xfffe1020304c +#define cfgBIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST 0xfffe10203050 +#define cfgBIF_CFG_DEV0_EPF3_1_PMI_CAP 0xfffe10203052 +#define cfgBIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL 0xfffe10203054 +#define cfgBIF_CFG_DEV0_EPF3_1_SBRN 0xfffe10203060 +#define cfgBIF_CFG_DEV0_EPF3_1_FLADJ 0xfffe10203061 +#define cfgBIF_CFG_DEV0_EPF3_1_DBESL_DBESLD 0xfffe10203062 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST 0xfffe10203064 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CAP 0xfffe10203066 +#define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CAP 0xfffe10203068 +#define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL 0xfffe1020306c +#define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS 0xfffe1020306e +#define cfgBIF_CFG_DEV0_EPF3_1_LINK_CAP 0xfffe10203070 +#define cfgBIF_CFG_DEV0_EPF3_1_LINK_CNTL 0xfffe10203074 +#define cfgBIF_CFG_DEV0_EPF3_1_LINK_STATUS 0xfffe10203076 +#define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CAP2 0xfffe10203088 +#define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2 0xfffe1020308c +#define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2 0xfffe1020308e +#define cfgBIF_CFG_DEV0_EPF3_1_LINK_CAP2 0xfffe10203090 +#define cfgBIF_CFG_DEV0_EPF3_1_LINK_CNTL2 0xfffe10203094 +#define cfgBIF_CFG_DEV0_EPF3_1_LINK_STATUS2 0xfffe10203096 +#define cfgBIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST 0xfffe102030a0 +#define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL 0xfffe102030a2 +#define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO 0xfffe102030a4 +#define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI 0xfffe102030a8 +#define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA 0xfffe102030a8 +#define cfgBIF_CFG_DEV0_EPF3_1_MSI_MASK 0xfffe102030ac +#define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64 0xfffe102030ac +#define cfgBIF_CFG_DEV0_EPF3_1_MSI_MASK_64 0xfffe102030b0 +#define cfgBIF_CFG_DEV0_EPF3_1_MSI_PENDING 0xfffe102030b0 +#define cfgBIF_CFG_DEV0_EPF3_1_MSI_PENDING_64 0xfffe102030b4 +#define cfgBIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST 0xfffe102030c0 +#define cfgBIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL 0xfffe102030c2 +#define cfgBIF_CFG_DEV0_EPF3_1_MSIX_TABLE 0xfffe102030c4 +#define cfgBIF_CFG_DEV0_EPF3_1_MSIX_PBA 0xfffe102030c8 +#define cfgBIF_CFG_DEV0_EPF3_1_SATA_CAP_0 0xfffe102030d0 +#define cfgBIF_CFG_DEV0_EPF3_1_SATA_CAP_1 0xfffe102030d4 +#define cfgBIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX 0xfffe102030d8 +#define cfgBIF_CFG_DEV0_EPF3_1_SATA_IDP_DATA 0xfffe102030dc +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10203100 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10203104 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1 0xfffe10203108 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2 0xfffe1020310c +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10203150 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS 0xfffe10203154 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK 0xfffe10203158 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1020315c +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS 0xfffe10203160 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK 0xfffe10203164 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10203168 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0 0xfffe1020316c +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1 0xfffe10203170 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2 0xfffe10203174 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3 0xfffe10203178 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0 0xfffe10203188 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1 0xfffe1020318c +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2 0xfffe10203190 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3 0xfffe10203194 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST 0xfffe10203200 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP 0xfffe10203204 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL 0xfffe10203208 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP 0xfffe1020320c +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL 0xfffe10203210 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP 0xfffe10203214 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL 0xfffe10203218 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP 0xfffe1020321c +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL 0xfffe10203220 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP 0xfffe10203224 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL 0xfffe10203228 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP 0xfffe1020322c +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL 0xfffe10203230 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0xfffe10203240 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT 0xfffe10203244 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA 0xfffe10203248 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP 0xfffe1020324c +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST 0xfffe10203250 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP 0xfffe10203254 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR 0xfffe10203258 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS 0xfffe1020325c +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL 0xfffe1020325e +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0xfffe10203260 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0xfffe10203261 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0xfffe10203262 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0xfffe10203263 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0xfffe10203264 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0xfffe10203265 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0xfffe10203266 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0xfffe10203267 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST 0xfffe102032a0 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP 0xfffe102032a4 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL 0xfffe102032a6 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST 0xfffe102032d0 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP 0xfffe102032d4 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL 0xfffe102032d6 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10203328 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP 0xfffe1020332c +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL 0xfffe1020332e +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST 0xfffe10203370 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP 0xfffe10203374 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL 0xfffe10203378 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0 0xfffe1020337c +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1 0xfffe1020337e +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2 0xfffe10203380 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3 0xfffe10203382 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4 0xfffe10203384 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5 0xfffe10203386 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6 0xfffe10203388 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7 0xfffe1020338a +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8 0xfffe1020338c +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9 0xfffe1020338e +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10 0xfffe10203390 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11 0xfffe10203392 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12 0xfffe10203394 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13 0xfffe10203396 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14 0xfffe10203398 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15 0xfffe1020339a +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16 0xfffe1020339c +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17 0xfffe1020339e +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18 0xfffe102033a0 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19 0xfffe102033a2 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20 0xfffe102033a4 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21 0xfffe102033a6 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22 0xfffe102033a8 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23 0xfffe102033aa +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24 0xfffe102033ac +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25 0xfffe102033ae +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26 0xfffe102033b0 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27 0xfffe102033b2 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28 0xfffe102033b4 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29 0xfffe102033b6 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30 0xfffe102033b8 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31 0xfffe102033ba +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32 0xfffe102033bc +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33 0xfffe102033be +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34 0xfffe102033c0 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35 0xfffe102033c2 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36 0xfffe102033c4 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37 0xfffe102033c6 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38 0xfffe102033c8 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39 0xfffe102033ca +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40 0xfffe102033cc +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41 0xfffe102033ce +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42 0xfffe102033d0 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43 0xfffe102033d2 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44 0xfffe102033d4 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45 0xfffe102033d6 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46 0xfffe102033d8 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47 0xfffe102033da +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48 0xfffe102033dc +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49 0xfffe102033de +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50 0xfffe102033e0 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51 0xfffe102033e2 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52 0xfffe102033e4 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53 0xfffe102033e6 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54 0xfffe102033e8 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55 0xfffe102033ea +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56 0xfffe102033ec +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57 0xfffe102033ee +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58 0xfffe102033f0 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59 0xfffe102033f2 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60 0xfffe102033f4 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61 0xfffe102033f6 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62 0xfffe102033f8 +#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63 0xfffe102033fa + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp +// base address: 0xfffe10300000 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID 0xfffe10300000 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID 0xfffe10300002 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_COMMAND 0xfffe10300004 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_STATUS 0xfffe10300006 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID 0xfffe10300008 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE 0xfffe10300009 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS 0xfffe1030000a +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS 0xfffe1030000b +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE 0xfffe1030000c +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_LATENCY 0xfffe1030000d +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_HEADER 0xfffe1030000e +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_BIST 0xfffe1030000f +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1 0xfffe10300010 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2 0xfffe10300014 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3 0xfffe10300018 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4 0xfffe1030001c +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5 0xfffe10300020 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6 0xfffe10300024 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_CARDBUS_CIS_PTR 0xfffe10300028 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID 0xfffe1030002c +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR 0xfffe10300030 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR 0xfffe10300034 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE 0xfffe1030003c +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN 0xfffe1030003d +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MIN_GRANT 0xfffe1030003e +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MAX_LATENCY 0xfffe1030003f +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST 0xfffe10300064 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP 0xfffe10300066 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP 0xfffe10300068 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL 0xfffe1030006c +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS 0xfffe1030006e +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP 0xfffe10300070 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL 0xfffe10300074 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS 0xfffe10300076 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2 0xfffe10300088 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2 0xfffe1030008c +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2 0xfffe1030008e +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2 0xfffe10300090 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2 0xfffe10300094 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2 0xfffe10300096 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST 0xfffe103000a0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL 0xfffe103000a2 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO 0xfffe103000a4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI 0xfffe103000a8 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA 0xfffe103000a8 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK 0xfffe103000ac +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64 0xfffe103000ac +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64 0xfffe103000b0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING 0xfffe103000b0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64 0xfffe103000b4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST 0xfffe103000c0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL 0xfffe103000c2 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE 0xfffe103000c4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA 0xfffe103000c8 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10300100 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10300104 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1 0xfffe10300108 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030010c +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10300150 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS 0xfffe10300154 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK 0xfffe10300158 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030015c +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS 0xfffe10300160 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK 0xfffe10300164 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10300168 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0 0xfffe1030016c +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1 0xfffe10300170 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2 0xfffe10300174 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3 0xfffe10300178 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0 0xfffe10300188 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030018c +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2 0xfffe10300190 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3 0xfffe10300194 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103002b0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP 0xfffe103002b4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL 0xfffe103002b6 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10300328 +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP 0xfffe1030032c +#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL 0xfffe1030032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp +// base address: 0xfffe10301000 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID 0xfffe10301000 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID 0xfffe10301002 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_COMMAND 0xfffe10301004 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_STATUS 0xfffe10301006 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID 0xfffe10301008 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE 0xfffe10301009 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS 0xfffe1030100a +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS 0xfffe1030100b +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE 0xfffe1030100c +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_LATENCY 0xfffe1030100d +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_HEADER 0xfffe1030100e +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_BIST 0xfffe1030100f +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1 0xfffe10301010 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2 0xfffe10301014 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3 0xfffe10301018 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4 0xfffe1030101c +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5 0xfffe10301020 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6 0xfffe10301024 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_CARDBUS_CIS_PTR 0xfffe10301028 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID 0xfffe1030102c +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR 0xfffe10301030 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR 0xfffe10301034 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE 0xfffe1030103c +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN 0xfffe1030103d +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MIN_GRANT 0xfffe1030103e +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MAX_LATENCY 0xfffe1030103f +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST 0xfffe10301064 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP 0xfffe10301066 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP 0xfffe10301068 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL 0xfffe1030106c +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS 0xfffe1030106e +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP 0xfffe10301070 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL 0xfffe10301074 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS 0xfffe10301076 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2 0xfffe10301088 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2 0xfffe1030108c +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2 0xfffe1030108e +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2 0xfffe10301090 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2 0xfffe10301094 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2 0xfffe10301096 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST 0xfffe103010a0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL 0xfffe103010a2 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO 0xfffe103010a4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI 0xfffe103010a8 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA 0xfffe103010a8 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK 0xfffe103010ac +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64 0xfffe103010ac +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64 0xfffe103010b0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING 0xfffe103010b0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64 0xfffe103010b4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST 0xfffe103010c0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL 0xfffe103010c2 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE 0xfffe103010c4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA 0xfffe103010c8 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10301100 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10301104 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1 0xfffe10301108 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030110c +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10301150 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS 0xfffe10301154 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK 0xfffe10301158 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030115c +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS 0xfffe10301160 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK 0xfffe10301164 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10301168 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0 0xfffe1030116c +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1 0xfffe10301170 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2 0xfffe10301174 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3 0xfffe10301178 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0 0xfffe10301188 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030118c +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2 0xfffe10301190 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3 0xfffe10301194 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103012b0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP 0xfffe103012b4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL 0xfffe103012b6 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10301328 +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP 0xfffe1030132c +#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL 0xfffe1030132e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp +// base address: 0xfffe10302000 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID 0xfffe10302000 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID 0xfffe10302002 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_COMMAND 0xfffe10302004 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_STATUS 0xfffe10302006 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID 0xfffe10302008 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE 0xfffe10302009 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS 0xfffe1030200a +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS 0xfffe1030200b +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE 0xfffe1030200c +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_LATENCY 0xfffe1030200d +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_HEADER 0xfffe1030200e +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_BIST 0xfffe1030200f +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1 0xfffe10302010 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2 0xfffe10302014 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3 0xfffe10302018 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4 0xfffe1030201c +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5 0xfffe10302020 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6 0xfffe10302024 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_CARDBUS_CIS_PTR 0xfffe10302028 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID 0xfffe1030202c +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR 0xfffe10302030 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR 0xfffe10302034 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE 0xfffe1030203c +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN 0xfffe1030203d +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MIN_GRANT 0xfffe1030203e +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MAX_LATENCY 0xfffe1030203f +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST 0xfffe10302064 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP 0xfffe10302066 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP 0xfffe10302068 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL 0xfffe1030206c +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS 0xfffe1030206e +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP 0xfffe10302070 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL 0xfffe10302074 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS 0xfffe10302076 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2 0xfffe10302088 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2 0xfffe1030208c +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2 0xfffe1030208e +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2 0xfffe10302090 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2 0xfffe10302094 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2 0xfffe10302096 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST 0xfffe103020a0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL 0xfffe103020a2 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO 0xfffe103020a4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI 0xfffe103020a8 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA 0xfffe103020a8 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK 0xfffe103020ac +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64 0xfffe103020ac +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64 0xfffe103020b0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING 0xfffe103020b0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64 0xfffe103020b4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST 0xfffe103020c0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL 0xfffe103020c2 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE 0xfffe103020c4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA 0xfffe103020c8 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10302100 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10302104 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1 0xfffe10302108 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030210c +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10302150 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS 0xfffe10302154 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK 0xfffe10302158 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030215c +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS 0xfffe10302160 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK 0xfffe10302164 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10302168 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0 0xfffe1030216c +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1 0xfffe10302170 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2 0xfffe10302174 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3 0xfffe10302178 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0 0xfffe10302188 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030218c +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2 0xfffe10302190 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3 0xfffe10302194 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103022b0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP 0xfffe103022b4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL 0xfffe103022b6 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10302328 +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP 0xfffe1030232c +#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL 0xfffe1030232e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp +// base address: 0xfffe10303000 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID 0xfffe10303000 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID 0xfffe10303002 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_COMMAND 0xfffe10303004 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_STATUS 0xfffe10303006 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID 0xfffe10303008 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE 0xfffe10303009 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS 0xfffe1030300a +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS 0xfffe1030300b +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE 0xfffe1030300c +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_LATENCY 0xfffe1030300d +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_HEADER 0xfffe1030300e +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_BIST 0xfffe1030300f +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1 0xfffe10303010 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2 0xfffe10303014 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3 0xfffe10303018 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4 0xfffe1030301c +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5 0xfffe10303020 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6 0xfffe10303024 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_CARDBUS_CIS_PTR 0xfffe10303028 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID 0xfffe1030302c +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR 0xfffe10303030 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR 0xfffe10303034 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE 0xfffe1030303c +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN 0xfffe1030303d +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MIN_GRANT 0xfffe1030303e +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MAX_LATENCY 0xfffe1030303f +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST 0xfffe10303064 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP 0xfffe10303066 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP 0xfffe10303068 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL 0xfffe1030306c +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS 0xfffe1030306e +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP 0xfffe10303070 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL 0xfffe10303074 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS 0xfffe10303076 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2 0xfffe10303088 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2 0xfffe1030308c +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2 0xfffe1030308e +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2 0xfffe10303090 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2 0xfffe10303094 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2 0xfffe10303096 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST 0xfffe103030a0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL 0xfffe103030a2 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO 0xfffe103030a4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI 0xfffe103030a8 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA 0xfffe103030a8 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK 0xfffe103030ac +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64 0xfffe103030ac +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64 0xfffe103030b0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING 0xfffe103030b0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64 0xfffe103030b4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST 0xfffe103030c0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL 0xfffe103030c2 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE 0xfffe103030c4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA 0xfffe103030c8 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10303100 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10303104 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1 0xfffe10303108 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030310c +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10303150 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS 0xfffe10303154 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK 0xfffe10303158 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030315c +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS 0xfffe10303160 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK 0xfffe10303164 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10303168 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0 0xfffe1030316c +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1 0xfffe10303170 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2 0xfffe10303174 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3 0xfffe10303178 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0 0xfffe10303188 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030318c +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2 0xfffe10303190 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3 0xfffe10303194 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103032b0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP 0xfffe103032b4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL 0xfffe103032b6 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10303328 +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP 0xfffe1030332c +#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL 0xfffe1030332e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp +// base address: 0xfffe10304000 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID 0xfffe10304000 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID 0xfffe10304002 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_COMMAND 0xfffe10304004 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_STATUS 0xfffe10304006 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID 0xfffe10304008 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE 0xfffe10304009 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS 0xfffe1030400a +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS 0xfffe1030400b +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE 0xfffe1030400c +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_LATENCY 0xfffe1030400d +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_HEADER 0xfffe1030400e +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_BIST 0xfffe1030400f +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1 0xfffe10304010 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2 0xfffe10304014 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3 0xfffe10304018 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4 0xfffe1030401c +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5 0xfffe10304020 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6 0xfffe10304024 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_CARDBUS_CIS_PTR 0xfffe10304028 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID 0xfffe1030402c +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR 0xfffe10304030 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR 0xfffe10304034 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE 0xfffe1030403c +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN 0xfffe1030403d +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MIN_GRANT 0xfffe1030403e +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MAX_LATENCY 0xfffe1030403f +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST 0xfffe10304064 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP 0xfffe10304066 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP 0xfffe10304068 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL 0xfffe1030406c +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS 0xfffe1030406e +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP 0xfffe10304070 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL 0xfffe10304074 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS 0xfffe10304076 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2 0xfffe10304088 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2 0xfffe1030408c +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2 0xfffe1030408e +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2 0xfffe10304090 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2 0xfffe10304094 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2 0xfffe10304096 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST 0xfffe103040a0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL 0xfffe103040a2 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO 0xfffe103040a4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI 0xfffe103040a8 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA 0xfffe103040a8 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK 0xfffe103040ac +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64 0xfffe103040ac +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64 0xfffe103040b0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING 0xfffe103040b0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64 0xfffe103040b4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST 0xfffe103040c0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL 0xfffe103040c2 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE 0xfffe103040c4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA 0xfffe103040c8 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10304100 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10304104 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1 0xfffe10304108 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030410c +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10304150 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS 0xfffe10304154 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK 0xfffe10304158 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030415c +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS 0xfffe10304160 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK 0xfffe10304164 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10304168 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0 0xfffe1030416c +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1 0xfffe10304170 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2 0xfffe10304174 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3 0xfffe10304178 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0 0xfffe10304188 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030418c +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2 0xfffe10304190 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3 0xfffe10304194 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103042b0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP 0xfffe103042b4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL 0xfffe103042b6 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10304328 +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP 0xfffe1030432c +#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL 0xfffe1030432e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp +// base address: 0xfffe10305000 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID 0xfffe10305000 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID 0xfffe10305002 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_COMMAND 0xfffe10305004 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_STATUS 0xfffe10305006 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID 0xfffe10305008 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE 0xfffe10305009 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS 0xfffe1030500a +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS 0xfffe1030500b +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE 0xfffe1030500c +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_LATENCY 0xfffe1030500d +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_HEADER 0xfffe1030500e +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_BIST 0xfffe1030500f +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1 0xfffe10305010 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2 0xfffe10305014 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3 0xfffe10305018 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4 0xfffe1030501c +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5 0xfffe10305020 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6 0xfffe10305024 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_CARDBUS_CIS_PTR 0xfffe10305028 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID 0xfffe1030502c +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR 0xfffe10305030 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR 0xfffe10305034 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE 0xfffe1030503c +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN 0xfffe1030503d +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MIN_GRANT 0xfffe1030503e +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MAX_LATENCY 0xfffe1030503f +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST 0xfffe10305064 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP 0xfffe10305066 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP 0xfffe10305068 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL 0xfffe1030506c +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS 0xfffe1030506e +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP 0xfffe10305070 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL 0xfffe10305074 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS 0xfffe10305076 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2 0xfffe10305088 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2 0xfffe1030508c +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2 0xfffe1030508e +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2 0xfffe10305090 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2 0xfffe10305094 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2 0xfffe10305096 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST 0xfffe103050a0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL 0xfffe103050a2 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO 0xfffe103050a4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI 0xfffe103050a8 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA 0xfffe103050a8 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK 0xfffe103050ac +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64 0xfffe103050ac +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64 0xfffe103050b0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING 0xfffe103050b0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64 0xfffe103050b4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST 0xfffe103050c0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL 0xfffe103050c2 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE 0xfffe103050c4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA 0xfffe103050c8 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10305100 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10305104 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1 0xfffe10305108 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030510c +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10305150 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS 0xfffe10305154 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK 0xfffe10305158 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030515c +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS 0xfffe10305160 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK 0xfffe10305164 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10305168 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0 0xfffe1030516c +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1 0xfffe10305170 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2 0xfffe10305174 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3 0xfffe10305178 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0 0xfffe10305188 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030518c +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2 0xfffe10305190 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3 0xfffe10305194 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103052b0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP 0xfffe103052b4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL 0xfffe103052b6 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10305328 +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP 0xfffe1030532c +#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL 0xfffe1030532e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp +// base address: 0xfffe10306000 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID 0xfffe10306000 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID 0xfffe10306002 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_COMMAND 0xfffe10306004 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_STATUS 0xfffe10306006 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID 0xfffe10306008 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE 0xfffe10306009 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS 0xfffe1030600a +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS 0xfffe1030600b +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE 0xfffe1030600c +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_LATENCY 0xfffe1030600d +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_HEADER 0xfffe1030600e +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_BIST 0xfffe1030600f +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1 0xfffe10306010 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2 0xfffe10306014 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3 0xfffe10306018 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4 0xfffe1030601c +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5 0xfffe10306020 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6 0xfffe10306024 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_CARDBUS_CIS_PTR 0xfffe10306028 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID 0xfffe1030602c +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR 0xfffe10306030 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR 0xfffe10306034 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE 0xfffe1030603c +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN 0xfffe1030603d +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MIN_GRANT 0xfffe1030603e +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MAX_LATENCY 0xfffe1030603f +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST 0xfffe10306064 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP 0xfffe10306066 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP 0xfffe10306068 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL 0xfffe1030606c +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS 0xfffe1030606e +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP 0xfffe10306070 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL 0xfffe10306074 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS 0xfffe10306076 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2 0xfffe10306088 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2 0xfffe1030608c +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2 0xfffe1030608e +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2 0xfffe10306090 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2 0xfffe10306094 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2 0xfffe10306096 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST 0xfffe103060a0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL 0xfffe103060a2 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO 0xfffe103060a4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI 0xfffe103060a8 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA 0xfffe103060a8 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK 0xfffe103060ac +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64 0xfffe103060ac +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64 0xfffe103060b0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING 0xfffe103060b0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64 0xfffe103060b4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST 0xfffe103060c0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL 0xfffe103060c2 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE 0xfffe103060c4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA 0xfffe103060c8 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10306100 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10306104 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1 0xfffe10306108 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030610c +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10306150 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS 0xfffe10306154 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK 0xfffe10306158 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030615c +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS 0xfffe10306160 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK 0xfffe10306164 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10306168 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0 0xfffe1030616c +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1 0xfffe10306170 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2 0xfffe10306174 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3 0xfffe10306178 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0 0xfffe10306188 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030618c +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2 0xfffe10306190 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3 0xfffe10306194 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103062b0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP 0xfffe103062b4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL 0xfffe103062b6 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10306328 +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP 0xfffe1030632c +#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL 0xfffe1030632e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp +// base address: 0xfffe10307000 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID 0xfffe10307000 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID 0xfffe10307002 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_COMMAND 0xfffe10307004 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_STATUS 0xfffe10307006 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID 0xfffe10307008 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE 0xfffe10307009 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS 0xfffe1030700a +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS 0xfffe1030700b +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE 0xfffe1030700c +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_LATENCY 0xfffe1030700d +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_HEADER 0xfffe1030700e +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_BIST 0xfffe1030700f +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1 0xfffe10307010 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2 0xfffe10307014 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3 0xfffe10307018 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4 0xfffe1030701c +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5 0xfffe10307020 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6 0xfffe10307024 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_CARDBUS_CIS_PTR 0xfffe10307028 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID 0xfffe1030702c +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR 0xfffe10307030 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR 0xfffe10307034 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE 0xfffe1030703c +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN 0xfffe1030703d +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MIN_GRANT 0xfffe1030703e +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MAX_LATENCY 0xfffe1030703f +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST 0xfffe10307064 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP 0xfffe10307066 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP 0xfffe10307068 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL 0xfffe1030706c +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS 0xfffe1030706e +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP 0xfffe10307070 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL 0xfffe10307074 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS 0xfffe10307076 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2 0xfffe10307088 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2 0xfffe1030708c +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2 0xfffe1030708e +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2 0xfffe10307090 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2 0xfffe10307094 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2 0xfffe10307096 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST 0xfffe103070a0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL 0xfffe103070a2 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO 0xfffe103070a4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI 0xfffe103070a8 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA 0xfffe103070a8 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK 0xfffe103070ac +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64 0xfffe103070ac +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64 0xfffe103070b0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING 0xfffe103070b0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64 0xfffe103070b4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST 0xfffe103070c0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL 0xfffe103070c2 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE 0xfffe103070c4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA 0xfffe103070c8 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10307100 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10307104 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1 0xfffe10307108 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030710c +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10307150 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS 0xfffe10307154 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK 0xfffe10307158 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030715c +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS 0xfffe10307160 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK 0xfffe10307164 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10307168 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0 0xfffe1030716c +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1 0xfffe10307170 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2 0xfffe10307174 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3 0xfffe10307178 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0 0xfffe10307188 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030718c +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2 0xfffe10307190 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3 0xfffe10307194 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103072b0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP 0xfffe103072b4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL 0xfffe103072b6 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10307328 +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP 0xfffe1030732c +#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL 0xfffe1030732e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp +// base address: 0xfffe10308000 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID 0xfffe10308000 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID 0xfffe10308002 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_COMMAND 0xfffe10308004 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_STATUS 0xfffe10308006 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID 0xfffe10308008 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE 0xfffe10308009 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS 0xfffe1030800a +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS 0xfffe1030800b +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE 0xfffe1030800c +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_LATENCY 0xfffe1030800d +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_HEADER 0xfffe1030800e +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_BIST 0xfffe1030800f +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1 0xfffe10308010 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2 0xfffe10308014 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3 0xfffe10308018 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4 0xfffe1030801c +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5 0xfffe10308020 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6 0xfffe10308024 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_CARDBUS_CIS_PTR 0xfffe10308028 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID 0xfffe1030802c +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR 0xfffe10308030 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR 0xfffe10308034 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE 0xfffe1030803c +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN 0xfffe1030803d +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MIN_GRANT 0xfffe1030803e +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MAX_LATENCY 0xfffe1030803f +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST 0xfffe10308064 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP 0xfffe10308066 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP 0xfffe10308068 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL 0xfffe1030806c +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS 0xfffe1030806e +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP 0xfffe10308070 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL 0xfffe10308074 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS 0xfffe10308076 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2 0xfffe10308088 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2 0xfffe1030808c +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2 0xfffe1030808e +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2 0xfffe10308090 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2 0xfffe10308094 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2 0xfffe10308096 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST 0xfffe103080a0 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL 0xfffe103080a2 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO 0xfffe103080a4 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI 0xfffe103080a8 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA 0xfffe103080a8 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK 0xfffe103080ac +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64 0xfffe103080ac +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64 0xfffe103080b0 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING 0xfffe103080b0 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64 0xfffe103080b4 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST 0xfffe103080c0 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL 0xfffe103080c2 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE 0xfffe103080c4 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA 0xfffe103080c8 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10308100 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10308104 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1 0xfffe10308108 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030810c +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10308150 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS 0xfffe10308154 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK 0xfffe10308158 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030815c +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS 0xfffe10308160 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK 0xfffe10308164 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10308168 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0 0xfffe1030816c +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1 0xfffe10308170 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2 0xfffe10308174 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3 0xfffe10308178 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0 0xfffe10308188 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030818c +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2 0xfffe10308190 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3 0xfffe10308194 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103082b0 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP 0xfffe103082b4 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL 0xfffe103082b6 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10308328 +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP 0xfffe1030832c +#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL 0xfffe1030832e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp +// base address: 0xfffe10309000 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID 0xfffe10309000 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID 0xfffe10309002 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_COMMAND 0xfffe10309004 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_STATUS 0xfffe10309006 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID 0xfffe10309008 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE 0xfffe10309009 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS 0xfffe1030900a +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS 0xfffe1030900b +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE 0xfffe1030900c +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_LATENCY 0xfffe1030900d +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_HEADER 0xfffe1030900e +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_BIST 0xfffe1030900f +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1 0xfffe10309010 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2 0xfffe10309014 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3 0xfffe10309018 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4 0xfffe1030901c +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5 0xfffe10309020 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6 0xfffe10309024 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_CARDBUS_CIS_PTR 0xfffe10309028 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID 0xfffe1030902c +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR 0xfffe10309030 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR 0xfffe10309034 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE 0xfffe1030903c +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN 0xfffe1030903d +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MIN_GRANT 0xfffe1030903e +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MAX_LATENCY 0xfffe1030903f +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST 0xfffe10309064 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP 0xfffe10309066 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP 0xfffe10309068 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL 0xfffe1030906c +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS 0xfffe1030906e +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP 0xfffe10309070 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL 0xfffe10309074 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS 0xfffe10309076 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2 0xfffe10309088 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2 0xfffe1030908c +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2 0xfffe1030908e +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2 0xfffe10309090 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2 0xfffe10309094 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2 0xfffe10309096 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST 0xfffe103090a0 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL 0xfffe103090a2 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO 0xfffe103090a4 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI 0xfffe103090a8 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA 0xfffe103090a8 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK 0xfffe103090ac +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64 0xfffe103090ac +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64 0xfffe103090b0 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING 0xfffe103090b0 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64 0xfffe103090b4 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST 0xfffe103090c0 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL 0xfffe103090c2 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE 0xfffe103090c4 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA 0xfffe103090c8 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10309100 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10309104 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1 0xfffe10309108 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030910c +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10309150 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS 0xfffe10309154 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK 0xfffe10309158 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030915c +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS 0xfffe10309160 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK 0xfffe10309164 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10309168 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0 0xfffe1030916c +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1 0xfffe10309170 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2 0xfffe10309174 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3 0xfffe10309178 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0 0xfffe10309188 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030918c +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2 0xfffe10309190 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3 0xfffe10309194 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103092b0 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP 0xfffe103092b4 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL 0xfffe103092b6 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10309328 +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP 0xfffe1030932c +#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL 0xfffe1030932e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp +// base address: 0xfffe1030a000 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID 0xfffe1030a000 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID 0xfffe1030a002 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_COMMAND 0xfffe1030a004 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_STATUS 0xfffe1030a006 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID 0xfffe1030a008 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE 0xfffe1030a009 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS 0xfffe1030a00a +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS 0xfffe1030a00b +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE 0xfffe1030a00c +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_LATENCY 0xfffe1030a00d +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_HEADER 0xfffe1030a00e +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_BIST 0xfffe1030a00f +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1 0xfffe1030a010 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2 0xfffe1030a014 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3 0xfffe1030a018 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4 0xfffe1030a01c +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5 0xfffe1030a020 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6 0xfffe1030a024 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_CARDBUS_CIS_PTR 0xfffe1030a028 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID 0xfffe1030a02c +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR 0xfffe1030a030 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR 0xfffe1030a034 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE 0xfffe1030a03c +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN 0xfffe1030a03d +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MIN_GRANT 0xfffe1030a03e +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MAX_LATENCY 0xfffe1030a03f +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST 0xfffe1030a064 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP 0xfffe1030a066 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP 0xfffe1030a068 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL 0xfffe1030a06c +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS 0xfffe1030a06e +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP 0xfffe1030a070 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL 0xfffe1030a074 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS 0xfffe1030a076 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2 0xfffe1030a088 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2 0xfffe1030a08c +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2 0xfffe1030a08e +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2 0xfffe1030a090 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2 0xfffe1030a094 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2 0xfffe1030a096 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST 0xfffe1030a0a0 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL 0xfffe1030a0a2 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO 0xfffe1030a0a4 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI 0xfffe1030a0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA 0xfffe1030a0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK 0xfffe1030a0ac +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64 0xfffe1030a0ac +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64 0xfffe1030a0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING 0xfffe1030a0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64 0xfffe1030a0b4 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST 0xfffe1030a0c0 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL 0xfffe1030a0c2 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE 0xfffe1030a0c4 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA 0xfffe1030a0c8 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030a100 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030a104 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1 0xfffe1030a108 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030a10c +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030a150 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS 0xfffe1030a154 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK 0xfffe1030a158 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030a15c +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS 0xfffe1030a160 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK 0xfffe1030a164 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030a168 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0 0xfffe1030a16c +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1 0xfffe1030a170 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2 0xfffe1030a174 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3 0xfffe1030a178 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0 0xfffe1030a188 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030a18c +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2 0xfffe1030a190 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3 0xfffe1030a194 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1030a2b0 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP 0xfffe1030a2b4 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL 0xfffe1030a2b6 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1030a328 +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP 0xfffe1030a32c +#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL 0xfffe1030a32e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp +// base address: 0xfffe1030b000 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID 0xfffe1030b000 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID 0xfffe1030b002 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_COMMAND 0xfffe1030b004 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_STATUS 0xfffe1030b006 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID 0xfffe1030b008 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE 0xfffe1030b009 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS 0xfffe1030b00a +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS 0xfffe1030b00b +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE 0xfffe1030b00c +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_LATENCY 0xfffe1030b00d +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_HEADER 0xfffe1030b00e +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_BIST 0xfffe1030b00f +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1 0xfffe1030b010 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2 0xfffe1030b014 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3 0xfffe1030b018 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4 0xfffe1030b01c +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5 0xfffe1030b020 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6 0xfffe1030b024 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_CARDBUS_CIS_PTR 0xfffe1030b028 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID 0xfffe1030b02c +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR 0xfffe1030b030 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR 0xfffe1030b034 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE 0xfffe1030b03c +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN 0xfffe1030b03d +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MIN_GRANT 0xfffe1030b03e +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MAX_LATENCY 0xfffe1030b03f +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST 0xfffe1030b064 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP 0xfffe1030b066 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP 0xfffe1030b068 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL 0xfffe1030b06c +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS 0xfffe1030b06e +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP 0xfffe1030b070 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL 0xfffe1030b074 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS 0xfffe1030b076 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2 0xfffe1030b088 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2 0xfffe1030b08c +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2 0xfffe1030b08e +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2 0xfffe1030b090 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2 0xfffe1030b094 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2 0xfffe1030b096 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST 0xfffe1030b0a0 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL 0xfffe1030b0a2 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO 0xfffe1030b0a4 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI 0xfffe1030b0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA 0xfffe1030b0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK 0xfffe1030b0ac +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64 0xfffe1030b0ac +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64 0xfffe1030b0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING 0xfffe1030b0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64 0xfffe1030b0b4 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST 0xfffe1030b0c0 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL 0xfffe1030b0c2 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE 0xfffe1030b0c4 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA 0xfffe1030b0c8 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030b100 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030b104 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1 0xfffe1030b108 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030b10c +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030b150 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS 0xfffe1030b154 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK 0xfffe1030b158 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030b15c +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS 0xfffe1030b160 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK 0xfffe1030b164 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030b168 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0 0xfffe1030b16c +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1 0xfffe1030b170 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2 0xfffe1030b174 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3 0xfffe1030b178 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0 0xfffe1030b188 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030b18c +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2 0xfffe1030b190 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3 0xfffe1030b194 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1030b2b0 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP 0xfffe1030b2b4 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL 0xfffe1030b2b6 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1030b328 +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP 0xfffe1030b32c +#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL 0xfffe1030b32e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp +// base address: 0xfffe1030c000 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID 0xfffe1030c000 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID 0xfffe1030c002 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_COMMAND 0xfffe1030c004 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_STATUS 0xfffe1030c006 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID 0xfffe1030c008 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE 0xfffe1030c009 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS 0xfffe1030c00a +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS 0xfffe1030c00b +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE 0xfffe1030c00c +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_LATENCY 0xfffe1030c00d +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_HEADER 0xfffe1030c00e +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_BIST 0xfffe1030c00f +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1 0xfffe1030c010 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2 0xfffe1030c014 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3 0xfffe1030c018 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4 0xfffe1030c01c +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5 0xfffe1030c020 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6 0xfffe1030c024 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_CARDBUS_CIS_PTR 0xfffe1030c028 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID 0xfffe1030c02c +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR 0xfffe1030c030 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR 0xfffe1030c034 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE 0xfffe1030c03c +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN 0xfffe1030c03d +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MIN_GRANT 0xfffe1030c03e +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MAX_LATENCY 0xfffe1030c03f +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST 0xfffe1030c064 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP 0xfffe1030c066 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP 0xfffe1030c068 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL 0xfffe1030c06c +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS 0xfffe1030c06e +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP 0xfffe1030c070 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL 0xfffe1030c074 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS 0xfffe1030c076 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2 0xfffe1030c088 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2 0xfffe1030c08c +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2 0xfffe1030c08e +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2 0xfffe1030c090 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2 0xfffe1030c094 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2 0xfffe1030c096 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST 0xfffe1030c0a0 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL 0xfffe1030c0a2 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO 0xfffe1030c0a4 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI 0xfffe1030c0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA 0xfffe1030c0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK 0xfffe1030c0ac +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64 0xfffe1030c0ac +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64 0xfffe1030c0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING 0xfffe1030c0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64 0xfffe1030c0b4 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST 0xfffe1030c0c0 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL 0xfffe1030c0c2 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE 0xfffe1030c0c4 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA 0xfffe1030c0c8 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030c100 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030c104 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1 0xfffe1030c108 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030c10c +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030c150 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS 0xfffe1030c154 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK 0xfffe1030c158 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030c15c +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS 0xfffe1030c160 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK 0xfffe1030c164 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030c168 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0 0xfffe1030c16c +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1 0xfffe1030c170 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2 0xfffe1030c174 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3 0xfffe1030c178 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0 0xfffe1030c188 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030c18c +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2 0xfffe1030c190 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3 0xfffe1030c194 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1030c2b0 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP 0xfffe1030c2b4 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL 0xfffe1030c2b6 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1030c328 +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP 0xfffe1030c32c +#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL 0xfffe1030c32e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp +// base address: 0xfffe1030d000 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID 0xfffe1030d000 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID 0xfffe1030d002 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_COMMAND 0xfffe1030d004 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_STATUS 0xfffe1030d006 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID 0xfffe1030d008 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE 0xfffe1030d009 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS 0xfffe1030d00a +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS 0xfffe1030d00b +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE 0xfffe1030d00c +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_LATENCY 0xfffe1030d00d +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_HEADER 0xfffe1030d00e +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_BIST 0xfffe1030d00f +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1 0xfffe1030d010 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2 0xfffe1030d014 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3 0xfffe1030d018 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4 0xfffe1030d01c +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5 0xfffe1030d020 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6 0xfffe1030d024 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_CARDBUS_CIS_PTR 0xfffe1030d028 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID 0xfffe1030d02c +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR 0xfffe1030d030 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR 0xfffe1030d034 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE 0xfffe1030d03c +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN 0xfffe1030d03d +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MIN_GRANT 0xfffe1030d03e +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MAX_LATENCY 0xfffe1030d03f +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST 0xfffe1030d064 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP 0xfffe1030d066 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP 0xfffe1030d068 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL 0xfffe1030d06c +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS 0xfffe1030d06e +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP 0xfffe1030d070 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL 0xfffe1030d074 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS 0xfffe1030d076 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2 0xfffe1030d088 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2 0xfffe1030d08c +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2 0xfffe1030d08e +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2 0xfffe1030d090 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2 0xfffe1030d094 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2 0xfffe1030d096 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST 0xfffe1030d0a0 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL 0xfffe1030d0a2 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO 0xfffe1030d0a4 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI 0xfffe1030d0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA 0xfffe1030d0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK 0xfffe1030d0ac +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64 0xfffe1030d0ac +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64 0xfffe1030d0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING 0xfffe1030d0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64 0xfffe1030d0b4 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST 0xfffe1030d0c0 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL 0xfffe1030d0c2 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE 0xfffe1030d0c4 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA 0xfffe1030d0c8 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030d100 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030d104 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1 0xfffe1030d108 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030d10c +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030d150 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS 0xfffe1030d154 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK 0xfffe1030d158 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030d15c +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS 0xfffe1030d160 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK 0xfffe1030d164 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030d168 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0 0xfffe1030d16c +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1 0xfffe1030d170 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2 0xfffe1030d174 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3 0xfffe1030d178 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0 0xfffe1030d188 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030d18c +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2 0xfffe1030d190 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3 0xfffe1030d194 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1030d2b0 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP 0xfffe1030d2b4 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL 0xfffe1030d2b6 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1030d328 +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP 0xfffe1030d32c +#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL 0xfffe1030d32e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp +// base address: 0xfffe1030e000 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID 0xfffe1030e000 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID 0xfffe1030e002 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_COMMAND 0xfffe1030e004 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_STATUS 0xfffe1030e006 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID 0xfffe1030e008 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE 0xfffe1030e009 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS 0xfffe1030e00a +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS 0xfffe1030e00b +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE 0xfffe1030e00c +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_LATENCY 0xfffe1030e00d +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_HEADER 0xfffe1030e00e +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_BIST 0xfffe1030e00f +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1 0xfffe1030e010 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2 0xfffe1030e014 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3 0xfffe1030e018 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4 0xfffe1030e01c +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5 0xfffe1030e020 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6 0xfffe1030e024 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_CARDBUS_CIS_PTR 0xfffe1030e028 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID 0xfffe1030e02c +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR 0xfffe1030e030 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR 0xfffe1030e034 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE 0xfffe1030e03c +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN 0xfffe1030e03d +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MIN_GRANT 0xfffe1030e03e +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MAX_LATENCY 0xfffe1030e03f +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST 0xfffe1030e064 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP 0xfffe1030e066 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP 0xfffe1030e068 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL 0xfffe1030e06c +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS 0xfffe1030e06e +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP 0xfffe1030e070 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL 0xfffe1030e074 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS 0xfffe1030e076 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2 0xfffe1030e088 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2 0xfffe1030e08c +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2 0xfffe1030e08e +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2 0xfffe1030e090 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2 0xfffe1030e094 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2 0xfffe1030e096 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST 0xfffe1030e0a0 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL 0xfffe1030e0a2 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO 0xfffe1030e0a4 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI 0xfffe1030e0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA 0xfffe1030e0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK 0xfffe1030e0ac +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64 0xfffe1030e0ac +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64 0xfffe1030e0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING 0xfffe1030e0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64 0xfffe1030e0b4 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST 0xfffe1030e0c0 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL 0xfffe1030e0c2 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE 0xfffe1030e0c4 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA 0xfffe1030e0c8 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030e100 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030e104 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1 0xfffe1030e108 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030e10c +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030e150 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS 0xfffe1030e154 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK 0xfffe1030e158 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030e15c +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS 0xfffe1030e160 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK 0xfffe1030e164 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030e168 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0 0xfffe1030e16c +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1 0xfffe1030e170 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2 0xfffe1030e174 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3 0xfffe1030e178 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0 0xfffe1030e188 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030e18c +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2 0xfffe1030e190 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3 0xfffe1030e194 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1030e2b0 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP 0xfffe1030e2b4 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL 0xfffe1030e2b6 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1030e328 +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP 0xfffe1030e32c +#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL 0xfffe1030e32e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp +// base address: 0xfffe1030f000 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID 0xfffe1030f000 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID 0xfffe1030f002 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_COMMAND 0xfffe1030f004 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_STATUS 0xfffe1030f006 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID 0xfffe1030f008 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE 0xfffe1030f009 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS 0xfffe1030f00a +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS 0xfffe1030f00b +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE 0xfffe1030f00c +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_LATENCY 0xfffe1030f00d +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_HEADER 0xfffe1030f00e +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_BIST 0xfffe1030f00f +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1 0xfffe1030f010 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2 0xfffe1030f014 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3 0xfffe1030f018 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4 0xfffe1030f01c +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5 0xfffe1030f020 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6 0xfffe1030f024 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_CARDBUS_CIS_PTR 0xfffe1030f028 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID 0xfffe1030f02c +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR 0xfffe1030f030 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR 0xfffe1030f034 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE 0xfffe1030f03c +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN 0xfffe1030f03d +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MIN_GRANT 0xfffe1030f03e +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MAX_LATENCY 0xfffe1030f03f +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST 0xfffe1030f064 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP 0xfffe1030f066 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP 0xfffe1030f068 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL 0xfffe1030f06c +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS 0xfffe1030f06e +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP 0xfffe1030f070 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL 0xfffe1030f074 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS 0xfffe1030f076 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2 0xfffe1030f088 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2 0xfffe1030f08c +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2 0xfffe1030f08e +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2 0xfffe1030f090 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2 0xfffe1030f094 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2 0xfffe1030f096 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST 0xfffe1030f0a0 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL 0xfffe1030f0a2 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO 0xfffe1030f0a4 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI 0xfffe1030f0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA 0xfffe1030f0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK 0xfffe1030f0ac +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64 0xfffe1030f0ac +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64 0xfffe1030f0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING 0xfffe1030f0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64 0xfffe1030f0b4 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST 0xfffe1030f0c0 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL 0xfffe1030f0c2 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE 0xfffe1030f0c4 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA 0xfffe1030f0c8 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030f100 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030f104 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1 0xfffe1030f108 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030f10c +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030f150 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS 0xfffe1030f154 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK 0xfffe1030f158 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030f15c +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS 0xfffe1030f160 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK 0xfffe1030f164 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030f168 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0 0xfffe1030f16c +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1 0xfffe1030f170 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2 0xfffe1030f174 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3 0xfffe1030f178 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0 0xfffe1030f188 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030f18c +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2 0xfffe1030f190 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3 0xfffe1030f194 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1030f2b0 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP 0xfffe1030f2b4 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL 0xfffe1030f2b6 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1030f328 +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP 0xfffe1030f32c +#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL 0xfffe1030f32e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf16_bifcfgdecp +// base address: 0xfffe10310000 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_VENDOR_ID 0xfffe10310000 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_ID 0xfffe10310002 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_COMMAND 0xfffe10310004 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_STATUS 0xfffe10310006 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_REVISION_ID 0xfffe10310008 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PROG_INTERFACE 0xfffe10310009 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_SUB_CLASS 0xfffe1031000a +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_CLASS 0xfffe1031000b +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_CACHE_LINE 0xfffe1031000c +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_LATENCY 0xfffe1031000d +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_HEADER 0xfffe1031000e +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_BIST 0xfffe1031000f +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_1 0xfffe10310010 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_2 0xfffe10310014 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_3 0xfffe10310018 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_4 0xfffe1031001c +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_5 0xfffe10310020 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_6 0xfffe10310024 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_CARDBUS_CIS_PTR 0xfffe10310028 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_ADAPTER_ID 0xfffe1031002c +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_ROM_BASE_ADDR 0xfffe10310030 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_CAP_PTR 0xfffe10310034 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_INTERRUPT_LINE 0xfffe1031003c +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_INTERRUPT_PIN 0xfffe1031003d +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MIN_GRANT 0xfffe1031003e +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MAX_LATENCY 0xfffe1031003f +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP_LIST 0xfffe10310064 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP 0xfffe10310066 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP 0xfffe10310068 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL 0xfffe1031006c +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS 0xfffe1031006e +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP 0xfffe10310070 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL 0xfffe10310074 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS 0xfffe10310076 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2 0xfffe10310088 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2 0xfffe1031008c +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS2 0xfffe1031008e +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2 0xfffe10310090 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2 0xfffe10310094 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2 0xfffe10310096 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_CAP_LIST 0xfffe103100a0 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL 0xfffe103100a2 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_ADDR_LO 0xfffe103100a4 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_ADDR_HI 0xfffe103100a8 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_DATA 0xfffe103100a8 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MASK 0xfffe103100ac +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_DATA_64 0xfffe103100ac +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MASK_64 0xfffe103100b0 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_PENDING 0xfffe103100b0 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_PENDING_64 0xfffe103100b4 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSIX_CAP_LIST 0xfffe103100c0 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSIX_MSG_CNTL 0xfffe103100c2 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSIX_TABLE 0xfffe103100c4 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSIX_PBA 0xfffe103100c8 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10310100 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10310104 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC1 0xfffe10310108 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031010c +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10310150 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS 0xfffe10310154 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK 0xfffe10310158 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031015c +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS 0xfffe10310160 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK 0xfffe10310164 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10310168 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG0 0xfffe1031016c +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG1 0xfffe10310170 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG2 0xfffe10310174 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG3 0xfffe10310178 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG0 0xfffe10310188 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031018c +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG2 0xfffe10310190 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG3 0xfffe10310194 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103102b0 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CAP 0xfffe103102b4 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CNTL 0xfffe103102b6 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10310328 +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CAP 0xfffe1031032c +#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CNTL 0xfffe1031032e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf17_bifcfgdecp +// base address: 0xfffe10311000 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_VENDOR_ID 0xfffe10311000 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_ID 0xfffe10311002 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_COMMAND 0xfffe10311004 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_STATUS 0xfffe10311006 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_REVISION_ID 0xfffe10311008 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PROG_INTERFACE 0xfffe10311009 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_SUB_CLASS 0xfffe1031100a +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_CLASS 0xfffe1031100b +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_CACHE_LINE 0xfffe1031100c +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_LATENCY 0xfffe1031100d +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_HEADER 0xfffe1031100e +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_BIST 0xfffe1031100f +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_1 0xfffe10311010 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_2 0xfffe10311014 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_3 0xfffe10311018 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_4 0xfffe1031101c +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_5 0xfffe10311020 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_6 0xfffe10311024 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_CARDBUS_CIS_PTR 0xfffe10311028 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_ADAPTER_ID 0xfffe1031102c +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_ROM_BASE_ADDR 0xfffe10311030 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_CAP_PTR 0xfffe10311034 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_INTERRUPT_LINE 0xfffe1031103c +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_INTERRUPT_PIN 0xfffe1031103d +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MIN_GRANT 0xfffe1031103e +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MAX_LATENCY 0xfffe1031103f +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP_LIST 0xfffe10311064 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP 0xfffe10311066 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP 0xfffe10311068 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL 0xfffe1031106c +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS 0xfffe1031106e +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP 0xfffe10311070 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL 0xfffe10311074 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS 0xfffe10311076 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2 0xfffe10311088 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2 0xfffe1031108c +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS2 0xfffe1031108e +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2 0xfffe10311090 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2 0xfffe10311094 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2 0xfffe10311096 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_CAP_LIST 0xfffe103110a0 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL 0xfffe103110a2 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_ADDR_LO 0xfffe103110a4 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_ADDR_HI 0xfffe103110a8 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_DATA 0xfffe103110a8 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MASK 0xfffe103110ac +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_DATA_64 0xfffe103110ac +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MASK_64 0xfffe103110b0 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_PENDING 0xfffe103110b0 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_PENDING_64 0xfffe103110b4 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSIX_CAP_LIST 0xfffe103110c0 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSIX_MSG_CNTL 0xfffe103110c2 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSIX_TABLE 0xfffe103110c4 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSIX_PBA 0xfffe103110c8 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10311100 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10311104 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC1 0xfffe10311108 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031110c +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10311150 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS 0xfffe10311154 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK 0xfffe10311158 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031115c +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS 0xfffe10311160 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK 0xfffe10311164 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10311168 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG0 0xfffe1031116c +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG1 0xfffe10311170 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG2 0xfffe10311174 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG3 0xfffe10311178 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG0 0xfffe10311188 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031118c +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG2 0xfffe10311190 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG3 0xfffe10311194 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103112b0 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CAP 0xfffe103112b4 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CNTL 0xfffe103112b6 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10311328 +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CAP 0xfffe1031132c +#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CNTL 0xfffe1031132e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf18_bifcfgdecp +// base address: 0xfffe10312000 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_VENDOR_ID 0xfffe10312000 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_ID 0xfffe10312002 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_COMMAND 0xfffe10312004 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_STATUS 0xfffe10312006 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_REVISION_ID 0xfffe10312008 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PROG_INTERFACE 0xfffe10312009 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_SUB_CLASS 0xfffe1031200a +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_CLASS 0xfffe1031200b +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_CACHE_LINE 0xfffe1031200c +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_LATENCY 0xfffe1031200d +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_HEADER 0xfffe1031200e +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_BIST 0xfffe1031200f +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_1 0xfffe10312010 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_2 0xfffe10312014 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_3 0xfffe10312018 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_4 0xfffe1031201c +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_5 0xfffe10312020 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_6 0xfffe10312024 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_CARDBUS_CIS_PTR 0xfffe10312028 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_ADAPTER_ID 0xfffe1031202c +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_ROM_BASE_ADDR 0xfffe10312030 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_CAP_PTR 0xfffe10312034 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_INTERRUPT_LINE 0xfffe1031203c +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_INTERRUPT_PIN 0xfffe1031203d +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MIN_GRANT 0xfffe1031203e +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MAX_LATENCY 0xfffe1031203f +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP_LIST 0xfffe10312064 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP 0xfffe10312066 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP 0xfffe10312068 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL 0xfffe1031206c +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS 0xfffe1031206e +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP 0xfffe10312070 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL 0xfffe10312074 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS 0xfffe10312076 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2 0xfffe10312088 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2 0xfffe1031208c +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS2 0xfffe1031208e +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2 0xfffe10312090 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2 0xfffe10312094 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2 0xfffe10312096 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_CAP_LIST 0xfffe103120a0 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL 0xfffe103120a2 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_ADDR_LO 0xfffe103120a4 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_ADDR_HI 0xfffe103120a8 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_DATA 0xfffe103120a8 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MASK 0xfffe103120ac +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_DATA_64 0xfffe103120ac +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MASK_64 0xfffe103120b0 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_PENDING 0xfffe103120b0 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_PENDING_64 0xfffe103120b4 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSIX_CAP_LIST 0xfffe103120c0 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSIX_MSG_CNTL 0xfffe103120c2 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSIX_TABLE 0xfffe103120c4 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSIX_PBA 0xfffe103120c8 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10312100 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10312104 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC1 0xfffe10312108 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031210c +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10312150 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS 0xfffe10312154 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK 0xfffe10312158 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031215c +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS 0xfffe10312160 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK 0xfffe10312164 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10312168 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG0 0xfffe1031216c +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG1 0xfffe10312170 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG2 0xfffe10312174 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG3 0xfffe10312178 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG0 0xfffe10312188 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031218c +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG2 0xfffe10312190 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG3 0xfffe10312194 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103122b0 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CAP 0xfffe103122b4 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CNTL 0xfffe103122b6 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10312328 +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CAP 0xfffe1031232c +#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CNTL 0xfffe1031232e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf19_bifcfgdecp +// base address: 0xfffe10313000 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_VENDOR_ID 0xfffe10313000 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_ID 0xfffe10313002 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_COMMAND 0xfffe10313004 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_STATUS 0xfffe10313006 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_REVISION_ID 0xfffe10313008 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PROG_INTERFACE 0xfffe10313009 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_SUB_CLASS 0xfffe1031300a +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_CLASS 0xfffe1031300b +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_CACHE_LINE 0xfffe1031300c +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_LATENCY 0xfffe1031300d +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_HEADER 0xfffe1031300e +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_BIST 0xfffe1031300f +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_1 0xfffe10313010 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_2 0xfffe10313014 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_3 0xfffe10313018 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_4 0xfffe1031301c +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_5 0xfffe10313020 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_6 0xfffe10313024 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_CARDBUS_CIS_PTR 0xfffe10313028 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_ADAPTER_ID 0xfffe1031302c +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_ROM_BASE_ADDR 0xfffe10313030 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_CAP_PTR 0xfffe10313034 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_INTERRUPT_LINE 0xfffe1031303c +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_INTERRUPT_PIN 0xfffe1031303d +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MIN_GRANT 0xfffe1031303e +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MAX_LATENCY 0xfffe1031303f +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP_LIST 0xfffe10313064 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP 0xfffe10313066 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP 0xfffe10313068 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL 0xfffe1031306c +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS 0xfffe1031306e +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP 0xfffe10313070 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL 0xfffe10313074 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS 0xfffe10313076 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2 0xfffe10313088 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2 0xfffe1031308c +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS2 0xfffe1031308e +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2 0xfffe10313090 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2 0xfffe10313094 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2 0xfffe10313096 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_CAP_LIST 0xfffe103130a0 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL 0xfffe103130a2 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_ADDR_LO 0xfffe103130a4 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_ADDR_HI 0xfffe103130a8 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_DATA 0xfffe103130a8 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MASK 0xfffe103130ac +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_DATA_64 0xfffe103130ac +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MASK_64 0xfffe103130b0 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_PENDING 0xfffe103130b0 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_PENDING_64 0xfffe103130b4 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSIX_CAP_LIST 0xfffe103130c0 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSIX_MSG_CNTL 0xfffe103130c2 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSIX_TABLE 0xfffe103130c4 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSIX_PBA 0xfffe103130c8 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10313100 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10313104 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC1 0xfffe10313108 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031310c +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10313150 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS 0xfffe10313154 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK 0xfffe10313158 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031315c +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS 0xfffe10313160 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK 0xfffe10313164 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10313168 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG0 0xfffe1031316c +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG1 0xfffe10313170 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG2 0xfffe10313174 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG3 0xfffe10313178 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG0 0xfffe10313188 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031318c +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG2 0xfffe10313190 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG3 0xfffe10313194 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103132b0 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CAP 0xfffe103132b4 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CNTL 0xfffe103132b6 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10313328 +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CAP 0xfffe1031332c +#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CNTL 0xfffe1031332e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf20_bifcfgdecp +// base address: 0xfffe10314000 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_VENDOR_ID 0xfffe10314000 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_ID 0xfffe10314002 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_COMMAND 0xfffe10314004 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_STATUS 0xfffe10314006 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_REVISION_ID 0xfffe10314008 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PROG_INTERFACE 0xfffe10314009 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_SUB_CLASS 0xfffe1031400a +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_CLASS 0xfffe1031400b +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_CACHE_LINE 0xfffe1031400c +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_LATENCY 0xfffe1031400d +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_HEADER 0xfffe1031400e +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_BIST 0xfffe1031400f +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_1 0xfffe10314010 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_2 0xfffe10314014 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_3 0xfffe10314018 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_4 0xfffe1031401c +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_5 0xfffe10314020 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_6 0xfffe10314024 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_CARDBUS_CIS_PTR 0xfffe10314028 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_ADAPTER_ID 0xfffe1031402c +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_ROM_BASE_ADDR 0xfffe10314030 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_CAP_PTR 0xfffe10314034 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_INTERRUPT_LINE 0xfffe1031403c +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_INTERRUPT_PIN 0xfffe1031403d +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MIN_GRANT 0xfffe1031403e +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MAX_LATENCY 0xfffe1031403f +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP_LIST 0xfffe10314064 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP 0xfffe10314066 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP 0xfffe10314068 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL 0xfffe1031406c +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS 0xfffe1031406e +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP 0xfffe10314070 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL 0xfffe10314074 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS 0xfffe10314076 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2 0xfffe10314088 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2 0xfffe1031408c +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS2 0xfffe1031408e +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2 0xfffe10314090 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2 0xfffe10314094 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2 0xfffe10314096 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_CAP_LIST 0xfffe103140a0 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL 0xfffe103140a2 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_ADDR_LO 0xfffe103140a4 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_ADDR_HI 0xfffe103140a8 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_DATA 0xfffe103140a8 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MASK 0xfffe103140ac +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_DATA_64 0xfffe103140ac +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MASK_64 0xfffe103140b0 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_PENDING 0xfffe103140b0 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_PENDING_64 0xfffe103140b4 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSIX_CAP_LIST 0xfffe103140c0 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSIX_MSG_CNTL 0xfffe103140c2 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSIX_TABLE 0xfffe103140c4 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSIX_PBA 0xfffe103140c8 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10314100 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10314104 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC1 0xfffe10314108 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031410c +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10314150 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS 0xfffe10314154 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK 0xfffe10314158 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031415c +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS 0xfffe10314160 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK 0xfffe10314164 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10314168 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG0 0xfffe1031416c +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG1 0xfffe10314170 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG2 0xfffe10314174 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG3 0xfffe10314178 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG0 0xfffe10314188 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031418c +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG2 0xfffe10314190 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG3 0xfffe10314194 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103142b0 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CAP 0xfffe103142b4 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CNTL 0xfffe103142b6 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10314328 +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CAP 0xfffe1031432c +#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CNTL 0xfffe1031432e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf21_bifcfgdecp +// base address: 0xfffe10315000 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_VENDOR_ID 0xfffe10315000 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_ID 0xfffe10315002 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_COMMAND 0xfffe10315004 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_STATUS 0xfffe10315006 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_REVISION_ID 0xfffe10315008 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PROG_INTERFACE 0xfffe10315009 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_SUB_CLASS 0xfffe1031500a +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_CLASS 0xfffe1031500b +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_CACHE_LINE 0xfffe1031500c +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_LATENCY 0xfffe1031500d +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_HEADER 0xfffe1031500e +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_BIST 0xfffe1031500f +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_1 0xfffe10315010 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_2 0xfffe10315014 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_3 0xfffe10315018 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_4 0xfffe1031501c +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_5 0xfffe10315020 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_6 0xfffe10315024 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_CARDBUS_CIS_PTR 0xfffe10315028 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_ADAPTER_ID 0xfffe1031502c +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_ROM_BASE_ADDR 0xfffe10315030 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_CAP_PTR 0xfffe10315034 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_INTERRUPT_LINE 0xfffe1031503c +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_INTERRUPT_PIN 0xfffe1031503d +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MIN_GRANT 0xfffe1031503e +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MAX_LATENCY 0xfffe1031503f +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP_LIST 0xfffe10315064 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP 0xfffe10315066 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP 0xfffe10315068 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL 0xfffe1031506c +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS 0xfffe1031506e +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP 0xfffe10315070 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL 0xfffe10315074 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS 0xfffe10315076 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2 0xfffe10315088 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2 0xfffe1031508c +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS2 0xfffe1031508e +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2 0xfffe10315090 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2 0xfffe10315094 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2 0xfffe10315096 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_CAP_LIST 0xfffe103150a0 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL 0xfffe103150a2 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_ADDR_LO 0xfffe103150a4 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_ADDR_HI 0xfffe103150a8 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_DATA 0xfffe103150a8 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MASK 0xfffe103150ac +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_DATA_64 0xfffe103150ac +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MASK_64 0xfffe103150b0 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_PENDING 0xfffe103150b0 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_PENDING_64 0xfffe103150b4 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSIX_CAP_LIST 0xfffe103150c0 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSIX_MSG_CNTL 0xfffe103150c2 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSIX_TABLE 0xfffe103150c4 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSIX_PBA 0xfffe103150c8 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10315100 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10315104 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC1 0xfffe10315108 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031510c +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10315150 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS 0xfffe10315154 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK 0xfffe10315158 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031515c +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS 0xfffe10315160 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK 0xfffe10315164 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10315168 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG0 0xfffe1031516c +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG1 0xfffe10315170 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG2 0xfffe10315174 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG3 0xfffe10315178 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG0 0xfffe10315188 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031518c +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG2 0xfffe10315190 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG3 0xfffe10315194 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103152b0 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CAP 0xfffe103152b4 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CNTL 0xfffe103152b6 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10315328 +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CAP 0xfffe1031532c +#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CNTL 0xfffe1031532e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf22_bifcfgdecp +// base address: 0xfffe10316000 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_VENDOR_ID 0xfffe10316000 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_ID 0xfffe10316002 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_COMMAND 0xfffe10316004 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_STATUS 0xfffe10316006 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_REVISION_ID 0xfffe10316008 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PROG_INTERFACE 0xfffe10316009 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_SUB_CLASS 0xfffe1031600a +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_CLASS 0xfffe1031600b +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_CACHE_LINE 0xfffe1031600c +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_LATENCY 0xfffe1031600d +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_HEADER 0xfffe1031600e +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_BIST 0xfffe1031600f +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_1 0xfffe10316010 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_2 0xfffe10316014 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_3 0xfffe10316018 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_4 0xfffe1031601c +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_5 0xfffe10316020 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_6 0xfffe10316024 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_CARDBUS_CIS_PTR 0xfffe10316028 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_ADAPTER_ID 0xfffe1031602c +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_ROM_BASE_ADDR 0xfffe10316030 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_CAP_PTR 0xfffe10316034 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_INTERRUPT_LINE 0xfffe1031603c +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_INTERRUPT_PIN 0xfffe1031603d +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MIN_GRANT 0xfffe1031603e +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MAX_LATENCY 0xfffe1031603f +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP_LIST 0xfffe10316064 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP 0xfffe10316066 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP 0xfffe10316068 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL 0xfffe1031606c +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS 0xfffe1031606e +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP 0xfffe10316070 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL 0xfffe10316074 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS 0xfffe10316076 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2 0xfffe10316088 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2 0xfffe1031608c +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS2 0xfffe1031608e +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2 0xfffe10316090 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2 0xfffe10316094 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2 0xfffe10316096 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_CAP_LIST 0xfffe103160a0 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL 0xfffe103160a2 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_ADDR_LO 0xfffe103160a4 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_ADDR_HI 0xfffe103160a8 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_DATA 0xfffe103160a8 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MASK 0xfffe103160ac +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_DATA_64 0xfffe103160ac +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MASK_64 0xfffe103160b0 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_PENDING 0xfffe103160b0 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_PENDING_64 0xfffe103160b4 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSIX_CAP_LIST 0xfffe103160c0 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSIX_MSG_CNTL 0xfffe103160c2 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSIX_TABLE 0xfffe103160c4 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSIX_PBA 0xfffe103160c8 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10316100 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10316104 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC1 0xfffe10316108 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031610c +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10316150 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS 0xfffe10316154 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK 0xfffe10316158 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031615c +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS 0xfffe10316160 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK 0xfffe10316164 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10316168 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG0 0xfffe1031616c +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG1 0xfffe10316170 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG2 0xfffe10316174 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG3 0xfffe10316178 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG0 0xfffe10316188 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031618c +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG2 0xfffe10316190 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG3 0xfffe10316194 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103162b0 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CAP 0xfffe103162b4 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CNTL 0xfffe103162b6 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10316328 +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CAP 0xfffe1031632c +#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CNTL 0xfffe1031632e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf23_bifcfgdecp +// base address: 0xfffe10317000 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_VENDOR_ID 0xfffe10317000 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_ID 0xfffe10317002 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_COMMAND 0xfffe10317004 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_STATUS 0xfffe10317006 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_REVISION_ID 0xfffe10317008 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PROG_INTERFACE 0xfffe10317009 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_SUB_CLASS 0xfffe1031700a +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_CLASS 0xfffe1031700b +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_CACHE_LINE 0xfffe1031700c +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_LATENCY 0xfffe1031700d +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_HEADER 0xfffe1031700e +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_BIST 0xfffe1031700f +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_1 0xfffe10317010 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_2 0xfffe10317014 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_3 0xfffe10317018 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_4 0xfffe1031701c +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_5 0xfffe10317020 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_6 0xfffe10317024 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_CARDBUS_CIS_PTR 0xfffe10317028 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_ADAPTER_ID 0xfffe1031702c +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_ROM_BASE_ADDR 0xfffe10317030 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_CAP_PTR 0xfffe10317034 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_INTERRUPT_LINE 0xfffe1031703c +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_INTERRUPT_PIN 0xfffe1031703d +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MIN_GRANT 0xfffe1031703e +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MAX_LATENCY 0xfffe1031703f +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP_LIST 0xfffe10317064 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP 0xfffe10317066 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP 0xfffe10317068 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL 0xfffe1031706c +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS 0xfffe1031706e +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP 0xfffe10317070 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL 0xfffe10317074 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS 0xfffe10317076 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2 0xfffe10317088 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2 0xfffe1031708c +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS2 0xfffe1031708e +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2 0xfffe10317090 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2 0xfffe10317094 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2 0xfffe10317096 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_CAP_LIST 0xfffe103170a0 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL 0xfffe103170a2 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_ADDR_LO 0xfffe103170a4 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_ADDR_HI 0xfffe103170a8 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_DATA 0xfffe103170a8 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MASK 0xfffe103170ac +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_DATA_64 0xfffe103170ac +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MASK_64 0xfffe103170b0 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_PENDING 0xfffe103170b0 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_PENDING_64 0xfffe103170b4 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSIX_CAP_LIST 0xfffe103170c0 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSIX_MSG_CNTL 0xfffe103170c2 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSIX_TABLE 0xfffe103170c4 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSIX_PBA 0xfffe103170c8 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10317100 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10317104 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC1 0xfffe10317108 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031710c +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10317150 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS 0xfffe10317154 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK 0xfffe10317158 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031715c +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS 0xfffe10317160 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK 0xfffe10317164 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10317168 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG0 0xfffe1031716c +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG1 0xfffe10317170 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG2 0xfffe10317174 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG3 0xfffe10317178 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG0 0xfffe10317188 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031718c +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG2 0xfffe10317190 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG3 0xfffe10317194 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103172b0 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CAP 0xfffe103172b4 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CNTL 0xfffe103172b6 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10317328 +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CAP 0xfffe1031732c +#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CNTL 0xfffe1031732e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf24_bifcfgdecp +// base address: 0xfffe10318000 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_VENDOR_ID 0xfffe10318000 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_ID 0xfffe10318002 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_COMMAND 0xfffe10318004 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_STATUS 0xfffe10318006 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_REVISION_ID 0xfffe10318008 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PROG_INTERFACE 0xfffe10318009 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_SUB_CLASS 0xfffe1031800a +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_CLASS 0xfffe1031800b +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_CACHE_LINE 0xfffe1031800c +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_LATENCY 0xfffe1031800d +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_HEADER 0xfffe1031800e +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_BIST 0xfffe1031800f +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_1 0xfffe10318010 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_2 0xfffe10318014 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_3 0xfffe10318018 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_4 0xfffe1031801c +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_5 0xfffe10318020 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_6 0xfffe10318024 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_CARDBUS_CIS_PTR 0xfffe10318028 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_ADAPTER_ID 0xfffe1031802c +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_ROM_BASE_ADDR 0xfffe10318030 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_CAP_PTR 0xfffe10318034 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_INTERRUPT_LINE 0xfffe1031803c +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_INTERRUPT_PIN 0xfffe1031803d +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MIN_GRANT 0xfffe1031803e +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MAX_LATENCY 0xfffe1031803f +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP_LIST 0xfffe10318064 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP 0xfffe10318066 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP 0xfffe10318068 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL 0xfffe1031806c +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS 0xfffe1031806e +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP 0xfffe10318070 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL 0xfffe10318074 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS 0xfffe10318076 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2 0xfffe10318088 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2 0xfffe1031808c +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS2 0xfffe1031808e +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2 0xfffe10318090 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2 0xfffe10318094 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2 0xfffe10318096 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_CAP_LIST 0xfffe103180a0 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL 0xfffe103180a2 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_ADDR_LO 0xfffe103180a4 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_ADDR_HI 0xfffe103180a8 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_DATA 0xfffe103180a8 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MASK 0xfffe103180ac +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_DATA_64 0xfffe103180ac +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MASK_64 0xfffe103180b0 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_PENDING 0xfffe103180b0 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_PENDING_64 0xfffe103180b4 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSIX_CAP_LIST 0xfffe103180c0 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSIX_MSG_CNTL 0xfffe103180c2 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSIX_TABLE 0xfffe103180c4 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSIX_PBA 0xfffe103180c8 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10318100 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10318104 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC1 0xfffe10318108 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031810c +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10318150 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS 0xfffe10318154 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK 0xfffe10318158 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031815c +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS 0xfffe10318160 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK 0xfffe10318164 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10318168 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG0 0xfffe1031816c +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG1 0xfffe10318170 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG2 0xfffe10318174 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG3 0xfffe10318178 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG0 0xfffe10318188 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031818c +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG2 0xfffe10318190 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG3 0xfffe10318194 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103182b0 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CAP 0xfffe103182b4 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CNTL 0xfffe103182b6 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10318328 +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CAP 0xfffe1031832c +#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CNTL 0xfffe1031832e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf25_bifcfgdecp +// base address: 0xfffe10319000 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_VENDOR_ID 0xfffe10319000 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_ID 0xfffe10319002 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_COMMAND 0xfffe10319004 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_STATUS 0xfffe10319006 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_REVISION_ID 0xfffe10319008 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PROG_INTERFACE 0xfffe10319009 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_SUB_CLASS 0xfffe1031900a +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_CLASS 0xfffe1031900b +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_CACHE_LINE 0xfffe1031900c +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_LATENCY 0xfffe1031900d +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_HEADER 0xfffe1031900e +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_BIST 0xfffe1031900f +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_1 0xfffe10319010 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_2 0xfffe10319014 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_3 0xfffe10319018 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_4 0xfffe1031901c +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_5 0xfffe10319020 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_6 0xfffe10319024 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_CARDBUS_CIS_PTR 0xfffe10319028 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_ADAPTER_ID 0xfffe1031902c +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_ROM_BASE_ADDR 0xfffe10319030 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_CAP_PTR 0xfffe10319034 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_INTERRUPT_LINE 0xfffe1031903c +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_INTERRUPT_PIN 0xfffe1031903d +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MIN_GRANT 0xfffe1031903e +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MAX_LATENCY 0xfffe1031903f +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP_LIST 0xfffe10319064 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP 0xfffe10319066 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP 0xfffe10319068 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL 0xfffe1031906c +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS 0xfffe1031906e +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP 0xfffe10319070 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL 0xfffe10319074 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS 0xfffe10319076 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2 0xfffe10319088 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2 0xfffe1031908c +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS2 0xfffe1031908e +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2 0xfffe10319090 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2 0xfffe10319094 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2 0xfffe10319096 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_CAP_LIST 0xfffe103190a0 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL 0xfffe103190a2 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_ADDR_LO 0xfffe103190a4 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_ADDR_HI 0xfffe103190a8 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_DATA 0xfffe103190a8 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MASK 0xfffe103190ac +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_DATA_64 0xfffe103190ac +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MASK_64 0xfffe103190b0 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_PENDING 0xfffe103190b0 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_PENDING_64 0xfffe103190b4 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSIX_CAP_LIST 0xfffe103190c0 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSIX_MSG_CNTL 0xfffe103190c2 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSIX_TABLE 0xfffe103190c4 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSIX_PBA 0xfffe103190c8 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10319100 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10319104 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC1 0xfffe10319108 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031910c +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10319150 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS 0xfffe10319154 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK 0xfffe10319158 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031915c +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS 0xfffe10319160 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK 0xfffe10319164 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10319168 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG0 0xfffe1031916c +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG1 0xfffe10319170 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG2 0xfffe10319174 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG3 0xfffe10319178 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG0 0xfffe10319188 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031918c +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG2 0xfffe10319190 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG3 0xfffe10319194 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103192b0 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CAP 0xfffe103192b4 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CNTL 0xfffe103192b6 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10319328 +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CAP 0xfffe1031932c +#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CNTL 0xfffe1031932e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf26_bifcfgdecp +// base address: 0xfffe1031a000 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_VENDOR_ID 0xfffe1031a000 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_ID 0xfffe1031a002 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_COMMAND 0xfffe1031a004 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_STATUS 0xfffe1031a006 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_REVISION_ID 0xfffe1031a008 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PROG_INTERFACE 0xfffe1031a009 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_SUB_CLASS 0xfffe1031a00a +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_CLASS 0xfffe1031a00b +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_CACHE_LINE 0xfffe1031a00c +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_LATENCY 0xfffe1031a00d +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_HEADER 0xfffe1031a00e +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_BIST 0xfffe1031a00f +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_1 0xfffe1031a010 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_2 0xfffe1031a014 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_3 0xfffe1031a018 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_4 0xfffe1031a01c +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_5 0xfffe1031a020 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_6 0xfffe1031a024 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_CARDBUS_CIS_PTR 0xfffe1031a028 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_ADAPTER_ID 0xfffe1031a02c +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_ROM_BASE_ADDR 0xfffe1031a030 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_CAP_PTR 0xfffe1031a034 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_INTERRUPT_LINE 0xfffe1031a03c +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_INTERRUPT_PIN 0xfffe1031a03d +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MIN_GRANT 0xfffe1031a03e +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MAX_LATENCY 0xfffe1031a03f +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP_LIST 0xfffe1031a064 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP 0xfffe1031a066 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP 0xfffe1031a068 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL 0xfffe1031a06c +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS 0xfffe1031a06e +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP 0xfffe1031a070 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL 0xfffe1031a074 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS 0xfffe1031a076 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2 0xfffe1031a088 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2 0xfffe1031a08c +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS2 0xfffe1031a08e +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2 0xfffe1031a090 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2 0xfffe1031a094 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2 0xfffe1031a096 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_CAP_LIST 0xfffe1031a0a0 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL 0xfffe1031a0a2 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_ADDR_LO 0xfffe1031a0a4 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_ADDR_HI 0xfffe1031a0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_DATA 0xfffe1031a0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MASK 0xfffe1031a0ac +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_DATA_64 0xfffe1031a0ac +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MASK_64 0xfffe1031a0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_PENDING 0xfffe1031a0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_PENDING_64 0xfffe1031a0b4 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSIX_CAP_LIST 0xfffe1031a0c0 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSIX_MSG_CNTL 0xfffe1031a0c2 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSIX_TABLE 0xfffe1031a0c4 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSIX_PBA 0xfffe1031a0c8 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1031a100 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1031a104 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC1 0xfffe1031a108 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031a10c +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1031a150 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS 0xfffe1031a154 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK 0xfffe1031a158 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031a15c +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS 0xfffe1031a160 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK 0xfffe1031a164 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1031a168 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG0 0xfffe1031a16c +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG1 0xfffe1031a170 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG2 0xfffe1031a174 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG3 0xfffe1031a178 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG0 0xfffe1031a188 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031a18c +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG2 0xfffe1031a190 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG3 0xfffe1031a194 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1031a2b0 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CAP 0xfffe1031a2b4 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CNTL 0xfffe1031a2b6 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1031a328 +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CAP 0xfffe1031a32c +#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CNTL 0xfffe1031a32e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf27_bifcfgdecp +// base address: 0xfffe1031b000 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_VENDOR_ID 0xfffe1031b000 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_ID 0xfffe1031b002 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_COMMAND 0xfffe1031b004 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_STATUS 0xfffe1031b006 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_REVISION_ID 0xfffe1031b008 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PROG_INTERFACE 0xfffe1031b009 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_SUB_CLASS 0xfffe1031b00a +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_CLASS 0xfffe1031b00b +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_CACHE_LINE 0xfffe1031b00c +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_LATENCY 0xfffe1031b00d +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_HEADER 0xfffe1031b00e +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_BIST 0xfffe1031b00f +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_1 0xfffe1031b010 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_2 0xfffe1031b014 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_3 0xfffe1031b018 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_4 0xfffe1031b01c +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_5 0xfffe1031b020 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_6 0xfffe1031b024 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_CARDBUS_CIS_PTR 0xfffe1031b028 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_ADAPTER_ID 0xfffe1031b02c +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_ROM_BASE_ADDR 0xfffe1031b030 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_CAP_PTR 0xfffe1031b034 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_INTERRUPT_LINE 0xfffe1031b03c +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_INTERRUPT_PIN 0xfffe1031b03d +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MIN_GRANT 0xfffe1031b03e +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MAX_LATENCY 0xfffe1031b03f +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP_LIST 0xfffe1031b064 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP 0xfffe1031b066 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP 0xfffe1031b068 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL 0xfffe1031b06c +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS 0xfffe1031b06e +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP 0xfffe1031b070 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL 0xfffe1031b074 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS 0xfffe1031b076 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2 0xfffe1031b088 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2 0xfffe1031b08c +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS2 0xfffe1031b08e +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2 0xfffe1031b090 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2 0xfffe1031b094 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2 0xfffe1031b096 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_CAP_LIST 0xfffe1031b0a0 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL 0xfffe1031b0a2 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_ADDR_LO 0xfffe1031b0a4 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_ADDR_HI 0xfffe1031b0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_DATA 0xfffe1031b0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MASK 0xfffe1031b0ac +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_DATA_64 0xfffe1031b0ac +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MASK_64 0xfffe1031b0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_PENDING 0xfffe1031b0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_PENDING_64 0xfffe1031b0b4 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSIX_CAP_LIST 0xfffe1031b0c0 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSIX_MSG_CNTL 0xfffe1031b0c2 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSIX_TABLE 0xfffe1031b0c4 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSIX_PBA 0xfffe1031b0c8 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1031b100 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1031b104 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC1 0xfffe1031b108 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031b10c +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1031b150 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS 0xfffe1031b154 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK 0xfffe1031b158 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031b15c +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS 0xfffe1031b160 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK 0xfffe1031b164 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1031b168 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG0 0xfffe1031b16c +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG1 0xfffe1031b170 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG2 0xfffe1031b174 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG3 0xfffe1031b178 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG0 0xfffe1031b188 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031b18c +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG2 0xfffe1031b190 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG3 0xfffe1031b194 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1031b2b0 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CAP 0xfffe1031b2b4 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CNTL 0xfffe1031b2b6 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1031b328 +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CAP 0xfffe1031b32c +#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CNTL 0xfffe1031b32e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf28_bifcfgdecp +// base address: 0xfffe1031c000 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_VENDOR_ID 0xfffe1031c000 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_ID 0xfffe1031c002 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_COMMAND 0xfffe1031c004 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_STATUS 0xfffe1031c006 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_REVISION_ID 0xfffe1031c008 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PROG_INTERFACE 0xfffe1031c009 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_SUB_CLASS 0xfffe1031c00a +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_CLASS 0xfffe1031c00b +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_CACHE_LINE 0xfffe1031c00c +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_LATENCY 0xfffe1031c00d +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_HEADER 0xfffe1031c00e +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_BIST 0xfffe1031c00f +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_1 0xfffe1031c010 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_2 0xfffe1031c014 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_3 0xfffe1031c018 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_4 0xfffe1031c01c +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_5 0xfffe1031c020 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_6 0xfffe1031c024 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_CARDBUS_CIS_PTR 0xfffe1031c028 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_ADAPTER_ID 0xfffe1031c02c +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_ROM_BASE_ADDR 0xfffe1031c030 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_CAP_PTR 0xfffe1031c034 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_INTERRUPT_LINE 0xfffe1031c03c +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_INTERRUPT_PIN 0xfffe1031c03d +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MIN_GRANT 0xfffe1031c03e +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MAX_LATENCY 0xfffe1031c03f +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP_LIST 0xfffe1031c064 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP 0xfffe1031c066 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP 0xfffe1031c068 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL 0xfffe1031c06c +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS 0xfffe1031c06e +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP 0xfffe1031c070 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL 0xfffe1031c074 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS 0xfffe1031c076 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2 0xfffe1031c088 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2 0xfffe1031c08c +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS2 0xfffe1031c08e +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2 0xfffe1031c090 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2 0xfffe1031c094 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2 0xfffe1031c096 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_CAP_LIST 0xfffe1031c0a0 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL 0xfffe1031c0a2 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_ADDR_LO 0xfffe1031c0a4 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_ADDR_HI 0xfffe1031c0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_DATA 0xfffe1031c0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MASK 0xfffe1031c0ac +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_DATA_64 0xfffe1031c0ac +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MASK_64 0xfffe1031c0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_PENDING 0xfffe1031c0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_PENDING_64 0xfffe1031c0b4 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSIX_CAP_LIST 0xfffe1031c0c0 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSIX_MSG_CNTL 0xfffe1031c0c2 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSIX_TABLE 0xfffe1031c0c4 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSIX_PBA 0xfffe1031c0c8 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1031c100 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1031c104 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC1 0xfffe1031c108 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031c10c +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1031c150 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS 0xfffe1031c154 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK 0xfffe1031c158 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031c15c +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS 0xfffe1031c160 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK 0xfffe1031c164 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1031c168 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG0 0xfffe1031c16c +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG1 0xfffe1031c170 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG2 0xfffe1031c174 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG3 0xfffe1031c178 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG0 0xfffe1031c188 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031c18c +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG2 0xfffe1031c190 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG3 0xfffe1031c194 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1031c2b0 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CAP 0xfffe1031c2b4 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CNTL 0xfffe1031c2b6 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1031c328 +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CAP 0xfffe1031c32c +#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CNTL 0xfffe1031c32e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf29_bifcfgdecp +// base address: 0xfffe1031d000 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_VENDOR_ID 0xfffe1031d000 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_ID 0xfffe1031d002 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_COMMAND 0xfffe1031d004 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_STATUS 0xfffe1031d006 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_REVISION_ID 0xfffe1031d008 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PROG_INTERFACE 0xfffe1031d009 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_SUB_CLASS 0xfffe1031d00a +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_CLASS 0xfffe1031d00b +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_CACHE_LINE 0xfffe1031d00c +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_LATENCY 0xfffe1031d00d +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_HEADER 0xfffe1031d00e +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_BIST 0xfffe1031d00f +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_1 0xfffe1031d010 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_2 0xfffe1031d014 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_3 0xfffe1031d018 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_4 0xfffe1031d01c +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_5 0xfffe1031d020 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_6 0xfffe1031d024 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_CARDBUS_CIS_PTR 0xfffe1031d028 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_ADAPTER_ID 0xfffe1031d02c +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_ROM_BASE_ADDR 0xfffe1031d030 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_CAP_PTR 0xfffe1031d034 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_INTERRUPT_LINE 0xfffe1031d03c +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_INTERRUPT_PIN 0xfffe1031d03d +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MIN_GRANT 0xfffe1031d03e +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MAX_LATENCY 0xfffe1031d03f +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP_LIST 0xfffe1031d064 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP 0xfffe1031d066 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP 0xfffe1031d068 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL 0xfffe1031d06c +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS 0xfffe1031d06e +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP 0xfffe1031d070 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL 0xfffe1031d074 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS 0xfffe1031d076 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2 0xfffe1031d088 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2 0xfffe1031d08c +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS2 0xfffe1031d08e +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2 0xfffe1031d090 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2 0xfffe1031d094 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2 0xfffe1031d096 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_CAP_LIST 0xfffe1031d0a0 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL 0xfffe1031d0a2 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_ADDR_LO 0xfffe1031d0a4 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_ADDR_HI 0xfffe1031d0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_DATA 0xfffe1031d0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MASK 0xfffe1031d0ac +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_DATA_64 0xfffe1031d0ac +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MASK_64 0xfffe1031d0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_PENDING 0xfffe1031d0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_PENDING_64 0xfffe1031d0b4 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSIX_CAP_LIST 0xfffe1031d0c0 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSIX_MSG_CNTL 0xfffe1031d0c2 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSIX_TABLE 0xfffe1031d0c4 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSIX_PBA 0xfffe1031d0c8 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1031d100 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1031d104 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC1 0xfffe1031d108 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031d10c +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1031d150 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS 0xfffe1031d154 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK 0xfffe1031d158 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031d15c +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS 0xfffe1031d160 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK 0xfffe1031d164 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1031d168 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG0 0xfffe1031d16c +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG1 0xfffe1031d170 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG2 0xfffe1031d174 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG3 0xfffe1031d178 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG0 0xfffe1031d188 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031d18c +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG2 0xfffe1031d190 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG3 0xfffe1031d194 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1031d2b0 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CAP 0xfffe1031d2b4 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CNTL 0xfffe1031d2b6 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1031d328 +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CAP 0xfffe1031d32c +#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CNTL 0xfffe1031d32e + + +// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf30_bifcfgdecp +// base address: 0xfffe1031e000 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_VENDOR_ID 0xfffe1031e000 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_ID 0xfffe1031e002 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_COMMAND 0xfffe1031e004 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_STATUS 0xfffe1031e006 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_REVISION_ID 0xfffe1031e008 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PROG_INTERFACE 0xfffe1031e009 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_SUB_CLASS 0xfffe1031e00a +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_CLASS 0xfffe1031e00b +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_CACHE_LINE 0xfffe1031e00c +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_LATENCY 0xfffe1031e00d +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_HEADER 0xfffe1031e00e +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_BIST 0xfffe1031e00f +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_1 0xfffe1031e010 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_2 0xfffe1031e014 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_3 0xfffe1031e018 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_4 0xfffe1031e01c +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_5 0xfffe1031e020 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_6 0xfffe1031e024 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_CARDBUS_CIS_PTR 0xfffe1031e028 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_ADAPTER_ID 0xfffe1031e02c +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_ROM_BASE_ADDR 0xfffe1031e030 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_CAP_PTR 0xfffe1031e034 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_INTERRUPT_LINE 0xfffe1031e03c +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_INTERRUPT_PIN 0xfffe1031e03d +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MIN_GRANT 0xfffe1031e03e +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MAX_LATENCY 0xfffe1031e03f +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP_LIST 0xfffe1031e064 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP 0xfffe1031e066 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP 0xfffe1031e068 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL 0xfffe1031e06c +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS 0xfffe1031e06e +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP 0xfffe1031e070 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL 0xfffe1031e074 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS 0xfffe1031e076 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2 0xfffe1031e088 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2 0xfffe1031e08c +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS2 0xfffe1031e08e +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2 0xfffe1031e090 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2 0xfffe1031e094 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2 0xfffe1031e096 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_CAP_LIST 0xfffe1031e0a0 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL 0xfffe1031e0a2 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_ADDR_LO 0xfffe1031e0a4 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_ADDR_HI 0xfffe1031e0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_DATA 0xfffe1031e0a8 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MASK 0xfffe1031e0ac +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_DATA_64 0xfffe1031e0ac +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MASK_64 0xfffe1031e0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_PENDING 0xfffe1031e0b0 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_PENDING_64 0xfffe1031e0b4 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSIX_CAP_LIST 0xfffe1031e0c0 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSIX_MSG_CNTL 0xfffe1031e0c2 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSIX_TABLE 0xfffe1031e0c4 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSIX_PBA 0xfffe1031e0c8 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1031e100 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1031e104 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC1 0xfffe1031e108 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031e10c +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1031e150 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS 0xfffe1031e154 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK 0xfffe1031e158 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031e15c +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS 0xfffe1031e160 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK 0xfffe1031e164 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1031e168 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG0 0xfffe1031e16c +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG1 0xfffe1031e170 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG2 0xfffe1031e174 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG3 0xfffe1031e178 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG0 0xfffe1031e188 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031e18c +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG2 0xfffe1031e190 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG3 0xfffe1031e194 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1031e2b0 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CAP 0xfffe1031e2b4 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CNTL 0xfffe1031e2b6 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1031e328 +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CAP 0xfffe1031e32c +#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CNTL 0xfffe1031e32e + + +// addressBlock: nbio_nbif0_rcc_shadow_reg_shadowdec +// base address: 0xfffe30000000 +#define cfgSHADOW_COMMAND 0xfffe30000004 +#define cfgSHADOW_BASE_ADDR_1 0xfffe30000010 +#define cfgSHADOW_BASE_ADDR_2 0xfffe30000014 +#define cfgSHADOW_SUB_BUS_NUMBER_LATENCY 0xfffe30000018 +#define cfgSHADOW_IO_BASE_LIMIT 0xfffe3000001c +#define cfgSHADOW_MEM_BASE_LIMIT 0xfffe30000020 +#define cfgSHADOW_PREF_BASE_LIMIT 0xfffe30000024 +#define cfgSHADOW_PREF_BASE_UPPER 0xfffe30000028 +#define cfgSHADOW_PREF_LIMIT_UPPER 0xfffe3000002c +#define cfgSHADOW_IO_BASE_LIMIT_HI 0xfffe30000030 +#define cfgSHADOW_IRQ_BRIDGE_CNTL 0xfffe3000003e +#define cfgSUC_INDEX 0xfffe300000e0 +#define cfgSUC_DATA 0xfffe300000e4 + + +// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC +// base address: 0x30300000 +#define cfgBIF_BX_PF1_MM_INDEX 0x30300000 +#define cfgBIF_BX_PF1_MM_DATA 0x30300004 +#define cfgBIF_BX_PF1_MM_INDEX_HI 0x30300018 + + +// addressBlock: nbio_nbif0_bif_bx_SYSDEC +// base address: 0x30300000 +#define cfgSYSHUB_INDEX_OVLP 0x30300020 +#define cfgSYSHUB_DATA_OVLP 0x30300024 +#define cfgPCIE_INDEX 0x30300030 +#define cfgPCIE_DATA 0x30300034 +#define cfgPCIE_INDEX2 0x30300038 +#define cfgPCIE_DATA2 0x3030003c +#define cfgSBIOS_SCRATCH_0 0x30300120 +#define cfgSBIOS_SCRATCH_1 0x30300124 +#define cfgSBIOS_SCRATCH_2 0x30300128 +#define cfgSBIOS_SCRATCH_3 0x3030012c +#define cfgBIOS_SCRATCH_0 0x30300130 +#define cfgBIOS_SCRATCH_1 0x30300134 +#define cfgBIOS_SCRATCH_2 0x30300138 +#define cfgBIOS_SCRATCH_3 0x3030013c +#define cfgBIOS_SCRATCH_4 0x30300140 +#define cfgBIOS_SCRATCH_5 0x30300144 +#define cfgBIOS_SCRATCH_6 0x30300148 +#define cfgBIOS_SCRATCH_7 0x3030014c +#define cfgBIOS_SCRATCH_8 0x30300150 +#define cfgBIOS_SCRATCH_9 0x30300154 +#define cfgBIOS_SCRATCH_10 0x30300158 +#define cfgBIOS_SCRATCH_11 0x3030015c +#define cfgBIOS_SCRATCH_12 0x30300160 +#define cfgBIOS_SCRATCH_13 0x30300164 +#define cfgBIOS_SCRATCH_14 0x30300168 +#define cfgBIOS_SCRATCH_15 0x3030016c +#define cfgBIF_RLC_INTR_CNTL 0x30300180 +#define cfgBIF_VCE_INTR_CNTL 0x30300184 +#define cfgBIF_UVD_INTR_CNTL 0x30300188 +#define cfgGFX_MMIOREG_CAM_ADDR0 0x30300200 +#define cfgGFX_MMIOREG_CAM_REMAP_ADDR0 0x30300204 +#define cfgGFX_MMIOREG_CAM_ADDR1 0x30300208 +#define cfgGFX_MMIOREG_CAM_REMAP_ADDR1 0x3030020c +#define cfgGFX_MMIOREG_CAM_ADDR2 0x30300210 +#define cfgGFX_MMIOREG_CAM_REMAP_ADDR2 0x30300214 +#define cfgGFX_MMIOREG_CAM_ADDR3 0x30300218 +#define cfgGFX_MMIOREG_CAM_REMAP_ADDR3 0x3030021c +#define cfgGFX_MMIOREG_CAM_ADDR4 0x30300220 +#define cfgGFX_MMIOREG_CAM_REMAP_ADDR4 0x30300224 +#define cfgGFX_MMIOREG_CAM_ADDR5 0x30300228 +#define cfgGFX_MMIOREG_CAM_REMAP_ADDR5 0x3030022c +#define cfgGFX_MMIOREG_CAM_ADDR6 0x30300230 +#define cfgGFX_MMIOREG_CAM_REMAP_ADDR6 0x30300234 +#define cfgGFX_MMIOREG_CAM_ADDR7 0x30300238 +#define cfgGFX_MMIOREG_CAM_REMAP_ADDR7 0x3030023c +#define cfgGFX_MMIOREG_CAM_CNTL 0x30300240 +#define cfgGFX_MMIOREG_CAM_ZERO_CPL 0x30300244 +#define cfgGFX_MMIOREG_CAM_ONE_CPL 0x30300248 +#define cfgGFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x3030024c + + +// addressBlock: nbio_nbif0_syshub_mmreg_syshubdec +// base address: 0x30300000 +#define cfgSYSHUB_INDEX 0x30300020 +#define cfgSYSHUB_DATA 0x30300024 + + +// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 +// base address: 0x30300000 +#define cfgRCC_BIF_STRAP0 0x30303480 +#define cfgRCC_BIF_STRAP1 0x30303484 +#define cfgRCC_BIF_STRAP2 0x30303488 +#define cfgRCC_BIF_STRAP3 0x3030348c +#define cfgRCC_BIF_STRAP4 0x30303490 +#define cfgRCC_BIF_STRAP5 0x30303494 +#define cfgRCC_BIF_STRAP6 0x30303498 +#define cfgRCC_DEV0_PORT_STRAP0 0x3030349c +#define cfgRCC_DEV0_PORT_STRAP1 0x303034a0 +#define cfgRCC_DEV0_PORT_STRAP2 0x303034a4 +#define cfgRCC_DEV0_PORT_STRAP3 0x303034a8 +#define cfgRCC_DEV0_PORT_STRAP4 0x303034ac +#define cfgRCC_DEV0_PORT_STRAP5 0x303034b0 +#define cfgRCC_DEV0_PORT_STRAP6 0x303034b4 +#define cfgRCC_DEV0_PORT_STRAP7 0x303034b8 +#define cfgRCC_DEV0_PORT_STRAP8 0x303034bc +#define cfgRCC_DEV0_PORT_STRAP9 0x303034c0 +#define cfgRCC_DEV0_EPF0_STRAP0 0x303034c4 +#define cfgRCC_DEV0_EPF0_STRAP1 0x303034c8 +#define cfgRCC_DEV0_EPF0_STRAP13 0x303034cc +#define cfgRCC_DEV0_EPF0_STRAP2 0x303034d0 +#define cfgRCC_DEV0_EPF0_STRAP3 0x303034d4 +#define cfgRCC_DEV0_EPF0_STRAP4 0x303034d8 +#define cfgRCC_DEV0_EPF0_STRAP5 0x303034dc +#define cfgRCC_DEV0_EPF0_STRAP8 0x303034e0 +#define cfgRCC_DEV0_EPF0_STRAP9 0x303034e4 +#define cfgRCC_DEV0_EPF1_STRAP0 0x303034e8 +#define cfgRCC_DEV0_EPF1_STRAP10 0x303034ec +#define cfgRCC_DEV0_EPF1_STRAP11 0x303034f0 +#define cfgRCC_DEV0_EPF1_STRAP12 0x303034f4 +#define cfgRCC_DEV0_EPF1_STRAP13 0x303034f8 +#define cfgRCC_DEV0_EPF1_STRAP2 0x303034fc +#define cfgRCC_DEV0_EPF1_STRAP3 0x30303500 +#define cfgRCC_DEV0_EPF1_STRAP4 0x30303504 +#define cfgRCC_DEV0_EPF1_STRAP5 0x30303508 +#define cfgRCC_DEV0_EPF1_STRAP6 0x3030350c +#define cfgRCC_DEV0_EPF1_STRAP7 0x30303510 + + +// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 +// base address: 0x30300000 +#define cfgEP_PCIE_SCRATCH 0x30303514 +#define cfgEP_PCIE_CNTL 0x3030351c +#define cfgEP_PCIE_INT_CNTL 0x30303520 +#define cfgEP_PCIE_INT_STATUS 0x30303524 +#define cfgEP_PCIE_RX_CNTL2 0x30303528 +#define cfgEP_PCIE_BUS_CNTL 0x3030352c +#define cfgEP_PCIE_CFG_CNTL 0x30303530 +#define cfgEP_PCIE_TX_LTR_CNTL 0x30303538 +#define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x3030353c +#define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x3030353d +#define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x3030353e +#define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x3030353f +#define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x30303540 +#define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x30303541 +#define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x30303542 +#define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x30303543 +#define cfgEP_PCIE_STRAP_MISC 0x30303544 +#define cfgEP_PCIE_STRAP_MISC2 0x30303548 +#define cfgEP_PCIE_F0_DPA_CAP 0x30303550 +#define cfgEP_PCIE_F0_DPA_LATENCY_INDICATOR 0x30303554 +#define cfgEP_PCIE_F0_DPA_CNTL 0x30303555 +#define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x30303557 +#define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x30303558 +#define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x30303559 +#define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x3030355a +#define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x3030355b +#define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x3030355c +#define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x3030355d +#define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x3030355e +#define cfgEP_PCIE_PME_CONTROL 0x3030355f +#define cfgEP_PCIEP_RESERVED 0x30303560 +#define cfgEP_PCIE_TX_CNTL 0x30303568 +#define cfgEP_PCIE_TX_REQUESTER_ID 0x3030356c +#define cfgEP_PCIE_ERR_CNTL 0x30303570 +#define cfgEP_PCIE_RX_CNTL 0x30303574 +#define cfgEP_PCIE_LC_SPEED_CNTL 0x30303578 + + +// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 +// base address: 0x30300000 +#define cfgDN_PCIE_RESERVED 0x30303580 +#define cfgDN_PCIE_SCRATCH 0x30303584 +#define cfgDN_PCIE_CNTL 0x3030358c +#define cfgDN_PCIE_CONFIG_CNTL 0x30303590 +#define cfgDN_PCIE_RX_CNTL2 0x30303594 +#define cfgDN_PCIE_BUS_CNTL 0x30303598 +#define cfgDN_PCIE_CFG_CNTL 0x3030359c +#define cfgDN_PCIE_STRAP_F0 0x303035a0 +#define cfgDN_PCIE_STRAP_MISC 0x303035a4 +#define cfgDN_PCIE_STRAP_MISC2 0x303035a8 + + +// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 +// base address: 0x30300000 +#define cfgPCIE_ERR_CNTL 0x303035bc +#define cfgPCIE_RX_CNTL 0x303035c0 +#define cfgPCIE_LC_SPEED_CNTL 0x303035c4 +#define cfgPCIE_LC_CNTL2 0x303035c8 +#define cfgPCIEP_STRAP_MISC 0x303035cc +#define cfgLTR_MSG_INFO_FROM_EP 0x303035d0 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975] +// base address: 0x30303480 +#define cfgRCC_DEV0_EPF0_RCC_ERR_LOG 0x30303694 +#define cfgRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN 0x30303780 +#define cfgRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE 0x3030378c +#define cfgRCC_DEV0_EPF0_RCC_CONFIG_RESERVED 0x30303790 +#define cfgRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER 0x30303794 + + +// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1 +// base address: 0x30300000 +#define cfgRCC_ERR_INT_CNTL 0x30303698 +#define cfgRCC_BACO_CNTL_MISC 0x3030369c +#define cfgRCC_RESET_EN 0x303036a0 +#define cfgRCC_VDM_SUPPORT 0x303036a4 +#define cfgRCC_MARGIN_PARAM_CNTL0 0x303036a8 +#define cfgRCC_MARGIN_PARAM_CNTL1 0x303036ac +#define cfgRCC_GPUIOV_REGION 0x303036b0 +#define cfgRCC_PEER_REG_RANGE0 0x30303778 +#define cfgRCC_PEER_REG_RANGE1 0x3030377c +#define cfgRCC_BUS_CNTL 0x30303784 +#define cfgRCC_CONFIG_CNTL 0x30303788 +#define cfgRCC_CONFIG_F0_BASE 0x30303798 +#define cfgRCC_CONFIG_APER_SIZE 0x3030379c +#define cfgRCC_CONFIG_REG_APER_SIZE 0x303037a0 +#define cfgRCC_XDMA_LO 0x303037a4 +#define cfgRCC_XDMA_HI 0x303037a8 +#define cfgRCC_FEATURES_CONTROL_MISC 0x303037ac +#define cfgRCC_BUSNUM_CNTL1 0x303037b0 +#define cfgRCC_BUSNUM_LIST0 0x303037b4 +#define cfgRCC_BUSNUM_LIST1 0x303037b8 +#define cfgRCC_BUSNUM_CNTL2 0x303037bc +#define cfgRCC_CAPTURE_HOST_BUSNUM 0x303037c0 +#define cfgRCC_HOST_BUSNUM 0x303037c4 +#define cfgRCC_PEER0_FB_OFFSET_HI 0x303037c8 +#define cfgRCC_PEER0_FB_OFFSET_LO 0x303037cc +#define cfgRCC_PEER1_FB_OFFSET_HI 0x303037d0 +#define cfgRCC_PEER1_FB_OFFSET_LO 0x303037d4 +#define cfgRCC_PEER2_FB_OFFSET_HI 0x303037d8 +#define cfgRCC_PEER2_FB_OFFSET_LO 0x303037dc +#define cfgRCC_PEER3_FB_OFFSET_HI 0x303037e0 +#define cfgRCC_PEER3_FB_OFFSET_LO 0x303037e4 +#define cfgRCC_DEVFUNCNUM_LIST0 0x303037e8 +#define cfgRCC_DEVFUNCNUM_LIST1 0x303037ec +#define cfgRCC_DEV0_LINK_CNTL 0x303037f4 +#define cfgRCC_CMN_LINK_CNTL 0x303037f8 +#define cfgRCC_EP_REQUESTERID_RESTORE 0x303037fc +#define cfgRCC_LTR_LSWITCH_CNTL 0x30303800 +#define cfgRCC_MH_ARB_CNTL 0x30303804 + + +// addressBlock: nbio_nbif0_bif_bx_BIFDEC1 +// base address: 0x30300000 +#define cfgCC_BIF_BX_STRAP0 0x30303808 +#define cfgCC_BIF_BX_PINSTRAP0 0x30303810 +#define cfgBIF_MM_INDACCESS_CNTL 0x30303818 +#define cfgBUS_CNTL 0x3030381c +#define cfgBIF_SCRATCH0 0x30303820 +#define cfgBIF_SCRATCH1 0x30303824 +#define cfgBX_RESET_EN 0x30303834 +#define cfgMM_CFGREGS_CNTL 0x30303838 +#define cfgBX_RESET_CNTL 0x30303840 +#define cfgINTERRUPT_CNTL 0x30303844 +#define cfgINTERRUPT_CNTL2 0x30303848 +#define cfgCLKREQB_PAD_CNTL 0x30303860 +#define cfgBIF_FEATURES_CONTROL_MISC 0x3030386c +#define cfgBIF_DOORBELL_CNTL 0x30303870 +#define cfgBIF_DOORBELL_INT_CNTL 0x30303874 +#define cfgBIF_FB_EN 0x3030387c +#define cfgBIF_INTR_CNTL 0x30303880 +#define cfgBIF_MST_TRANS_PENDING_VF 0x303038a4 +#define cfgBIF_SLV_TRANS_PENDING_VF 0x303038a8 +#define cfgBACO_CNTL 0x303038ac +#define cfgBIF_BACO_EXIT_TIME0 0x303038b0 +#define cfgBIF_BACO_EXIT_TIMER1 0x303038b4 +#define cfgBIF_BACO_EXIT_TIMER2 0x303038b8 +#define cfgBIF_BACO_EXIT_TIMER3 0x303038bc +#define cfgBIF_BACO_EXIT_TIMER4 0x303038c0 +#define cfgMEM_TYPE_CNTL 0x303038c4 +#define cfgNBIF_GFX_ADDR_LUT_CNTL 0x303038cc +#define cfgNBIF_GFX_ADDR_LUT_0 0x303038d0 +#define cfgNBIF_GFX_ADDR_LUT_1 0x303038d4 +#define cfgNBIF_GFX_ADDR_LUT_2 0x303038d8 +#define cfgNBIF_GFX_ADDR_LUT_3 0x303038dc +#define cfgNBIF_GFX_ADDR_LUT_4 0x303038e0 +#define cfgNBIF_GFX_ADDR_LUT_5 0x303038e4 +#define cfgNBIF_GFX_ADDR_LUT_6 0x303038e8 +#define cfgNBIF_GFX_ADDR_LUT_7 0x303038ec +#define cfgNBIF_GFX_ADDR_LUT_8 0x303038f0 +#define cfgNBIF_GFX_ADDR_LUT_9 0x303038f4 +#define cfgNBIF_GFX_ADDR_LUT_10 0x303038f8 +#define cfgNBIF_GFX_ADDR_LUT_11 0x303038fc +#define cfgNBIF_GFX_ADDR_LUT_12 0x30303900 +#define cfgNBIF_GFX_ADDR_LUT_13 0x30303904 +#define cfgNBIF_GFX_ADDR_LUT_14 0x30303908 +#define cfgNBIF_GFX_ADDR_LUT_15 0x3030390c +#define cfgREMAP_HDP_MEM_FLUSH_CNTL 0x30303934 +#define cfgREMAP_HDP_REG_FLUSH_CNTL 0x30303938 +#define cfgBIF_RB_CNTL 0x3030393c +#define cfgBIF_RB_BASE 0x30303940 +#define cfgBIF_RB_RPTR 0x30303944 +#define cfgBIF_RB_WPTR 0x30303948 +#define cfgBIF_RB_WPTR_ADDR_HI 0x3030394c +#define cfgBIF_RB_WPTR_ADDR_LO 0x30303950 +#define cfgMAILBOX_INDEX 0x30303954 +#define cfgBIF_MP1_INTR_CTRL 0x30303988 +#define cfgBIF_UVD_GPUIOV_CFG_SIZE 0x3030398c +#define cfgBIF_VCE_GPUIOV_CFG_SIZE 0x30303990 +#define cfgBIF_GFX_SDMA_GPUIOV_CFG_SIZE 0x30303994 +#define cfgBIF_PERSTB_PAD_CNTL 0x303039a0 +#define cfgBIF_PX_EN_PAD_CNTL 0x303039a4 +#define cfgBIF_REFPADKIN_PAD_CNTL 0x303039a8 +#define cfgBIF_CLKREQB_PAD_CNTL 0x303039ac +#define cfgBIF_PWRBRK_PAD_CNTL 0x303039b0 +#define cfgBIF_WAKEB_PAD_CNTL 0x303039b4 +#define cfgBIF_VAUX_PRESENT_PAD_CNTL 0x303039b8 + + +// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 +// base address: 0x30300000 +#define cfgBIF_BX_PF_BIF_BME_STATUS 0x3030382c +#define cfgBIF_BX_PF_BIF_ATOMIC_ERR_LOG 0x30303830 +#define cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x3030384c +#define cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x30303850 +#define cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL 0x30303854 +#define cfgBIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL 0x30303858 +#define cfgBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL 0x3030385c +#define cfgBIF_BX_PF_GPU_HDP_FLUSH_REQ 0x30303898 +#define cfgBIF_BX_PF_GPU_HDP_FLUSH_DONE 0x3030389c +#define cfgBIF_BX_PF_BIF_TRANS_PENDING 0x303038a0 +#define cfgBIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS 0x303038c8 +#define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0 0x30303958 +#define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1 0x3030395c +#define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2 0x30303960 +#define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3 0x30303964 +#define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0 0x30303968 +#define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1 0x3030396c +#define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2 0x30303970 +#define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3 0x30303974 +#define cfgBIF_BX_PF_MAILBOX_CONTROL 0x30303978 +#define cfgBIF_BX_PF_MAILBOX_INT_CNTL 0x3030397c +#define cfgBIF_BX_PF_BIF_VMHV_MAILBOX 0x30303980 + + +// addressBlock: nbio_nbif0_gdc_GDCDEC +// base address: 0x30300000 +#define cfgA2S_CNTL_CL0 0x30303ac0 +#define cfgA2S_CNTL_CL1 0x30303ac4 +#define cfgA2S_CNTL3_CL0 0x30303b00 +#define cfgA2S_CNTL3_CL1 0x30303b04 +#define cfgA2S_CNTL_SW0 0x30303b40 +#define cfgA2S_CNTL_SW1 0x30303b44 +#define cfgA2S_CNTL_SW2 0x30303b48 +#define cfgA2S_CPLBUF_ALLOC_CNTL 0x30303b70 +#define cfgA2S_TAG_ALLOC_0 0x30303b74 +#define cfgA2S_TAG_ALLOC_1 0x30303b78 +#define cfgA2S_MISC_CNTL 0x30303b84 +#define cfgNGDC_SDP_PORT_CTRL 0x30303b88 +#define cfgSHUB_REGS_IF_CTL 0x30303b8c +#define cfgNGDC_MGCG_CTRL 0x30303ba8 +#define cfgNGDC_RESERVED_0 0x30303bac +#define cfgNGDC_RESERVED_1 0x30303bb0 +#define cfgNGDC_SDP_PORT_CTRL_SOCCLK 0x30303bb4 +#define cfgBIF_SDMA0_DOORBELL_RANGE 0x30303bc0 +#define cfgBIF_SDMA1_DOORBELL_RANGE 0x30303bc4 +#define cfgBIF_IH_DOORBELL_RANGE 0x30303bc8 +#define cfgBIF_MMSCH0_DOORBELL_RANGE 0x30303bcc +#define cfgBIF_ACV_DOORBELL_RANGE 0x30303bd0 +#define cfgBIF_DOORBELL_FENCE_CNTL 0x30303bf8 +#define cfgS2A_MISC_CNTL 0x30303bfc +#define cfgNGDC_PG_MISC_CTRL 0x30303c40 +#define cfgNGDC_PGMST_CTRL 0x30303c44 +#define cfgNGDC_PGSLV_CTRL 0x30303c48 + + +// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2 +// base address: 0x30300000 +#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO 0x30342000 +#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI 0x30342004 +#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA 0x30342008 +#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL 0x3034200c +#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO 0x30342010 +#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI 0x30342014 +#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA 0x30342018 +#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL 0x3034201c +#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO 0x30342020 +#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI 0x30342024 +#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA 0x30342028 +#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL 0x3034202c +#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO 0x30342030 +#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI 0x30342034 +#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA 0x30342038 +#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL 0x3034203c +#define cfgRCC_DEV0_EPF0_GFXMSIX_PBA 0x30343000 + +#endif |