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path: root/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h
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Diffstat (limited to 'drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h')
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h118945
1 files changed, 118945 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h
new file mode 100644
index 000000000000..88602479a1aa
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h
@@ -0,0 +1,118945 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _nbio_7_0_SH_MASK_HEADER
+#define _nbio_7_0_SH_MASK_HEADER
+
+
+// addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec
+//NB_NBCFG0_NB_VENDOR_ID
+#define NB_NBCFG0_NB_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define NB_NBCFG0_NB_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//NB_NBCFG0_NB_DEVICE_ID
+#define NB_NBCFG0_NB_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define NB_NBCFG0_NB_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//NB_NBCFG0_NB_COMMAND
+#define NB_NBCFG0_NB_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define NB_NBCFG0_NB_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define NB_NBCFG0_NB_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define NB_NBCFG0_NB_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define NB_NBCFG0_NB_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define NB_NBCFG0_NB_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+//NB_NBCFG0_NB_STATUS
+#define NB_NBCFG0_NB_STATUS__CAP_LIST__SHIFT 0x4
+#define NB_NBCFG0_NB_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define NB_NBCFG0_NB_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define NB_NBCFG0_NB_STATUS__CAP_LIST_MASK 0x0010L
+#define NB_NBCFG0_NB_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define NB_NBCFG0_NB_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+//NB_NBCFG0_NB_REVISION_ID
+#define NB_NBCFG0_NB_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define NB_NBCFG0_NB_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define NB_NBCFG0_NB_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define NB_NBCFG0_NB_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//NB_NBCFG0_NB_REGPROG_INF
+#define NB_NBCFG0_NB_REGPROG_INF__REG_LEVEL_PROG_INF__SHIFT 0x0
+#define NB_NBCFG0_NB_REGPROG_INF__REG_LEVEL_PROG_INF_MASK 0xFFL
+//NB_NBCFG0_NB_SUB_CLASS
+#define NB_NBCFG0_NB_SUB_CLASS__SUB_CLASS_INF__SHIFT 0x0
+#define NB_NBCFG0_NB_SUB_CLASS__SUB_CLASS_INF_MASK 0xFFL
+//NB_NBCFG0_NB_BASE_CODE
+#define NB_NBCFG0_NB_BASE_CODE__BASE_CLASS_CODE__SHIFT 0x0
+#define NB_NBCFG0_NB_BASE_CODE__BASE_CLASS_CODE_MASK 0xFFL
+//NB_NBCFG0_NB_CACHE_LINE
+#define NB_NBCFG0_NB_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define NB_NBCFG0_NB_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//NB_NBCFG0_NB_LATENCY
+#define NB_NBCFG0_NB_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define NB_NBCFG0_NB_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//NB_NBCFG0_NB_HEADER
+#define NB_NBCFG0_NB_HEADER__HEADER_TYPE__SHIFT 0x0
+#define NB_NBCFG0_NB_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define NB_NBCFG0_NB_HEADER__HEADER_TYPE_MASK 0x7FL
+#define NB_NBCFG0_NB_HEADER__DEVICE_TYPE_MASK 0x80L
+//NB_NBCFG0_NB_ADAPTER_ID
+#define NB_NBCFG0_NB_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define NB_NBCFG0_NB_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define NB_NBCFG0_NB_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define NB_NBCFG0_NB_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//NB_NBCFG0_NB_CAPABILITIES_PTR
+#define NB_NBCFG0_NB_CAPABILITIES_PTR__CAP_PTR__SHIFT 0x0
+#define NB_NBCFG0_NB_CAPABILITIES_PTR__CAP_PTR_MASK 0x000000FFL
+//NB_NBCFG0_NB_HEADER_W
+#define NB_NBCFG0_NB_HEADER_W__DEVICE_TYPE__SHIFT 0x7
+#define NB_NBCFG0_NB_HEADER_W__DEVICE_TYPE_MASK 0x00000080L
+//NB_NBCFG0_NB_PCI_CTRL
+#define NB_NBCFG0_NB_PCI_CTRL__PMEDis__SHIFT 0x4
+#define NB_NBCFG0_NB_PCI_CTRL__SErrDis__SHIFT 0x5
+#define NB_NBCFG0_NB_PCI_CTRL__MMIOEnable__SHIFT 0x17
+#define NB_NBCFG0_NB_PCI_CTRL__HPDis__SHIFT 0x1a
+#define NB_NBCFG0_NB_PCI_CTRL__PMEDis_MASK 0x00000010L
+#define NB_NBCFG0_NB_PCI_CTRL__SErrDis_MASK 0x00000020L
+#define NB_NBCFG0_NB_PCI_CTRL__MMIOEnable_MASK 0x00800000L
+#define NB_NBCFG0_NB_PCI_CTRL__HPDis_MASK 0x04000000L
+//NB_NBCFG0_NB_ADAPTER_ID_W
+#define NB_NBCFG0_NB_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define NB_NBCFG0_NB_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define NB_NBCFG0_NB_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define NB_NBCFG0_NB_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//NB_NBCFG0_NB_SMN_INDEX_EXTENSION_0
+#define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_0__NB_SMN_INDEX_EXTENSION_0__SHIFT 0x0
+#define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_0__NB_SMN_INDEX_EXTENSION_0_MASK 0x0000000FL
+//NB_NBCFG0_NB_SMN_INDEX_0
+#define NB_NBCFG0_NB_SMN_INDEX_0__NB_SMN_INDEX_0__SHIFT 0x0
+#define NB_NBCFG0_NB_SMN_INDEX_0__NB_SMN_INDEX_0_MASK 0xFFFFFFFFL
+//NB_NBCFG0_NB_SMN_DATA_0
+#define NB_NBCFG0_NB_SMN_DATA_0__NB_SMN_DATA_0__SHIFT 0x0
+#define NB_NBCFG0_NB_SMN_DATA_0__NB_SMN_DATA_0_MASK 0xFFFFFFFFL
+//NB_NBCFG0_NBCFG_SCRATCH_0
+#define NB_NBCFG0_NBCFG_SCRATCH_0__NBCFG_SCRATCH_0__SHIFT 0x0
+#define NB_NBCFG0_NBCFG_SCRATCH_0__NBCFG_SCRATCH_0_MASK 0xFFFFFFFFL
+//NB_NBCFG0_NBCFG_SCRATCH_1
+#define NB_NBCFG0_NBCFG_SCRATCH_1__NBCFG_SCRATCH_1__SHIFT 0x0
+#define NB_NBCFG0_NBCFG_SCRATCH_1__NBCFG_SCRATCH_1_MASK 0xFFFFFFFFL
+//NB_NBCFG0_NBCFG_SCRATCH_2
+#define NB_NBCFG0_NBCFG_SCRATCH_2__NBCFG_SCRATCH_2__SHIFT 0x0
+#define NB_NBCFG0_NBCFG_SCRATCH_2__NBCFG_SCRATCH_2_MASK 0xFFFFFFFFL
+//NB_NBCFG0_NBCFG_SCRATCH_3
+#define NB_NBCFG0_NBCFG_SCRATCH_3__NBCFG_SCRATCH_3__SHIFT 0x0
+#define NB_NBCFG0_NBCFG_SCRATCH_3__NBCFG_SCRATCH_3_MASK 0xFFFFFFFFL
+//NB_NBCFG0_NBCFG_SCRATCH_4
+#define NB_NBCFG0_NBCFG_SCRATCH_4__NBCFG_SCRATCH_4__SHIFT 0x0
+#define NB_NBCFG0_NBCFG_SCRATCH_4__NBCFG_SCRATCH_4_MASK 0xFFFFFFFFL
+//NB_NBCFG0_NB_PCI_ARB
+#define NB_NBCFG0_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3
+#define NB_NBCFG0_NB_PCI_ARB__PMEMode__SHIFT 0x8
+#define NB_NBCFG0_NB_PCI_ARB__PMETurnOff__SHIFT 0x9
+#define NB_NBCFG0_NB_PCI_ARB__PMETOAckStatus__SHIFT 0xa
+#define NB_NBCFG0_NB_PCI_ARB__PMETarget__SHIFT 0x10
+#define NB_NBCFG0_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L
+#define NB_NBCFG0_NB_PCI_ARB__PMEMode_MASK 0x00000100L
+#define NB_NBCFG0_NB_PCI_ARB__PMETurnOff_MASK 0x00000200L
+#define NB_NBCFG0_NB_PCI_ARB__PMETOAckStatus_MASK 0x00000400L
+#define NB_NBCFG0_NB_PCI_ARB__PMETarget_MASK 0x00FF0000L
+//NB_NBCFG0_NB_DRAM_SLOT1_BASE
+#define NB_NBCFG0_NB_DRAM_SLOT1_BASE__DRAM_BASE__SHIFT 0x17
+#define NB_NBCFG0_NB_DRAM_SLOT1_BASE__DRAM_BASE_MASK 0xFF800000L
+//NB_NBCFG0_NB_TOP_OF_DRAM_SLOT1
+#define NB_NBCFG0_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_BIT_32__SHIFT 0x0
+#define NB_NBCFG0_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17
+#define NB_NBCFG0_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_BIT_32_MASK 0x00000001L
+#define NB_NBCFG0_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L
+//NB_NBCFG0_NB_SMN_INDEX_EXTENSION_1
+#define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_1__NB_SMN_INDEX_EXTENSION_1__SHIFT 0x0
+#define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_1__NB_SMN_INDEX_EXTENSION_1_MASK 0x0000000FL
+//NB_NBCFG0_NB_SMN_INDEX_1
+#define NB_NBCFG0_NB_SMN_INDEX_1__NB_SMN_INDEX_1__SHIFT 0x0
+#define NB_NBCFG0_NB_SMN_INDEX_1__NB_SMN_INDEX_1_MASK 0xFFFFFFFFL
+//NB_NBCFG0_NB_SMN_DATA_1
+#define NB_NBCFG0_NB_SMN_DATA_1__NB_SMN_DATA_1__SHIFT 0x0
+#define NB_NBCFG0_NB_SMN_DATA_1__NB_SMN_DATA_1_MASK 0xFFFFFFFFL
+//NB_NBCFG0_NB_INDEX_DATA_MUTEX0
+#define NB_NBCFG0_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0__SHIFT 0x0
+#define NB_NBCFG0_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_UNLOCK__SHIFT 0x1f
+#define NB_NBCFG0_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_MASK 0x7FFFFFFFL
+#define NB_NBCFG0_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_UNLOCK_MASK 0x80000000L
+//NB_NBCFG0_NB_INDEX_DATA_MUTEX1
+#define NB_NBCFG0_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1__SHIFT 0x0
+#define NB_NBCFG0_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_UNLOCK__SHIFT 0x1f
+#define NB_NBCFG0_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_MASK 0x7FFFFFFFL
+#define NB_NBCFG0_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_UNLOCK_MASK 0x80000000L
+//NB_NBCFG0_NB_SMN_INDEX_EXTENSION_2
+#define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_2__NB_SMN_INDEX_EXTENSION_2__SHIFT 0x0
+#define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_2__NB_SMN_INDEX_EXTENSION_2_MASK 0x0000000FL
+//NB_NBCFG0_NB_SMN_INDEX_2
+#define NB_NBCFG0_NB_SMN_INDEX_2__NB_SMN_INDEX_2__SHIFT 0x0
+#define NB_NBCFG0_NB_SMN_INDEX_2__NB_SMN_INDEX_2_MASK 0xFFFFFFFFL
+//NB_NBCFG0_NB_SMN_DATA_2
+#define NB_NBCFG0_NB_SMN_DATA_2__NB_SMN_DATA_2__SHIFT 0x0
+#define NB_NBCFG0_NB_SMN_DATA_2__NB_SMN_DATA_2_MASK 0xFFFFFFFFL
+//NB_NBCFG0_NB_SMN_INDEX_EXTENSION_3
+#define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_3__NB_SMN_INDEX_EXTENSION_3__SHIFT 0x0
+#define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_3__NB_SMN_INDEX_EXTENSION_3_MASK 0x0000000FL
+//NB_NBCFG0_NB_SMN_INDEX_3
+#define NB_NBCFG0_NB_SMN_INDEX_3__NB_SMN_INDEX_3__SHIFT 0x0
+#define NB_NBCFG0_NB_SMN_INDEX_3__NB_SMN_INDEX_3_MASK 0xFFFFFFFFL
+//NB_NBCFG0_NB_SMN_DATA_3
+#define NB_NBCFG0_NB_SMN_DATA_3__NB_SMN_DATA_3__SHIFT 0x0
+#define NB_NBCFG0_NB_SMN_DATA_3__NB_SMN_DATA_3_MASK 0xFFFFFFFFL
+//NB_NBCFG0_NB_SMN_INDEX_EXTENSION_4
+#define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_4__NB_SMN_INDEX_EXTENSION_4__SHIFT 0x0
+#define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_4__NB_SMN_INDEX_EXTENSION_4_MASK 0x0000000FL
+//NB_NBCFG0_NB_SMN_INDEX_4
+#define NB_NBCFG0_NB_SMN_INDEX_4__NB_SMN_INDEX_4__SHIFT 0x0
+#define NB_NBCFG0_NB_SMN_INDEX_4__NB_SMN_INDEX_4_MASK 0xFFFFFFFFL
+//NB_NBCFG0_NB_SMN_DATA_4
+#define NB_NBCFG0_NB_SMN_DATA_4__NB_SMN_DATA_4__SHIFT 0x0
+#define NB_NBCFG0_NB_SMN_DATA_4__NB_SMN_DATA_4_MASK 0xFFFFFFFFL
+//NB_NBCFG0_NB_SMN_INDEX_EXTENSION_5
+#define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_5__NB_SMN_INDEX_EXTENSION_5__SHIFT 0x0
+#define NB_NBCFG0_NB_SMN_INDEX_EXTENSION_5__NB_SMN_INDEX_EXTENSION_5_MASK 0x0000000FL
+//NB_NBCFG0_NB_SMN_INDEX_5
+#define NB_NBCFG0_NB_SMN_INDEX_5__NB_SMN_INDEX_5__SHIFT 0x0
+#define NB_NBCFG0_NB_SMN_INDEX_5__NB_SMN_INDEX_5_MASK 0xFFFFFFFFL
+//NB_NBCFG0_NB_SMN_DATA_5
+#define NB_NBCFG0_NB_SMN_DATA_5__NB_SMN_DATA_5__SHIFT 0x0
+#define NB_NBCFG0_NB_SMN_DATA_5__NB_SMN_DATA_5_MASK 0xFFFFFFFFL
+//NB_NBCFG0_NB_PERF_CNT_CTRL
+#define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_CNT_EN__SHIFT 0x0
+#define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_SHADOW_WR__SHIFT 0x1
+#define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET__SHIFT 0x2
+#define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY__SHIFT 0x8
+#define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY_EN__SHIFT 0xf
+#define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY__SHIFT 0x10
+#define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY_EN__SHIFT 0x17
+#define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_CNT_EN_MASK 0x00000001L
+#define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_SHADOW_WR_MASK 0x00000002L
+#define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_MASK 0x00000004L
+#define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY_MASK 0x00000F00L
+#define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY_EN_MASK 0x00008000L
+#define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY_MASK 0x000F0000L
+#define NB_NBCFG0_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY_EN_MASK 0x00800000L
+//NB_NBCFG0_NB_SMN_INDEX_6
+#define NB_NBCFG0_NB_SMN_INDEX_6__NB_SMN_INDEX_6__SHIFT 0x0
+#define NB_NBCFG0_NB_SMN_INDEX_6__NB_SMN_INDEX_6_MASK 0xFFFFFFFFL
+//NB_NBCFG0_NB_SMN_DATA_6
+#define NB_NBCFG0_NB_SMN_DATA_6__NB_SMN_DATA_6__SHIFT 0x0
+#define NB_NBCFG0_NB_SMN_DATA_6__NB_SMN_DATA_6_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_iohub_iommu_l2_iommul2cfg
+//IOMMU_L2_0_IOMMU_VENDOR_ID
+#define IOMMU_L2_0_IOMMU_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//IOMMU_L2_0_IOMMU_DEVICE_ID
+#define IOMMU_L2_0_IOMMU_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//IOMMU_L2_0_IOMMU_COMMAND
+#define IOMMU_L2_0_IOMMU_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define IOMMU_L2_0_IOMMU_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define IOMMU_L2_0_IOMMU_COMMAND__Reserved1__SHIFT 0x3
+#define IOMMU_L2_0_IOMMU_COMMAND__PARITY_ERROR_EN__SHIFT 0x6
+#define IOMMU_L2_0_IOMMU_COMMAND__Reserved0__SHIFT 0x7
+#define IOMMU_L2_0_IOMMU_COMMAND__SERR_EN__SHIFT 0x8
+#define IOMMU_L2_0_IOMMU_COMMAND__Reserved2__SHIFT 0x9
+#define IOMMU_L2_0_IOMMU_COMMAND__INTERRUPT_DIS__SHIFT 0xa
+#define IOMMU_L2_0_IOMMU_COMMAND__Reserved__SHIFT 0xb
+#define IOMMU_L2_0_IOMMU_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define IOMMU_L2_0_IOMMU_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define IOMMU_L2_0_IOMMU_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define IOMMU_L2_0_IOMMU_COMMAND__Reserved1_MASK 0x0038L
+#define IOMMU_L2_0_IOMMU_COMMAND__PARITY_ERROR_EN_MASK 0x0040L
+#define IOMMU_L2_0_IOMMU_COMMAND__Reserved0_MASK 0x0080L
+#define IOMMU_L2_0_IOMMU_COMMAND__SERR_EN_MASK 0x0100L
+#define IOMMU_L2_0_IOMMU_COMMAND__Reserved2_MASK 0x0200L
+#define IOMMU_L2_0_IOMMU_COMMAND__INTERRUPT_DIS_MASK 0x0400L
+#define IOMMU_L2_0_IOMMU_COMMAND__Reserved_MASK 0xF800L
+//IOMMU_L2_0_IOMMU_STATUS
+#define IOMMU_L2_0_IOMMU_STATUS__Reserved__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_STATUS__INT_Status__SHIFT 0x3
+#define IOMMU_L2_0_IOMMU_STATUS__CAP_LIST__SHIFT 0x4
+#define IOMMU_L2_0_IOMMU_STATUS__Reserved1__SHIFT 0x5
+#define IOMMU_L2_0_IOMMU_STATUS__MASTER_DATA_ERROR__SHIFT 0x8
+#define IOMMU_L2_0_IOMMU_STATUS__Reserved2__SHIFT 0x9
+#define IOMMU_L2_0_IOMMU_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define IOMMU_L2_0_IOMMU_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define IOMMU_L2_0_IOMMU_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define IOMMU_L2_0_IOMMU_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define IOMMU_L2_0_IOMMU_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define IOMMU_L2_0_IOMMU_STATUS__Reserved_MASK 0x0007L
+#define IOMMU_L2_0_IOMMU_STATUS__INT_Status_MASK 0x0008L
+#define IOMMU_L2_0_IOMMU_STATUS__CAP_LIST_MASK 0x0010L
+#define IOMMU_L2_0_IOMMU_STATUS__Reserved1_MASK 0x00E0L
+#define IOMMU_L2_0_IOMMU_STATUS__MASTER_DATA_ERROR_MASK 0x0100L
+#define IOMMU_L2_0_IOMMU_STATUS__Reserved2_MASK 0x0600L
+#define IOMMU_L2_0_IOMMU_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define IOMMU_L2_0_IOMMU_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define IOMMU_L2_0_IOMMU_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define IOMMU_L2_0_IOMMU_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define IOMMU_L2_0_IOMMU_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//IOMMU_L2_0_IOMMU_REVISION_ID
+#define IOMMU_L2_0_IOMMU_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define IOMMU_L2_0_IOMMU_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define IOMMU_L2_0_IOMMU_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//IOMMU_L2_0_IOMMU_REGPROG_INF
+#define IOMMU_L2_0_IOMMU_REGPROG_INF__REG_LEVEL_PROG_INF__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_REGPROG_INF__REG_LEVEL_PROG_INF_MASK 0xFFL
+//IOMMU_L2_0_IOMMU_SUB_CLASS
+#define IOMMU_L2_0_IOMMU_SUB_CLASS__SUB_CLASS_INF__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_SUB_CLASS__SUB_CLASS_INF_MASK 0xFFL
+//IOMMU_L2_0_IOMMU_BASE_CODE
+#define IOMMU_L2_0_IOMMU_BASE_CODE__BASE_CLASS_CODE__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_BASE_CODE__BASE_CLASS_CODE_MASK 0xFFL
+//IOMMU_L2_0_IOMMU_CACHE_LINE
+#define IOMMU_L2_0_IOMMU_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//IOMMU_L2_0_IOMMU_LATENCY
+#define IOMMU_L2_0_IOMMU_LATENCY__LATENCY__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_LATENCY__LATENCY_MASK 0xFFL
+//IOMMU_L2_0_IOMMU_HEADER
+#define IOMMU_L2_0_IOMMU_HEADER__HEADER_TYPE__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_HEADER__HEADER_TYPE_MASK 0xFFL
+//IOMMU_L2_0_IOMMU_BIST
+#define IOMMU_L2_0_IOMMU_BIST__BIST_COMP__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_BIST__BIST_STRT__SHIFT 0x6
+#define IOMMU_L2_0_IOMMU_BIST__BIST_CAP__SHIFT 0x7
+#define IOMMU_L2_0_IOMMU_BIST__BIST_COMP_MASK 0x0FL
+#define IOMMU_L2_0_IOMMU_BIST__BIST_STRT_MASK 0x40L
+#define IOMMU_L2_0_IOMMU_BIST__BIST_CAP_MASK 0x80L
+//IOMMU_L2_0_IOMMU_ADAPTER_ID
+#define IOMMU_L2_0_IOMMU_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define IOMMU_L2_0_IOMMU_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define IOMMU_L2_0_IOMMU_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//IOMMU_L2_0_IOMMU_CAPABILITIES_PTR
+#define IOMMU_L2_0_IOMMU_CAPABILITIES_PTR__CAP_PTR__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_CAPABILITIES_PTR__CAP_PTR_MASK 0x000000FFL
+//IOMMU_L2_0_IOMMU_INTERRUPT_LINE
+#define IOMMU_L2_0_IOMMU_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//IOMMU_L2_0_IOMMU_INTERRUPT_PIN
+#define IOMMU_L2_0_IOMMU_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//IOMMU_L2_0_IOMMU_CAP_HEADER
+#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_ID__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_PTR__SHIFT 0x8
+#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_TYPE__SHIFT 0x10
+#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_REV__SHIFT 0x13
+#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_IO_TLBSUP__SHIFT 0x18
+#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_HT_TUNNEL_SUP__SHIFT 0x19
+#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_NP_CACHE__SHIFT 0x1a
+#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_EFR_SUP__SHIFT 0x1b
+#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_EXT__SHIFT 0x1c
+#define IOMMU_L2_0_IOMMU_CAP_HEADER__Reserved__SHIFT 0x1d
+#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_ID_MASK 0x000000FFL
+#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_PTR_MASK 0x0000FF00L
+#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_TYPE_MASK 0x00070000L
+#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_REV_MASK 0x00F80000L
+#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_IO_TLBSUP_MASK 0x01000000L
+#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_HT_TUNNEL_SUP_MASK 0x02000000L
+#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_NP_CACHE_MASK 0x04000000L
+#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_EFR_SUP_MASK 0x08000000L
+#define IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_EXT_MASK 0x10000000L
+#define IOMMU_L2_0_IOMMU_CAP_HEADER__Reserved_MASK 0xE0000000L
+//IOMMU_L2_0_IOMMU_CAP_BASE_LO
+#define IOMMU_L2_0_IOMMU_CAP_BASE_LO__IOMMU_ENABLE__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_CAP_BASE_LO__Reserved__SHIFT 0x1
+#define IOMMU_L2_0_IOMMU_CAP_BASE_LO__IOMMU_BASE_ADDR_LO__SHIFT 0x13
+#define IOMMU_L2_0_IOMMU_CAP_BASE_LO__IOMMU_ENABLE_MASK 0x00000001L
+#define IOMMU_L2_0_IOMMU_CAP_BASE_LO__Reserved_MASK 0x00003FFEL
+#define IOMMU_L2_0_IOMMU_CAP_BASE_LO__IOMMU_BASE_ADDR_LO_MASK 0xFFF80000L
+//IOMMU_L2_0_IOMMU_CAP_BASE_HI
+#define IOMMU_L2_0_IOMMU_CAP_BASE_HI__IOMMU_BASE_ADDR_HI__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_CAP_BASE_HI__IOMMU_BASE_ADDR_HI_MASK 0xFFFFFFFFL
+//IOMMU_L2_0_IOMMU_CAP_RANGE
+#define IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_UNIT_ID__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_CAP_RANGE__Reserved__SHIFT 0x5
+#define IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_RNG_VALID__SHIFT 0x7
+#define IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_BUS_NUMBER__SHIFT 0x8
+#define IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_FIRST_DEVICE__SHIFT 0x10
+#define IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_LAST_DEVICE__SHIFT 0x18
+#define IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_UNIT_ID_MASK 0x0000001FL
+#define IOMMU_L2_0_IOMMU_CAP_RANGE__Reserved_MASK 0x00000060L
+#define IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_RNG_VALID_MASK 0x00000080L
+#define IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_BUS_NUMBER_MASK 0x0000FF00L
+#define IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_FIRST_DEVICE_MASK 0x00FF0000L
+#define IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_LAST_DEVICE_MASK 0xFF000000L
+//IOMMU_L2_0_IOMMU_CAP_MISC
+#define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_MSI_NUM__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_GVA_SIZE__SHIFT 0x5
+#define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_PA_SIZE__SHIFT 0x8
+#define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_VA_SIZE__SHIFT 0xf
+#define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV__SHIFT 0x16
+#define IOMMU_L2_0_IOMMU_CAP_MISC__Reserved1__SHIFT 0x17
+#define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_MSI_NUM_PPR__SHIFT 0x1b
+#define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_MSI_NUM_MASK 0x0000001FL
+#define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_GVA_SIZE_MASK 0x000000E0L
+#define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_PA_SIZE_MASK 0x00007F00L
+#define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_VA_SIZE_MASK 0x003F8000L
+#define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV_MASK 0x00400000L
+#define IOMMU_L2_0_IOMMU_CAP_MISC__Reserved1_MASK 0x07800000L
+#define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_MSI_NUM_PPR_MASK 0xF8000000L
+//IOMMU_L2_0_IOMMU_CAP_MISC_1
+#define IOMMU_L2_0_IOMMU_CAP_MISC_1__IOMMU_MSI_NUM_GA__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE__SHIFT 0x5
+#define IOMMU_L2_0_IOMMU_CAP_MISC_1__DVM_MODE__SHIFT 0x6
+#define IOMMU_L2_0_IOMMU_CAP_MISC_1__SMMUMMIO_EN__SHIFT 0xf
+#define IOMMU_L2_0_IOMMU_CAP_MISC_1__SMMUMMIO_LOCK__SHIFT 0x1f
+#define IOMMU_L2_0_IOMMU_CAP_MISC_1__IOMMU_MSI_NUM_GA_MASK 0x0000001FL
+#define IOMMU_L2_0_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE_MASK 0x00000020L
+#define IOMMU_L2_0_IOMMU_CAP_MISC_1__DVM_MODE_MASK 0x000000C0L
+#define IOMMU_L2_0_IOMMU_CAP_MISC_1__SMMUMMIO_EN_MASK 0x00008000L
+#define IOMMU_L2_0_IOMMU_CAP_MISC_1__SMMUMMIO_LOCK_MASK 0x80000000L
+//IOMMU_L2_0_IOMMU_MSI_CAP
+#define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_CAP_ID__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_CAP_PTR__SHIFT 0x8
+#define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_EN__SHIFT 0x10
+#define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_MULT_MESS_CAP__SHIFT 0x11
+#define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_MULT_MESS_EN__SHIFT 0x14
+#define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_64_EN__SHIFT 0x17
+#define IOMMU_L2_0_IOMMU_MSI_CAP__Reserved__SHIFT 0x18
+#define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_CAP_ID_MASK 0x000000FFL
+#define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_CAP_PTR_MASK 0x0000FF00L
+#define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_EN_MASK 0x00010000L
+#define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_MULT_MESS_CAP_MASK 0x000E0000L
+#define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_MULT_MESS_EN_MASK 0x00700000L
+#define IOMMU_L2_0_IOMMU_MSI_CAP__MSI_64_EN_MASK 0x00800000L
+#define IOMMU_L2_0_IOMMU_MSI_CAP__Reserved_MASK 0xFF000000L
+//IOMMU_L2_0_IOMMU_MSI_ADDR_LO
+#define IOMMU_L2_0_IOMMU_MSI_ADDR_LO__Reserved__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_MSI_ADDR_LO__MSI_ADDR_LO__SHIFT 0x2
+#define IOMMU_L2_0_IOMMU_MSI_ADDR_LO__Reserved_MASK 0x00000003L
+#define IOMMU_L2_0_IOMMU_MSI_ADDR_LO__MSI_ADDR_LO_MASK 0xFFFFFFFCL
+//IOMMU_L2_0_IOMMU_MSI_ADDR_HI
+#define IOMMU_L2_0_IOMMU_MSI_ADDR_HI__MSI_ADDR_HI__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_MSI_ADDR_HI__MSI_ADDR_HI_MASK 0xFFFFFFFFL
+//IOMMU_L2_0_IOMMU_MSI_DATA
+#define IOMMU_L2_0_IOMMU_MSI_DATA__MSI_DATA__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_MSI_DATA__Reserved__SHIFT 0x10
+#define IOMMU_L2_0_IOMMU_MSI_DATA__MSI_DATA_MASK 0x0000FFFFL
+#define IOMMU_L2_0_IOMMU_MSI_DATA__Reserved_MASK 0xFFFF0000L
+//IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP
+#define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_ID__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR__SHIFT 0x8
+#define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_EN__SHIFT 0x10
+#define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_FIXD__SHIFT 0x11
+#define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_RSV__SHIFT 0x12
+#define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE__SHIFT 0x1b
+#define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_ID_MASK 0x000000FFL
+#define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR_MASK 0x0000FF00L
+#define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_EN_MASK 0x00010000L
+#define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_FIXD_MASK 0x00020000L
+#define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_RSV_MASK 0x07FC0000L
+#define IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE_MASK 0xF8000000L
+//IOMMU_L2_0_IOMMU_ADAPTER_ID_W
+#define IOMMU_L2_0_IOMMU_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_W__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_ADAPTER_ID_W__SUBSYSTEM_ID_W__SHIFT 0x10
+#define IOMMU_L2_0_IOMMU_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_W_MASK 0x0000FFFFL
+#define IOMMU_L2_0_IOMMU_ADAPTER_ID_W__SUBSYSTEM_ID_W_MASK 0xFFFF0000L
+//IOMMU_L2_0_IOMMU_CONTROL_W
+#define IOMMU_L2_0_IOMMU_CONTROL_W__INTERRUPT_PIN_W__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_CONTROL_W__MINOR_REV_ID_W__SHIFT 0x4
+#define IOMMU_L2_0_IOMMU_CONTROL_W__IO_TLBSUP_W__SHIFT 0x8
+#define IOMMU_L2_0_IOMMU_CONTROL_W__EFR_SUP_W__SHIFT 0x9
+#define IOMMU_L2_0_IOMMU_CONTROL_W__MSI_MULT_MESS_CAP_W__SHIFT 0xa
+#define IOMMU_L2_0_IOMMU_CONTROL_W__IOMMU_CAP_EXT_W__SHIFT 0xd
+#define IOMMU_L2_0_IOMMU_CONTROL_W__INTERRUPT_PIN_W_MASK 0x00000007L
+#define IOMMU_L2_0_IOMMU_CONTROL_W__MINOR_REV_ID_W_MASK 0x000000F0L
+#define IOMMU_L2_0_IOMMU_CONTROL_W__IO_TLBSUP_W_MASK 0x00000100L
+#define IOMMU_L2_0_IOMMU_CONTROL_W__EFR_SUP_W_MASK 0x00000200L
+#define IOMMU_L2_0_IOMMU_CONTROL_W__MSI_MULT_MESS_CAP_W_MASK 0x00001C00L
+#define IOMMU_L2_0_IOMMU_CONTROL_W__IOMMU_CAP_EXT_W_MASK 0x00002000L
+//IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__PREF_SUP_W__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__PPR_SUP_W__SHIFT 0x1
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved3__SHIFT 0x2
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__NX_SUP_W__SHIFT 0x3
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__GT_SUP_W__SHIFT 0x4
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved2__SHIFT 0x5
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__IA_SUP_W__SHIFT 0x6
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__GA_SUP_W__SHIFT 0x7
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__HE_SUP_W__SHIFT 0x8
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__PC_SUP_W__SHIFT 0x9
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__HATS_W__SHIFT 0xa
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__US_SUP_W__SHIFT 0xc
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved5__SHIFT 0xd
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__GAM_SUP_W__SHIFT 0x15
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__PPRF_W__SHIFT 0x18
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved6__SHIFT 0x1a
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__EVENTF_W__SHIFT 0x1c
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__GLX_SUP_W__SHIFT 0x1e
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__PREF_SUP_W_MASK 0x00000001L
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__PPR_SUP_W_MASK 0x00000002L
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved3_MASK 0x00000004L
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__NX_SUP_W_MASK 0x00000008L
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__GT_SUP_W_MASK 0x00000010L
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved2_MASK 0x00000020L
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__IA_SUP_W_MASK 0x00000040L
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__GA_SUP_W_MASK 0x00000080L
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__HE_SUP_W_MASK 0x00000100L
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__PC_SUP_W_MASK 0x00000200L
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__HATS_W_MASK 0x00000C00L
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__US_SUP_W_MASK 0x00001000L
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved5_MASK 0x001FE000L
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__GAM_SUP_W_MASK 0x00E00000L
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__PPRF_W_MASK 0x03000000L
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved6_MASK 0x0C000000L
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__EVENTF_W_MASK 0x30000000L
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__GLX_SUP_W_MASK 0xC0000000L
+//IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__PAS_MAX_W__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__Reserved1__SHIFT 0x4
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__DTE_seg_W__SHIFT 0x6
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__PPR_OVERFLOW_EARLY_SUP_W__SHIFT 0x8
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__PPR_AUTORESP_SUP_W__SHIFT 0x9
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__BLOCK_STOPMARK_SUP_W__SHIFT 0xa
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__MARCnum_SUP_W__SHIFT 0xb
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__SNOOP_ATTRS_SUP_W__SHIFT 0xd
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__GIo_SUP_W__SHIFT 0xe
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__HA_SUP_W__SHIFT 0xf
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__EPH_SUP_W__SHIFT 0x10
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__ATTRFW_SUP_W__SHIFT 0x11
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__V2_HD_DIS_SUP_W__SHIFT 0x12
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__InvIotlbTypeSup_W__SHIFT 0x13
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__HD_SUP_W__SHIFT 0x14
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__Reserved__SHIFT 0x15
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__PAS_MAX_W_MASK 0x0000000FL
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__Reserved1_MASK 0x00000030L
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__DTE_seg_W_MASK 0x000000C0L
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__PPR_OVERFLOW_EARLY_SUP_W_MASK 0x00000100L
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__PPR_AUTORESP_SUP_W_MASK 0x00000200L
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__BLOCK_STOPMARK_SUP_W_MASK 0x00000400L
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__MARCnum_SUP_W_MASK 0x00001800L
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__SNOOP_ATTRS_SUP_W_MASK 0x00002000L
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__GIo_SUP_W_MASK 0x00004000L
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__HA_SUP_W_MASK 0x00008000L
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__EPH_SUP_W_MASK 0x00010000L
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__ATTRFW_SUP_W_MASK 0x00020000L
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__V2_HD_DIS_SUP_W_MASK 0x00040000L
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__InvIotlbTypeSup_W_MASK 0x00080000L
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__HD_SUP_W_MASK 0x00100000L
+#define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__Reserved_MASK 0xFFE00000L
+//IOMMU_L2_0_IOMMU_RANGE_W
+#define IOMMU_L2_0_IOMMU_RANGE_W__Reserved__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_RANGE_W__RNG_VALID_W__SHIFT 0x7
+#define IOMMU_L2_0_IOMMU_RANGE_W__BUS_NUMBER_W__SHIFT 0x8
+#define IOMMU_L2_0_IOMMU_RANGE_W__FIRST_DEVICE_W__SHIFT 0x10
+#define IOMMU_L2_0_IOMMU_RANGE_W__LAST_DEVICE_W__SHIFT 0x18
+#define IOMMU_L2_0_IOMMU_RANGE_W__Reserved_MASK 0x0000007FL
+#define IOMMU_L2_0_IOMMU_RANGE_W__RNG_VALID_W_MASK 0x00000080L
+#define IOMMU_L2_0_IOMMU_RANGE_W__BUS_NUMBER_W_MASK 0x0000FF00L
+#define IOMMU_L2_0_IOMMU_RANGE_W__FIRST_DEVICE_W_MASK 0x00FF0000L
+#define IOMMU_L2_0_IOMMU_RANGE_W__LAST_DEVICE_W_MASK 0xFF000000L
+//IOMMU_L2_0_IOMMU_DSFX_CONTROL
+#define IOMMU_L2_0_IOMMU_DSFX_CONTROL__DSFXSup__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_DSFX_CONTROL__REVISION_MINOR__SHIFT 0x18
+#define IOMMU_L2_0_IOMMU_DSFX_CONTROL__REVISION_MAJOR__SHIFT 0x1c
+#define IOMMU_L2_0_IOMMU_DSFX_CONTROL__DSFXSup_MASK 0x00FFFFFFL
+#define IOMMU_L2_0_IOMMU_DSFX_CONTROL__REVISION_MINOR_MASK 0x0F000000L
+#define IOMMU_L2_0_IOMMU_DSFX_CONTROL__REVISION_MAJOR_MASK 0xF0000000L
+//IOMMU_L2_0_IOMMU_DSSX_DUMMY_0
+#define IOMMU_L2_0_IOMMU_DSSX_DUMMY_0__DSSX_status_set__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_DSSX_DUMMY_0__Reserved__SHIFT 0x18
+#define IOMMU_L2_0_IOMMU_DSSX_DUMMY_0__DSSX_status_set_MASK 0x00FFFFFFL
+#define IOMMU_L2_0_IOMMU_DSSX_DUMMY_0__Reserved_MASK 0xFF000000L
+//IOMMU_L2_0_IOMMU_DSCX_DUMMY_0
+#define IOMMU_L2_0_IOMMU_DSCX_DUMMY_0__DSCX_CNTRL_set__SHIFT 0x0
+#define IOMMU_L2_0_IOMMU_DSCX_DUMMY_0__Reserved__SHIFT 0x18
+#define IOMMU_L2_0_IOMMU_DSCX_DUMMY_0__DSCX_CNTRL_set_MASK 0x00FFFFFFL
+#define IOMMU_L2_0_IOMMU_DSCX_DUMMY_0__Reserved_MASK 0xFF000000L
+//IOMMU_L2_0_L2B_POISON_DVM_CNTRL
+#define IOMMU_L2_0_L2B_POISON_DVM_CNTRL__DVM_POISON_RESP_MODE__SHIFT 0x0
+#define IOMMU_L2_0_L2B_POISON_DVM_CNTRL__DVM_POISON_RESP_MODE_MASK 0x00000003L
+//IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control
+#define IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control__StallNPReqEn__SHIFT 0x0
+#define IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control__StallPReqEn__SHIFT 0x2
+#define IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control__StallMemReqEn__SHIFT 0x8
+#define IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn__SHIFT 0xe
+#define IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control__StallNPReqEn_MASK 0x00000003L
+#define IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control__StallPReqEn_MASK 0x0000000CL
+#define IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control__StallMemReqEn_MASK 0x00000300L
+#define IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn_MASK 0x0000C000L
+//IOMMU_L2_0_IOHC_L2_HostRsp_Stall_Control
+#define IOMMU_L2_0_IOHC_L2_HostRsp_Stall_Control__StallUpRdRspEn__SHIFT 0x4
+#define IOMMU_L2_0_IOHC_L2_HostRsp_Stall_Control__StallUpRdRspEn_MASK 0x00000030L
+//IOMMU_L2_0_SMMU_MMIO_IDR0_W
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__S2P_W__SHIFT 0x0
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__S1P_W__SHIFT 0x1
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__TTF_W__SHIFT 0x2
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__COHACC_W__SHIFT 0x4
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__BTM_W__SHIFT 0x5
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__HTTU_W__SHIFT 0x6
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__DORMHINT_W__SHIFT 0x8
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__Hyp_W__SHIFT 0x9
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__ATS_W__SHIFT 0xa
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__PERFCTRS_W__SHIFT 0xb
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__ASID16_W__SHIFT 0xc
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__MSI_W__SHIFT 0xd
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__SEV_W__SHIFT 0xe
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__ATOS_W__SHIFT 0xf
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__PRI_W__SHIFT 0x10
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__VMW_W__SHIFT 0x11
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__VMID16_W__SHIFT 0x12
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__CD2L_W__SHIFT 0x13
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__VATOS_W__SHIFT 0x14
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__TTENDIAN_W__SHIFT 0x15
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__STALL_MODEL_W__SHIFT 0x18
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__TERM_MODEL_W__SHIFT 0x1a
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__ST_LEVEL_W__SHIFT 0x1b
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__RAS_W__SHIFT 0x1d
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__S2P_W_MASK 0x00000001L
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__S1P_W_MASK 0x00000002L
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__TTF_W_MASK 0x0000000CL
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__COHACC_W_MASK 0x00000010L
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__BTM_W_MASK 0x00000020L
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__HTTU_W_MASK 0x000000C0L
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__DORMHINT_W_MASK 0x00000100L
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__Hyp_W_MASK 0x00000200L
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__ATS_W_MASK 0x00000400L
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__PERFCTRS_W_MASK 0x00000800L
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__ASID16_W_MASK 0x00001000L
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__MSI_W_MASK 0x00002000L
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__SEV_W_MASK 0x00004000L
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__ATOS_W_MASK 0x00008000L
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__PRI_W_MASK 0x00010000L
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__VMW_W_MASK 0x00020000L
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__VMID16_W_MASK 0x00040000L
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__CD2L_W_MASK 0x00080000L
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__VATOS_W_MASK 0x00100000L
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__TTENDIAN_W_MASK 0x00600000L
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__STALL_MODEL_W_MASK 0x03000000L
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__TERM_MODEL_W_MASK 0x04000000L
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__ST_LEVEL_W_MASK 0x18000000L
+#define IOMMU_L2_0_SMMU_MMIO_IDR0_W__RAS_W_MASK 0x20000000L
+//IOMMU_L2_0_SMMU_MMIO_IDR1_W
+#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__SIDSIZE_W__SHIFT 0x0
+#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__SSIDSIZE_W__SHIFT 0x6
+#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__PRIQS_W__SHIFT 0xb
+#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__EVENTQS_W__SHIFT 0x10
+#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__CMDQS_W__SHIFT 0x15
+#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__ATTR_PERMS_OVR_W__SHIFT 0x1a
+#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__ATTR_TYPES_OVR_W__SHIFT 0x1b
+#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__REL_W__SHIFT 0x1c
+#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__QUEUES_PRESET_W__SHIFT 0x1d
+#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__TABLES_PRESET_W__SHIFT 0x1e
+#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__SIDSIZE_W_MASK 0x0000003FL
+#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__SSIDSIZE_W_MASK 0x000007C0L
+#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__PRIQS_W_MASK 0x0000F800L
+#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__EVENTQS_W_MASK 0x001F0000L
+#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__CMDQS_W_MASK 0x03E00000L
+#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__ATTR_PERMS_OVR_W_MASK 0x04000000L
+#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__ATTR_TYPES_OVR_W_MASK 0x08000000L
+#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__REL_W_MASK 0x10000000L
+#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__QUEUES_PRESET_W_MASK 0x20000000L
+#define IOMMU_L2_0_SMMU_MMIO_IDR1_W__TABLES_PRESET_W_MASK 0x40000000L
+//IOMMU_L2_0_SMMU_MMIO_IDR2_W
+#define IOMMU_L2_0_SMMU_MMIO_IDR2_W__BA_VATOS_W__SHIFT 0x0
+#define IOMMU_L2_0_SMMU_MMIO_IDR2_W__BA_RAS_W__SHIFT 0xa
+#define IOMMU_L2_0_SMMU_MMIO_IDR2_W__BA_VATOS_W_MASK 0x000003FFL
+#define IOMMU_L2_0_SMMU_MMIO_IDR2_W__BA_RAS_W_MASK 0x000FFC00L
+//IOMMU_L2_0_SMMU_MMIO_IDR3_W
+#define IOMMU_L2_0_SMMU_MMIO_IDR3_W__HAD_W__SHIFT 0x2
+#define IOMMU_L2_0_SMMU_MMIO_IDR3_W__HAD_W_MASK 0x00000004L
+//IOMMU_L2_0_SMMU_MMIO_IDR5_W
+#define IOMMU_L2_0_SMMU_MMIO_IDR5_W__OAS_W__SHIFT 0x0
+#define IOMMU_L2_0_SMMU_MMIO_IDR5_W__GRAN4K_W__SHIFT 0x4
+#define IOMMU_L2_0_SMMU_MMIO_IDR5_W__GRAN16K_W__SHIFT 0x5
+#define IOMMU_L2_0_SMMU_MMIO_IDR5_W__GRAN64K_W__SHIFT 0x6
+#define IOMMU_L2_0_SMMU_MMIO_IDR5_W__STALL_MAX_W__SHIFT 0x10
+#define IOMMU_L2_0_SMMU_MMIO_IDR5_W__OAS_W_MASK 0x00000007L
+#define IOMMU_L2_0_SMMU_MMIO_IDR5_W__GRAN4K_W_MASK 0x00000010L
+#define IOMMU_L2_0_SMMU_MMIO_IDR5_W__GRAN16K_W_MASK 0x00000020L
+#define IOMMU_L2_0_SMMU_MMIO_IDR5_W__GRAN64K_W_MASK 0x00000040L
+#define IOMMU_L2_0_SMMU_MMIO_IDR5_W__STALL_MAX_W_MASK 0xFFFF0000L
+//IOMMU_L2_0_SMMU_MMIO_IIDR_W
+#define IOMMU_L2_0_SMMU_MMIO_IIDR_W__Implementer_W__SHIFT 0x0
+#define IOMMU_L2_0_SMMU_MMIO_IIDR_W__Revision_W__SHIFT 0xc
+#define IOMMU_L2_0_SMMU_MMIO_IIDR_W__Variant_W__SHIFT 0x10
+#define IOMMU_L2_0_SMMU_MMIO_IIDR_W__ProductID_W__SHIFT 0x14
+#define IOMMU_L2_0_SMMU_MMIO_IIDR_W__Implementer_W_MASK 0x00000FFFL
+#define IOMMU_L2_0_SMMU_MMIO_IIDR_W__Revision_W_MASK 0x0000F000L
+#define IOMMU_L2_0_SMMU_MMIO_IIDR_W__Variant_W_MASK 0x000F0000L
+#define IOMMU_L2_0_SMMU_MMIO_IIDR_W__ProductID_W_MASK 0xFFF00000L
+//IOMMU_L2_0_SMMU_AIDR_W
+#define IOMMU_L2_0_SMMU_AIDR_W__ArchMinorRev_W__SHIFT 0x0
+#define IOMMU_L2_0_SMMU_AIDR_W__ArchMajorRev_W__SHIFT 0x4
+#define IOMMU_L2_0_SMMU_AIDR_W__ArchMinorRev_W_MASK 0x0000000FL
+#define IOMMU_L2_0_SMMU_AIDR_W__ArchMajorRev_W_MASK 0x000000F0L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp
+//BIF_CFG_DEV0_RC0_VENDOR_ID
+#define BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC0_DEVICE_ID
+#define BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC0_COMMAND
+#define BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_RC0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_RC0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_RC0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_RC0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_RC0_STATUS
+#define BIF_CFG_DEV0_RC0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_RC0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_RC0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_RC0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_RC0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_RC0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_RC0_REVISION_ID
+#define BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_RC0_PROG_INTERFACE
+#define BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_RC0_SUB_CLASS
+#define BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_RC0_BASE_CLASS
+#define BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_RC0_CACHE_LINE
+#define BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_RC0_LATENCY
+#define BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_RC0_HEADER
+#define BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_RC0_BIST
+#define BIF_CFG_DEV0_RC0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_RC0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_RC0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_RC0_BASE_ADDR_1
+#define BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY
+#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC0_IO_BASE_LIMIT
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIF_CFG_DEV0_RC0_SECONDARY_STATUS
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT
+#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT
+#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC0_PREF_BASE_UPPER
+#define BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER
+#define BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_RC0_CAP_PTR
+#define BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_RC0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_RC0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+//BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL
+#define BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIF_CFG_DEV0_RC0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_PMI_CAP
+#define BIF_CFG_DEV0_RC0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_RC0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_PCIE_CAP
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_RC0_DEVICE_CAP
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_RC0_DEVICE_CNTL
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIF_CFG_DEV0_RC0_DEVICE_STATUS
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_RC0_LINK_CAP
+#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC0_LINK_CNTL
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_RC0_LINK_STATUS
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_RC0_SLOT_CAP
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIF_CFG_DEV0_RC0_SLOT_CNTL
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+//BIF_CFG_DEV0_RC0_SLOT_STATUS
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIF_CFG_DEV0_RC0_ROOT_CNTL
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIF_CFG_DEV0_RC0_ROOT_CAP
+#define BIF_CFG_DEV0_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIF_CFG_DEV0_RC0_ROOT_STATUS
+#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIF_CFG_DEV0_RC0_DEVICE_CAP2
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_RC0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_RC0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC0_LINK_CAP2
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_RC0_LINK_CNTL2
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_RC0_LINK_STATUS2
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_RC0_SLOT_CAP2
+#define BIF_CFG_DEV0_RC0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_SLOT_CNTL2
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC0_SLOT_STATUS2
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_RC0_SSID_CAP_LIST
+#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_SSID_CAP
+#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST
+#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_MSI_MAP_CAP
+#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIF_CFG_DEV0_RC0_MSI_MAP_ADDR_LO
+#define BIF_CFG_DEV0_RC0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define BIF_CFG_DEV0_RC0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC0_MSI_MAP_ADDR_HI
+#define BIF_CFG_DEV0_RC0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID
+#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp
+//BIF_CFG_DEV1_RC0_VENDOR_ID
+#define BIF_CFG_DEV1_RC0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC0_DEVICE_ID
+#define BIF_CFG_DEV1_RC0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC0_COMMAND
+#define BIF_CFG_DEV1_RC0_COMMAND__IOEN_DN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_COMMAND__MEMEN_DN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_RC0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV1_RC0_COMMAND__IOEN_DN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC0_COMMAND__MEMEN_DN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_RC0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_RC0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV1_RC0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_RC0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_RC0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV1_RC0_STATUS
+#define BIF_CFG_DEV1_RC0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV1_RC0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV1_RC0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV1_RC0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV1_RC0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV1_RC0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV1_RC0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_RC0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV1_RC0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV1_RC0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV1_RC0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV1_RC0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV1_RC0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV1_RC0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV1_RC0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV1_RC0_REVISION_ID
+#define BIF_CFG_DEV1_RC0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV1_RC0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV1_RC0_PROG_INTERFACE
+#define BIF_CFG_DEV1_RC0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV1_RC0_SUB_CLASS
+#define BIF_CFG_DEV1_RC0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_RC0_BASE_CLASS
+#define BIF_CFG_DEV1_RC0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_RC0_CACHE_LINE
+#define BIF_CFG_DEV1_RC0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV1_RC0_LATENCY
+#define BIF_CFG_DEV1_RC0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV1_RC0_HEADER
+#define BIF_CFG_DEV1_RC0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV1_RC0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV1_RC0_BIST
+#define BIF_CFG_DEV1_RC0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV1_RC0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV1_RC0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV1_RC0_BASE_ADDR_1
+#define BIF_CFG_DEV1_RC0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY
+#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC0_IO_BASE_LIMIT
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIF_CFG_DEV1_RC0_SECONDARY_STATUS
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT
+#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT
+#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC0_PREF_BASE_UPPER
+#define BIF_CFG_DEV1_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER
+#define BIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_RC0_CAP_PTR
+#define BIF_CFG_DEV1_RC0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV1_RC0_INTERRUPT_LINE
+#define BIF_CFG_DEV1_RC0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV1_RC0_INTERRUPT_PIN
+#define BIF_CFG_DEV1_RC0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+//BIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL
+#define BIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIF_CFG_DEV1_RC0_PMI_CAP_LIST
+#define BIF_CFG_DEV1_RC0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_RC0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_PMI_CAP
+#define BIF_CFG_DEV1_RC0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV1_RC0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_RC0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV1_RC0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV1_RC0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV1_RC0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV1_RC0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV1_RC0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV1_RC0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC0_PCIE_CAP_LIST
+#define BIF_CFG_DEV1_RC0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_RC0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_PCIE_CAP
+#define BIF_CFG_DEV1_RC0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV1_RC0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV1_RC0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV1_RC0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV1_RC0_DEVICE_CAP
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV1_RC0_DEVICE_CNTL
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIF_CFG_DEV1_RC0_DEVICE_STATUS
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV1_RC0_LINK_CAP
+#define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_RC0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV1_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV1_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV1_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV1_RC0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV1_RC0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV1_RC0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV1_RC0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV1_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV1_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV1_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV1_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV1_RC0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC0_LINK_CNTL
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV1_RC0_LINK_STATUS
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV1_RC0_SLOT_CAP
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIF_CFG_DEV1_RC0_SLOT_CNTL
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+//BIF_CFG_DEV1_RC0_SLOT_STATUS
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIF_CFG_DEV1_RC0_ROOT_CNTL
+#define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIF_CFG_DEV1_RC0_ROOT_CAP
+#define BIF_CFG_DEV1_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIF_CFG_DEV1_RC0_ROOT_STATUS
+#define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIF_CFG_DEV1_RC0_DEVICE_CAP2
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV1_RC0_DEVICE_CNTL2
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV1_RC0_DEVICE_STATUS2
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC0_LINK_CAP2
+#define BIF_CFG_DEV1_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV1_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV1_RC0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV1_RC0_LINK_CNTL2
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV1_RC0_LINK_STATUS2
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV1_RC0_SLOT_CAP2
+#define BIF_CFG_DEV1_RC0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_SLOT_CNTL2
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC0_SLOT_STATUS2
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC0_MSI_CAP_LIST
+#define BIF_CFG_DEV1_RC0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_RC0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_MSI_MSG_CNTL
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_MSI_MSG_DATA
+#define BIF_CFG_DEV1_RC0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_RC0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV1_RC0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_RC0_SSID_CAP_LIST
+#define BIF_CFG_DEV1_RC0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_RC0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_SSID_CAP
+#define BIF_CFG_DEV1_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST
+#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_MSI_MAP_CAP
+#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIF_CFG_DEV1_RC0_MSI_MAP_ADDR_LO
+#define BIF_CFG_DEV1_RC0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define BIF_CFG_DEV1_RC0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC0_MSI_MAP_ADDR_HI
+#define BIF_CFG_DEV1_RC0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV1_RC0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID
+#define BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC0_PCIE_ACS_CAP
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+
+
+// addressBlock: nbio_iohub_nb_pciedummy0_pciedummy_cfgdec
+//NB_PCIEDUMMY0_0_DEVICE_VENDOR_ID
+#define NB_PCIEDUMMY0_0_DEVICE_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define NB_PCIEDUMMY0_0_DEVICE_VENDOR_ID__DEVICE_ID__SHIFT 0x10
+#define NB_PCIEDUMMY0_0_DEVICE_VENDOR_ID__VENDOR_ID_MASK 0x0000FFFFL
+#define NB_PCIEDUMMY0_0_DEVICE_VENDOR_ID__DEVICE_ID_MASK 0xFFFF0000L
+//NB_PCIEDUMMY0_0_STATUS_COMMAND
+#define NB_PCIEDUMMY0_0_STATUS_COMMAND__COMMAND__SHIFT 0x0
+#define NB_PCIEDUMMY0_0_STATUS_COMMAND__STATUS__SHIFT 0x10
+#define NB_PCIEDUMMY0_0_STATUS_COMMAND__COMMAND_MASK 0x0000FFFFL
+#define NB_PCIEDUMMY0_0_STATUS_COMMAND__STATUS_MASK 0xFFFF0000L
+//NB_PCIEDUMMY0_0_CLASS_CODE_REVID
+#define NB_PCIEDUMMY0_0_CLASS_CODE_REVID__REVID__SHIFT 0x0
+#define NB_PCIEDUMMY0_0_CLASS_CODE_REVID__CLASS_CODE__SHIFT 0x8
+#define NB_PCIEDUMMY0_0_CLASS_CODE_REVID__REVID_MASK 0x000000FFL
+#define NB_PCIEDUMMY0_0_CLASS_CODE_REVID__CLASS_CODE_MASK 0xFFFFFF00L
+//NB_PCIEDUMMY0_0_HEADER_TYPE
+#define NB_PCIEDUMMY0_0_HEADER_TYPE__HEADER_TYPE__SHIFT 0x10
+#define NB_PCIEDUMMY0_0_HEADER_TYPE__DEVICE_TYPE__SHIFT 0x17
+#define NB_PCIEDUMMY0_0_HEADER_TYPE__HEADER_TYPE_MASK 0x007F0000L
+#define NB_PCIEDUMMY0_0_HEADER_TYPE__DEVICE_TYPE_MASK 0x00800000L
+//NB_PCIEDUMMY0_0_HEADER_TYPE_W
+#define NB_PCIEDUMMY0_0_HEADER_TYPE_W__DEVICE_TYPE__SHIFT 0x7
+#define NB_PCIEDUMMY0_0_HEADER_TYPE_W__DEVICE_TYPE_MASK 0x00000080L
+
+
+// addressBlock: nbio_iohub_nb_pciedummy1_pciedummy_cfgdec
+//NB_PCIEDUMMY1_0_DEVICE_VENDOR_ID
+#define NB_PCIEDUMMY1_0_DEVICE_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define NB_PCIEDUMMY1_0_DEVICE_VENDOR_ID__DEVICE_ID__SHIFT 0x10
+#define NB_PCIEDUMMY1_0_DEVICE_VENDOR_ID__VENDOR_ID_MASK 0x0000FFFFL
+#define NB_PCIEDUMMY1_0_DEVICE_VENDOR_ID__DEVICE_ID_MASK 0xFFFF0000L
+//NB_PCIEDUMMY1_0_STATUS_COMMAND
+#define NB_PCIEDUMMY1_0_STATUS_COMMAND__COMMAND__SHIFT 0x0
+#define NB_PCIEDUMMY1_0_STATUS_COMMAND__STATUS__SHIFT 0x10
+#define NB_PCIEDUMMY1_0_STATUS_COMMAND__COMMAND_MASK 0x0000FFFFL
+#define NB_PCIEDUMMY1_0_STATUS_COMMAND__STATUS_MASK 0xFFFF0000L
+//NB_PCIEDUMMY1_0_CLASS_CODE_REVID
+#define NB_PCIEDUMMY1_0_CLASS_CODE_REVID__REVID__SHIFT 0x0
+#define NB_PCIEDUMMY1_0_CLASS_CODE_REVID__CLASS_CODE__SHIFT 0x8
+#define NB_PCIEDUMMY1_0_CLASS_CODE_REVID__REVID_MASK 0x000000FFL
+#define NB_PCIEDUMMY1_0_CLASS_CODE_REVID__CLASS_CODE_MASK 0xFFFFFF00L
+//NB_PCIEDUMMY1_0_HEADER_TYPE
+#define NB_PCIEDUMMY1_0_HEADER_TYPE__HEADER_TYPE__SHIFT 0x10
+#define NB_PCIEDUMMY1_0_HEADER_TYPE__DEVICE_TYPE__SHIFT 0x17
+#define NB_PCIEDUMMY1_0_HEADER_TYPE__HEADER_TYPE_MASK 0x007F0000L
+#define NB_PCIEDUMMY1_0_HEADER_TYPE__DEVICE_TYPE_MASK 0x00800000L
+//NB_PCIEDUMMY1_0_HEADER_TYPE_W
+#define NB_PCIEDUMMY1_0_HEADER_TYPE_W__DEVICE_TYPE__SHIFT 0x7
+#define NB_PCIEDUMMY1_0_HEADER_TYPE_W__DEVICE_TYPE_MASK 0x00000080L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp
+//VENDOR_ID
+#define VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//DEVICE_ID
+#define DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//COMMAND
+#define COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define COMMAND__AD_STEPPING__SHIFT 0x7
+#define COMMAND__SERR_EN__SHIFT 0x8
+#define COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define COMMAND__INT_DIS__SHIFT 0xa
+#define COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define COMMAND__AD_STEPPING_MASK 0x0080L
+#define COMMAND__SERR_EN_MASK 0x0100L
+#define COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define COMMAND__INT_DIS_MASK 0x0400L
+//STATUS
+#define STATUS__INT_STATUS__SHIFT 0x3
+#define STATUS__CAP_LIST__SHIFT 0x4
+#define STATUS__PCI_66_EN__SHIFT 0x5
+#define STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define STATUS__INT_STATUS_MASK 0x0008L
+#define STATUS__CAP_LIST_MASK 0x0010L
+#define STATUS__PCI_66_EN_MASK 0x0020L
+#define STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//REVISION_ID
+#define REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//PROG_INTERFACE
+#define PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//SUB_CLASS
+#define SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BASE_CLASS
+#define BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//CACHE_LINE
+#define CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//LATENCY
+#define LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define LATENCY__LATENCY_TIMER_MASK 0xFFL
+//HEADER
+#define HEADER__HEADER_TYPE__SHIFT 0x0
+#define HEADER__DEVICE_TYPE__SHIFT 0x7
+#define HEADER__HEADER_TYPE_MASK 0x7FL
+#define HEADER__DEVICE_TYPE_MASK 0x80L
+//BIST
+#define BIST__BIST_COMP__SHIFT 0x0
+#define BIST__BIST_STRT__SHIFT 0x6
+#define BIST__BIST_CAP__SHIFT 0x7
+#define BIST__BIST_COMP_MASK 0x0FL
+#define BIST__BIST_STRT_MASK 0x40L
+#define BIST__BIST_CAP_MASK 0x80L
+//BASE_ADDR_1
+#define BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BASE_ADDR_2
+#define BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BASE_ADDR_3
+#define BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BASE_ADDR_4
+#define BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BASE_ADDR_5
+#define BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BASE_ADDR_6
+#define BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//ADAPTER_ID
+#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//ROM_BASE_ADDR
+#define ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//CAP_PTR
+#define CAP_PTR__CAP_PTR__SHIFT 0x0
+#define CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//INTERRUPT_LINE
+#define INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//INTERRUPT_PIN
+#define INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//MIN_GRANT
+#define MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define MIN_GRANT__MIN_GNT_MASK 0xFFL
+//MAX_LATENCY
+#define MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//VENDOR_CAP_LIST
+#define VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//ADAPTER_ID_W
+#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//PMI_CAP_LIST
+#define PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//PMI_CAP
+#define PMI_CAP__VERSION__SHIFT 0x0
+#define PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define PMI_CAP__VERSION_MASK 0x0007L
+#define PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//PMI_STATUS_CNTL
+#define PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//PCIE_CAP_LIST
+#define PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//PCIE_CAP
+#define PCIE_CAP__VERSION__SHIFT 0x0
+#define PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define PCIE_CAP__VERSION_MASK 0x000FL
+#define PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//DEVICE_CAP
+#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//DEVICE_CNTL
+#define DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//DEVICE_STATUS
+#define DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//LINK_CAP
+#define LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//LINK_CNTL
+#define LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//LINK_STATUS
+#define LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//DEVICE_CAP2
+#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//DEVICE_CNTL2
+#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//DEVICE_STATUS2
+#define DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//LINK_CAP2
+#define LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define LINK_CAP2__RESERVED__SHIFT 0x9
+#define LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//LINK_CNTL2
+#define LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//LINK_STATUS2
+#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//SLOT_CAP2
+#define SLOT_CAP2__RESERVED__SHIFT 0x0
+#define SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//SLOT_CNTL2
+#define SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//SLOT_STATUS2
+#define SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//MSI_CAP_LIST
+#define MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//MSI_MSG_CNTL
+#define MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//MSI_MSG_ADDR_LO
+#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//MSI_MSG_ADDR_HI
+#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//MSI_MSG_DATA
+#define MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//MSI_MASK
+#define MSI_MASK__MSI_MASK__SHIFT 0x0
+#define MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//MSI_MSG_DATA_64
+#define MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//MSI_MASK_64
+#define MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//MSI_PENDING
+#define MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//MSI_PENDING_64
+#define MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//MSIX_CAP_LIST
+#define MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//MSIX_MSG_CNTL
+#define MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//MSIX_TABLE
+#define MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//MSIX_PBA
+#define MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PCIE_VENDOR_SPECIFIC_HDR
+#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//PCIE_VENDOR_SPECIFIC1
+#define PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC2
+#define PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//PCIE_VC_ENH_CAP_LIST
+#define PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PCIE_PORT_VC_CAP_REG1
+#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//PCIE_PORT_VC_CAP_REG2
+#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//PCIE_PORT_VC_CNTL
+#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//PCIE_PORT_VC_STATUS
+#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//PCIE_VC0_RESOURCE_CAP
+#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//PCIE_VC0_RESOURCE_CNTL
+#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//PCIE_VC0_RESOURCE_STATUS
+#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//PCIE_VC1_RESOURCE_CAP
+#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//PCIE_VC1_RESOURCE_CNTL
+#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//PCIE_VC1_RESOURCE_STATUS
+#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PCIE_DEV_SERIAL_NUM_DW1
+#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//PCIE_DEV_SERIAL_NUM_DW2
+#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PCIE_UNCORR_ERR_STATUS
+#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//PCIE_UNCORR_ERR_MASK
+#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//PCIE_UNCORR_ERR_SEVERITY
+#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//PCIE_CORR_ERR_STATUS
+#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//PCIE_CORR_ERR_MASK
+#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//PCIE_ADV_ERR_CAP_CNTL
+#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//PCIE_HDR_LOG0
+#define PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//PCIE_HDR_LOG1
+#define PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//PCIE_HDR_LOG2
+#define PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//PCIE_HDR_LOG3
+#define PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//PCIE_TLP_PREFIX_LOG0
+#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//PCIE_TLP_PREFIX_LOG1
+#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//PCIE_TLP_PREFIX_LOG2
+#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//PCIE_TLP_PREFIX_LOG3
+#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//PCIE_BAR_ENH_CAP_LIST
+#define PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PCIE_BAR1_CAP
+#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//PCIE_BAR1_CNTL
+#define PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//PCIE_BAR2_CAP
+#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//PCIE_BAR2_CNTL
+#define PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//PCIE_BAR3_CAP
+#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//PCIE_BAR3_CNTL
+#define PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//PCIE_BAR4_CAP
+#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//PCIE_BAR4_CNTL
+#define PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//PCIE_BAR5_CAP
+#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//PCIE_BAR5_CNTL
+#define PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//PCIE_BAR6_CAP
+#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//PCIE_BAR6_CNTL
+#define PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PCIE_PWR_BUDGET_DATA_SELECT
+#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//PCIE_PWR_BUDGET_DATA
+#define PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//PCIE_PWR_BUDGET_CAP
+#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//PCIE_DPA_ENH_CAP_LIST
+#define PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PCIE_DPA_CAP
+#define PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//PCIE_DPA_LATENCY_INDICATOR
+#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//PCIE_DPA_STATUS
+#define PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//PCIE_DPA_CNTL
+#define PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_SECONDARY_ENH_CAP_LIST
+#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PCIE_LINK_CNTL3
+#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL
+//PCIE_LANE_ERROR_STATUS
+#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//PCIE_LANE_0_EQUALIZATION_CNTL
+#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//PCIE_LANE_1_EQUALIZATION_CNTL
+#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//PCIE_LANE_2_EQUALIZATION_CNTL
+#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//PCIE_LANE_3_EQUALIZATION_CNTL
+#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//PCIE_LANE_4_EQUALIZATION_CNTL
+#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//PCIE_LANE_5_EQUALIZATION_CNTL
+#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//PCIE_LANE_6_EQUALIZATION_CNTL
+#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//PCIE_LANE_7_EQUALIZATION_CNTL
+#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//PCIE_LANE_8_EQUALIZATION_CNTL
+#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//PCIE_LANE_9_EQUALIZATION_CNTL
+#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//PCIE_LANE_10_EQUALIZATION_CNTL
+#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//PCIE_LANE_11_EQUALIZATION_CNTL
+#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//PCIE_LANE_12_EQUALIZATION_CNTL
+#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//PCIE_LANE_13_EQUALIZATION_CNTL
+#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//PCIE_LANE_14_EQUALIZATION_CNTL
+#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//PCIE_LANE_15_EQUALIZATION_CNTL
+#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//PCIE_ACS_ENH_CAP_LIST
+#define PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PCIE_ACS_CAP
+#define PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//PCIE_ACS_CNTL
+#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//PCIE_ATS_ENH_CAP_LIST
+#define PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PCIE_ATS_CAP
+#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//PCIE_ATS_CNTL
+#define PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//PCIE_PAGE_REQ_ENH_CAP_LIST
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PCIE_PAGE_REQ_CNTL
+#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
+#define PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
+#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L
+#define PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L
+//PCIE_PAGE_REQ_STATUS
+#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0
+#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1
+#define PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8
+#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf
+#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L
+#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L
+#define PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L
+#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L
+//PCIE_OUTSTAND_PAGE_REQ_CAPACITY
+#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0
+#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL
+//PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
+#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL
+//PCIE_PASID_ENH_CAP_LIST
+#define PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PCIE_PASID_CAP
+#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//PCIE_PASID_CNTL
+#define PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//PCIE_TPH_REQR_ENH_CAP_LIST
+#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PCIE_TPH_REQR_CAP
+#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//PCIE_TPH_REQR_CNTL
+#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//PCIE_MC_ENH_CAP_LIST
+#define PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PCIE_MC_CAP
+#define PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//PCIE_MC_CNTL
+#define PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//PCIE_MC_ADDR0
+#define PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//PCIE_MC_ADDR1
+#define PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//PCIE_MC_RCV0
+#define PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//PCIE_MC_RCV1
+#define PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//PCIE_MC_BLOCK_ALL0
+#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//PCIE_MC_BLOCK_ALL1
+#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//PCIE_MC_BLOCK_UNTRANSLATED_0
+#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//PCIE_MC_BLOCK_UNTRANSLATED_1
+#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//PCIE_LTR_ENH_CAP_LIST
+#define PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PCIE_LTR_CAP
+#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//PCIE_ARI_ENH_CAP_LIST
+#define PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PCIE_ARI_CAP
+#define PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//PCIE_ARI_CNTL
+#define PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//PCIE_SRIOV_ENH_CAP_LIST
+#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PCIE_SRIOV_CAP
+#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0
+#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1
+#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15
+#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L
+#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L
+#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L
+//PCIE_SRIOV_CONTROL
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3
+#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L
+#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L
+//PCIE_SRIOV_STATUS
+#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0
+#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L
+//PCIE_SRIOV_INITIAL_VFS
+#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0
+#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL
+//PCIE_SRIOV_TOTAL_VFS
+#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0
+#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL
+//PCIE_SRIOV_NUM_VFS
+#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0
+#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL
+//PCIE_SRIOV_FUNC_DEP_LINK
+#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0
+#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0x00FFL
+//PCIE_SRIOV_FIRST_VF_OFFSET
+#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0
+#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL
+//PCIE_SRIOV_VF_STRIDE
+#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0
+#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL
+//PCIE_SRIOV_VF_DEVICE_ID
+#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0
+#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL
+//PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0
+#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL
+//PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0
+#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL
+//PCIE_SRIOV_VF_BASE_ADDR_0
+#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0
+#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//PCIE_SRIOV_VF_BASE_ADDR_1
+#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0
+#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//PCIE_SRIOV_VF_BASE_ADDR_2
+#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0
+#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//PCIE_SRIOV_VF_BASE_ADDR_3
+#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0
+#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//PCIE_SRIOV_VF_BASE_ADDR_4
+#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0
+#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//PCIE_SRIOV_VF_BASE_ADDR_5
+#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0
+#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT 0x0
+#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3
+#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK 0x00000007L
+#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L
+//PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x00000001L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x00000002L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp
+//BIF_CFG_DEV0_EPF1_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_COMMAND
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF1_0_STATUS
+#define BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_LATENCY
+#define BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_HEADER
+#define BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF1_0_BIST
+#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_PMI_CAP
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF1_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF1_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF1_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF1_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF1_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF1_0_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF1_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF1_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF1_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
+#define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0x00FFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x00000002L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp
+//BIF_CFG_DEV0_EPF2_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF2_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_0_COMMAND
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF2_0_STATUS
+#define BIF_CFG_DEV0_EPF2_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF2_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF2_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_LATENCY
+#define BIF_CFG_DEV0_EPF2_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_HEADER
+#define BIF_CFG_DEV0_EPF2_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF2_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF2_0_BIST
+#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF2_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF2_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF2_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PMI_CAP
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_0_SBRN
+#define BIF_CFG_DEV0_EPF2_0_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_FLADJ
+#define BIF_CFG_DEV0_EPF2_0_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_FLADJ__FLADJ_MASK 0x3FL
+//BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF2_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF2_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF2_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF2_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF2_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF2_0_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF2_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF2_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_0_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF2_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF2_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF2_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF2_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF2_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF2_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF2_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF2_0_SATA_CAP_0
+#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_0_SATA_CAP_1
+#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX
+#define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA
+#define BIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp
+//BIF_CFG_DEV0_EPF3_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF3_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_0_COMMAND
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF3_0_STATUS
+#define BIF_CFG_DEV0_EPF3_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF3_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF3_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF3_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_LATENCY
+#define BIF_CFG_DEV0_EPF3_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_HEADER
+#define BIF_CFG_DEV0_EPF3_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF3_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF3_0_BIST
+#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF3_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF3_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF3_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PMI_CAP
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_0_SBRN
+#define BIF_CFG_DEV0_EPF3_0_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_FLADJ
+#define BIF_CFG_DEV0_EPF3_0_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_FLADJ__FLADJ_MASK 0x3FL
+//BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF3_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF3_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF3_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF3_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF3_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF3_0_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF3_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF3_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_0_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF3_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF3_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF3_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF3_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF3_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF3_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF3_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF3_0_SATA_CAP_0
+#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_0_SATA_CAP_1
+#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX
+#define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA
+#define BIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp
+//BIF_CFG_DEV0_EPF4_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF4_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_0_COMMAND
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF4_0_STATUS
+#define BIF_CFG_DEV0_EPF4_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF4_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF4_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF4_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF4_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF4_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF4_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF4_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF4_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF4_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF4_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF4_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF4_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_LATENCY
+#define BIF_CFG_DEV0_EPF4_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_HEADER
+#define BIF_CFG_DEV0_EPF4_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF4_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF4_0_BIST
+#define BIF_CFG_DEV0_EPF4_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF4_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF4_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF4_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF4_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF4_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF4_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PMI_CAP
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF4_0_SBRN
+#define BIF_CFG_DEV0_EPF4_0_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_FLADJ
+#define BIF_CFG_DEV0_EPF4_0_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_FLADJ__FLADJ_MASK 0x3FL
+//BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF4_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF4_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF4_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF4_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF4_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF4_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF4_0_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF4_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF4_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_0_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF4_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF4_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF4_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF4_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF4_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF4_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF4_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF4_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF4_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF4_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF4_0_SATA_CAP_0
+#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF4_0_SATA_CAP_1
+#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV0_EPF4_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX
+#define BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF4_0_SATA_IDP_DATA
+#define BIF_CFG_DEV0_EPF4_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp
+//BIF_CFG_DEV0_EPF5_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF5_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_0_COMMAND
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF5_0_STATUS
+#define BIF_CFG_DEV0_EPF5_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF5_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF5_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF5_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF5_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF5_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF5_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF5_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF5_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF5_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF5_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF5_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF5_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_LATENCY
+#define BIF_CFG_DEV0_EPF5_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_HEADER
+#define BIF_CFG_DEV0_EPF5_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF5_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF5_0_BIST
+#define BIF_CFG_DEV0_EPF5_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF5_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF5_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF5_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF5_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF5_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF5_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PMI_CAP
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF5_0_SBRN
+#define BIF_CFG_DEV0_EPF5_0_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_FLADJ
+#define BIF_CFG_DEV0_EPF5_0_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_FLADJ__FLADJ_MASK 0x3FL
+//BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF5_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF5_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF5_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF5_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF5_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF5_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF5_0_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF5_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF5_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_0_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF5_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF5_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF5_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF5_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF5_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF5_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF5_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF5_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF5_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF5_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF5_0_SATA_CAP_0
+#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF5_0_SATA_CAP_1
+#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV0_EPF5_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX
+#define BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF5_0_SATA_IDP_DATA
+#define BIF_CFG_DEV0_EPF5_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp
+//BIF_CFG_DEV0_EPF6_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF6_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_0_COMMAND
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF6_0_STATUS
+#define BIF_CFG_DEV0_EPF6_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF6_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF6_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF6_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF6_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF6_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF6_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF6_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF6_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF6_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF6_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF6_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF6_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_LATENCY
+#define BIF_CFG_DEV0_EPF6_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_HEADER
+#define BIF_CFG_DEV0_EPF6_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF6_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF6_0_BIST
+#define BIF_CFG_DEV0_EPF6_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF6_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF6_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF6_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF6_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF6_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF6_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PMI_CAP
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF6_0_SBRN
+#define BIF_CFG_DEV0_EPF6_0_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_FLADJ
+#define BIF_CFG_DEV0_EPF6_0_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_FLADJ__FLADJ_MASK 0x3FL
+//BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF6_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF6_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF6_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF6_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF6_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF6_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF6_0_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF6_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF6_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_0_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF6_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF6_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF6_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF6_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF6_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF6_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF6_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF6_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF6_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF6_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF6_0_SATA_CAP_0
+#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF6_0_SATA_CAP_1
+#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV0_EPF6_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX
+#define BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF6_0_SATA_IDP_DATA
+#define BIF_CFG_DEV0_EPF6_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf7_bifcfgdecp
+//BIF_CFG_DEV0_EPF7_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF7_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF7_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF7_0_COMMAND
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF7_0_STATUS
+#define BIF_CFG_DEV0_EPF7_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF7_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF7_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF7_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF7_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF7_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF7_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF7_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF7_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF7_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF7_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF7_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF7_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF7_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF7_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF7_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_LATENCY
+#define BIF_CFG_DEV0_EPF7_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_HEADER
+#define BIF_CFG_DEV0_EPF7_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF7_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF7_0_BIST
+#define BIF_CFG_DEV0_EPF7_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF7_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF7_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF7_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF7_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF7_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF7_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PMI_CAP
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF7_0_SBRN
+#define BIF_CFG_DEV0_EPF7_0_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_FLADJ
+#define BIF_CFG_DEV0_EPF7_0_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_FLADJ__FLADJ_MASK 0x3FL
+//BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF7_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF7_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF7_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF7_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF7_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF7_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF7_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF7_0_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF7_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF7_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF7_0_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF7_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF7_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF7_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF7_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF7_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF7_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF7_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF7_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF7_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF7_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF7_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF7_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF7_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF7_0_SATA_CAP_0
+#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF7_0_SATA_CAP_1
+#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV0_EPF7_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX
+#define BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF7_0_SATA_IDP_DATA
+#define BIF_CFG_DEV0_EPF7_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_epf0_bifcfgdecp
+//BIF_CFG_DEV1_EPF0_0_VENDOR_ID
+#define BIF_CFG_DEV1_EPF0_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF0_0_DEVICE_ID
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF0_0_COMMAND
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV1_EPF0_0_STATUS
+#define BIF_CFG_DEV1_EPF0_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF0_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV1_EPF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV1_EPF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV1_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF0_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_0_REVISION_ID
+#define BIF_CFG_DEV1_EPF0_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_0_PROG_INTERFACE
+#define BIF_CFG_DEV1_EPF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_SUB_CLASS
+#define BIF_CFG_DEV1_EPF0_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_BASE_CLASS
+#define BIF_CFG_DEV1_EPF0_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_CACHE_LINE
+#define BIF_CFG_DEV1_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_LATENCY
+#define BIF_CFG_DEV1_EPF0_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_HEADER
+#define BIF_CFG_DEV1_EPF0_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV1_EPF0_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV1_EPF0_0_BIST
+#define BIF_CFG_DEV1_EPF0_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV1_EPF0_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV1_EPF0_0_BASE_ADDR_1
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_BASE_ADDR_2
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_BASE_ADDR_3
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_BASE_ADDR_4
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_BASE_ADDR_5
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_BASE_ADDR_6
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_ADAPTER_ID
+#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_CAP_PTR
+#define BIF_CFG_DEV1_EPF0_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE
+#define BIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN
+#define BIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_MIN_GRANT
+#define BIF_CFG_DEV1_EPF0_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_MAX_LATENCY
+#define BIF_CFG_DEV1_EPF0_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W
+#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PMI_CAP
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV1_EPF0_0_DEVICE_CAP
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV1_EPF0_0_LINK_CAP
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_0_LINK_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV1_EPF0_0_LINK_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF0_0_LINK_CAP2
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV1_EPF0_0_LINK_CNTL2
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV1_EPF0_0_LINK_STATUS2
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV1_EPF0_0_SLOT_CAP2
+#define BIF_CFG_DEV1_EPF0_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_SLOT_CNTL2
+#define BIF_CFG_DEV1_EPF0_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF0_0_SLOT_STATUS2
+#define BIF_CFG_DEV1_EPF0_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_EPF0_0_MSI_MASK
+#define BIF_CFG_DEV1_EPF0_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_EPF0_0_MSI_MASK_64
+#define BIF_CFG_DEV1_EPF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_MSI_PENDING
+#define BIF_CFG_DEV1_EPF0_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_MSI_PENDING_64
+#define BIF_CFG_DEV1_EPF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_0_MSIX_TABLE
+#define BIF_CFG_DEV1_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF0_0_MSIX_PBA
+#define BIF_CFG_DEV1_EPF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF0_0_SATA_CAP_0
+#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_0_SATA_CAP_1
+#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV1_EPF0_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX
+#define BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV1_EPF0_0_SATA_IDP_DATA
+#define BIF_CFG_DEV1_EPF0_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_epf1_bifcfgdecp
+//BIF_CFG_DEV1_EPF1_0_VENDOR_ID
+#define BIF_CFG_DEV1_EPF1_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF1_0_DEVICE_ID
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF1_0_COMMAND
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV1_EPF1_0_STATUS
+#define BIF_CFG_DEV1_EPF1_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF1_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV1_EPF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV1_EPF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV1_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF1_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF1_0_REVISION_ID
+#define BIF_CFG_DEV1_EPF1_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF1_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV1_EPF1_0_PROG_INTERFACE
+#define BIF_CFG_DEV1_EPF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_SUB_CLASS
+#define BIF_CFG_DEV1_EPF1_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_BASE_CLASS
+#define BIF_CFG_DEV1_EPF1_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_CACHE_LINE
+#define BIF_CFG_DEV1_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_LATENCY
+#define BIF_CFG_DEV1_EPF1_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_HEADER
+#define BIF_CFG_DEV1_EPF1_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV1_EPF1_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV1_EPF1_0_BIST
+#define BIF_CFG_DEV1_EPF1_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF1_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV1_EPF1_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV1_EPF1_0_BASE_ADDR_1
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_BASE_ADDR_2
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_BASE_ADDR_3
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_BASE_ADDR_4
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_BASE_ADDR_5
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_BASE_ADDR_6
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_ADAPTER_ID
+#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_CAP_PTR
+#define BIF_CFG_DEV1_EPF1_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE
+#define BIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN
+#define BIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_MIN_GRANT
+#define BIF_CFG_DEV1_EPF1_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_MAX_LATENCY
+#define BIF_CFG_DEV1_EPF1_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W
+#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PMI_CAP
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF1_0_SBRN
+#define BIF_CFG_DEV1_EPF1_0_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_FLADJ
+#define BIF_CFG_DEV1_EPF1_0_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_FLADJ__FLADJ_MASK 0x3FL
+//BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD
+#define BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV1_EPF1_0_DEVICE_CAP
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV1_EPF1_0_LINK_CAP
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF1_0_LINK_CNTL
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV1_EPF1_0_LINK_STATUS
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF1_0_LINK_CAP2
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV1_EPF1_0_LINK_CNTL2
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV1_EPF1_0_LINK_STATUS2
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV1_EPF1_0_SLOT_CAP2
+#define BIF_CFG_DEV1_EPF1_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_SLOT_CNTL2
+#define BIF_CFG_DEV1_EPF1_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF1_0_SLOT_STATUS2
+#define BIF_CFG_DEV1_EPF1_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_EPF1_0_MSI_MASK
+#define BIF_CFG_DEV1_EPF1_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_EPF1_0_MSI_MASK_64
+#define BIF_CFG_DEV1_EPF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_MSI_PENDING
+#define BIF_CFG_DEV1_EPF1_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_MSI_PENDING_64
+#define BIF_CFG_DEV1_EPF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV1_EPF1_0_MSIX_TABLE
+#define BIF_CFG_DEV1_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF1_0_MSIX_PBA
+#define BIF_CFG_DEV1_EPF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF1_0_SATA_CAP_0
+#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF1_0_SATA_CAP_1
+#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV1_EPF1_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX
+#define BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV1_EPF1_0_SATA_IDP_DATA
+#define BIF_CFG_DEV1_EPF1_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_epf2_bifcfgdecp
+//BIF_CFG_DEV1_EPF2_0_VENDOR_ID
+#define BIF_CFG_DEV1_EPF2_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF2_0_DEVICE_ID
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF2_0_COMMAND
+#define BIF_CFG_DEV1_EPF2_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF2_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF2_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF2_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF2_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF2_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF2_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF2_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF2_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF2_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF2_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV1_EPF2_0_STATUS
+#define BIF_CFG_DEV1_EPF2_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF2_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF2_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF2_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF2_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF2_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV1_EPF2_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF2_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV1_EPF2_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV1_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF2_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF2_0_REVISION_ID
+#define BIF_CFG_DEV1_EPF2_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF2_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV1_EPF2_0_PROG_INTERFACE
+#define BIF_CFG_DEV1_EPF2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_0_SUB_CLASS
+#define BIF_CFG_DEV1_EPF2_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_0_BASE_CLASS
+#define BIF_CFG_DEV1_EPF2_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_0_CACHE_LINE
+#define BIF_CFG_DEV1_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_0_LATENCY
+#define BIF_CFG_DEV1_EPF2_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_0_HEADER
+#define BIF_CFG_DEV1_EPF2_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV1_EPF2_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV1_EPF2_0_BIST
+#define BIF_CFG_DEV1_EPF2_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF2_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV1_EPF2_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV1_EPF2_0_BASE_ADDR_1
+#define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_0_BASE_ADDR_2
+#define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_0_BASE_ADDR_3
+#define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_0_BASE_ADDR_4
+#define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_0_BASE_ADDR_5
+#define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_0_BASE_ADDR_6
+#define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_0_ADAPTER_ID
+#define BIF_CFG_DEV1_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF2_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV1_EPF2_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_0_CAP_PTR
+#define BIF_CFG_DEV1_EPF2_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV1_EPF2_0_INTERRUPT_LINE
+#define BIF_CFG_DEV1_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_0_INTERRUPT_PIN
+#define BIF_CFG_DEV1_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_0_MIN_GRANT
+#define BIF_CFG_DEV1_EPF2_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_0_MAX_LATENCY
+#define BIF_CFG_DEV1_EPF2_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV1_EPF2_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV1_EPF2_0_ADAPTER_ID_W
+#define BIF_CFG_DEV1_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF2_0_PMI_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF2_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF2_0_PMI_CAP
+#define BIF_CFG_DEV1_EPF2_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF2_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF2_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF2_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF2_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV1_EPF2_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF2_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF2_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF2_0_SBRN
+#define BIF_CFG_DEV1_EPF2_0_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_0_FLADJ
+#define BIF_CFG_DEV1_EPF2_0_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_FLADJ__FLADJ_MASK 0x3FL
+//BIF_CFG_DEV1_EPF2_0_DBESL_DBESLD
+#define BIF_CFG_DEV1_EPF2_0_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_0_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF2_0_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV1_EPF2_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF2_0_PCIE_CAP
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV1_EPF2_0_DEVICE_CAP
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV1_EPF2_0_LINK_CAP
+#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF2_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF2_0_LINK_CNTL
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV1_EPF2_0_LINK_STATUS
+#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS2
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF2_0_LINK_CAP2
+#define BIF_CFG_DEV1_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_0_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV1_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF2_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV1_EPF2_0_LINK_CNTL2
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV1_EPF2_0_LINK_STATUS2
+#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV1_EPF2_0_SLOT_CAP2
+#define BIF_CFG_DEV1_EPF2_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_0_SLOT_CNTL2
+#define BIF_CFG_DEV1_EPF2_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF2_0_SLOT_STATUS2
+#define BIF_CFG_DEV1_EPF2_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF2_0_MSI_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF2_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV1_EPF2_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV1_EPF2_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_0_MSI_MSG_DATA
+#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_EPF2_0_MSI_MASK
+#define BIF_CFG_DEV1_EPF2_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_EPF2_0_MSI_MASK_64
+#define BIF_CFG_DEV1_EPF2_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_0_MSI_PENDING
+#define BIF_CFG_DEV1_EPF2_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_0_MSI_PENDING_64
+#define BIF_CFG_DEV1_EPF2_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF2_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF2_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV1_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF2_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV1_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF2_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV1_EPF2_0_MSIX_TABLE
+#define BIF_CFG_DEV1_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF2_0_MSIX_PBA
+#define BIF_CFG_DEV1_EPF2_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF2_0_SATA_CAP_0
+#define BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV1_EPF2_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF2_0_SATA_CAP_1
+#define BIF_CFG_DEV1_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV1_EPF2_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF2_0_SATA_IDP_INDEX
+#define BIF_CFG_DEV1_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV1_EPF2_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV1_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV1_EPF2_0_SATA_IDP_DATA
+#define BIF_CFG_DEV1_EPF2_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV1_EPF2_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF2_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV1_EPF2_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_pcie0_bifplr0_cfgdecp
+//BIFPLR0_0_VENDOR_ID
+#define BIFPLR0_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR0_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR0_0_DEVICE_ID
+#define BIFPLR0_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR0_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR0_0_COMMAND
+#define BIFPLR0_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR0_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR0_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR0_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR0_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR0_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR0_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR0_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR0_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR0_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR0_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR0_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR0_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR0_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR0_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR0_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR0_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR0_0_STATUS
+#define BIFPLR0_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR0_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR0_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR0_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR0_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR0_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR0_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR0_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR0_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR0_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR0_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR0_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR0_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR0_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR0_0_REVISION_ID
+#define BIFPLR0_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR0_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR0_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR0_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR0_0_PROG_INTERFACE
+#define BIFPLR0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR0_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR0_0_SUB_CLASS
+#define BIFPLR0_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR0_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR0_0_BASE_CLASS
+#define BIFPLR0_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR0_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR0_0_CACHE_LINE
+#define BIFPLR0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR0_0_LATENCY
+#define BIFPLR0_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR0_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR0_0_HEADER
+#define BIFPLR0_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR0_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR0_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR0_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR0_0_BIST
+#define BIFPLR0_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR0_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR0_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR0_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR0_0_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR0_0_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR0_0_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR0_0_IO_BASE_LIMIT
+#define BIFPLR0_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR0_0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR0_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR0_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR0_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR0_0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR0_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR0_0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR0_0_SECONDARY_STATUS
+#define BIFPLR0_0_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR0_0_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR0_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR0_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR0_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR0_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR0_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR0_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR0_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR0_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR0_0_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR0_0_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR0_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR0_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR0_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR0_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR0_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR0_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR0_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR0_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR0_0_MEM_BASE_LIMIT
+#define BIFPLR0_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR0_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR0_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR0_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR0_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR0_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR0_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR0_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR0_0_PREF_BASE_LIMIT
+#define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR0_0_PREF_BASE_UPPER
+#define BIFPLR0_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR0_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PREF_LIMIT_UPPER
+#define BIFPLR0_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR0_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR0_0_IO_BASE_LIMIT_HI
+#define BIFPLR0_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR0_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR0_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR0_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR0_0_CAP_PTR
+#define BIFPLR0_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR0_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIFPLR0_0_INTERRUPT_LINE
+#define BIFPLR0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR0_0_INTERRUPT_PIN
+#define BIFPLR0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR0_0_IRQ_BRIDGE_CNTL
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+//BIFPLR0_0_EXT_BRIDGE_CNTL
+#define BIFPLR0_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR0_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR0_0_PMI_CAP_LIST
+#define BIFPLR0_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR0_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR0_0_PMI_CAP
+#define BIFPLR0_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR0_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR0_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR0_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR0_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR0_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR0_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR0_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR0_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR0_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR0_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR0_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR0_0_PMI_STATUS_CNTL
+#define BIFPLR0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR0_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR0_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR0_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR0_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR0_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR0_0_PCIE_CAP_LIST
+#define BIFPLR0_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR0_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR0_0_PCIE_CAP
+#define BIFPLR0_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR0_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR0_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR0_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR0_0_DEVICE_CAP
+#define BIFPLR0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR0_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR0_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR0_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR0_0_DEVICE_CNTL
+#define BIFPLR0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR0_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR0_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR0_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR0_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR0_0_DEVICE_STATUS
+#define BIFPLR0_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR0_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR0_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR0_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR0_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR0_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR0_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR0_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIFPLR0_0_LINK_CAP
+#define BIFPLR0_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR0_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR0_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR0_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR0_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR0_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR0_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR0_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR0_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR0_0_LINK_CNTL
+#define BIFPLR0_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR0_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR0_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR0_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR0_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR0_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR0_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIFPLR0_0_LINK_STATUS
+#define BIFPLR0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR0_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR0_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR0_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR0_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR0_0_SLOT_CAP
+#define BIFPLR0_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR0_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR0_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR0_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR0_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR0_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR0_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR0_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR0_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR0_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR0_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR0_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR0_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR0_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR0_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR0_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR0_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR0_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR0_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR0_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR0_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR0_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR0_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR0_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR0_0_SLOT_CNTL
+#define BIFPLR0_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR0_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR0_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR0_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR0_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR0_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR0_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR0_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR0_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR0_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR0_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR0_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR0_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR0_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR0_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR0_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR0_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR0_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR0_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR0_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR0_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR0_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR0_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR0_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR0_0_SLOT_STATUS
+#define BIFPLR0_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR0_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR0_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR0_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR0_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR0_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR0_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR0_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR0_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR0_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR0_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR0_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR0_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR0_0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR0_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR0_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR0_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR0_0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR0_0_ROOT_CNTL
+#define BIFPLR0_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR0_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR0_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR0_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR0_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR0_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR0_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR0_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR0_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR0_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR0_0_ROOT_CAP
+#define BIFPLR0_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR0_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR0_0_ROOT_STATUS
+#define BIFPLR0_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR0_0_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR0_0_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR0_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR0_0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR0_0_DEVICE_CAP2
+#define BIFPLR0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIFPLR0_0_DEVICE_CNTL2
+#define BIFPLR0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR0_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR0_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR0_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR0_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR0_0_DEVICE_STATUS2
+#define BIFPLR0_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR0_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR0_0_LINK_CAP2
+#define BIFPLR0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIFPLR0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR0_0_LINK_CAP2__RESERVED__SHIFT 0x13
+#define BIFPLR0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L
+#define BIFPLR0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L
+#define BIFPLR0_0_LINK_CAP2__RESERVED_MASK 0xFFF80000L
+//BIFPLR0_0_LINK_CNTL2
+#define BIFPLR0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR0_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR0_0_LINK_STATUS2
+#define BIFPLR0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIFPLR0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIFPLR0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIFPLR0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIFPLR0_0_SLOT_CAP2
+#define BIFPLR0_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR0_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR0_0_SLOT_CNTL2
+#define BIFPLR0_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR0_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR0_0_SLOT_STATUS2
+#define BIFPLR0_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR0_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR0_0_MSI_CAP_LIST
+#define BIFPLR0_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR0_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR0_0_MSI_MSG_CNTL
+#define BIFPLR0_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR0_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR0_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR0_0_MSI_MSG_ADDR_LO
+#define BIFPLR0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR0_0_MSI_MSG_ADDR_HI
+#define BIFPLR0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR0_0_MSI_MSG_DATA
+#define BIFPLR0_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR0_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIFPLR0_0_MSI_MSG_DATA_64
+#define BIFPLR0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR0_0_SSID_CAP_LIST
+#define BIFPLR0_0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR0_0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR0_0_SSID_CAP
+#define BIFPLR0_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR0_0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR0_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR0_0_MSI_MAP_CAP_LIST
+#define BIFPLR0_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR0_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR0_0_MSI_MAP_CAP
+#define BIFPLR0_0_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR0_0_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR0_0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR0_0_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR0_0_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR0_0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR0_0_MSI_MAP_ADDR_LO
+#define BIFPLR0_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define BIFPLR0_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L
+//BIFPLR0_0_MSI_MAP_ADDR_HI
+#define BIFPLR0_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define BIFPLR0_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR0_0_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_0_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR0_0_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR0_0_PCIE_PORT_VC_CNTL
+#define BIFPLR0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR0_0_PCIE_PORT_VC_STATUS
+#define BIFPLR0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR0_0_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR0_0_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR0_0_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR0_0_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_0_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR0_0_PCIE_UNCORR_ERR_MASK
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR0_0_PCIE_CORR_ERR_STATUS
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR0_0_PCIE_CORR_ERR_MASK
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIFPLR0_0_PCIE_HDR_LOG0
+#define BIFPLR0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_HDR_LOG1
+#define BIFPLR0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_HDR_LOG2
+#define BIFPLR0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_HDR_LOG3
+#define BIFPLR0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_ROOT_ERR_CMD
+#define BIFPLR0_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR0_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR0_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR0_0_PCIE_ROOT_ERR_STATUS
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR0_0_PCIE_ERR_SRC_ID
+#define BIFPLR0_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR0_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR0_0_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_0_PCIE_LINK_CNTL3
+#define BIFPLR0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define BIFPLR0_0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10
+#define BIFPLR0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+#define BIFPLR0_0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L
+//BIFPLR0_0_PCIE_LANE_ERROR_STATUS
+#define BIFPLR0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIFPLR0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIFPLR0_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_0_PCIE_ACS_CAP
+#define BIFPLR0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR0_0_PCIE_ACS_CNTL
+#define BIFPLR0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR0_0_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_0_PCIE_MC_CAP
+#define BIFPLR0_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR0_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR0_0_PCIE_MC_CNTL
+#define BIFPLR0_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR0_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR0_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR0_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR0_0_PCIE_MC_ADDR0
+#define BIFPLR0_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR0_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR0_0_PCIE_MC_ADDR1
+#define BIFPLR0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_MC_RCV0
+#define BIFPLR0_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR0_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_MC_RCV1
+#define BIFPLR0_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR0_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_MC_BLOCK_ALL0
+#define BIFPLR0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_MC_BLOCK_ALL1
+#define BIFPLR0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR0_0_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR0_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR0_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_0_PCIE_L1_PM_SUB_CAP
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR0_0_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR0_0_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_0_PCIE_DPC_CAP_LIST
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR0_0_PCIE_DPC_CNTL
+#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR0_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR0_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR0_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR0_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR0_0_PCIE_DPC_STATUS
+#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR0_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR0_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR0_0_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR0_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR0_0_PCIE_RP_PIO_STATUS
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR0_0_PCIE_RP_PIO_MASK
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR0_0_PCIE_RP_PIO_SEVERITY
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR0_0_PCIE_RP_PIO_SYSERROR
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR0_0_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR0_0_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_RP_PIO_IMPSPEC_LOG
+#define BIFPLR0_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_ESM_CAP_LIST
+#define BIFPLR0_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_0_PCIE_ESM_HEADER_1
+#define BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR0_0_PCIE_ESM_HEADER_2
+#define BIFPLR0_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR0_0_PCIE_ESM_STATUS
+#define BIFPLR0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR0_0_PCIE_ESM_CTRL
+#define BIFPLR0_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8
+#define BIFPLR0_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR0_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL
+#define BIFPLR0_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L
+#define BIFPLR0_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR0_0_PCIE_ESM_CAP_1
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR0_0_PCIE_ESM_CAP_2
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR0_0_PCIE_ESM_CAP_3
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR0_0_PCIE_ESM_CAP_4
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR0_0_PCIE_ESM_CAP_5
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR0_0_PCIE_ESM_CAP_6
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR0_0_PCIE_ESM_CAP_7
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+
+
+// addressBlock: nbio_pcie0_bifplr1_cfgdecp
+//BIFPLR1_0_VENDOR_ID
+#define BIFPLR1_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR1_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR1_0_DEVICE_ID
+#define BIFPLR1_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR1_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR1_0_COMMAND
+#define BIFPLR1_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR1_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR1_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR1_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR1_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR1_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR1_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR1_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR1_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR1_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR1_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR1_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR1_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR1_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR1_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR1_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR1_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR1_0_STATUS
+#define BIFPLR1_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR1_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR1_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR1_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR1_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR1_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR1_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR1_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR1_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR1_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR1_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR1_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR1_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR1_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR1_0_REVISION_ID
+#define BIFPLR1_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR1_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR1_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR1_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR1_0_PROG_INTERFACE
+#define BIFPLR1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR1_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR1_0_SUB_CLASS
+#define BIFPLR1_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR1_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR1_0_BASE_CLASS
+#define BIFPLR1_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR1_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR1_0_CACHE_LINE
+#define BIFPLR1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR1_0_LATENCY
+#define BIFPLR1_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR1_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR1_0_HEADER
+#define BIFPLR1_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR1_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR1_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR1_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR1_0_BIST
+#define BIFPLR1_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR1_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR1_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR1_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR1_0_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR1_0_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR1_0_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR1_0_IO_BASE_LIMIT
+#define BIFPLR1_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR1_0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR1_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR1_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR1_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR1_0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR1_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR1_0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR1_0_SECONDARY_STATUS
+#define BIFPLR1_0_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR1_0_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR1_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR1_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR1_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR1_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR1_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR1_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR1_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR1_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR1_0_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR1_0_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR1_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR1_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR1_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR1_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR1_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR1_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR1_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR1_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR1_0_MEM_BASE_LIMIT
+#define BIFPLR1_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR1_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR1_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR1_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR1_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR1_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR1_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR1_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR1_0_PREF_BASE_LIMIT
+#define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR1_0_PREF_BASE_UPPER
+#define BIFPLR1_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR1_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PREF_LIMIT_UPPER
+#define BIFPLR1_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR1_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR1_0_IO_BASE_LIMIT_HI
+#define BIFPLR1_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR1_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR1_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR1_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR1_0_CAP_PTR
+#define BIFPLR1_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR1_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIFPLR1_0_INTERRUPT_LINE
+#define BIFPLR1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR1_0_INTERRUPT_PIN
+#define BIFPLR1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR1_0_IRQ_BRIDGE_CNTL
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+//BIFPLR1_0_EXT_BRIDGE_CNTL
+#define BIFPLR1_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR1_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR1_0_PMI_CAP_LIST
+#define BIFPLR1_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR1_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR1_0_PMI_CAP
+#define BIFPLR1_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR1_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR1_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR1_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR1_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR1_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR1_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR1_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR1_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR1_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR1_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR1_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR1_0_PMI_STATUS_CNTL
+#define BIFPLR1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR1_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR1_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR1_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR1_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR1_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR1_0_PCIE_CAP_LIST
+#define BIFPLR1_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR1_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR1_0_PCIE_CAP
+#define BIFPLR1_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR1_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR1_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR1_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR1_0_DEVICE_CAP
+#define BIFPLR1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR1_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR1_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR1_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR1_0_DEVICE_CNTL
+#define BIFPLR1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR1_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR1_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR1_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR1_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR1_0_DEVICE_STATUS
+#define BIFPLR1_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR1_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR1_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR1_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR1_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR1_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR1_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR1_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIFPLR1_0_LINK_CAP
+#define BIFPLR1_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR1_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR1_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR1_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR1_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR1_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR1_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR1_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR1_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR1_0_LINK_CNTL
+#define BIFPLR1_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR1_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR1_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR1_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR1_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR1_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR1_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIFPLR1_0_LINK_STATUS
+#define BIFPLR1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR1_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR1_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR1_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR1_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR1_0_SLOT_CAP
+#define BIFPLR1_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR1_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR1_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR1_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR1_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR1_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR1_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR1_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR1_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR1_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR1_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR1_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR1_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR1_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR1_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR1_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR1_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR1_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR1_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR1_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR1_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR1_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR1_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR1_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR1_0_SLOT_CNTL
+#define BIFPLR1_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR1_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR1_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR1_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR1_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR1_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR1_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR1_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR1_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR1_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR1_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR1_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR1_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR1_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR1_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR1_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR1_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR1_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR1_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR1_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR1_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR1_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR1_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR1_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR1_0_SLOT_STATUS
+#define BIFPLR1_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR1_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR1_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR1_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR1_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR1_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR1_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR1_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR1_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR1_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR1_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR1_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR1_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR1_0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR1_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR1_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR1_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR1_0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR1_0_ROOT_CNTL
+#define BIFPLR1_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR1_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR1_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR1_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR1_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR1_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR1_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR1_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR1_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR1_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR1_0_ROOT_CAP
+#define BIFPLR1_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR1_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR1_0_ROOT_STATUS
+#define BIFPLR1_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR1_0_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR1_0_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR1_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR1_0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR1_0_DEVICE_CAP2
+#define BIFPLR1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIFPLR1_0_DEVICE_CNTL2
+#define BIFPLR1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR1_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR1_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR1_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR1_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR1_0_DEVICE_STATUS2
+#define BIFPLR1_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR1_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR1_0_LINK_CAP2
+#define BIFPLR1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIFPLR1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR1_0_LINK_CAP2__RESERVED__SHIFT 0x13
+#define BIFPLR1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L
+#define BIFPLR1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L
+#define BIFPLR1_0_LINK_CAP2__RESERVED_MASK 0xFFF80000L
+//BIFPLR1_0_LINK_CNTL2
+#define BIFPLR1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR1_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR1_0_LINK_STATUS2
+#define BIFPLR1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIFPLR1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIFPLR1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIFPLR1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIFPLR1_0_SLOT_CAP2
+#define BIFPLR1_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR1_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR1_0_SLOT_CNTL2
+#define BIFPLR1_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR1_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR1_0_SLOT_STATUS2
+#define BIFPLR1_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR1_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR1_0_MSI_CAP_LIST
+#define BIFPLR1_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR1_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR1_0_MSI_MSG_CNTL
+#define BIFPLR1_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR1_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR1_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR1_0_MSI_MSG_ADDR_LO
+#define BIFPLR1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR1_0_MSI_MSG_ADDR_HI
+#define BIFPLR1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR1_0_MSI_MSG_DATA
+#define BIFPLR1_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR1_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIFPLR1_0_MSI_MSG_DATA_64
+#define BIFPLR1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR1_0_SSID_CAP_LIST
+#define BIFPLR1_0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR1_0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR1_0_SSID_CAP
+#define BIFPLR1_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR1_0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR1_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR1_0_MSI_MAP_CAP_LIST
+#define BIFPLR1_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR1_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR1_0_MSI_MAP_CAP
+#define BIFPLR1_0_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR1_0_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR1_0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR1_0_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR1_0_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR1_0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR1_0_MSI_MAP_ADDR_LO
+#define BIFPLR1_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define BIFPLR1_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L
+//BIFPLR1_0_MSI_MAP_ADDR_HI
+#define BIFPLR1_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define BIFPLR1_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR1_0_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_0_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR1_0_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR1_0_PCIE_PORT_VC_CNTL
+#define BIFPLR1_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR1_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR1_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR1_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR1_0_PCIE_PORT_VC_STATUS
+#define BIFPLR1_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR1_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR1_0_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR1_0_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR1_0_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR1_0_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_0_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR1_0_PCIE_UNCORR_ERR_MASK
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR1_0_PCIE_CORR_ERR_STATUS
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR1_0_PCIE_CORR_ERR_MASK
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIFPLR1_0_PCIE_HDR_LOG0
+#define BIFPLR1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_HDR_LOG1
+#define BIFPLR1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_HDR_LOG2
+#define BIFPLR1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_HDR_LOG3
+#define BIFPLR1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_ROOT_ERR_CMD
+#define BIFPLR1_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR1_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR1_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR1_0_PCIE_ROOT_ERR_STATUS
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR1_0_PCIE_ERR_SRC_ID
+#define BIFPLR1_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR1_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR1_0_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_0_PCIE_LINK_CNTL3
+#define BIFPLR1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR1_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define BIFPLR1_0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10
+#define BIFPLR1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+#define BIFPLR1_0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L
+//BIFPLR1_0_PCIE_LANE_ERROR_STATUS
+#define BIFPLR1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIFPLR1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIFPLR1_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_0_PCIE_ACS_CAP
+#define BIFPLR1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR1_0_PCIE_ACS_CNTL
+#define BIFPLR1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR1_0_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_0_PCIE_MC_CAP
+#define BIFPLR1_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR1_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR1_0_PCIE_MC_CNTL
+#define BIFPLR1_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR1_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR1_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR1_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR1_0_PCIE_MC_ADDR0
+#define BIFPLR1_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR1_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR1_0_PCIE_MC_ADDR1
+#define BIFPLR1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_MC_RCV0
+#define BIFPLR1_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR1_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_MC_RCV1
+#define BIFPLR1_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR1_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_MC_BLOCK_ALL0
+#define BIFPLR1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_MC_BLOCK_ALL1
+#define BIFPLR1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR1_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR1_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR1_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR1_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR1_0_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR1_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR1_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_0_PCIE_L1_PM_SUB_CAP
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR1_0_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR1_0_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_0_PCIE_DPC_CAP_LIST
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR1_0_PCIE_DPC_CNTL
+#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR1_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR1_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR1_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR1_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR1_0_PCIE_DPC_STATUS
+#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR1_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR1_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR1_0_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR1_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR1_0_PCIE_RP_PIO_STATUS
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR1_0_PCIE_RP_PIO_MASK
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR1_0_PCIE_RP_PIO_SEVERITY
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR1_0_PCIE_RP_PIO_SYSERROR
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR1_0_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR1_0_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_RP_PIO_IMPSPEC_LOG
+#define BIFPLR1_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_ESM_CAP_LIST
+#define BIFPLR1_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_0_PCIE_ESM_HEADER_1
+#define BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR1_0_PCIE_ESM_HEADER_2
+#define BIFPLR1_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR1_0_PCIE_ESM_STATUS
+#define BIFPLR1_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR1_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR1_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR1_0_PCIE_ESM_CTRL
+#define BIFPLR1_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8
+#define BIFPLR1_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR1_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL
+#define BIFPLR1_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L
+#define BIFPLR1_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR1_0_PCIE_ESM_CAP_1
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR1_0_PCIE_ESM_CAP_2
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR1_0_PCIE_ESM_CAP_3
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR1_0_PCIE_ESM_CAP_4
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR1_0_PCIE_ESM_CAP_5
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR1_0_PCIE_ESM_CAP_6
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR1_0_PCIE_ESM_CAP_7
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+
+
+// addressBlock: nbio_pcie0_bifplr2_cfgdecp
+//BIFPLR2_0_VENDOR_ID
+#define BIFPLR2_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR2_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR2_0_DEVICE_ID
+#define BIFPLR2_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR2_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR2_0_COMMAND
+#define BIFPLR2_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR2_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR2_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR2_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR2_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR2_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR2_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR2_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR2_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR2_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR2_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR2_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR2_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR2_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR2_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR2_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR2_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR2_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR2_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR2_0_STATUS
+#define BIFPLR2_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR2_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR2_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR2_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR2_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR2_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR2_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR2_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR2_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR2_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR2_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR2_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR2_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR2_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR2_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR2_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR2_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR2_0_REVISION_ID
+#define BIFPLR2_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR2_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR2_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR2_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR2_0_PROG_INTERFACE
+#define BIFPLR2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR2_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR2_0_SUB_CLASS
+#define BIFPLR2_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR2_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR2_0_BASE_CLASS
+#define BIFPLR2_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR2_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR2_0_CACHE_LINE
+#define BIFPLR2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR2_0_LATENCY
+#define BIFPLR2_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR2_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR2_0_HEADER
+#define BIFPLR2_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR2_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR2_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR2_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR2_0_BIST
+#define BIFPLR2_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR2_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR2_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR2_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR2_0_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR2_0_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR2_0_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR2_0_IO_BASE_LIMIT
+#define BIFPLR2_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR2_0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR2_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR2_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR2_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR2_0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR2_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR2_0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR2_0_SECONDARY_STATUS
+#define BIFPLR2_0_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR2_0_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR2_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR2_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR2_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR2_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR2_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR2_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR2_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR2_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR2_0_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR2_0_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR2_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR2_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR2_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR2_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR2_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR2_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR2_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR2_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR2_0_MEM_BASE_LIMIT
+#define BIFPLR2_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR2_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR2_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR2_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR2_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR2_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR2_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR2_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR2_0_PREF_BASE_LIMIT
+#define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR2_0_PREF_BASE_UPPER
+#define BIFPLR2_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR2_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PREF_LIMIT_UPPER
+#define BIFPLR2_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR2_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR2_0_IO_BASE_LIMIT_HI
+#define BIFPLR2_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR2_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR2_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR2_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR2_0_CAP_PTR
+#define BIFPLR2_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR2_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIFPLR2_0_INTERRUPT_LINE
+#define BIFPLR2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR2_0_INTERRUPT_PIN
+#define BIFPLR2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR2_0_IRQ_BRIDGE_CNTL
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+//BIFPLR2_0_EXT_BRIDGE_CNTL
+#define BIFPLR2_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR2_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR2_0_PMI_CAP_LIST
+#define BIFPLR2_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR2_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR2_0_PMI_CAP
+#define BIFPLR2_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR2_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR2_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR2_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR2_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR2_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR2_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR2_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR2_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR2_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR2_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR2_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR2_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR2_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR2_0_PMI_STATUS_CNTL
+#define BIFPLR2_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR2_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR2_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR2_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR2_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR2_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR2_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR2_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR2_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR2_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR2_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR2_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR2_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR2_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR2_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR2_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR2_0_PCIE_CAP_LIST
+#define BIFPLR2_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR2_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR2_0_PCIE_CAP
+#define BIFPLR2_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR2_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR2_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR2_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR2_0_DEVICE_CAP
+#define BIFPLR2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR2_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR2_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR2_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR2_0_DEVICE_CNTL
+#define BIFPLR2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR2_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR2_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR2_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR2_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR2_0_DEVICE_STATUS
+#define BIFPLR2_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR2_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR2_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR2_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR2_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR2_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR2_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR2_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIFPLR2_0_LINK_CAP
+#define BIFPLR2_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR2_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR2_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR2_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR2_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR2_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR2_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR2_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR2_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR2_0_LINK_CNTL
+#define BIFPLR2_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR2_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR2_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR2_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR2_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR2_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR2_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIFPLR2_0_LINK_STATUS
+#define BIFPLR2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR2_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR2_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR2_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR2_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR2_0_SLOT_CAP
+#define BIFPLR2_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR2_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR2_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR2_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR2_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR2_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR2_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR2_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR2_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR2_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR2_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR2_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR2_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR2_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR2_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR2_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR2_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR2_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR2_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR2_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR2_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR2_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR2_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR2_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR2_0_SLOT_CNTL
+#define BIFPLR2_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR2_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR2_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR2_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR2_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR2_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR2_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR2_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR2_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR2_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR2_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR2_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR2_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR2_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR2_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR2_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR2_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR2_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR2_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR2_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR2_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR2_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR2_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR2_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR2_0_SLOT_STATUS
+#define BIFPLR2_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR2_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR2_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR2_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR2_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR2_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR2_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR2_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR2_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR2_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR2_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR2_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR2_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR2_0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR2_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR2_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR2_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR2_0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR2_0_ROOT_CNTL
+#define BIFPLR2_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR2_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR2_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR2_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR2_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR2_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR2_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR2_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR2_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR2_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR2_0_ROOT_CAP
+#define BIFPLR2_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR2_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR2_0_ROOT_STATUS
+#define BIFPLR2_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR2_0_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR2_0_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR2_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR2_0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR2_0_DEVICE_CAP2
+#define BIFPLR2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIFPLR2_0_DEVICE_CNTL2
+#define BIFPLR2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR2_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR2_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR2_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR2_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR2_0_DEVICE_STATUS2
+#define BIFPLR2_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR2_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR2_0_LINK_CAP2
+#define BIFPLR2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIFPLR2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR2_0_LINK_CAP2__RESERVED__SHIFT 0x13
+#define BIFPLR2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L
+#define BIFPLR2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L
+#define BIFPLR2_0_LINK_CAP2__RESERVED_MASK 0xFFF80000L
+//BIFPLR2_0_LINK_CNTL2
+#define BIFPLR2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR2_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR2_0_LINK_STATUS2
+#define BIFPLR2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIFPLR2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIFPLR2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIFPLR2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIFPLR2_0_SLOT_CAP2
+#define BIFPLR2_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR2_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR2_0_SLOT_CNTL2
+#define BIFPLR2_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR2_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR2_0_SLOT_STATUS2
+#define BIFPLR2_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR2_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR2_0_MSI_CAP_LIST
+#define BIFPLR2_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR2_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR2_0_MSI_MSG_CNTL
+#define BIFPLR2_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR2_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR2_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR2_0_MSI_MSG_ADDR_LO
+#define BIFPLR2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR2_0_MSI_MSG_ADDR_HI
+#define BIFPLR2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR2_0_MSI_MSG_DATA
+#define BIFPLR2_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR2_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIFPLR2_0_MSI_MSG_DATA_64
+#define BIFPLR2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR2_0_SSID_CAP_LIST
+#define BIFPLR2_0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR2_0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR2_0_SSID_CAP
+#define BIFPLR2_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR2_0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR2_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR2_0_MSI_MAP_CAP_LIST
+#define BIFPLR2_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR2_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR2_0_MSI_MAP_CAP
+#define BIFPLR2_0_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR2_0_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR2_0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR2_0_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR2_0_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR2_0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR2_0_MSI_MAP_ADDR_LO
+#define BIFPLR2_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define BIFPLR2_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L
+//BIFPLR2_0_MSI_MAP_ADDR_HI
+#define BIFPLR2_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define BIFPLR2_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR2_0_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_0_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR2_0_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR2_0_PCIE_PORT_VC_CNTL
+#define BIFPLR2_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR2_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR2_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR2_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR2_0_PCIE_PORT_VC_STATUS
+#define BIFPLR2_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR2_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR2_0_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR2_0_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR2_0_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR2_0_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_0_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR2_0_PCIE_UNCORR_ERR_MASK
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR2_0_PCIE_CORR_ERR_STATUS
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR2_0_PCIE_CORR_ERR_MASK
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIFPLR2_0_PCIE_HDR_LOG0
+#define BIFPLR2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_HDR_LOG1
+#define BIFPLR2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_HDR_LOG2
+#define BIFPLR2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_HDR_LOG3
+#define BIFPLR2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_ROOT_ERR_CMD
+#define BIFPLR2_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR2_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR2_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR2_0_PCIE_ROOT_ERR_STATUS
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR2_0_PCIE_ERR_SRC_ID
+#define BIFPLR2_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR2_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR2_0_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_0_PCIE_LINK_CNTL3
+#define BIFPLR2_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR2_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define BIFPLR2_0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10
+#define BIFPLR2_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+#define BIFPLR2_0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L
+//BIFPLR2_0_PCIE_LANE_ERROR_STATUS
+#define BIFPLR2_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIFPLR2_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIFPLR2_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_0_PCIE_ACS_CAP
+#define BIFPLR2_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR2_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR2_0_PCIE_ACS_CNTL
+#define BIFPLR2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR2_0_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_0_PCIE_MC_CAP
+#define BIFPLR2_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR2_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR2_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR2_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR2_0_PCIE_MC_CNTL
+#define BIFPLR2_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR2_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR2_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR2_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR2_0_PCIE_MC_ADDR0
+#define BIFPLR2_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR2_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR2_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR2_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR2_0_PCIE_MC_ADDR1
+#define BIFPLR2_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR2_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_MC_RCV0
+#define BIFPLR2_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR2_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_MC_RCV1
+#define BIFPLR2_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR2_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_MC_BLOCK_ALL0
+#define BIFPLR2_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR2_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_MC_BLOCK_ALL1
+#define BIFPLR2_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR2_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR2_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR2_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR2_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR2_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR2_0_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR2_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR2_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_0_PCIE_L1_PM_SUB_CAP
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR2_0_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR2_0_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_0_PCIE_DPC_CAP_LIST
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR2_0_PCIE_DPC_CNTL
+#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR2_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR2_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR2_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR2_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR2_0_PCIE_DPC_STATUS
+#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR2_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR2_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR2_0_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR2_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR2_0_PCIE_RP_PIO_STATUS
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR2_0_PCIE_RP_PIO_MASK
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR2_0_PCIE_RP_PIO_SEVERITY
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR2_0_PCIE_RP_PIO_SYSERROR
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR2_0_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR2_0_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_RP_PIO_IMPSPEC_LOG
+#define BIFPLR2_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_ESM_CAP_LIST
+#define BIFPLR2_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_0_PCIE_ESM_HEADER_1
+#define BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR2_0_PCIE_ESM_HEADER_2
+#define BIFPLR2_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR2_0_PCIE_ESM_STATUS
+#define BIFPLR2_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR2_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR2_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR2_0_PCIE_ESM_CTRL
+#define BIFPLR2_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8
+#define BIFPLR2_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR2_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL
+#define BIFPLR2_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L
+#define BIFPLR2_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR2_0_PCIE_ESM_CAP_1
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR2_0_PCIE_ESM_CAP_2
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR2_0_PCIE_ESM_CAP_3
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR2_0_PCIE_ESM_CAP_4
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR2_0_PCIE_ESM_CAP_5
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR2_0_PCIE_ESM_CAP_6
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR2_0_PCIE_ESM_CAP_7
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+
+
+// addressBlock: nbio_pcie0_bifplr3_cfgdecp
+//BIFPLR3_0_VENDOR_ID
+#define BIFPLR3_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR3_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR3_0_DEVICE_ID
+#define BIFPLR3_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR3_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR3_0_COMMAND
+#define BIFPLR3_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR3_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR3_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR3_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR3_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR3_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR3_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR3_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR3_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR3_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR3_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR3_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR3_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR3_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR3_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR3_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR3_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR3_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR3_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR3_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR3_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR3_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR3_0_STATUS
+#define BIFPLR3_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR3_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR3_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR3_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR3_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR3_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR3_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR3_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR3_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR3_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR3_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR3_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR3_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR3_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR3_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR3_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR3_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR3_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR3_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR3_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR3_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR3_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR3_0_REVISION_ID
+#define BIFPLR3_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR3_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR3_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR3_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR3_0_PROG_INTERFACE
+#define BIFPLR3_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR3_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR3_0_SUB_CLASS
+#define BIFPLR3_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR3_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR3_0_BASE_CLASS
+#define BIFPLR3_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR3_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR3_0_CACHE_LINE
+#define BIFPLR3_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR3_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR3_0_LATENCY
+#define BIFPLR3_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR3_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR3_0_HEADER
+#define BIFPLR3_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR3_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR3_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR3_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR3_0_BIST
+#define BIFPLR3_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR3_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR3_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR3_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR3_0_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR3_0_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR3_0_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR3_0_IO_BASE_LIMIT
+#define BIFPLR3_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR3_0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR3_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR3_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR3_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR3_0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR3_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR3_0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR3_0_SECONDARY_STATUS
+#define BIFPLR3_0_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR3_0_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR3_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR3_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR3_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR3_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR3_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR3_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR3_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR3_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR3_0_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR3_0_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR3_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR3_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR3_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR3_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR3_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR3_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR3_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR3_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR3_0_MEM_BASE_LIMIT
+#define BIFPLR3_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR3_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR3_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR3_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR3_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR3_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR3_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR3_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR3_0_PREF_BASE_LIMIT
+#define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR3_0_PREF_BASE_UPPER
+#define BIFPLR3_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR3_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PREF_LIMIT_UPPER
+#define BIFPLR3_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR3_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR3_0_IO_BASE_LIMIT_HI
+#define BIFPLR3_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR3_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR3_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR3_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR3_0_CAP_PTR
+#define BIFPLR3_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR3_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIFPLR3_0_INTERRUPT_LINE
+#define BIFPLR3_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR3_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR3_0_INTERRUPT_PIN
+#define BIFPLR3_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR3_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR3_0_IRQ_BRIDGE_CNTL
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+//BIFPLR3_0_EXT_BRIDGE_CNTL
+#define BIFPLR3_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR3_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR3_0_PMI_CAP_LIST
+#define BIFPLR3_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR3_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR3_0_PMI_CAP
+#define BIFPLR3_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR3_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR3_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR3_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR3_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR3_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR3_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR3_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR3_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR3_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR3_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR3_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR3_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR3_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR3_0_PMI_STATUS_CNTL
+#define BIFPLR3_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR3_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR3_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR3_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR3_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR3_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR3_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR3_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR3_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR3_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR3_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR3_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR3_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR3_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR3_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR3_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR3_0_PCIE_CAP_LIST
+#define BIFPLR3_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR3_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR3_0_PCIE_CAP
+#define BIFPLR3_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR3_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR3_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR3_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR3_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR3_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR3_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR3_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR3_0_DEVICE_CAP
+#define BIFPLR3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR3_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR3_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR3_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR3_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR3_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR3_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR3_0_DEVICE_CNTL
+#define BIFPLR3_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR3_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR3_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR3_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR3_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR3_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR3_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR3_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR3_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR3_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR3_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR3_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR3_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR3_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR3_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR3_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR3_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR3_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR3_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR3_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR3_0_DEVICE_STATUS
+#define BIFPLR3_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR3_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR3_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR3_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR3_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR3_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR3_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR3_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR3_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR3_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR3_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR3_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIFPLR3_0_LINK_CAP
+#define BIFPLR3_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR3_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR3_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR3_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR3_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR3_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR3_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR3_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR3_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR3_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR3_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR3_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR3_0_LINK_CNTL
+#define BIFPLR3_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR3_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR3_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR3_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR3_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR3_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR3_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR3_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR3_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR3_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR3_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR3_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIFPLR3_0_LINK_STATUS
+#define BIFPLR3_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR3_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR3_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR3_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR3_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR3_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR3_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR3_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR3_0_SLOT_CAP
+#define BIFPLR3_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR3_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR3_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR3_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR3_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR3_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR3_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR3_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR3_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR3_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR3_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR3_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR3_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR3_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR3_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR3_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR3_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR3_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR3_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR3_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR3_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR3_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR3_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR3_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR3_0_SLOT_CNTL
+#define BIFPLR3_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR3_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR3_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR3_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR3_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR3_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR3_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR3_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR3_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR3_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR3_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR3_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR3_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR3_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR3_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR3_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR3_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR3_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR3_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR3_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR3_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR3_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR3_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR3_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR3_0_SLOT_STATUS
+#define BIFPLR3_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR3_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR3_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR3_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR3_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR3_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR3_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR3_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR3_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR3_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR3_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR3_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR3_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR3_0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR3_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR3_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR3_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR3_0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR3_0_ROOT_CNTL
+#define BIFPLR3_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR3_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR3_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR3_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR3_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR3_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR3_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR3_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR3_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR3_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR3_0_ROOT_CAP
+#define BIFPLR3_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR3_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR3_0_ROOT_STATUS
+#define BIFPLR3_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR3_0_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR3_0_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR3_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR3_0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR3_0_DEVICE_CAP2
+#define BIFPLR3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR3_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR3_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR3_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR3_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIFPLR3_0_DEVICE_CNTL2
+#define BIFPLR3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR3_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR3_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR3_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR3_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR3_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR3_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR3_0_DEVICE_STATUS2
+#define BIFPLR3_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR3_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR3_0_LINK_CAP2
+#define BIFPLR3_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR3_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIFPLR3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR3_0_LINK_CAP2__RESERVED__SHIFT 0x13
+#define BIFPLR3_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR3_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L
+#define BIFPLR3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L
+#define BIFPLR3_0_LINK_CAP2__RESERVED_MASK 0xFFF80000L
+//BIFPLR3_0_LINK_CNTL2
+#define BIFPLR3_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR3_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR3_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR3_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR3_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR3_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR3_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR3_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR3_0_LINK_STATUS2
+#define BIFPLR3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIFPLR3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIFPLR3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIFPLR3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIFPLR3_0_SLOT_CAP2
+#define BIFPLR3_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR3_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR3_0_SLOT_CNTL2
+#define BIFPLR3_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR3_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR3_0_SLOT_STATUS2
+#define BIFPLR3_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR3_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR3_0_MSI_CAP_LIST
+#define BIFPLR3_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR3_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR3_0_MSI_MSG_CNTL
+#define BIFPLR3_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR3_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR3_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR3_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR3_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR3_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR3_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR3_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR3_0_MSI_MSG_ADDR_LO
+#define BIFPLR3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR3_0_MSI_MSG_ADDR_HI
+#define BIFPLR3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR3_0_MSI_MSG_DATA
+#define BIFPLR3_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR3_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIFPLR3_0_MSI_MSG_DATA_64
+#define BIFPLR3_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR3_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR3_0_SSID_CAP_LIST
+#define BIFPLR3_0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR3_0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR3_0_SSID_CAP
+#define BIFPLR3_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR3_0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR3_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR3_0_MSI_MAP_CAP_LIST
+#define BIFPLR3_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR3_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR3_0_MSI_MAP_CAP
+#define BIFPLR3_0_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR3_0_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR3_0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR3_0_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR3_0_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR3_0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR3_0_MSI_MAP_ADDR_LO
+#define BIFPLR3_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define BIFPLR3_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L
+//BIFPLR3_0_MSI_MAP_ADDR_HI
+#define BIFPLR3_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define BIFPLR3_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR3_0_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_0_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR3_0_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR3_0_PCIE_PORT_VC_CNTL
+#define BIFPLR3_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR3_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR3_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR3_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR3_0_PCIE_PORT_VC_STATUS
+#define BIFPLR3_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR3_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR3_0_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR3_0_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR3_0_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR3_0_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_0_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR3_0_PCIE_UNCORR_ERR_MASK
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR3_0_PCIE_CORR_ERR_STATUS
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR3_0_PCIE_CORR_ERR_MASK
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIFPLR3_0_PCIE_HDR_LOG0
+#define BIFPLR3_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_HDR_LOG1
+#define BIFPLR3_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_HDR_LOG2
+#define BIFPLR3_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_HDR_LOG3
+#define BIFPLR3_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_ROOT_ERR_CMD
+#define BIFPLR3_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR3_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR3_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR3_0_PCIE_ROOT_ERR_STATUS
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR3_0_PCIE_ERR_SRC_ID
+#define BIFPLR3_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR3_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR3_0_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_0_PCIE_LINK_CNTL3
+#define BIFPLR3_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR3_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define BIFPLR3_0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10
+#define BIFPLR3_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+#define BIFPLR3_0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L
+//BIFPLR3_0_PCIE_LANE_ERROR_STATUS
+#define BIFPLR3_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIFPLR3_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIFPLR3_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_0_PCIE_ACS_CAP
+#define BIFPLR3_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR3_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR3_0_PCIE_ACS_CNTL
+#define BIFPLR3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR3_0_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_0_PCIE_MC_CAP
+#define BIFPLR3_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR3_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR3_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR3_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR3_0_PCIE_MC_CNTL
+#define BIFPLR3_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR3_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR3_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR3_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR3_0_PCIE_MC_ADDR0
+#define BIFPLR3_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR3_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR3_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR3_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR3_0_PCIE_MC_ADDR1
+#define BIFPLR3_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR3_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_MC_RCV0
+#define BIFPLR3_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR3_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_MC_RCV1
+#define BIFPLR3_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR3_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_MC_BLOCK_ALL0
+#define BIFPLR3_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR3_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_MC_BLOCK_ALL1
+#define BIFPLR3_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR3_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR3_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR3_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR3_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR3_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR3_0_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR3_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR3_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_0_PCIE_L1_PM_SUB_CAP
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR3_0_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR3_0_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_0_PCIE_DPC_CAP_LIST
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR3_0_PCIE_DPC_CNTL
+#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR3_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR3_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR3_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR3_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR3_0_PCIE_DPC_STATUS
+#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR3_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR3_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR3_0_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR3_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR3_0_PCIE_RP_PIO_STATUS
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR3_0_PCIE_RP_PIO_MASK
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR3_0_PCIE_RP_PIO_SEVERITY
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR3_0_PCIE_RP_PIO_SYSERROR
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR3_0_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR3_0_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_RP_PIO_IMPSPEC_LOG
+#define BIFPLR3_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_ESM_CAP_LIST
+#define BIFPLR3_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_0_PCIE_ESM_HEADER_1
+#define BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR3_0_PCIE_ESM_HEADER_2
+#define BIFPLR3_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR3_0_PCIE_ESM_STATUS
+#define BIFPLR3_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR3_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR3_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR3_0_PCIE_ESM_CTRL
+#define BIFPLR3_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8
+#define BIFPLR3_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR3_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL
+#define BIFPLR3_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L
+#define BIFPLR3_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR3_0_PCIE_ESM_CAP_1
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR3_0_PCIE_ESM_CAP_2
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR3_0_PCIE_ESM_CAP_3
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR3_0_PCIE_ESM_CAP_4
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR3_0_PCIE_ESM_CAP_5
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR3_0_PCIE_ESM_CAP_6
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR3_0_PCIE_ESM_CAP_7
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+
+
+// addressBlock: nbio_pcie0_bifplr4_cfgdecp
+//BIFPLR4_0_VENDOR_ID
+#define BIFPLR4_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR4_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR4_0_DEVICE_ID
+#define BIFPLR4_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR4_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR4_0_COMMAND
+#define BIFPLR4_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR4_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR4_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR4_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR4_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR4_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR4_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR4_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR4_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR4_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR4_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR4_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR4_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR4_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR4_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR4_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR4_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR4_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR4_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR4_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR4_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR4_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR4_0_STATUS
+#define BIFPLR4_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR4_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR4_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR4_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR4_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR4_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR4_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR4_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR4_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR4_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR4_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR4_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR4_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR4_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR4_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR4_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR4_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR4_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR4_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR4_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR4_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR4_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR4_0_REVISION_ID
+#define BIFPLR4_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR4_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR4_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR4_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR4_0_PROG_INTERFACE
+#define BIFPLR4_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR4_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR4_0_SUB_CLASS
+#define BIFPLR4_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR4_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR4_0_BASE_CLASS
+#define BIFPLR4_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR4_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR4_0_CACHE_LINE
+#define BIFPLR4_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR4_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR4_0_LATENCY
+#define BIFPLR4_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR4_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR4_0_HEADER
+#define BIFPLR4_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR4_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR4_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR4_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR4_0_BIST
+#define BIFPLR4_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR4_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR4_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR4_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR4_0_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR4_0_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR4_0_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR4_0_IO_BASE_LIMIT
+#define BIFPLR4_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR4_0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR4_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR4_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR4_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR4_0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR4_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR4_0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR4_0_SECONDARY_STATUS
+#define BIFPLR4_0_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR4_0_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR4_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR4_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR4_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR4_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR4_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR4_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR4_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR4_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR4_0_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR4_0_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR4_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR4_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR4_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR4_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR4_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR4_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR4_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR4_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR4_0_MEM_BASE_LIMIT
+#define BIFPLR4_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR4_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR4_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR4_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR4_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR4_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR4_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR4_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR4_0_PREF_BASE_LIMIT
+#define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR4_0_PREF_BASE_UPPER
+#define BIFPLR4_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR4_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PREF_LIMIT_UPPER
+#define BIFPLR4_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR4_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR4_0_IO_BASE_LIMIT_HI
+#define BIFPLR4_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR4_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR4_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR4_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR4_0_CAP_PTR
+#define BIFPLR4_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR4_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIFPLR4_0_INTERRUPT_LINE
+#define BIFPLR4_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR4_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR4_0_INTERRUPT_PIN
+#define BIFPLR4_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR4_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR4_0_IRQ_BRIDGE_CNTL
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+//BIFPLR4_0_EXT_BRIDGE_CNTL
+#define BIFPLR4_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR4_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR4_0_PMI_CAP_LIST
+#define BIFPLR4_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR4_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR4_0_PMI_CAP
+#define BIFPLR4_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR4_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR4_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR4_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR4_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR4_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR4_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR4_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR4_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR4_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR4_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR4_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR4_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR4_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR4_0_PMI_STATUS_CNTL
+#define BIFPLR4_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR4_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR4_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR4_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR4_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR4_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR4_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR4_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR4_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR4_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR4_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR4_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR4_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR4_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR4_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR4_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR4_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR4_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR4_0_PCIE_CAP_LIST
+#define BIFPLR4_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR4_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR4_0_PCIE_CAP
+#define BIFPLR4_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR4_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR4_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR4_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR4_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR4_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR4_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR4_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR4_0_DEVICE_CAP
+#define BIFPLR4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR4_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR4_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR4_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR4_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR4_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR4_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR4_0_DEVICE_CNTL
+#define BIFPLR4_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR4_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR4_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR4_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR4_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR4_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR4_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR4_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR4_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR4_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR4_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR4_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR4_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR4_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR4_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR4_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR4_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR4_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR4_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR4_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR4_0_DEVICE_STATUS
+#define BIFPLR4_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR4_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR4_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR4_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR4_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR4_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR4_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR4_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR4_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR4_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR4_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR4_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIFPLR4_0_LINK_CAP
+#define BIFPLR4_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR4_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR4_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR4_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR4_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR4_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR4_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR4_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR4_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR4_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR4_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR4_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR4_0_LINK_CNTL
+#define BIFPLR4_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR4_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR4_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR4_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR4_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR4_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR4_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR4_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR4_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR4_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR4_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR4_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIFPLR4_0_LINK_STATUS
+#define BIFPLR4_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR4_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR4_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR4_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR4_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR4_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR4_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR4_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR4_0_SLOT_CAP
+#define BIFPLR4_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR4_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR4_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR4_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR4_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR4_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR4_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR4_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR4_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR4_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR4_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR4_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR4_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR4_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR4_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR4_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR4_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR4_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR4_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR4_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR4_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR4_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR4_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR4_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR4_0_SLOT_CNTL
+#define BIFPLR4_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR4_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR4_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR4_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR4_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR4_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR4_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR4_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR4_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR4_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR4_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR4_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR4_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR4_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR4_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR4_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR4_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR4_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR4_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR4_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR4_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR4_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR4_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR4_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR4_0_SLOT_STATUS
+#define BIFPLR4_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR4_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR4_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR4_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR4_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR4_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR4_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR4_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR4_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR4_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR4_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR4_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR4_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR4_0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR4_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR4_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR4_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR4_0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR4_0_ROOT_CNTL
+#define BIFPLR4_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR4_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR4_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR4_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR4_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR4_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR4_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR4_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR4_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR4_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR4_0_ROOT_CAP
+#define BIFPLR4_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR4_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR4_0_ROOT_STATUS
+#define BIFPLR4_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR4_0_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR4_0_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR4_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR4_0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR4_0_DEVICE_CAP2
+#define BIFPLR4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR4_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR4_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR4_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR4_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIFPLR4_0_DEVICE_CNTL2
+#define BIFPLR4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR4_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR4_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR4_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR4_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR4_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR4_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR4_0_DEVICE_STATUS2
+#define BIFPLR4_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR4_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR4_0_LINK_CAP2
+#define BIFPLR4_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR4_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR4_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIFPLR4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR4_0_LINK_CAP2__RESERVED__SHIFT 0x13
+#define BIFPLR4_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR4_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR4_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L
+#define BIFPLR4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L
+#define BIFPLR4_0_LINK_CAP2__RESERVED_MASK 0xFFF80000L
+//BIFPLR4_0_LINK_CNTL2
+#define BIFPLR4_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR4_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR4_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR4_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR4_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR4_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR4_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR4_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR4_0_LINK_STATUS2
+#define BIFPLR4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIFPLR4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIFPLR4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIFPLR4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIFPLR4_0_SLOT_CAP2
+#define BIFPLR4_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR4_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR4_0_SLOT_CNTL2
+#define BIFPLR4_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR4_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR4_0_SLOT_STATUS2
+#define BIFPLR4_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR4_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR4_0_MSI_CAP_LIST
+#define BIFPLR4_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR4_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR4_0_MSI_MSG_CNTL
+#define BIFPLR4_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR4_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR4_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR4_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR4_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR4_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR4_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR4_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR4_0_MSI_MSG_ADDR_LO
+#define BIFPLR4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR4_0_MSI_MSG_ADDR_HI
+#define BIFPLR4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR4_0_MSI_MSG_DATA
+#define BIFPLR4_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR4_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIFPLR4_0_MSI_MSG_DATA_64
+#define BIFPLR4_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR4_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR4_0_SSID_CAP_LIST
+#define BIFPLR4_0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR4_0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR4_0_SSID_CAP
+#define BIFPLR4_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR4_0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR4_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR4_0_MSI_MAP_CAP_LIST
+#define BIFPLR4_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR4_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR4_0_MSI_MAP_CAP
+#define BIFPLR4_0_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR4_0_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR4_0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR4_0_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR4_0_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR4_0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR4_0_MSI_MAP_ADDR_LO
+#define BIFPLR4_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define BIFPLR4_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L
+//BIFPLR4_0_MSI_MAP_ADDR_HI
+#define BIFPLR4_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define BIFPLR4_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR4_0_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_0_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR4_0_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR4_0_PCIE_PORT_VC_CNTL
+#define BIFPLR4_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR4_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR4_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR4_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR4_0_PCIE_PORT_VC_STATUS
+#define BIFPLR4_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR4_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR4_0_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR4_0_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR4_0_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR4_0_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_0_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR4_0_PCIE_UNCORR_ERR_MASK
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR4_0_PCIE_CORR_ERR_STATUS
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR4_0_PCIE_CORR_ERR_MASK
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIFPLR4_0_PCIE_HDR_LOG0
+#define BIFPLR4_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_HDR_LOG1
+#define BIFPLR4_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_HDR_LOG2
+#define BIFPLR4_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_HDR_LOG3
+#define BIFPLR4_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_ROOT_ERR_CMD
+#define BIFPLR4_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR4_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR4_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR4_0_PCIE_ROOT_ERR_STATUS
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR4_0_PCIE_ERR_SRC_ID
+#define BIFPLR4_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR4_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR4_0_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_0_PCIE_LINK_CNTL3
+#define BIFPLR4_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR4_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define BIFPLR4_0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10
+#define BIFPLR4_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+#define BIFPLR4_0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L
+//BIFPLR4_0_PCIE_LANE_ERROR_STATUS
+#define BIFPLR4_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIFPLR4_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIFPLR4_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_0_PCIE_ACS_CAP
+#define BIFPLR4_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR4_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR4_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR4_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR4_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR4_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR4_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR4_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR4_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR4_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR4_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR4_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR4_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR4_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR4_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR4_0_PCIE_ACS_CNTL
+#define BIFPLR4_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR4_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR4_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR4_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR4_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR4_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR4_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR4_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR4_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR4_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR4_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR4_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR4_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR4_0_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_0_PCIE_MC_CAP
+#define BIFPLR4_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR4_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR4_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR4_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR4_0_PCIE_MC_CNTL
+#define BIFPLR4_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR4_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR4_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR4_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR4_0_PCIE_MC_ADDR0
+#define BIFPLR4_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR4_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR4_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR4_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR4_0_PCIE_MC_ADDR1
+#define BIFPLR4_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR4_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_MC_RCV0
+#define BIFPLR4_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR4_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_MC_RCV1
+#define BIFPLR4_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR4_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_MC_BLOCK_ALL0
+#define BIFPLR4_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR4_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_MC_BLOCK_ALL1
+#define BIFPLR4_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR4_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR4_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR4_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR4_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR4_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR4_0_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR4_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR4_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_0_PCIE_L1_PM_SUB_CAP
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR4_0_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR4_0_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_0_PCIE_DPC_CAP_LIST
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR4_0_PCIE_DPC_CNTL
+#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR4_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR4_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR4_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR4_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR4_0_PCIE_DPC_STATUS
+#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR4_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR4_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR4_0_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR4_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR4_0_PCIE_RP_PIO_STATUS
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR4_0_PCIE_RP_PIO_MASK
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR4_0_PCIE_RP_PIO_SEVERITY
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR4_0_PCIE_RP_PIO_SYSERROR
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR4_0_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR4_0_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_RP_PIO_IMPSPEC_LOG
+#define BIFPLR4_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_ESM_CAP_LIST
+#define BIFPLR4_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_0_PCIE_ESM_HEADER_1
+#define BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR4_0_PCIE_ESM_HEADER_2
+#define BIFPLR4_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR4_0_PCIE_ESM_STATUS
+#define BIFPLR4_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR4_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR4_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR4_0_PCIE_ESM_CTRL
+#define BIFPLR4_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8
+#define BIFPLR4_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR4_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL
+#define BIFPLR4_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L
+#define BIFPLR4_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR4_0_PCIE_ESM_CAP_1
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR4_0_PCIE_ESM_CAP_2
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR4_0_PCIE_ESM_CAP_3
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR4_0_PCIE_ESM_CAP_4
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR4_0_PCIE_ESM_CAP_5
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR4_0_PCIE_ESM_CAP_6
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR4_0_PCIE_ESM_CAP_7
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+
+
+// addressBlock: nbio_pcie0_bifplr5_cfgdecp
+//BIFPLR5_0_VENDOR_ID
+#define BIFPLR5_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR5_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR5_0_DEVICE_ID
+#define BIFPLR5_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR5_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR5_0_COMMAND
+#define BIFPLR5_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR5_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR5_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR5_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR5_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR5_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR5_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR5_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR5_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR5_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR5_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR5_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR5_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR5_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR5_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR5_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR5_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR5_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR5_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR5_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR5_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR5_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR5_0_STATUS
+#define BIFPLR5_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR5_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR5_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR5_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR5_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR5_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR5_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR5_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR5_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR5_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR5_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR5_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR5_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR5_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR5_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR5_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR5_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR5_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR5_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR5_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR5_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR5_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR5_0_REVISION_ID
+#define BIFPLR5_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR5_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR5_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR5_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR5_0_PROG_INTERFACE
+#define BIFPLR5_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR5_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR5_0_SUB_CLASS
+#define BIFPLR5_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR5_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR5_0_BASE_CLASS
+#define BIFPLR5_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR5_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR5_0_CACHE_LINE
+#define BIFPLR5_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR5_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR5_0_LATENCY
+#define BIFPLR5_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR5_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR5_0_HEADER
+#define BIFPLR5_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR5_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR5_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR5_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR5_0_BIST
+#define BIFPLR5_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR5_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR5_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR5_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR5_0_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR5_0_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR5_0_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR5_0_IO_BASE_LIMIT
+#define BIFPLR5_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR5_0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR5_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR5_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR5_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR5_0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR5_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR5_0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR5_0_SECONDARY_STATUS
+#define BIFPLR5_0_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR5_0_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR5_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR5_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR5_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR5_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR5_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR5_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR5_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR5_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR5_0_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR5_0_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR5_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR5_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR5_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR5_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR5_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR5_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR5_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR5_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR5_0_MEM_BASE_LIMIT
+#define BIFPLR5_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR5_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR5_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR5_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR5_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR5_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR5_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR5_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR5_0_PREF_BASE_LIMIT
+#define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR5_0_PREF_BASE_UPPER
+#define BIFPLR5_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR5_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PREF_LIMIT_UPPER
+#define BIFPLR5_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR5_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR5_0_IO_BASE_LIMIT_HI
+#define BIFPLR5_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR5_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR5_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR5_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR5_0_CAP_PTR
+#define BIFPLR5_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR5_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIFPLR5_0_INTERRUPT_LINE
+#define BIFPLR5_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR5_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR5_0_INTERRUPT_PIN
+#define BIFPLR5_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR5_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR5_0_IRQ_BRIDGE_CNTL
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+//BIFPLR5_0_EXT_BRIDGE_CNTL
+#define BIFPLR5_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR5_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR5_0_PMI_CAP_LIST
+#define BIFPLR5_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR5_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR5_0_PMI_CAP
+#define BIFPLR5_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR5_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR5_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR5_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR5_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR5_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR5_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR5_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR5_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR5_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR5_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR5_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR5_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR5_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR5_0_PMI_STATUS_CNTL
+#define BIFPLR5_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR5_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR5_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR5_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR5_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR5_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR5_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR5_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR5_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR5_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR5_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR5_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR5_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR5_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR5_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR5_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR5_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR5_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR5_0_PCIE_CAP_LIST
+#define BIFPLR5_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR5_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR5_0_PCIE_CAP
+#define BIFPLR5_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR5_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR5_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR5_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR5_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR5_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR5_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR5_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR5_0_DEVICE_CAP
+#define BIFPLR5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR5_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR5_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR5_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR5_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR5_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR5_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR5_0_DEVICE_CNTL
+#define BIFPLR5_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR5_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR5_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR5_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR5_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR5_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR5_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR5_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR5_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR5_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR5_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR5_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR5_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR5_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR5_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR5_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR5_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR5_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR5_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR5_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR5_0_DEVICE_STATUS
+#define BIFPLR5_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR5_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR5_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR5_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR5_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR5_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR5_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR5_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR5_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR5_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR5_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR5_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIFPLR5_0_LINK_CAP
+#define BIFPLR5_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR5_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR5_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR5_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR5_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR5_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR5_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR5_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR5_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR5_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR5_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR5_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR5_0_LINK_CNTL
+#define BIFPLR5_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR5_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR5_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR5_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR5_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR5_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR5_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR5_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR5_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR5_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR5_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR5_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIFPLR5_0_LINK_STATUS
+#define BIFPLR5_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR5_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR5_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR5_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR5_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR5_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR5_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR5_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR5_0_SLOT_CAP
+#define BIFPLR5_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR5_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR5_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR5_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR5_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR5_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR5_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR5_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR5_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR5_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR5_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR5_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR5_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR5_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR5_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR5_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR5_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR5_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR5_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR5_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR5_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR5_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR5_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR5_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR5_0_SLOT_CNTL
+#define BIFPLR5_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR5_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR5_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR5_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR5_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR5_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR5_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR5_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR5_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR5_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR5_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR5_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR5_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR5_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR5_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR5_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR5_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR5_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR5_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR5_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR5_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR5_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR5_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR5_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR5_0_SLOT_STATUS
+#define BIFPLR5_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR5_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR5_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR5_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR5_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR5_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR5_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR5_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR5_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR5_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR5_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR5_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR5_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR5_0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR5_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR5_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR5_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR5_0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR5_0_ROOT_CNTL
+#define BIFPLR5_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR5_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR5_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR5_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR5_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR5_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR5_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR5_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR5_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR5_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR5_0_ROOT_CAP
+#define BIFPLR5_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR5_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR5_0_ROOT_STATUS
+#define BIFPLR5_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR5_0_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR5_0_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR5_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR5_0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR5_0_DEVICE_CAP2
+#define BIFPLR5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR5_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR5_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR5_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR5_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIFPLR5_0_DEVICE_CNTL2
+#define BIFPLR5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR5_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR5_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR5_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR5_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR5_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR5_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR5_0_DEVICE_STATUS2
+#define BIFPLR5_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR5_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR5_0_LINK_CAP2
+#define BIFPLR5_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR5_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR5_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIFPLR5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR5_0_LINK_CAP2__RESERVED__SHIFT 0x13
+#define BIFPLR5_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR5_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR5_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L
+#define BIFPLR5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L
+#define BIFPLR5_0_LINK_CAP2__RESERVED_MASK 0xFFF80000L
+//BIFPLR5_0_LINK_CNTL2
+#define BIFPLR5_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR5_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR5_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR5_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR5_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR5_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR5_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR5_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR5_0_LINK_STATUS2
+#define BIFPLR5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIFPLR5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIFPLR5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIFPLR5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIFPLR5_0_SLOT_CAP2
+#define BIFPLR5_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR5_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR5_0_SLOT_CNTL2
+#define BIFPLR5_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR5_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR5_0_SLOT_STATUS2
+#define BIFPLR5_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR5_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR5_0_MSI_CAP_LIST
+#define BIFPLR5_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR5_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR5_0_MSI_MSG_CNTL
+#define BIFPLR5_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR5_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR5_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR5_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR5_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR5_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR5_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR5_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR5_0_MSI_MSG_ADDR_LO
+#define BIFPLR5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR5_0_MSI_MSG_ADDR_HI
+#define BIFPLR5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR5_0_MSI_MSG_DATA
+#define BIFPLR5_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR5_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIFPLR5_0_MSI_MSG_DATA_64
+#define BIFPLR5_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR5_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR5_0_SSID_CAP_LIST
+#define BIFPLR5_0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR5_0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR5_0_SSID_CAP
+#define BIFPLR5_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR5_0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR5_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR5_0_MSI_MAP_CAP_LIST
+#define BIFPLR5_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR5_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR5_0_MSI_MAP_CAP
+#define BIFPLR5_0_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR5_0_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR5_0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR5_0_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR5_0_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR5_0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR5_0_MSI_MAP_ADDR_LO
+#define BIFPLR5_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define BIFPLR5_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L
+//BIFPLR5_0_MSI_MAP_ADDR_HI
+#define BIFPLR5_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define BIFPLR5_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR5_0_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_0_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR5_0_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR5_0_PCIE_PORT_VC_CNTL
+#define BIFPLR5_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR5_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR5_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR5_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR5_0_PCIE_PORT_VC_STATUS
+#define BIFPLR5_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR5_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR5_0_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR5_0_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR5_0_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR5_0_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_0_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR5_0_PCIE_UNCORR_ERR_MASK
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR5_0_PCIE_CORR_ERR_STATUS
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR5_0_PCIE_CORR_ERR_MASK
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIFPLR5_0_PCIE_HDR_LOG0
+#define BIFPLR5_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_HDR_LOG1
+#define BIFPLR5_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_HDR_LOG2
+#define BIFPLR5_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_HDR_LOG3
+#define BIFPLR5_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_ROOT_ERR_CMD
+#define BIFPLR5_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR5_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR5_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR5_0_PCIE_ROOT_ERR_STATUS
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR5_0_PCIE_ERR_SRC_ID
+#define BIFPLR5_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR5_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR5_0_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_0_PCIE_LINK_CNTL3
+#define BIFPLR5_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR5_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define BIFPLR5_0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10
+#define BIFPLR5_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+#define BIFPLR5_0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L
+//BIFPLR5_0_PCIE_LANE_ERROR_STATUS
+#define BIFPLR5_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIFPLR5_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIFPLR5_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_0_PCIE_ACS_CAP
+#define BIFPLR5_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR5_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR5_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR5_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR5_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR5_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR5_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR5_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR5_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR5_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR5_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR5_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR5_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR5_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR5_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR5_0_PCIE_ACS_CNTL
+#define BIFPLR5_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR5_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR5_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR5_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR5_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR5_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR5_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR5_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR5_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR5_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR5_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR5_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR5_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR5_0_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_0_PCIE_MC_CAP
+#define BIFPLR5_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR5_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR5_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR5_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR5_0_PCIE_MC_CNTL
+#define BIFPLR5_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR5_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR5_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR5_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR5_0_PCIE_MC_ADDR0
+#define BIFPLR5_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR5_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR5_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR5_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR5_0_PCIE_MC_ADDR1
+#define BIFPLR5_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR5_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_MC_RCV0
+#define BIFPLR5_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR5_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_MC_RCV1
+#define BIFPLR5_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR5_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_MC_BLOCK_ALL0
+#define BIFPLR5_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR5_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_MC_BLOCK_ALL1
+#define BIFPLR5_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR5_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR5_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR5_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR5_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR5_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR5_0_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR5_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR5_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_0_PCIE_L1_PM_SUB_CAP
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR5_0_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR5_0_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_0_PCIE_DPC_CAP_LIST
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR5_0_PCIE_DPC_CNTL
+#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR5_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR5_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR5_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR5_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR5_0_PCIE_DPC_STATUS
+#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR5_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR5_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR5_0_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR5_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR5_0_PCIE_RP_PIO_STATUS
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR5_0_PCIE_RP_PIO_MASK
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR5_0_PCIE_RP_PIO_SEVERITY
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR5_0_PCIE_RP_PIO_SYSERROR
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR5_0_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR5_0_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_RP_PIO_IMPSPEC_LOG
+#define BIFPLR5_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_ESM_CAP_LIST
+#define BIFPLR5_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_0_PCIE_ESM_HEADER_1
+#define BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR5_0_PCIE_ESM_HEADER_2
+#define BIFPLR5_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR5_0_PCIE_ESM_STATUS
+#define BIFPLR5_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR5_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR5_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR5_0_PCIE_ESM_CTRL
+#define BIFPLR5_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8
+#define BIFPLR5_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR5_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL
+#define BIFPLR5_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L
+#define BIFPLR5_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR5_0_PCIE_ESM_CAP_1
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR5_0_PCIE_ESM_CAP_2
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR5_0_PCIE_ESM_CAP_3
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR5_0_PCIE_ESM_CAP_4
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR5_0_PCIE_ESM_CAP_5
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR5_0_PCIE_ESM_CAP_6
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR5_0_PCIE_ESM_CAP_7
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+
+
+// addressBlock: nbio_pcie0_bifplr6_cfgdecp
+//BIFPLR6_0_VENDOR_ID
+#define BIFPLR6_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR6_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR6_0_DEVICE_ID
+#define BIFPLR6_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR6_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR6_0_COMMAND
+#define BIFPLR6_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR6_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR6_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR6_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR6_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR6_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR6_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR6_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR6_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR6_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR6_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR6_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR6_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR6_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR6_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR6_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR6_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR6_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR6_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR6_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR6_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR6_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR6_0_STATUS
+#define BIFPLR6_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR6_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR6_0_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR6_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR6_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR6_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR6_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR6_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR6_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR6_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR6_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR6_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR6_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR6_0_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR6_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR6_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR6_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR6_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR6_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR6_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR6_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR6_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR6_0_REVISION_ID
+#define BIFPLR6_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR6_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR6_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR6_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR6_0_PROG_INTERFACE
+#define BIFPLR6_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR6_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR6_0_SUB_CLASS
+#define BIFPLR6_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR6_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR6_0_BASE_CLASS
+#define BIFPLR6_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR6_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR6_0_CACHE_LINE
+#define BIFPLR6_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR6_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR6_0_LATENCY
+#define BIFPLR6_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR6_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR6_0_HEADER
+#define BIFPLR6_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR6_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR6_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR6_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR6_0_BIST
+#define BIFPLR6_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR6_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR6_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR6_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR6_0_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR6_0_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR6_0_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR6_0_IO_BASE_LIMIT
+#define BIFPLR6_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR6_0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR6_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR6_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR6_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR6_0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR6_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR6_0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR6_0_SECONDARY_STATUS
+#define BIFPLR6_0_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR6_0_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR6_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR6_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR6_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR6_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR6_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR6_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR6_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR6_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR6_0_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR6_0_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR6_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR6_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR6_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR6_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR6_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR6_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR6_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR6_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR6_0_MEM_BASE_LIMIT
+#define BIFPLR6_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR6_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR6_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR6_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR6_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR6_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR6_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR6_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR6_0_PREF_BASE_LIMIT
+#define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR6_0_PREF_BASE_UPPER
+#define BIFPLR6_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR6_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PREF_LIMIT_UPPER
+#define BIFPLR6_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR6_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR6_0_IO_BASE_LIMIT_HI
+#define BIFPLR6_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR6_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR6_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR6_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR6_0_CAP_PTR
+#define BIFPLR6_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR6_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIFPLR6_0_INTERRUPT_LINE
+#define BIFPLR6_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR6_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR6_0_INTERRUPT_PIN
+#define BIFPLR6_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR6_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR6_0_IRQ_BRIDGE_CNTL
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+//BIFPLR6_0_EXT_BRIDGE_CNTL
+#define BIFPLR6_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR6_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR6_0_PMI_CAP_LIST
+#define BIFPLR6_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR6_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR6_0_PMI_CAP
+#define BIFPLR6_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR6_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR6_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR6_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR6_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR6_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR6_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR6_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR6_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR6_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR6_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR6_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR6_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR6_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR6_0_PMI_STATUS_CNTL
+#define BIFPLR6_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR6_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR6_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR6_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR6_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR6_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR6_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR6_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR6_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR6_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR6_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR6_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR6_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR6_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR6_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR6_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR6_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR6_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR6_0_PCIE_CAP_LIST
+#define BIFPLR6_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR6_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR6_0_PCIE_CAP
+#define BIFPLR6_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR6_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR6_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR6_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR6_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR6_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR6_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR6_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR6_0_DEVICE_CAP
+#define BIFPLR6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR6_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR6_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR6_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR6_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR6_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR6_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR6_0_DEVICE_CNTL
+#define BIFPLR6_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR6_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR6_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR6_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR6_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR6_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR6_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR6_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR6_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR6_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR6_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR6_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR6_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR6_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR6_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR6_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR6_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR6_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR6_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR6_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR6_0_DEVICE_STATUS
+#define BIFPLR6_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR6_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR6_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR6_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR6_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR6_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR6_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR6_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR6_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR6_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR6_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR6_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIFPLR6_0_LINK_CAP
+#define BIFPLR6_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR6_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR6_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR6_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR6_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR6_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR6_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR6_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR6_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR6_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR6_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR6_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR6_0_LINK_CNTL
+#define BIFPLR6_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR6_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR6_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR6_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR6_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR6_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR6_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR6_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR6_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR6_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR6_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR6_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIFPLR6_0_LINK_STATUS
+#define BIFPLR6_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR6_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR6_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR6_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR6_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR6_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR6_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR6_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR6_0_SLOT_CAP
+#define BIFPLR6_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR6_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR6_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR6_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR6_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR6_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR6_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR6_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR6_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR6_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR6_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR6_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR6_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR6_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR6_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR6_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR6_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR6_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR6_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR6_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR6_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR6_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR6_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR6_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR6_0_SLOT_CNTL
+#define BIFPLR6_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR6_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR6_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR6_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR6_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR6_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR6_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR6_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR6_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR6_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR6_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR6_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR6_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR6_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR6_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR6_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR6_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR6_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR6_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR6_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR6_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR6_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR6_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR6_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR6_0_SLOT_STATUS
+#define BIFPLR6_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR6_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR6_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR6_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR6_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR6_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR6_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR6_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR6_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR6_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR6_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR6_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR6_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR6_0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR6_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR6_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR6_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR6_0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR6_0_ROOT_CNTL
+#define BIFPLR6_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR6_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR6_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR6_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR6_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR6_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR6_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR6_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR6_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR6_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR6_0_ROOT_CAP
+#define BIFPLR6_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR6_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR6_0_ROOT_STATUS
+#define BIFPLR6_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR6_0_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR6_0_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR6_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR6_0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR6_0_DEVICE_CAP2
+#define BIFPLR6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR6_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR6_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR6_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR6_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIFPLR6_0_DEVICE_CNTL2
+#define BIFPLR6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR6_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR6_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR6_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR6_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR6_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR6_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR6_0_DEVICE_STATUS2
+#define BIFPLR6_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR6_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR6_0_LINK_CAP2
+#define BIFPLR6_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR6_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR6_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIFPLR6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR6_0_LINK_CAP2__RESERVED__SHIFT 0x13
+#define BIFPLR6_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR6_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR6_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L
+#define BIFPLR6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L
+#define BIFPLR6_0_LINK_CAP2__RESERVED_MASK 0xFFF80000L
+//BIFPLR6_0_LINK_CNTL2
+#define BIFPLR6_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR6_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR6_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR6_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR6_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR6_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR6_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR6_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR6_0_LINK_STATUS2
+#define BIFPLR6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIFPLR6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIFPLR6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIFPLR6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIFPLR6_0_SLOT_CAP2
+#define BIFPLR6_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR6_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR6_0_SLOT_CNTL2
+#define BIFPLR6_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR6_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR6_0_SLOT_STATUS2
+#define BIFPLR6_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR6_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR6_0_MSI_CAP_LIST
+#define BIFPLR6_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR6_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR6_0_MSI_MSG_CNTL
+#define BIFPLR6_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR6_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR6_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR6_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR6_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR6_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR6_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR6_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR6_0_MSI_MSG_ADDR_LO
+#define BIFPLR6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR6_0_MSI_MSG_ADDR_HI
+#define BIFPLR6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR6_0_MSI_MSG_DATA
+#define BIFPLR6_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR6_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIFPLR6_0_MSI_MSG_DATA_64
+#define BIFPLR6_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR6_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR6_0_SSID_CAP_LIST
+#define BIFPLR6_0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR6_0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR6_0_SSID_CAP
+#define BIFPLR6_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR6_0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR6_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR6_0_MSI_MAP_CAP_LIST
+#define BIFPLR6_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR6_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR6_0_MSI_MAP_CAP
+#define BIFPLR6_0_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR6_0_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR6_0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR6_0_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR6_0_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR6_0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR6_0_MSI_MAP_ADDR_LO
+#define BIFPLR6_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define BIFPLR6_0_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L
+//BIFPLR6_0_MSI_MAP_ADDR_HI
+#define BIFPLR6_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define BIFPLR6_0_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR6_0_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_0_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR6_0_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR6_0_PCIE_PORT_VC_CNTL
+#define BIFPLR6_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR6_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR6_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR6_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR6_0_PCIE_PORT_VC_STATUS
+#define BIFPLR6_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR6_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR6_0_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR6_0_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR6_0_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR6_0_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_0_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR6_0_PCIE_UNCORR_ERR_MASK
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR6_0_PCIE_CORR_ERR_STATUS
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR6_0_PCIE_CORR_ERR_MASK
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIFPLR6_0_PCIE_HDR_LOG0
+#define BIFPLR6_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_HDR_LOG1
+#define BIFPLR6_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_HDR_LOG2
+#define BIFPLR6_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_HDR_LOG3
+#define BIFPLR6_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_ROOT_ERR_CMD
+#define BIFPLR6_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR6_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR6_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR6_0_PCIE_ROOT_ERR_STATUS
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR6_0_PCIE_ERR_SRC_ID
+#define BIFPLR6_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR6_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR6_0_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_0_PCIE_LINK_CNTL3
+#define BIFPLR6_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR6_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define BIFPLR6_0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10
+#define BIFPLR6_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+#define BIFPLR6_0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L
+//BIFPLR6_0_PCIE_LANE_ERROR_STATUS
+#define BIFPLR6_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIFPLR6_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIFPLR6_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_0_PCIE_ACS_CAP
+#define BIFPLR6_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR6_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR6_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR6_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR6_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR6_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR6_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR6_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR6_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR6_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR6_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR6_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR6_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR6_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR6_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR6_0_PCIE_ACS_CNTL
+#define BIFPLR6_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR6_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR6_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR6_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR6_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR6_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR6_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR6_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR6_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR6_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR6_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR6_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR6_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR6_0_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_0_PCIE_MC_CAP
+#define BIFPLR6_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR6_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR6_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR6_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR6_0_PCIE_MC_CNTL
+#define BIFPLR6_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR6_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR6_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR6_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR6_0_PCIE_MC_ADDR0
+#define BIFPLR6_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR6_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR6_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR6_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR6_0_PCIE_MC_ADDR1
+#define BIFPLR6_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR6_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_MC_RCV0
+#define BIFPLR6_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR6_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_MC_RCV1
+#define BIFPLR6_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR6_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_MC_BLOCK_ALL0
+#define BIFPLR6_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR6_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_MC_BLOCK_ALL1
+#define BIFPLR6_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR6_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR6_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR6_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR6_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR6_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR6_0_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR6_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR6_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_0_PCIE_L1_PM_SUB_CAP
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR6_0_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR6_0_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_0_PCIE_DPC_CAP_LIST
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR6_0_PCIE_DPC_CNTL
+#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR6_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR6_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR6_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR6_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR6_0_PCIE_DPC_STATUS
+#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR6_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR6_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR6_0_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR6_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR6_0_PCIE_RP_PIO_STATUS
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR6_0_PCIE_RP_PIO_MASK
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR6_0_PCIE_RP_PIO_SEVERITY
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR6_0_PCIE_RP_PIO_SYSERROR
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR6_0_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR6_0_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_RP_PIO_IMPSPEC_LOG
+#define BIFPLR6_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_0_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_ESM_CAP_LIST
+#define BIFPLR6_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_0_PCIE_ESM_HEADER_1
+#define BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR6_0_PCIE_ESM_HEADER_2
+#define BIFPLR6_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR6_0_PCIE_ESM_STATUS
+#define BIFPLR6_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR6_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR6_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR6_0_PCIE_ESM_CTRL
+#define BIFPLR6_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8
+#define BIFPLR6_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR6_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL
+#define BIFPLR6_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L
+#define BIFPLR6_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR6_0_PCIE_ESM_CAP_1
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR6_0_PCIE_ESM_CAP_2
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR6_0_PCIE_ESM_CAP_3
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR6_0_PCIE_ESM_CAP_4
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR6_0_PCIE_ESM_CAP_5
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR6_0_PCIE_ESM_CAP_6
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR6_0_PCIE_ESM_CAP_7
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+
+
+// addressBlock: nbio_dbgu0_dbgudec
+//port_a_addr
+#define port_a_addr__Index__SHIFT 0x0
+#define port_a_addr__Reserved__SHIFT 0x8
+#define port_a_addr__ReadEnable__SHIFT 0x1f
+#define port_a_addr__Index_MASK 0x000000FFL
+#define port_a_addr__Reserved_MASK 0x7FFFFF00L
+#define port_a_addr__ReadEnable_MASK 0x80000000L
+//port_a_data_lo
+#define port_a_data_lo__Data__SHIFT 0x0
+#define port_a_data_lo__Data_MASK 0xFFFFFFFFL
+//port_a_data_hi
+#define port_a_data_hi__Data__SHIFT 0x0
+#define port_a_data_hi__Data_MASK 0xFFFFFFFFL
+//port_b_addr
+#define port_b_addr__Index__SHIFT 0x0
+#define port_b_addr__Reserved__SHIFT 0x8
+#define port_b_addr__ReadEnable__SHIFT 0x1f
+#define port_b_addr__Index_MASK 0x000000FFL
+#define port_b_addr__Reserved_MASK 0x7FFFFF00L
+#define port_b_addr__ReadEnable_MASK 0x80000000L
+//port_b_data_lo
+#define port_b_data_lo__Data__SHIFT 0x0
+#define port_b_data_lo__Data_MASK 0xFFFFFFFFL
+//port_b_data_hi
+#define port_b_data_hi__Data__SHIFT 0x0
+#define port_b_data_hi__Data_MASK 0xFFFFFFFFL
+//port_c_addr
+#define port_c_addr__Index__SHIFT 0x0
+#define port_c_addr__Reserved__SHIFT 0x8
+#define port_c_addr__ReadEnable__SHIFT 0x1f
+#define port_c_addr__Index_MASK 0x000000FFL
+#define port_c_addr__Reserved_MASK 0x7FFFFF00L
+#define port_c_addr__ReadEnable_MASK 0x80000000L
+//port_c_data_lo
+#define port_c_data_lo__Data__SHIFT 0x0
+#define port_c_data_lo__Data_MASK 0xFFFFFFFFL
+//port_c_data_hi
+#define port_c_data_hi__Data__SHIFT 0x0
+#define port_c_data_hi__Data_MASK 0xFFFFFFFFL
+//port_d_addr
+#define port_d_addr__Index__SHIFT 0x0
+#define port_d_addr__Reserved__SHIFT 0x8
+#define port_d_addr__ReadEnable__SHIFT 0x1f
+#define port_d_addr__Index_MASK 0x000000FFL
+#define port_d_addr__Reserved_MASK 0x7FFFFF00L
+#define port_d_addr__ReadEnable_MASK 0x80000000L
+//port_d_data_lo
+#define port_d_data_lo__Data__SHIFT 0x0
+#define port_d_data_lo__Data_MASK 0xFFFFFFFFL
+//port_d_data_hi
+#define port_d_data_hi__Data__SHIFT 0x0
+#define port_d_data_hi__Data_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_gdc_GDCDEC
+//GDC0_NGDC_SDP_PORT_CTRL
+#define GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0
+#define GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK 0x0000003FL
+//GDC0_SHUB_REGS_IF_CTL
+#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0
+#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L
+//GDC0_NGDC_RESERVED_0
+#define GDC0_NGDC_RESERVED_0__RESERVED__SHIFT 0x0
+#define GDC0_NGDC_RESERVED_0__RESERVED_MASK 0xFFFFFFFFL
+//GDC0_NGDC_RESERVED_1
+#define GDC0_NGDC_RESERVED_1__RESERVED__SHIFT 0x0
+#define GDC0_NGDC_RESERVED_1__RESERVED_MASK 0xFFFFFFFFL
+//GDC0_NGDC_SDP_PORT_CTRL_SOCCLK
+#define GDC0_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK__SHIFT 0x0
+#define GDC0_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK_MASK 0x0000003FL
+//GDC0_BIF_SDMA0_DOORBELL_RANGE
+#define GDC0_BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define GDC0_BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define GDC0_BIF_SDMA0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define GDC0_BIF_SDMA0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//GDC0_BIF_SDMA1_DOORBELL_RANGE
+#define GDC0_BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define GDC0_BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define GDC0_BIF_SDMA1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define GDC0_BIF_SDMA1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//GDC0_BIF_IH_DOORBELL_RANGE
+#define GDC0_BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define GDC0_BIF_IH_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define GDC0_BIF_IH_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define GDC0_BIF_IH_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//GDC0_BIF_MMSCH0_DOORBELL_RANGE
+#define GDC0_BIF_MMSCH0_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define GDC0_BIF_MMSCH0_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define GDC0_BIF_MMSCH0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define GDC0_BIF_MMSCH0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//GDC0_ATDMA_MISC_CNTL
+#define GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT 0x0
+#define GDC0_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0x1
+#define GDC0_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT 0x10
+#define GDC0_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT 0x18
+#define GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK 0x00000001L
+#define GDC0_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000002L
+#define GDC0_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK 0x00FF0000L
+#define GDC0_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK 0xFF000000L
+//GDC0_BIF_DOORBELL_FENCE_CNTL
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE__SHIFT 0x0
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE_MASK 0x00000001L
+//GDC0_S2A_MISC_CNTL
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__SHIFT 0x0
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__SHIFT 0x1
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__SHIFT 0x2
+#define GDC0_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT 0x3
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS_MASK 0x00000001L
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS_MASK 0x00000002L
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS_MASK 0x00000004L
+#define GDC0_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK 0x00000008L
+//GDC0_GDC_PG_MISC_CNTL
+#define GDC0_GDC_PG_MISC_CNTL__GDC_PG_RESET_SELECT_COLD_RESET__SHIFT 0x0
+#define GDC0_GDC_PG_MISC_CNTL__GDC_PG_RESET_SELECT_COLD_RESET_MASK 0x00000001L
+
+
+// addressBlock: nbio_nbif0_syshub_mmreg_direct_syshubdirect
+//SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__SHIFT 0x1f
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000004L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000008L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000010L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000020L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000040L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000080L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00010000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00020000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00040000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00080000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00100000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00200000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00400000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00800000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x10000000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN_MASK 0x80000000L
+//SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SOCCLK
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER_MASK 0x0000FFFFL
+//SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__SHIFT 0xf
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__SHIFT 0x11
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en_MASK 0x00008000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en_MASK 0x00010000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en_MASK 0x00020000L
+//SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__SHIFT 0xf
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__SHIFT 0x11
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en_MASK 0x00008000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en_MASK 0x00010000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en_MASK 0x00020000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L
+//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L
+//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_SYSHUB_QOS_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L
+//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL0_CNTL
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL1_CNTL
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL2_CNTL
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL0_CNTL
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL1_CNTL
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL2_CNTL
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL3_CNTL
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL4_CNTL
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL
+#define SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL__SYSHUB_CG_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL__SYSHUB_CG_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER_MASK 0x0000FF00L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER_MASK 0x00FF0000L
+//SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__SHIFT 0x2
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__SHIFT 0x3
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__SHIFT 0x4
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__SHIFT 0x5
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__SHIFT 0x6
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__SHIFT 0x7
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__SHIFT 0xa
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__SHIFT 0xb
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__SHIFT 0xc
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__SHIFT 0xd
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__SHIFT 0xe
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__SHIFT 0xf
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2_MASK 0x00000004L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3_MASK 0x00000008L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4_MASK 0x00000010L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5_MASK 0x00000020L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6_MASK 0x00000040L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7_MASK 0x00000080L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9_MASK 0x00000200L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10_MASK 0x00000400L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11_MASK 0x00000800L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12_MASK 0x00001000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13_MASK 0x00002000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14_MASK 0x00004000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15_MASK 0x00008000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF_MASK 0x00010000L
+//SYSHUB_MMREG_DIRECT_SYSHUB_HP_TIMER
+#define SYSHUB_MMREG_DIRECT_SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_SYSHUB_HP_TIMER__SYSHUB_HP_TIMER_MASK 0xFFFFFFFFL
+//SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_MODE_SOCCLK__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HYSTERESIS_SOCCLK__SHIFT 0x2
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HST_DIS_SOCCLK__SHIFT 0xa
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DMA_DIS_SOCCLK__SHIFT 0xb
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_REGS_DIS_SOCCLK__SHIFT 0xc
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_AER_DIS_SOCCLK__SHIFT 0xd
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_MODE_SOCCLK_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HYSTERESIS_SOCCLK_MASK 0x000003FCL
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HST_DIS_SOCCLK_MASK 0x00000400L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DMA_DIS_SOCCLK_MASK 0x00000800L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_REGS_DIS_SOCCLK_MASK 0x00001000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_AER_DIS_SOCCLK_MASK 0x00002000L
+//SYSHUB_MMREG_DIRECT_SYSUB_CPF_DOORBELL_RS_RESET
+#define SYSHUB_MMREG_DIRECT_SYSUB_CPF_DOORBELL_RS_RESET__SYSHUB_CPF_DOORBELL_RS_RESET__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_SYSUB_CPF_DOORBELL_RS_RESET__SYSHUB_CPF_DOORBELL_RS_RESET_MASK 0x00000001L
+//SYSHUB_MMREG_DIRECT_SYSHUB_SCRATCH
+#define SYSHUB_MMREG_DIRECT_SYSHUB_SCRATCH__SCRATCH__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_SYSHUB_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL
+//SYSHUB_MMREG_DIRECT_SYSHUB_CL_MASK
+#define SYSHUB_MMREG_DIRECT_SYSHUB_CL_MASK__MP1DRAM_MASK_DIS__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_SYSHUB_CL_MASK__MP1_MASK_DIS__SHIFT 0x2
+#define SYSHUB_MMREG_DIRECT_SYSHUB_CL_MASK__MP1DRAM_MASK_DIS_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_CL_MASK__MP1_MASK_DIS_MASK 0x00000004L
+//SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__SHIFT 0x1f
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000004L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000008L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000010L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000020L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000040L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000080L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00010000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00020000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00040000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00080000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00100000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00200000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00400000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00800000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x10000000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN_MASK 0x80000000L
+//SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SHUBCLK
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER_MASK 0x0000FFFFL
+//SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__SHIFT 0xf
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en_MASK 0x00008000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en_MASK 0x00010000L
+//SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__SHIFT 0xf
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en_MASK 0x00008000L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en_MASK 0x00010000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L
+//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L
+//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_MODE_SHUBCLK__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HYSTERESIS_SHUBCLK__SHIFT 0x2
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HST_DIS_SHUBCLK__SHIFT 0xa
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_DMA_DIS_SHUBCLK__SHIFT 0xb
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_REGS_DIS_SHUBCLK__SHIFT 0xc
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_MODE_SHUBCLK_MASK 0x00000002L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HYSTERESIS_SHUBCLK_MASK 0x000003FCL
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HST_DIS_SHUBCLK_MASK 0x00000400L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_DMA_DIS_SHUBCLK_MASK 0x00000800L
+#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_REGS_DIS_SHUBCLK_MASK 0x00001000L
+//SYSHUB_MMREG_DIRECT_NIC400_0_ASIB_0_FN_MOD
+#define SYSHUB_MMREG_DIRECT_NIC400_0_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_0_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_0_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_0_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_0_FN_MOD_BM_ISS
+#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_0_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_0_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_0_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_0_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_1_FN_MOD_BM_ISS
+#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_1_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_1_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_1_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_1_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_1_ASIB_0_FN_MOD
+#define SYSHUB_MMREG_DIRECT_NIC400_1_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_1_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_1_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_1_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_0_FN_MOD
+#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_0_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_0_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_0_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_0_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_1_FN_MOD
+#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_1_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_1_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_1_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_1_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_2_FN_MOD
+#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_2_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_2_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_2_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_2_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_0_FN_MOD
+#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_1_FN_MOD
+#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_1_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_1_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_1_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_1_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_2_FN_MOD
+#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_2_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_2_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_2_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_2_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_3_FN_MOD
+#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_3_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_3_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_3_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_3_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_4_FN_MOD
+#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_4_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_4_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_4_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_4_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_2_AMIB_0_FN_MOD_BM_ISS
+#define SYSHUB_MMREG_DIRECT_NIC400_2_AMIB_0_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_2_AMIB_0_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_2_AMIB_0_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_2_AMIB_0_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_0_FN_MOD
+#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_1_FN_MOD
+#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_1_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_1_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_1_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_1_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_2_FN_MOD
+#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_2_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_2_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_2_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_2_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_3_FN_MOD
+#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_3_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_3_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_3_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_3_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_4_FN_MOD
+#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_4_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_4_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_4_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_5_ASIB_4_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_5_AMIB_0_FN_MOD
+#define SYSHUB_MMREG_DIRECT_NIC400_5_AMIB_0_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_5_AMIB_0_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_5_AMIB_0_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_5_AMIB_0_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_4_ASIB_0_FN_MOD
+#define SYSHUB_MMREG_DIRECT_NIC400_4_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_4_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_4_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_4_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_4_ASIB_1_FN_MOD
+#define SYSHUB_MMREG_DIRECT_NIC400_4_ASIB_1_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_4_ASIB_1_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_4_ASIB_1_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_4_ASIB_1_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_DIRECT_NIC400_4_AMIB_0_FN_MOD
+#define SYSHUB_MMREG_DIRECT_NIC400_4_AMIB_0_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_DIRECT_NIC400_4_AMIB_0_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_DIRECT_NIC400_4_AMIB_0_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_DIRECT_NIC400_4_AMIB_0_FN_MOD__write_iss_override_MASK 0x00000002L
+
+
+// addressBlock: nbio_nbif0_nbif_sion_SIONDEC
+//SION_CL0_RdRsp_BurstTarget_REG0
+#define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_RdRsp_BurstTarget_REG1
+#define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_RdRsp_TimeSlot_REG0
+#define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_RdRsp_TimeSlot_REG1
+#define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_WrRsp_BurstTarget_REG0
+#define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_WrRsp_BurstTarget_REG1
+#define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_WrRsp_TimeSlot_REG0
+#define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_WrRsp_TimeSlot_REG1
+#define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_Req_BurstTarget_REG0
+#define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_Req_BurstTarget_REG1
+#define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_Req_TimeSlot_REG0
+#define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_Req_TimeSlot_REG1
+#define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_ReqPoolCredit_Alloc_REG0
+#define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_ReqPoolCredit_Alloc_REG1
+#define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_DataPoolCredit_Alloc_REG0
+#define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_DataPoolCredit_Alloc_REG1
+#define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_RdRspPoolCredit_Alloc_REG0
+#define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_RdRspPoolCredit_Alloc_REG1
+#define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_WrRspPoolCredit_Alloc_REG0
+#define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_WrRspPoolCredit_Alloc_REG1
+#define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_RdRsp_BurstTarget_REG0
+#define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_RdRsp_BurstTarget_REG1
+#define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_RdRsp_TimeSlot_REG0
+#define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_RdRsp_TimeSlot_REG1
+#define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_WrRsp_BurstTarget_REG0
+#define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_WrRsp_BurstTarget_REG1
+#define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_WrRsp_TimeSlot_REG0
+#define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_WrRsp_TimeSlot_REG1
+#define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_Req_BurstTarget_REG0
+#define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_Req_BurstTarget_REG1
+#define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_Req_TimeSlot_REG0
+#define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_Req_TimeSlot_REG1
+#define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_ReqPoolCredit_Alloc_REG0
+#define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_ReqPoolCredit_Alloc_REG1
+#define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_DataPoolCredit_Alloc_REG0
+#define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_DataPoolCredit_Alloc_REG1
+#define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_RdRspPoolCredit_Alloc_REG0
+#define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_RdRspPoolCredit_Alloc_REG1
+#define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_WrRspPoolCredit_Alloc_REG0
+#define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_WrRspPoolCredit_Alloc_REG1
+#define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_RdRsp_BurstTarget_REG0
+#define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_RdRsp_BurstTarget_REG1
+#define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_RdRsp_TimeSlot_REG0
+#define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_RdRsp_TimeSlot_REG1
+#define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_WrRsp_BurstTarget_REG0
+#define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_WrRsp_BurstTarget_REG1
+#define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_WrRsp_TimeSlot_REG0
+#define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_WrRsp_TimeSlot_REG1
+#define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_Req_BurstTarget_REG0
+#define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_Req_BurstTarget_REG1
+#define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_Req_TimeSlot_REG0
+#define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_Req_TimeSlot_REG1
+#define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_ReqPoolCredit_Alloc_REG0
+#define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_ReqPoolCredit_Alloc_REG1
+#define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_DataPoolCredit_Alloc_REG0
+#define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_DataPoolCredit_Alloc_REG1
+#define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_RdRspPoolCredit_Alloc_REG0
+#define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_RdRspPoolCredit_Alloc_REG1
+#define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_WrRspPoolCredit_Alloc_REG0
+#define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_WrRspPoolCredit_Alloc_REG1
+#define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL3_RdRsp_BurstTarget_REG0
+#define SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL3_RdRsp_BurstTarget_REG1
+#define SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL3_RdRsp_TimeSlot_REG0
+#define SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL3_RdRsp_TimeSlot_REG1
+#define SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL3_WrRsp_BurstTarget_REG0
+#define SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL3_WrRsp_BurstTarget_REG1
+#define SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL3_WrRsp_TimeSlot_REG0
+#define SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL3_WrRsp_TimeSlot_REG1
+#define SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL3_Req_BurstTarget_REG0
+#define SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL3_Req_BurstTarget_REG1
+#define SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL3_Req_TimeSlot_REG0
+#define SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL3_Req_TimeSlot_REG1
+#define SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL3_ReqPoolCredit_Alloc_REG0
+#define SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL3_ReqPoolCredit_Alloc_REG1
+#define SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL3_DataPoolCredit_Alloc_REG0
+#define SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL3_DataPoolCredit_Alloc_REG1
+#define SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL3_RdRspPoolCredit_Alloc_REG0
+#define SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL3_RdRspPoolCredit_Alloc_REG1
+#define SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL3_WrRspPoolCredit_Alloc_REG0
+#define SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL3_WrRspPoolCredit_Alloc_REG1
+#define SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CNTL_REG0
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT 0x0
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT 0x1
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT 0x2
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT 0x3
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT 0x4
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT 0x5
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT 0x6
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT 0x7
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT 0x8
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT 0x9
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__SHIFT 0xa
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__SHIFT 0xb
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__SHIFT 0xc
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__SHIFT 0xd
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__SHIFT 0xe
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__SHIFT 0xf
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__SHIFT 0x10
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__SHIFT 0x11
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__SHIFT 0x12
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__SHIFT 0x13
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_MASK 0x00000001L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_MASK 0x00000002L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_MASK 0x00000004L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_MASK 0x00000008L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_MASK 0x00000010L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_MASK 0x00000020L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_MASK 0x00000040L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_MASK 0x00000080L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_MASK 0x00000100L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_MASK 0x00000200L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0_MASK 0x00000400L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1_MASK 0x00000800L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2_MASK 0x00001000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3_MASK 0x00002000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4_MASK 0x00004000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5_MASK 0x00008000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6_MASK 0x00010000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7_MASK 0x00020000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8_MASK 0x00040000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9_MASK 0x00080000L
+//SION_CNTL_REG1
+#define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD__SHIFT 0x0
+#define SION_CNTL_REG1__CG_OFF_HYSTERESIS__SHIFT 0x8
+#define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD_MASK 0x000000FFL
+#define SION_CNTL_REG1__CG_OFF_HYSTERESIS_MASK 0x0000FF00L
+
+
+// addressBlock: nbio_nbif0_gdc_rst_GDCRST_DEC
+//SHUB_PF_FLR_RST
+#define SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0
+#define SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1
+#define SHUB_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT 0x2
+#define SHUB_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT 0x3
+#define SHUB_PF_FLR_RST__DEV0_PF4_FLR_RST__SHIFT 0x4
+#define SHUB_PF_FLR_RST__DEV0_PF5_FLR_RST__SHIFT 0x5
+#define SHUB_PF_FLR_RST__DEV0_PF6_FLR_RST__SHIFT 0x6
+#define SHUB_PF_FLR_RST__DEV0_PF7_FLR_RST__SHIFT 0x7
+#define SHUB_PF_FLR_RST__DEV1_PF0_FLR_RST__SHIFT 0x8
+#define SHUB_PF_FLR_RST__DEV1_PF1_FLR_RST__SHIFT 0x9
+#define SHUB_PF_FLR_RST__DEV1_PF2_FLR_RST__SHIFT 0xa
+#define SHUB_PF_FLR_RST__DEV1_PF3_FLR_RST__SHIFT 0xb
+#define SHUB_PF_FLR_RST__DEV1_PF4_FLR_RST__SHIFT 0xc
+#define SHUB_PF_FLR_RST__DEV1_PF5_FLR_RST__SHIFT 0xd
+#define SHUB_PF_FLR_RST__DEV1_PF6_FLR_RST__SHIFT 0xe
+#define SHUB_PF_FLR_RST__DEV1_PF7_FLR_RST__SHIFT 0xf
+#define SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK 0x00000001L
+#define SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK 0x00000002L
+#define SHUB_PF_FLR_RST__DEV0_PF2_FLR_RST_MASK 0x00000004L
+#define SHUB_PF_FLR_RST__DEV0_PF3_FLR_RST_MASK 0x00000008L
+#define SHUB_PF_FLR_RST__DEV0_PF4_FLR_RST_MASK 0x00000010L
+#define SHUB_PF_FLR_RST__DEV0_PF5_FLR_RST_MASK 0x00000020L
+#define SHUB_PF_FLR_RST__DEV0_PF6_FLR_RST_MASK 0x00000040L
+#define SHUB_PF_FLR_RST__DEV0_PF7_FLR_RST_MASK 0x00000080L
+#define SHUB_PF_FLR_RST__DEV1_PF0_FLR_RST_MASK 0x00000100L
+#define SHUB_PF_FLR_RST__DEV1_PF1_FLR_RST_MASK 0x00000200L
+#define SHUB_PF_FLR_RST__DEV1_PF2_FLR_RST_MASK 0x00000400L
+#define SHUB_PF_FLR_RST__DEV1_PF3_FLR_RST_MASK 0x00000800L
+#define SHUB_PF_FLR_RST__DEV1_PF4_FLR_RST_MASK 0x00001000L
+#define SHUB_PF_FLR_RST__DEV1_PF5_FLR_RST_MASK 0x00002000L
+#define SHUB_PF_FLR_RST__DEV1_PF6_FLR_RST_MASK 0x00004000L
+#define SHUB_PF_FLR_RST__DEV1_PF7_FLR_RST_MASK 0x00008000L
+//SHUB_GFX_DRV_VPU_RST
+#define SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST__SHIFT 0x0
+#define SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST_MASK 0x00000001L
+//SHUB_LINK_RESET
+#define SHUB_LINK_RESET__LINK_P0_RESET__SHIFT 0x0
+#define SHUB_LINK_RESET__LINK_P1_RESET__SHIFT 0x1
+#define SHUB_LINK_RESET__LINK_P0_RESET_MASK 0x00000001L
+#define SHUB_LINK_RESET__LINK_P1_RESET_MASK 0x00000002L
+//SHUB_PF0_VF_FLR_RST
+#define SHUB_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__SHIFT 0x0
+#define SHUB_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__SHIFT 0x1
+#define SHUB_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__SHIFT 0x2
+#define SHUB_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__SHIFT 0x3
+#define SHUB_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__SHIFT 0x4
+#define SHUB_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__SHIFT 0x5
+#define SHUB_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__SHIFT 0x6
+#define SHUB_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__SHIFT 0x7
+#define SHUB_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__SHIFT 0x8
+#define SHUB_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__SHIFT 0x9
+#define SHUB_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__SHIFT 0xa
+#define SHUB_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__SHIFT 0xb
+#define SHUB_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__SHIFT 0xc
+#define SHUB_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__SHIFT 0xd
+#define SHUB_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__SHIFT 0xe
+#define SHUB_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__SHIFT 0xf
+#define SHUB_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__SHIFT 0x1f
+#define SHUB_PF0_VF_FLR_RST__PF0_VF0_FLR_RST_MASK 0x00000001L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF1_FLR_RST_MASK 0x00000002L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF2_FLR_RST_MASK 0x00000004L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF3_FLR_RST_MASK 0x00000008L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF4_FLR_RST_MASK 0x00000010L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF5_FLR_RST_MASK 0x00000020L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF6_FLR_RST_MASK 0x00000040L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF7_FLR_RST_MASK 0x00000080L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF8_FLR_RST_MASK 0x00000100L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF9_FLR_RST_MASK 0x00000200L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF10_FLR_RST_MASK 0x00000400L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF11_FLR_RST_MASK 0x00000800L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF12_FLR_RST_MASK 0x00001000L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF13_FLR_RST_MASK 0x00002000L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF14_FLR_RST_MASK 0x00004000L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF15_FLR_RST_MASK 0x00008000L
+#define SHUB_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST_MASK 0x80000000L
+//SHUB_HARD_RST_CTRL
+#define SHUB_HARD_RST_CTRL__COR_RESET_EN__SHIFT 0x0
+#define SHUB_HARD_RST_CTRL__REG_RESET_EN__SHIFT 0x1
+#define SHUB_HARD_RST_CTRL__STY_RESET_EN__SHIFT 0x2
+#define SHUB_HARD_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3
+#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4
+#define SHUB_HARD_RST_CTRL__COR_RESET_EN_MASK 0x00000001L
+#define SHUB_HARD_RST_CTRL__REG_RESET_EN_MASK 0x00000002L
+#define SHUB_HARD_RST_CTRL__STY_RESET_EN_MASK 0x00000004L
+#define SHUB_HARD_RST_CTRL__NIC400_RESET_EN_MASK 0x00000008L
+#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000010L
+//SHUB_SOFT_RST_CTRL
+#define SHUB_SOFT_RST_CTRL__COR_RESET_EN__SHIFT 0x0
+#define SHUB_SOFT_RST_CTRL__REG_RESET_EN__SHIFT 0x1
+#define SHUB_SOFT_RST_CTRL__STY_RESET_EN__SHIFT 0x2
+#define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3
+#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4
+#define SHUB_SOFT_RST_CTRL__COR_RESET_EN_MASK 0x00000001L
+#define SHUB_SOFT_RST_CTRL__REG_RESET_EN_MASK 0x00000002L
+#define SHUB_SOFT_RST_CTRL__STY_RESET_EN_MASK 0x00000004L
+#define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN_MASK 0x00000008L
+#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000010L
+//SHUB_SDP_PORT_RST
+#define SHUB_SDP_PORT_RST__SDP_PORT_RST__SHIFT 0x0
+#define SHUB_SDP_PORT_RST__SDP_PORT_RST_MASK 0x00000001L
+//SHUB_RST_MISC_TRL
+#define SHUB_RST_MISC_TRL__RSMU_SOFT_RST_ATOMIC__SHIFT 0x0
+#define SHUB_RST_MISC_TRL__RSMU_SOFT_RST_CYCLE__SHIFT 0x10
+#define SHUB_RST_MISC_TRL__RSMU_SOFT_RST_ATOMIC_MASK 0x00000001L
+#define SHUB_RST_MISC_TRL__RSMU_SOFT_RST_CYCLE_MASK 0x00FF0000L
+
+
+// addressBlock: nbio_nbif0_gdc_ras_gdc_ras_regblk
+//GDC_RAS_LEAF0_CTRL
+#define GDC_RAS_LEAF0_CTRL__POISON_DET_EN__SHIFT 0x0
+#define GDC_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define GDC_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define GDC_RAS_LEAF0_CTRL__PARITY_DET_EN__SHIFT 0x4
+#define GDC_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
+#define GDC_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT 0x6
+#define GDC_RAS_LEAF0_CTRL__LOCAL_ERR_REPORT_EN__SHIFT 0x7
+#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_RECV__SHIFT 0x10
+#define GDC_RAS_LEAF0_CTRL__LINK_DIS_RECV__SHIFT 0x11
+#define GDC_RAS_LEAF0_CTRL__POISON_ERR_DET__SHIFT 0x12
+#define GDC_RAS_LEAF0_CTRL__PARITY_ERR_DET__SHIFT 0x13
+#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_SENT__SHIFT 0x14
+#define GDC_RAS_LEAF0_CTRL__EGRESS_STALLED__SHIFT 0x15
+#define GDC_RAS_LEAF0_CTRL__POISON_DET_EN_MASK 0x00000001L
+#define GDC_RAS_LEAF0_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDC_RAS_LEAF0_CTRL__POISON_STALL_EN_MASK 0x00000004L
+#define GDC_RAS_LEAF0_CTRL__PARITY_DET_EN_MASK 0x00000010L
+#define GDC_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L
+#define GDC_RAS_LEAF0_CTRL__PARITY_STALL_EN_MASK 0x00000040L
+#define GDC_RAS_LEAF0_CTRL__LOCAL_ERR_REPORT_EN_MASK 0x00000080L
+#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_RECV_MASK 0x00010000L
+#define GDC_RAS_LEAF0_CTRL__LINK_DIS_RECV_MASK 0x00020000L
+#define GDC_RAS_LEAF0_CTRL__POISON_ERR_DET_MASK 0x00040000L
+#define GDC_RAS_LEAF0_CTRL__PARITY_ERR_DET_MASK 0x00080000L
+#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_SENT_MASK 0x00100000L
+#define GDC_RAS_LEAF0_CTRL__EGRESS_STALLED_MASK 0x00200000L
+//GDC_RAS_LEAF1_CTRL
+#define GDC_RAS_LEAF1_CTRL__POISON_DET_EN__SHIFT 0x0
+#define GDC_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define GDC_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define GDC_RAS_LEAF1_CTRL__PARITY_DET_EN__SHIFT 0x4
+#define GDC_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
+#define GDC_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT 0x6
+#define GDC_RAS_LEAF1_CTRL__LOCAL_ERR_REPORT_EN__SHIFT 0x7
+#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_RECV__SHIFT 0x10
+#define GDC_RAS_LEAF1_CTRL__LINK_DIS_RECV__SHIFT 0x11
+#define GDC_RAS_LEAF1_CTRL__POISON_ERR_DET__SHIFT 0x12
+#define GDC_RAS_LEAF1_CTRL__PARITY_ERR_DET__SHIFT 0x13
+#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_SENT__SHIFT 0x14
+#define GDC_RAS_LEAF1_CTRL__EGRESS_STALLED__SHIFT 0x15
+#define GDC_RAS_LEAF1_CTRL__POISON_DET_EN_MASK 0x00000001L
+#define GDC_RAS_LEAF1_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDC_RAS_LEAF1_CTRL__POISON_STALL_EN_MASK 0x00000004L
+#define GDC_RAS_LEAF1_CTRL__PARITY_DET_EN_MASK 0x00000010L
+#define GDC_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L
+#define GDC_RAS_LEAF1_CTRL__PARITY_STALL_EN_MASK 0x00000040L
+#define GDC_RAS_LEAF1_CTRL__LOCAL_ERR_REPORT_EN_MASK 0x00000080L
+#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_RECV_MASK 0x00010000L
+#define GDC_RAS_LEAF1_CTRL__LINK_DIS_RECV_MASK 0x00020000L
+#define GDC_RAS_LEAF1_CTRL__POISON_ERR_DET_MASK 0x00040000L
+#define GDC_RAS_LEAF1_CTRL__PARITY_ERR_DET_MASK 0x00080000L
+#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_SENT_MASK 0x00100000L
+#define GDC_RAS_LEAF1_CTRL__EGRESS_STALLED_MASK 0x00200000L
+//GDC_RAS_LEAF2_CTRL
+#define GDC_RAS_LEAF2_CTRL__POISON_DET_EN__SHIFT 0x0
+#define GDC_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define GDC_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define GDC_RAS_LEAF2_CTRL__PARITY_DET_EN__SHIFT 0x4
+#define GDC_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
+#define GDC_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT 0x6
+#define GDC_RAS_LEAF2_CTRL__LOCAL_ERR_REPORT_EN__SHIFT 0x7
+#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_RECV__SHIFT 0x10
+#define GDC_RAS_LEAF2_CTRL__LINK_DIS_RECV__SHIFT 0x11
+#define GDC_RAS_LEAF2_CTRL__POISON_ERR_DET__SHIFT 0x12
+#define GDC_RAS_LEAF2_CTRL__PARITY_ERR_DET__SHIFT 0x13
+#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_SENT__SHIFT 0x14
+#define GDC_RAS_LEAF2_CTRL__EGRESS_STALLED__SHIFT 0x15
+#define GDC_RAS_LEAF2_CTRL__POISON_DET_EN_MASK 0x00000001L
+#define GDC_RAS_LEAF2_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDC_RAS_LEAF2_CTRL__POISON_STALL_EN_MASK 0x00000004L
+#define GDC_RAS_LEAF2_CTRL__PARITY_DET_EN_MASK 0x00000010L
+#define GDC_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L
+#define GDC_RAS_LEAF2_CTRL__PARITY_STALL_EN_MASK 0x00000040L
+#define GDC_RAS_LEAF2_CTRL__LOCAL_ERR_REPORT_EN_MASK 0x00000080L
+#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_RECV_MASK 0x00010000L
+#define GDC_RAS_LEAF2_CTRL__LINK_DIS_RECV_MASK 0x00020000L
+#define GDC_RAS_LEAF2_CTRL__POISON_ERR_DET_MASK 0x00040000L
+#define GDC_RAS_LEAF2_CTRL__PARITY_ERR_DET_MASK 0x00080000L
+#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_SENT_MASK 0x00100000L
+#define GDC_RAS_LEAF2_CTRL__EGRESS_STALLED_MASK 0x00200000L
+//GDC_RAS_LEAF3_CTRL
+#define GDC_RAS_LEAF3_CTRL__POISON_DET_EN__SHIFT 0x0
+#define GDC_RAS_LEAF3_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define GDC_RAS_LEAF3_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define GDC_RAS_LEAF3_CTRL__PARITY_DET_EN__SHIFT 0x4
+#define GDC_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
+#define GDC_RAS_LEAF3_CTRL__PARITY_STALL_EN__SHIFT 0x6
+#define GDC_RAS_LEAF3_CTRL__LOCAL_ERR_REPORT_EN__SHIFT 0x7
+#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_RECV__SHIFT 0x10
+#define GDC_RAS_LEAF3_CTRL__LINK_DIS_RECV__SHIFT 0x11
+#define GDC_RAS_LEAF3_CTRL__POISON_ERR_DET__SHIFT 0x12
+#define GDC_RAS_LEAF3_CTRL__PARITY_ERR_DET__SHIFT 0x13
+#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_SENT__SHIFT 0x14
+#define GDC_RAS_LEAF3_CTRL__EGRESS_STALLED__SHIFT 0x15
+#define GDC_RAS_LEAF3_CTRL__POISON_DET_EN_MASK 0x00000001L
+#define GDC_RAS_LEAF3_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDC_RAS_LEAF3_CTRL__POISON_STALL_EN_MASK 0x00000004L
+#define GDC_RAS_LEAF3_CTRL__PARITY_DET_EN_MASK 0x00000010L
+#define GDC_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L
+#define GDC_RAS_LEAF3_CTRL__PARITY_STALL_EN_MASK 0x00000040L
+#define GDC_RAS_LEAF3_CTRL__LOCAL_ERR_REPORT_EN_MASK 0x00000080L
+#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_RECV_MASK 0x00010000L
+#define GDC_RAS_LEAF3_CTRL__LINK_DIS_RECV_MASK 0x00020000L
+#define GDC_RAS_LEAF3_CTRL__POISON_ERR_DET_MASK 0x00040000L
+#define GDC_RAS_LEAF3_CTRL__PARITY_ERR_DET_MASK 0x00080000L
+#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_SENT_MASK 0x00100000L
+#define GDC_RAS_LEAF3_CTRL__EGRESS_STALLED_MASK 0x00200000L
+//GDC_RAS_LEAF4_CTRL
+#define GDC_RAS_LEAF4_CTRL__POISON_DET_EN__SHIFT 0x0
+#define GDC_RAS_LEAF4_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define GDC_RAS_LEAF4_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define GDC_RAS_LEAF4_CTRL__PARITY_DET_EN__SHIFT 0x4
+#define GDC_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
+#define GDC_RAS_LEAF4_CTRL__PARITY_STALL_EN__SHIFT 0x6
+#define GDC_RAS_LEAF4_CTRL__LOCAL_ERR_REPORT_EN__SHIFT 0x7
+#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_RECV__SHIFT 0x10
+#define GDC_RAS_LEAF4_CTRL__LINK_DIS_RECV__SHIFT 0x11
+#define GDC_RAS_LEAF4_CTRL__POISON_ERR_DET__SHIFT 0x12
+#define GDC_RAS_LEAF4_CTRL__PARITY_ERR_DET__SHIFT 0x13
+#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_SENT__SHIFT 0x14
+#define GDC_RAS_LEAF4_CTRL__EGRESS_STALLED__SHIFT 0x15
+#define GDC_RAS_LEAF4_CTRL__POISON_DET_EN_MASK 0x00000001L
+#define GDC_RAS_LEAF4_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDC_RAS_LEAF4_CTRL__POISON_STALL_EN_MASK 0x00000004L
+#define GDC_RAS_LEAF4_CTRL__PARITY_DET_EN_MASK 0x00000010L
+#define GDC_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L
+#define GDC_RAS_LEAF4_CTRL__PARITY_STALL_EN_MASK 0x00000040L
+#define GDC_RAS_LEAF4_CTRL__LOCAL_ERR_REPORT_EN_MASK 0x00000080L
+#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_RECV_MASK 0x00010000L
+#define GDC_RAS_LEAF4_CTRL__LINK_DIS_RECV_MASK 0x00020000L
+#define GDC_RAS_LEAF4_CTRL__POISON_ERR_DET_MASK 0x00040000L
+#define GDC_RAS_LEAF4_CTRL__PARITY_ERR_DET_MASK 0x00080000L
+#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_SENT_MASK 0x00100000L
+#define GDC_RAS_LEAF4_CTRL__EGRESS_STALLED_MASK 0x00200000L
+//GDC_RAS_LEAF5_CTRL
+#define GDC_RAS_LEAF5_CTRL__POISON_DET_EN__SHIFT 0x0
+#define GDC_RAS_LEAF5_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define GDC_RAS_LEAF5_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define GDC_RAS_LEAF5_CTRL__PARITY_DET_EN__SHIFT 0x4
+#define GDC_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
+#define GDC_RAS_LEAF5_CTRL__PARITY_STALL_EN__SHIFT 0x6
+#define GDC_RAS_LEAF5_CTRL__LOCAL_ERR_REPORT_EN__SHIFT 0x7
+#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_RECV__SHIFT 0x10
+#define GDC_RAS_LEAF5_CTRL__LINK_DIS_RECV__SHIFT 0x11
+#define GDC_RAS_LEAF5_CTRL__POISON_ERR_DET__SHIFT 0x12
+#define GDC_RAS_LEAF5_CTRL__PARITY_ERR_DET__SHIFT 0x13
+#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_SENT__SHIFT 0x14
+#define GDC_RAS_LEAF5_CTRL__EGRESS_STALLED__SHIFT 0x15
+#define GDC_RAS_LEAF5_CTRL__POISON_DET_EN_MASK 0x00000001L
+#define GDC_RAS_LEAF5_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDC_RAS_LEAF5_CTRL__POISON_STALL_EN_MASK 0x00000004L
+#define GDC_RAS_LEAF5_CTRL__PARITY_DET_EN_MASK 0x00000010L
+#define GDC_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L
+#define GDC_RAS_LEAF5_CTRL__PARITY_STALL_EN_MASK 0x00000040L
+#define GDC_RAS_LEAF5_CTRL__LOCAL_ERR_REPORT_EN_MASK 0x00000080L
+#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_RECV_MASK 0x00010000L
+#define GDC_RAS_LEAF5_CTRL__LINK_DIS_RECV_MASK 0x00020000L
+#define GDC_RAS_LEAF5_CTRL__POISON_ERR_DET_MASK 0x00040000L
+#define GDC_RAS_LEAF5_CTRL__PARITY_ERR_DET_MASK 0x00080000L
+#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_SENT_MASK 0x00100000L
+#define GDC_RAS_LEAF5_CTRL__EGRESS_STALLED_MASK 0x00200000L
+
+
+// addressBlock: nbio_iohub_iommu_l2mmio_l2mmiocfg
+//IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_0__Reserved1__SHIFT 0x9
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_BASE_LO__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE_MASK 0x000001FFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_0__Reserved1_MASK 0x00000E00L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_BASE_LO_MASK 0xFFFFF000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_1__DEV_TBL_BASE_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_1__Reserved0__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_1__DEV_TBL_BASE_HI_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_1__Reserved0_MASK 0xFFF00000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_0__Reserved1__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_0__COM_BASE_LO__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_0__Reserved1_MASK 0x00000FFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_0__COM_BASE_LO_MASK 0xFFFFF000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1__COM_BASE_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1__Reserved1__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1__COM_LEN__SHIFT 0x18
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1__Reserved0__SHIFT 0x1c
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1__COM_BASE_HI_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1__Reserved1_MASK 0x00F00000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1__COM_LEN_MASK 0x0F000000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1__Reserved0_MASK 0xF0000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_0__Reserved1__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_0__EVENT_BASE_LO__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_0__Reserved1_MASK 0x00000FFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_0__EVENT_BASE_LO_MASK 0xFFFFF000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1__EVENT_BASE_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1__Reserved1__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1__EVENT_LEN__SHIFT 0x18
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1__Reserved0__SHIFT 0x1c
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1__EVENT_BASE_HI_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1__Reserved1_MASK 0x00F00000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1__EVENT_LEN_MASK 0x0F000000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1__Reserved0_MASK 0xF0000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__IOMMU_EN__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__HT_TUN_EN__SHIFT 0x1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__EVENT_LOG_EN__SHIFT 0x2
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__EVENT_INT_EN__SHIFT 0x3
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__COM_WAIT_INTEN__SHIFT 0x4
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__INV_TIMEOUT__SHIFT 0x5
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PASS_PW__SHIFT 0x8
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__RES_PASS_PW__SHIFT 0x9
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__COHERENT__SHIFT 0xa
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__ISOC__SHIFT 0xb
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__CMD_BUF_EN__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PPR_LOG_EN__SHIFT 0xd
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PPR_INT_EN__SHIFT 0xe
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PPR_EN__SHIFT 0xf
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GT_EN__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GA_EN__SHIFT 0x11
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__TLPT__SHIFT 0x12
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__SMIF_EN__SHIFT 0x16
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__SMIF_LOG_EN__SHIFT 0x18
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GAM_EN__SHIFT 0x19
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GA_LOG_EN__SHIFT 0x1c
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GA_INT_EN__SHIFT 0x1d
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PPRQ__SHIFT 0x1e
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__IOMMU_EN_MASK 0x00000001L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__HT_TUN_EN_MASK 0x00000002L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__EVENT_LOG_EN_MASK 0x00000004L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__EVENT_INT_EN_MASK 0x00000008L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__COM_WAIT_INTEN_MASK 0x00000010L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__INV_TIMEOUT_MASK 0x000000E0L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PASS_PW_MASK 0x00000100L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__RES_PASS_PW_MASK 0x00000200L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__COHERENT_MASK 0x00000400L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__ISOC_MASK 0x00000800L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__CMD_BUF_EN_MASK 0x00001000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PPR_LOG_EN_MASK 0x00002000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PPR_INT_EN_MASK 0x00004000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PPR_EN_MASK 0x00008000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GT_EN_MASK 0x00010000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GA_EN_MASK 0x00020000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__TLPT_MASK 0x003C0000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__SMIF_EN_MASK 0x00400000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__SMIF_LOG_EN_MASK 0x01000000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GAM_EN_MASK 0x0E000000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GA_LOG_EN_MASK 0x10000000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GA_INT_EN_MASK 0x20000000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PPRQ_MASK 0xC0000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__EVENTQ__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__DTE_SEG_EN__SHIFT 0x2
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__Reserved1__SHIFT 0x4
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__PRIV_ABORT_EN__SHIFT 0x5
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__PPR_Auto_resp_en__SHIFT 0x7
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__MARC_en__SHIFT 0x8
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__Block_StopMark_En__SHIFT 0x9
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__PPR_Auto_resp_AON__SHIFT 0xa
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__DVM_DOMAIN_PNE__SHIFT 0xb
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__DVM_ERR_EN__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__EPH_EN__SHIFT 0xd
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__HW_Prefetch_AD__SHIFT 0xe
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__V2_HD_Dis__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__Reserved0__SHIFT 0x11
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__EVENTQ_MASK 0x00000003L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__DTE_SEG_EN_MASK 0x0000000CL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__Reserved1_MASK 0x00000010L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__PRIV_ABORT_EN_MASK 0x00000060L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__PPR_Auto_resp_en_MASK 0x00000080L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__MARC_en_MASK 0x00000100L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__Block_StopMark_En_MASK 0x00000200L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__PPR_Auto_resp_AON_MASK 0x00000400L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__DVM_DOMAIN_PNE_MASK 0x00000800L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__DVM_ERR_EN_MASK 0x00001000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__EPH_EN_MASK 0x00002000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__HW_Prefetch_AD_MASK 0x0000C000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__V2_HD_Dis_MASK 0x00010000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__Reserved0_MASK 0xFFFE0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0__EX_EN__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW__SHIFT 0x1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0__Reserved0__SHIFT 0x2
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0__EX_EN_MASK 0x00000001L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW_MASK 0x00000002L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0__Reserved0_MASK 0x00000FFCL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO_MASK 0xFFFFF000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_1__Reserved0__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_1__Reserved0_MASK 0xFFF00000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_0__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_0__Reserved0_MASK 0x00000FFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO_MASK 0xFFFFF000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_1__Reserved0__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_1__Reserved0_MASK 0xFFF00000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__PREF_SUP__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__PPR_SUP__SHIFT 0x1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__XT_SUP__SHIFT 0x2
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__NX_SUP__SHIFT 0x3
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GT_SUP__SHIFT 0x4
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__Reserved__SHIFT 0x5
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__IA_SUP__SHIFT 0x6
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GA_SUP__SHIFT 0x7
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__HE_SUP__SHIFT 0x8
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__PC_SUP__SHIFT 0x9
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__HATS__SHIFT 0xa
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GATS__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GLX_SUP__SHIFT 0xe
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__SMIF_SUP__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__SMIF_RC__SHIFT 0x12
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GAM_SUP__SHIFT 0x15
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__PPRF__SHIFT 0x18
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GAF__SHIFT 0x1a
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__EVENTF__SHIFT 0x1c
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__DVM_ERR_SUP__SHIFT 0x1e
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__Reserved1__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__PREF_SUP_MASK 0x00000001L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__PPR_SUP_MASK 0x00000002L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__XT_SUP_MASK 0x00000004L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__NX_SUP_MASK 0x00000008L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GT_SUP_MASK 0x00000010L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__Reserved_MASK 0x00000020L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__IA_SUP_MASK 0x00000040L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GA_SUP_MASK 0x00000080L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__HE_SUP_MASK 0x00000100L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__PC_SUP_MASK 0x00000200L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__HATS_MASK 0x00000C00L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GATS_MASK 0x00003000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GLX_SUP_MASK 0x0000C000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__SMIF_SUP_MASK 0x00030000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__SMIF_RC_MASK 0x001C0000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GAM_SUP_MASK 0x00E00000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__PPRF_MASK 0x03000000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GAF_MASK 0x0C000000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__EVENTF_MASK 0x30000000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__DVM_ERR_SUP_MASK 0x40000000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__Reserved1_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__PAS_MAX__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__Reserved1__SHIFT 0x4
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__US_SUP__SHIFT 0x5
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__DTE_seg__SHIFT 0x6
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__PPR_OVERFLOW_EARLY_SUP__SHIFT 0x8
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__PPR_AUTORESP_SUP__SHIFT 0x9
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__MARCnum__SHIFT 0xa
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__BLOCK_STOPMARK_SUP__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__GMC_IOMMU_BYPASS_SUP__SHIFT 0xd
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__MMIO_MSI_CAP_SUP__SHIFT 0xe
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__SNOOP_ATTRS_SUP__SHIFT 0xf
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__GIo_SUP__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__HA_SUP__SHIFT 0x11
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__EPH_SUP__SHIFT 0x12
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__ATTRFW_SUP__SHIFT 0x13
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__HD_SUP__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__V2_HD_DIS_SUP__SHIFT 0x15
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__InvIotlbTypeSup__SHIFT 0x16
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__Reserved0__SHIFT 0x17
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__PAS_MAX_MASK 0x0000000FL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__Reserved1_MASK 0x00000010L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__US_SUP_MASK 0x00000020L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__DTE_seg_MASK 0x000000C0L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__PPR_OVERFLOW_EARLY_SUP_MASK 0x00000100L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__PPR_AUTORESP_SUP_MASK 0x00000200L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__MARCnum_MASK 0x00000C00L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__BLOCK_STOPMARK_SUP_MASK 0x00001000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__GMC_IOMMU_BYPASS_SUP_MASK 0x00002000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__MMIO_MSI_CAP_SUP_MASK 0x00004000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__SNOOP_ATTRS_SUP_MASK 0x00008000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__GIo_SUP_MASK 0x00010000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__HA_SUP_MASK 0x00020000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__EPH_SUP_MASK 0x00040000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__ATTRFW_SUP_MASK 0x00080000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__HD_SUP_MASK 0x00100000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__V2_HD_DIS_SUP_MASK 0x00200000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__InvIotlbTypeSup_MASK 0x00400000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__Reserved0_MASK 0xFF800000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_0__Reserved1__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_0__PPR_BASE_LO__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_0__Reserved1_MASK 0x00000FFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_0__PPR_BASE_LO_MASK 0xFFFFF000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1__PPR_BASE_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1__Reserved1__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1__PPR_LEN__SHIFT 0x18
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1__Reserved0__SHIFT 0x1c
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1__PPR_BASE_HI_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1__Reserved1_MASK 0x00F00000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1__PPR_LEN_MASK 0x0F000000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1__Reserved0_MASK 0xF0000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_0__FIRST_EV_CODE_LO__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_0__FIRST_EV_CODE_LO_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_1__FIRST_EV_CODE_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_1__EV_CODE__SHIFT 0x1c
+#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_1__FIRST_EV_CODE_HI_MASK 0x0FFFFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_1__EV_CODE_MASK 0xF0000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_LOWER_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_LOWER_0__SECOND_EV_CODE_LO__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_LOWER_0__SECOND_EV_CODE_LO_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_LOWER_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_LOWER_1__SECOND_EV_CODE_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_LOWER_1__SECOND_EV_CODE_HI_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_0__HEV__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_0__HEO__SHIFT 0x1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_0__Reserved__SHIFT 0x2
+#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_0__HEV_MASK 0x00000001L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_0__HEO_MASK 0x00000002L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_0__Reserved_MASK 0xFFFFFFFCL
+//IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_1__Reserved__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_1__Reserved_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0__SmiDID_0__SHIFT 0x0
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0__SmiDV_0__SHIFT 0x10
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0__SmiFLock_0__SHIFT 0x11
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0__Reserved__SHIFT 0x12
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0__SmiDID_0_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0__SmiDV_0_MASK 0x00010000L
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0__SmiFLock_0_MASK 0x00020000L
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0__Reserved_MASK 0xFFFC0000L
+//IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_1
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_1__Reserved__SHIFT 0x0
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_1__Reserved_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0__SmiDID_1__SHIFT 0x0
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0__SmiDV_1__SHIFT 0x10
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0__SmiFLock_1__SHIFT 0x11
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0__Reserved__SHIFT 0x12
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0__SmiDID_1_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0__SmiDV_1_MASK 0x00010000L
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0__SmiFLock_1_MASK 0x00020000L
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0__Reserved_MASK 0xFFFC0000L
+//IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_1
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_1__Reserved__SHIFT 0x0
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_1__Reserved_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0__SmiDID_2__SHIFT 0x0
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0__SmiDV_2__SHIFT 0x10
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0__SmiFLock_2__SHIFT 0x11
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0__Reserved__SHIFT 0x12
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0__SmiDID_2_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0__SmiDV_2_MASK 0x00010000L
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0__SmiFLock_2_MASK 0x00020000L
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0__Reserved_MASK 0xFFFC0000L
+//IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_1
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_1__Reserved__SHIFT 0x0
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_1__Reserved_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0__SmiDID_3__SHIFT 0x0
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0__SmiDV_3__SHIFT 0x10
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0__SmiFLock_3__SHIFT 0x11
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0__Reserved__SHIFT 0x12
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0__SmiDID_3_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0__SmiDV_3_MASK 0x00010000L
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0__SmiFLock_3_MASK 0x00020000L
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0__Reserved_MASK 0xFFFC0000L
+//IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_1
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_1__Reserved__SHIFT 0x0
+#define IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_1__Reserved_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_0__GA_LOG_BASE_LO__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_0__GA_LOG_BASE_LO_MASK 0xFFFFF000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_1__GA_LOG_BASE_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_1__GA_LOG_LEN__SHIFT 0x18
+#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_1__GA_LOG_BASE_HI_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_1__GA_LOG_LEN_MASK 0x0F000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0__GA_LOG_TAILPTR_ADDR_LO__SHIFT 0x3
+#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0__GA_LOG_TAILPTR_ADDR_LO_MASK 0xFFFFFFF8L
+//IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1__GA_LOG_TAILPTR_ADDR_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1__GA_LOG_TAILPTR_ADDR_HI_MASK 0x000FFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_0__Reserved1__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_0__PPR_B_BASE_LO__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_0__Reserved1_MASK 0x00000FFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_0__PPR_B_BASE_LO_MASK 0xFFFFF000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1__PPR_B_BASE_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1__Reserved1__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1__PPR_B_LEN__SHIFT 0x18
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1__Reserved0__SHIFT 0x1c
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1__PPR_B_BASE_HI_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1__Reserved1_MASK 0x00F00000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1__PPR_B_LEN_MASK 0x0F000000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1__Reserved0_MASK 0xF0000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_0__Reserved1__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_0__EVENT_B_BASE_LO__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_0__Reserved1_MASK 0x00000FFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_0__EVENT_B_BASE_LO_MASK 0xFFFFF000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1__EVENT_B_BASE_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1__Reserved1__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1__EVENT_B_LEN__SHIFT 0x18
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1__Reserved0__SHIFT 0x1c
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1__EVENT_B_BASE_HI_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1__Reserved1_MASK 0x00F00000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1__EVENT_B_LEN_MASK 0x0F000000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1__Reserved0_MASK 0xF0000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_0__Reserved1__SHIFT 0x9
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_BASE_LO__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE_MASK 0x000001FFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_0__Reserved1_MASK 0x00000E00L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_BASE_LO_MASK 0xFFFFF000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_1__DEV_TBL_1_BASE_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_1__Reserved0__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_1__DEV_TBL_1_BASE_HI_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_1__Reserved0_MASK 0xFFF00000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_0__Reserved1__SHIFT 0x9
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_BASE_LO__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE_MASK 0x000001FFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_0__Reserved1_MASK 0x00000E00L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_BASE_LO_MASK 0xFFFFF000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_1__DEV_TBL_2_BASE_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_1__Reserved0__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_1__DEV_TBL_2_BASE_HI_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_1__Reserved0_MASK 0xFFF00000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_0__Reserved1__SHIFT 0x9
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_BASE_LO__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE_MASK 0x000001FFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_0__Reserved1_MASK 0x00000E00L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_BASE_LO_MASK 0xFFFFF000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_1__DEV_TBL_3_BASE_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_1__Reserved0__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_1__DEV_TBL_3_BASE_HI_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_1__Reserved0_MASK 0xFFF00000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_0__Reserved1__SHIFT 0x9
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_BASE_LO__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE_MASK 0x000001FFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_0__Reserved1_MASK 0x00000E00L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_BASE_LO_MASK 0xFFFFF000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_1__DEV_TBL_4_BASE_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_1__Reserved0__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_1__DEV_TBL_4_BASE_HI_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_1__Reserved0_MASK 0xFFF00000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_0__Reserved1__SHIFT 0x9
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_BASE_LO__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE_MASK 0x000001FFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_0__Reserved1_MASK 0x00000E00L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_BASE_LO_MASK 0xFFFFF000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_1__DEV_TBL_5_BASE_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_1__Reserved0__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_1__DEV_TBL_5_BASE_HI_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_1__Reserved0_MASK 0xFFF00000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_0__Reserved1__SHIFT 0x9
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_BASE_LO__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE_MASK 0x000001FFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_0__Reserved1_MASK 0x00000E00L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_BASE_LO_MASK 0xFFFFF000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_1__DEV_TBL_6_BASE_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_1__Reserved0__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_1__DEV_TBL_6_BASE_HI_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_1__Reserved0_MASK 0xFFF00000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_0__Reserved1__SHIFT 0x9
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_BASE_LO__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE_MASK 0x000001FFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_0__Reserved1_MASK 0x00000E00L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_BASE_LO_MASK 0xFFFFF000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_1__DEV_TBL_7_BASE_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_1__Reserved0__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_1__DEV_TBL_7_BASE_HI_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_1__Reserved0_MASK 0xFFF00000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DSFX
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DSFX__DSFXSup__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DSFX__REVISION_MINOR__SHIFT 0x18
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DSFX__REVISION_MAJOR__SHIFT 0x1c
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DSFX__DSFXSup_MASK 0x00FFFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DSFX__REVISION_MINOR_MASK 0x0F000000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DSFX__REVISION_MAJOR_MASK 0xF0000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DSCX
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DSCX__DSCX_CNTRL__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DSCX__REVISION_MINOR__SHIFT 0x18
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DSCX__REVISION_MAJOR__SHIFT 0x1c
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DSCX__DSCX_CNTRL_MASK 0x00FFFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DSCX__REVISION_MINOR_MASK 0x0F000000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DSCX__REVISION_MAJOR_MASK 0xF0000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DSSX
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DSSX__DSSX_status__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DSSX__REVISION_MINOR__SHIFT 0x18
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DSSX__REVISION_MAJOR__SHIFT 0x1c
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DSSX__DSSX_status_MASK 0x00FFFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DSSX__REVISION_MINOR_MASK 0x0F000000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DSSX__REVISION_MAJOR_MASK 0xF0000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC__IOMMU_MSI_NUM__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC__Reserved1__SHIFT 0x5
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC__IOMMU_MSI_NUM_PPR__SHIFT 0x1b
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC__IOMMU_MSI_NUM_MASK 0x0000001FL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC__Reserved1_MASK 0x07FFFFE0L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC__IOMMU_MSI_NUM_PPR_MASK 0xF8000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC_1__IOMMU_MSI_NUM_GA__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC_1__Reserved__SHIFT 0x5
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC_1__IOMMU_MSI_NUM_GA_MASK 0x0000001FL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC_1__Reserved_MASK 0xFFFFFFE0L
+//IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_CAP_ID__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_CAP_PTR__SHIFT 0x8
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_EN__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_MULT_MESS_CAP__SHIFT 0x11
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_MULT_MESS_EN__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_64_EN__SHIFT 0x17
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__Reserved__SHIFT 0x18
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_CAP_ID_MASK 0x000000FFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_CAP_PTR_MASK 0x0000FF00L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_EN_MASK 0x00010000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_MULT_MESS_CAP_MASK 0x000E0000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_MULT_MESS_EN_MASK 0x00700000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_64_EN_MASK 0x00800000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__Reserved_MASK 0xFF000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_LO
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_LO__Reserved__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_LO__MSI_ADDR_LO__SHIFT 0x2
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_LO__Reserved_MASK 0x00000003L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_LO__MSI_ADDR_LO_MASK 0xFFFFFFFCL
+//IOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_HI
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_HI__MSI_ADDR_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_HI__MSI_ADDR_HI_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_MSI_DATA
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_DATA__MSI_DATA__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_DATA__Reserved__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_DATA__MSI_DATA_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_DATA__Reserved_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_ID__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR__SHIFT 0x8
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_EN__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_FIXD__SHIFT 0x11
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_RSV__SHIFT 0x12
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE__SHIFT 0x1b
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_ID_MASK 0x000000FFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR_MASK 0x0000FF00L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_EN_MASK 0x00010000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_FIXD_MASK 0x00020000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_RSV_MASK 0x07FC0000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE_MASK 0xF8000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_CONTROL_W
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CONTROL_W__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CONTROL_W__GMC_IOMMU_BYPASS__SHIFT 0xd
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CONTROL_W__Reserved1__SHIFT 0xe
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CONTROL_W__Reserved0_MASK 0x00001FFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CONTROL_W__GMC_IOMMU_BYPASS_MASK 0x00002000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CONTROL_W__Reserved1_MASK 0xFFFFC000L
+//IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_0
+#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_0__Reserved__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_0__MARCBaseAddr_L_0__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_0__Reserved_MASK 0x00000FFFL
+#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_0__MARCBaseAddr_L_0_MASK 0xFFFFF000L
+//IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_0
+#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_0__MARCBaseAddr_H_0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_0__Reserved__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_0__MARCBaseAddr_H_0_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_0__Reserved_MASK 0xFFF00000L
+//IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0__MARCEnable_0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0__MARCReadOnly_0__SHIFT 0x1
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0__Reserved__SHIFT 0x2
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0__MARCRelocAddr_L_0__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0__MARCEnable_0_MASK 0x00000001L
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0__MARCReadOnly_0_MASK 0x00000002L
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0__Reserved_MASK 0x00000FFCL
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0__MARCRelocAddr_L_0_MASK 0xFFFFF000L
+//IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_0
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_0__MARCRelocAddr_H_0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_0__Reserved__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_0__MARCRelocAddr_H_0_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_0__Reserved_MASK 0xFFF00000L
+//IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_0
+#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_0__Reserved__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_0__MARCLen_L_0__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_0__Reserved_MASK 0x00000FFFL
+#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_0__MARCLen_L_0_MASK 0xFFFFF000L
+//IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_0
+#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_0__MARCLen_H_0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_0__Reserved__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_0__MARCLen_H_0_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_0__Reserved_MASK 0xFFF00000L
+//IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_1
+#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_1__Reserved__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_1__MARCBaseAddr_L_1__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_1__Reserved_MASK 0x00000FFFL
+#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_1__MARCBaseAddr_L_1_MASK 0xFFFFF000L
+//IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_1
+#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_1__MARCBaseAddr_H_1__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_1__Reserved__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_1__MARCBaseAddr_H_1_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_1__Reserved_MASK 0xFFF00000L
+//IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1__MARCEnable_1__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1__MARCReadOnly_1__SHIFT 0x1
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1__Reserved__SHIFT 0x2
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1__MARCRelocAddr_L_1__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1__MARCEnable_1_MASK 0x00000001L
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1__MARCReadOnly_1_MASK 0x00000002L
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1__Reserved_MASK 0x00000FFCL
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1__MARCRelocAddr_L_1_MASK 0xFFFFF000L
+//IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_1
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_1__MARCRelocAddr_H_1__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_1__Reserved__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_1__MARCRelocAddr_H_1_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_1__Reserved_MASK 0xFFF00000L
+//IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_1
+#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_1__Reserved__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_1__MARCLen_L_1__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_1__Reserved_MASK 0x00000FFFL
+#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_1__MARCLen_L_1_MASK 0xFFFFF000L
+//IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_1
+#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_1__MARCLen_H_1__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_1__Reserved__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_1__MARCLen_H_1_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_1__Reserved_MASK 0xFFF00000L
+//IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_2
+#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_2__Reserved__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_2__MARCBaseAddr_L_2__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_2__Reserved_MASK 0x00000FFFL
+#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_2__MARCBaseAddr_L_2_MASK 0xFFFFF000L
+//IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_2
+#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_2__MARCBaseAddr_H_2__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_2__Reserved__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_2__MARCBaseAddr_H_2_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_2__Reserved_MASK 0xFFF00000L
+//IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2__MARCEnable_2__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2__MARCReadOnly_2__SHIFT 0x1
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2__Reserved__SHIFT 0x2
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2__MARCRelocAddr_L_2__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2__MARCEnable_2_MASK 0x00000001L
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2__MARCReadOnly_2_MASK 0x00000002L
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2__Reserved_MASK 0x00000FFCL
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2__MARCRelocAddr_L_2_MASK 0xFFFFF000L
+//IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_2
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_2__MARCRelocAddr_H_2__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_2__Reserved__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_2__MARCRelocAddr_H_2_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_2__Reserved_MASK 0xFFF00000L
+//IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_2
+#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_2__Reserved__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_2__MARCLen_L_2__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_2__Reserved_MASK 0x00000FFFL
+#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_2__MARCLen_L_2_MASK 0xFFFFF000L
+//IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_2
+#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_2__MARCLen_H_2__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_2__Reserved__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_2__MARCLen_H_2_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_2__Reserved_MASK 0xFFF00000L
+//IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_3
+#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_3__Reserved__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_3__MARCBaseAddr_L_3__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_3__Reserved_MASK 0x00000FFFL
+#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_3__MARCBaseAddr_L_3_MASK 0xFFFFF000L
+//IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_3
+#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_3__MARCBaseAddr_H_3__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_3__Reserved__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_3__MARCBaseAddr_H_3_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_3__Reserved_MASK 0xFFF00000L
+//IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3__MARCEnable_3__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3__MARCReadOnly_3__SHIFT 0x1
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3__Reserved__SHIFT 0x2
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3__MARCRelocAddr_L_3__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3__MARCEnable_3_MASK 0x00000001L
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3__MARCReadOnly_3_MASK 0x00000002L
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3__Reserved_MASK 0x00000FFCL
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3__MARCRelocAddr_L_3_MASK 0xFFFFF000L
+//IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_3
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_3__MARCRelocAddr_H_3__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_3__Reserved__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_3__MARCRelocAddr_H_3_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_3__Reserved_MASK 0xFFF00000L
+//IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_3
+#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_3__Reserved__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_3__MARCLen_L_3__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_3__Reserved_MASK 0x00000FFFL
+#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_3__MARCLen_L_3_MASK 0xFFFFF000L
+//IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_3
+#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_3__MARCLen_H_3__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_3__Reserved__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_3__MARCLen_H_3_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_3__Reserved_MASK 0xFFF00000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_0__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_0__CMD_HDPTR__SHIFT 0x4
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_0__Reserved1__SHIFT 0x13
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_0__Reserved0_MASK 0x0000000FL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_0__CMD_HDPTR_MASK 0x0007FFF0L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_0__Reserved1_MASK 0xFFF80000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_1__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_0__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_0__CMD_TAILPTR__SHIFT 0x4
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_0__Reserved1__SHIFT 0x13
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_0__Reserved0_MASK 0x0000000FL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_0__CMD_TAILPTR_MASK 0x0007FFF0L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_0__Reserved1_MASK 0xFFF80000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_1__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_0__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_0__EVENT_HDPTR__SHIFT 0x4
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_0__Reserved1__SHIFT 0x13
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_0__Reserved0_MASK 0x0000000FL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_0__EVENT_HDPTR_MASK 0x0007FFF0L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_0__Reserved1_MASK 0xFFF80000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_1__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_0__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_0__EVENT_TAILPTR__SHIFT 0x4
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_0__Reserved1__SHIFT 0x13
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_0__Reserved0_MASK 0x0000000FL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_0__EVENT_TAILPTR_MASK 0x0007FFF0L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_0__Reserved1_MASK 0xFFF80000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_1__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_OVERFLOW__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_LOGINT__SHIFT 0x1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__COMWAIT_INT__SHIFT 0x2
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_LOGRUN__SHIFT 0x3
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__CMD_BUFRUN__SHIFT 0x4
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_OVERFLOW__SHIFT 0x5
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_INT__SHIFT 0x6
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_RUN__SHIFT 0x7
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__GA_RUN__SHIFT 0x8
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__GA_OVERFLOW__SHIFT 0x9
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__GA_INT__SHIFT 0xa
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_B_OVERFLOW__SHIFT 0xb
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_BUF_ACTIVE__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__Reserved0__SHIFT 0xd
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_B_OVERFLOW__SHIFT 0xf
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_BUF_ACTIVE__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_B_OVERFLOW_EARLY__SHIFT 0x11
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_OVERFLOW_EARLY__SHIFT 0x12
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__Reserved1__SHIFT 0x13
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_OVERFLOW_MASK 0x00000001L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_LOGINT_MASK 0x00000002L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__COMWAIT_INT_MASK 0x00000004L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_LOGRUN_MASK 0x00000008L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__CMD_BUFRUN_MASK 0x00000010L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_OVERFLOW_MASK 0x00000020L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_INT_MASK 0x00000040L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_RUN_MASK 0x00000080L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__GA_RUN_MASK 0x00000100L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__GA_OVERFLOW_MASK 0x00000200L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__GA_INT_MASK 0x00000400L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_B_OVERFLOW_MASK 0x00000800L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_BUF_ACTIVE_MASK 0x00001000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__Reserved0_MASK 0x00006000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_B_OVERFLOW_MASK 0x00008000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_BUF_ACTIVE_MASK 0x00010000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_B_OVERFLOW_EARLY_MASK 0x00020000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_OVERFLOW_EARLY_MASK 0x00040000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__Reserved1_MASK 0xFFF80000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_1__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_0__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_0__PPR_HDPTR__SHIFT 0x4
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_0__Reserved1__SHIFT 0x13
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_0__Reserved0_MASK 0x0000000FL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_0__PPR_HDPTR_MASK 0x0007FFF0L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_0__Reserved1_MASK 0xFFF80000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_1__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_0__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_0__PPR_TAILPTR__SHIFT 0x4
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_0__Reserved1__SHIFT 0x13
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_0__Reserved0_MASK 0x0000000FL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_0__PPR_TAILPTR_MASK 0x0007FFF0L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_0__Reserved1_MASK 0xFFF80000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_1__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_0__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_0__GA_HDPTR__SHIFT 0x3
+#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_0__Reserved1__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_0__Reserved0_MASK 0x00000007L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_0__GA_HDPTR_MASK 0x0000FFF8L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_0__Reserved1_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_1__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_0__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_0__GA_TAILPTR__SHIFT 0x3
+#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_0__Reserved1__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_0__Reserved0_MASK 0x00000007L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_0__GA_TAILPTR_MASK 0x0000FFF8L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_0__Reserved1_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_1__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_0__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_0__PPR_B_HDPTR__SHIFT 0x4
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_0__Reserved1__SHIFT 0x13
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_0__Reserved0_MASK 0x0000000FL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_0__PPR_B_HDPTR_MASK 0x0007FFF0L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_0__Reserved1_MASK 0xFFF80000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_1__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__PPR_B_TAILPTR__SHIFT 0x4
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__Reserved1__SHIFT 0x13
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__Reserved0_MASK 0x0000000FL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__PPR_B_TAILPTR_MASK 0x0007FFF0L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__Reserved1_MASK 0xFFF80000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_1__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__EVENT_B_HDPTR__SHIFT 0x4
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__Reserved1__SHIFT 0x13
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__Reserved0_MASK 0x0000000FL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__EVENT_B_HDPTR_MASK 0x0007FFF0L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__Reserved1_MASK 0xFFF80000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_1__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__EVENT_B_TAILPTR__SHIFT 0x4
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__Reserved1__SHIFT 0x13
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__Reserved0_MASK 0x0000000FL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__EVENT_B_TAILPTR_MASK 0x0007FFF0L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__Reserved1_MASK 0xFFF80000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_1__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_PPR_AUTORESP_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_AUTORESP_0__PPR_Auto_resp_code__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_AUTORESP_0__PPR_Auto_resp_mask_gn__SHIFT 0x4
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_AUTORESP_0__Reserved0__SHIFT 0x5
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_AUTORESP_0__PPR_Auto_resp_code_MASK 0x0000000FL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_AUTORESP_0__PPR_Auto_resp_mask_gn_MASK 0x00000010L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_AUTORESP_0__Reserved0_MASK 0xFFFFFFE0L
+//IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_threshold__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__Reserved0__SHIFT 0xf
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_int_en__SHIFT 0x1e
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_en__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_threshold_MASK 0x00007FFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__Reserved0_MASK 0x3FFF8000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_int_en_MASK 0x40000000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_en_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_threshold__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__Reserved0__SHIFT 0xf
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_int_en__SHIFT 0x1e
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_en__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_threshold_MASK 0x00007FFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__Reserved0_MASK 0x3FFF8000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_int_en_MASK 0x40000000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_en_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__N_COUNTER__SHIFT 0x7
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__Reserved1__SHIFT 0xb
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__N_COUNTER_BANKS__SHIFT 0xc
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__Reserved2__SHIFT 0x12
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__Reserved0_MASK 0x0000007FL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__N_COUNTER_MASK 0x00000780L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__Reserved1_MASK 0x00000800L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__N_COUNTER_BANKS_MASK 0x0003F000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__Reserved2_MASK 0xFFFC0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_1__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0__PASID_LOCK_LO__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0__PASID_LOCK_LO_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1__PASID_LOCK_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1__PASID_LOCK_HI_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0__DOMAIN_LOCK_LO__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0__DOMAIN_LOCK_LO_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1__DOMAIN_LOCK_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1__DOMAIN_LOCK_HI_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0__DEVID_LOCK_LO__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0__DEVID_LOCK_LO_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1__DEVID_LOCK_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1__DEVID_LOCK_HI_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_0__ICOUNTER_0_0_LO__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_0__ICOUNTER_0_0_LO_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1__ICOUNTER_0_0_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1__Reserved__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1__ICOUNTER_0_0_HI_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1__Reserved_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CSOURCE_0_0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__Reserved1__SHIFT 0x8
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__COUNT_UNITS_0_0__SHIFT 0x1e
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CAC_0_0__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CSOURCE_0_0_MASK 0x000000FFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__Reserved1_MASK 0x3FFFFF00L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__COUNT_UNITS_0_0_MASK 0x40000000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CAC_0_0_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASID_MATCH_0_0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASMEN_0_0__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASID_MATCH_0_0_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASMEN_0_0_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__PASID_MASK_0_0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__PASID_MASK_0_0_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMAIN_MATCH_0_0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMMEN_0_0__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMAIN_MATCH_0_0_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMMEN_0_0_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__DOMAIN_MASK_0_0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__DOMAIN_MASK_0_0_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DEVICEID_MATCH_0_0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DIDMEN_0_0__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DEVICEID_MATCH_0_0_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DIDMEN_0_0_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__DEVICEID_MASK_0_0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__DEVICEID_MASK_0_0_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0__EVENT_NOTE_0_0_LO__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0__EVENT_NOTE_0_0_LO_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__EVENT_NOTE_0_0_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__Reserved0__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__CERE_0_0__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__EVENT_NOTE_0_0_HI_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__Reserved0_MASK 0x7FF00000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__CERE_0_0_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_0__ICOUNTER_0_1_LO__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_0__ICOUNTER_0_1_LO_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1__ICOUNTER_0_1_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1__Reserved__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1__ICOUNTER_0_1_HI_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1__Reserved_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CSOURCE_0_1__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__Reserved1__SHIFT 0x8
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__COUNT_UNITS_0_1__SHIFT 0x1e
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CAC_0_1__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CSOURCE_0_1_MASK 0x000000FFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__Reserved1_MASK 0x3FFFFF00L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__COUNT_UNITS_0_1_MASK 0x40000000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CAC_0_1_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASID_MATCH_0_1__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASMEN_0_1__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASID_MATCH_0_1_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASMEN_0_1_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__PASID_MASK_0_1__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__PASID_MASK_0_1_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMAIN_MATCH_0_1__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMMEN_0_1__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMAIN_MATCH_0_1_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMMEN_0_1_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__DOMAIN_MASK_0_1__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__DOMAIN_MASK_0_1_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DEVICEID_MATCH_0_1__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DIDMEN_0_1__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DEVICEID_MATCH_0_1_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DIDMEN_0_1_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__DEVICEID_MASK_0_1__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__DEVICEID_MASK_0_1_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0__EVENT_NOTE_0_1_LO__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0__EVENT_NOTE_0_1_LO_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__EVENT_NOTE_0_1_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__Reserved0__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__CERE_0_1__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__EVENT_NOTE_0_1_HI_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__Reserved0_MASK 0x7FF00000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__CERE_0_1_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_0__ICOUNTER_0_2_LO__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_0__ICOUNTER_0_2_LO_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1__ICOUNTER_0_2_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1__Reserved__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1__ICOUNTER_0_2_HI_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1__Reserved_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CSOURCE_0_2__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__Reserved1__SHIFT 0x8
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__COUNT_UNITS_0_2__SHIFT 0x1e
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CAC_0_2__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CSOURCE_0_2_MASK 0x000000FFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__Reserved1_MASK 0x3FFFFF00L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__COUNT_UNITS_0_2_MASK 0x40000000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CAC_0_2_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASID_MATCH_0_2__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASMEN_0_2__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASID_MATCH_0_2_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASMEN_0_2_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__PASID_MASK_0_2__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__PASID_MASK_0_2_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMAIN_MATCH_0_2__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMMEN_0_2__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMAIN_MATCH_0_2_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMMEN_0_2_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__DOMAIN_MASK_0_2__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__DOMAIN_MASK_0_2_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DEVICEID_MATCH_0_2__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DIDMEN_0_2__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DEVICEID_MATCH_0_2_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DIDMEN_0_2_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__DEVICEID_MASK_0_2__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__DEVICEID_MASK_0_2_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0__EVENT_NOTE_0_2_LO__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0__EVENT_NOTE_0_2_LO_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__EVENT_NOTE_0_2_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__Reserved0__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__CERE_0_2__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__EVENT_NOTE_0_2_HI_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__Reserved0_MASK 0x7FF00000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__CERE_0_2_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_0__ICOUNTER_0_3_LO__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_0__ICOUNTER_0_3_LO_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1__ICOUNTER_0_3_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1__Reserved__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1__ICOUNTER_0_3_HI_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1__Reserved_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CSOURCE_0_3__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__Reserved1__SHIFT 0x8
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__COUNT_UNITS_0_3__SHIFT 0x1e
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CAC_0_3__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CSOURCE_0_3_MASK 0x000000FFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__Reserved1_MASK 0x3FFFFF00L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__COUNT_UNITS_0_3_MASK 0x40000000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CAC_0_3_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASID_MATCH_0_3__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASMEN_0_3__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASID_MATCH_0_3_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASMEN_0_3_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__PASID_MASK_0_3__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__PASID_MASK_0_3_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMAIN_MATCH_0_3__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMMEN_0_3__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMAIN_MATCH_0_3_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMMEN_0_3_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__DOMAIN_MASK_0_3__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__DOMAIN_MASK_0_3_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DEVICEID_MATCH_0_3__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DIDMEN_0_3__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DEVICEID_MATCH_0_3_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DIDMEN_0_3_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__DEVICEID_MASK_0_3__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__DEVICEID_MASK_0_3_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0__EVENT_NOTE_0_3_LO__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0__EVENT_NOTE_0_3_LO_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__EVENT_NOTE_0_3_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__Reserved0__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__CERE_0_3__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__EVENT_NOTE_0_3_HI_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__Reserved0_MASK 0x7FF00000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__CERE_0_3_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_0__ICOUNTER_1_0_LO__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_0__ICOUNTER_1_0_LO_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1__ICOUNTER_1_0_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1__Reserved__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1__ICOUNTER_1_0_HI_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1__Reserved_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CSOURCE_1_0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__Reserved1__SHIFT 0x8
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__COUNT_UNITS_1_0__SHIFT 0x1e
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CAC_1_0__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CSOURCE_1_0_MASK 0x000000FFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__Reserved1_MASK 0x3FFFFF00L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__COUNT_UNITS_1_0_MASK 0x40000000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CAC_1_0_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASID_MATCH_1_0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASMEN_1_0__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASID_MATCH_1_0_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASMEN_1_0_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__PASID_MASK_1_0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__PASID_MASK_1_0_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMAIN_MATCH_1_0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMMEN_1_0__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMAIN_MATCH_1_0_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMMEN_1_0_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__DOMAIN_MASK_1_0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__DOMAIN_MASK_1_0_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DEVICEID_MATCH_1_0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DIDMEN_1_0__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DEVICEID_MATCH_1_0_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DIDMEN_1_0_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__DEVICEID_MASK_1_0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__DEVICEID_MASK_1_0_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0__EVENT_NOTE_1_0_LO__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0__EVENT_NOTE_1_0_LO_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__EVENT_NOTE_1_0_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__Reserved0__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__CERE_1_0__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__EVENT_NOTE_1_0_HI_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__Reserved0_MASK 0x7FF00000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__CERE_1_0_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_0__ICOUNTER_1_1_LO__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_0__ICOUNTER_1_1_LO_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1__ICOUNTER_1_1_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1__Reserved__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1__ICOUNTER_1_1_HI_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1__Reserved_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CSOURCE_1_1__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__Reserved1__SHIFT 0x8
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__COUNT_UNITS_1_1__SHIFT 0x1e
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CAC_1_1__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CSOURCE_1_1_MASK 0x000000FFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__Reserved1_MASK 0x3FFFFF00L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__COUNT_UNITS_1_1_MASK 0x40000000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CAC_1_1_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASID_MATCH_1_1__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASMEN_1_1__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASID_MATCH_1_1_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASMEN_1_1_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__PASID_MASK_1_1__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__PASID_MASK_1_1_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMAIN_MATCH_1_1__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMMEN_1_1__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMAIN_MATCH_1_1_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMMEN_1_1_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__DOMAIN_MASK_1_1__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__DOMAIN_MASK_1_1_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DEVICEID_MATCH_1_1__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DIDMEN_1_1__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DEVICEID_MATCH_1_1_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DIDMEN_1_1_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__DEVICEID_MASK_1_1__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__DEVICEID_MASK_1_1_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0__EVENT_NOTE_1_1_LO__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0__EVENT_NOTE_1_1_LO_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__EVENT_NOTE_1_1_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__Reserved0__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__CERE_1_1__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__EVENT_NOTE_1_1_HI_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__Reserved0_MASK 0x7FF00000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__CERE_1_1_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_0__ICOUNTER_1_2_LO__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_0__ICOUNTER_1_2_LO_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1__ICOUNTER_1_2_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1__Reserved__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1__ICOUNTER_1_2_HI_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1__Reserved_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CSOURCE_1_2__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__Reserved1__SHIFT 0x8
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__COUNT_UNITS_1_2__SHIFT 0x1e
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CAC_1_2__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CSOURCE_1_2_MASK 0x000000FFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__Reserved1_MASK 0x3FFFFF00L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__COUNT_UNITS_1_2_MASK 0x40000000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CAC_1_2_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASID_MATCH_1_2__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASMEN_1_2__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASID_MATCH_1_2_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASMEN_1_2_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__PASID_MASK_1_2__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__PASID_MASK_1_2_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMAIN_MATCH_1_2__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMMEN_1_2__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMAIN_MATCH_1_2_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMMEN_1_2_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__DOMAIN_MASK_1_2__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__DOMAIN_MASK_1_2_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DEVICEID_MATCH_1_2__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DIDMEN_1_2__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DEVICEID_MATCH_1_2_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DIDMEN_1_2_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__DEVICEID_MASK_1_2__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__DEVICEID_MASK_1_2_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0__EVENT_NOTE_1_2_LO__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0__EVENT_NOTE_1_2_LO_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__EVENT_NOTE_1_2_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__Reserved0__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__CERE_1_2__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__EVENT_NOTE_1_2_HI_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__Reserved0_MASK 0x7FF00000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__CERE_1_2_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_0__ICOUNTER_1_3_LO__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_0__ICOUNTER_1_3_LO_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1__ICOUNTER_1_3_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1__Reserved__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1__ICOUNTER_1_3_HI_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1__Reserved_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CSOURCE_1_3__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__Reserved1__SHIFT 0x8
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__COUNT_UNITS_1_3__SHIFT 0x1e
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CAC_1_3__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CSOURCE_1_3_MASK 0x000000FFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__Reserved1_MASK 0x3FFFFF00L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__COUNT_UNITS_1_3_MASK 0x40000000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CAC_1_3_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1__Reserved0__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASID_MATCH_1_3__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASMEN_1_3__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASID_MATCH_1_3_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASMEN_1_3_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__PASID_MASK_1_3__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__PASID_MASK_1_3_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMAIN_MATCH_1_3__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMMEN_1_3__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMAIN_MATCH_1_3_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMMEN_1_3_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__DOMAIN_MASK_1_3__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__DOMAIN_MASK_1_3_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DEVICEID_MATCH_1_3__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DIDMEN_1_3__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DEVICEID_MATCH_1_3_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DIDMEN_1_3_MASK 0x80000000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__DEVICEID_MASK_1_3__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__DEVICEID_MASK_1_3_MASK 0x0000FFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0__EVENT_NOTE_1_3_LO__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0__EVENT_NOTE_1_3_LO_MASK 0xFFFFFFFFL
+//IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__EVENT_NOTE_1_3_HI__SHIFT 0x0
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__Reserved0__SHIFT 0x14
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__CERE_1_3__SHIFT 0x1f
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__EVENT_NOTE_1_3_HI_MASK 0x000FFFFFL
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__Reserved0_MASK 0x7FF00000L
+#define IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__CERE_1_3_MASK 0x80000000L
+
+
+// addressBlock: nbio_iohub_nb_ioapicmio_ioapic_miodec
+//IOAPICMIO_INDEX
+#define IOAPICMIO_INDEX__IOAPICMIO_INDEX_data__SHIFT 0x0
+#define IOAPICMIO_INDEX__IOAPICMIO_INDEX_data_MASK 0xFFFFFFFFL
+//IOAPICMIO_DATA
+#define IOAPICMIO_DATA__IOAPICMIO_DATA__SHIFT 0x0
+#define IOAPICMIO_DATA__IOAPICMIO_DATA_MASK 0xFFFFFFFFL
+//IRQ_PIN_ASSERTION_REGISTER
+#define IRQ_PIN_ASSERTION_REGISTER__Input_IRQ__SHIFT 0x0
+#define IRQ_PIN_ASSERTION_REGISTER__Input_IRQ_MASK 0x000000FFL
+//EOI_REGISTER
+#define EOI_REGISTER__Vector__SHIFT 0x0
+#define EOI_REGISTER__Vector_MASK 0x000000FFL
+
+
+// addressBlock: nbio_iohub_nb_ioapicmioindex_ioapic_mioindexdec
+//IOAPIC_ID_REGISTER
+#define IOAPIC_ID_REGISTER__DEV_ID__SHIFT 0x18
+#define IOAPIC_ID_REGISTER__EXTEND_ID__SHIFT 0x1c
+#define IOAPIC_ID_REGISTER__DEV_ID_MASK 0x0F000000L
+#define IOAPIC_ID_REGISTER__EXTEND_ID_MASK 0xF0000000L
+//IOAPIC_VERSION_REGISTER
+#define IOAPIC_VERSION_REGISTER__Version__SHIFT 0x0
+#define IOAPIC_VERSION_REGISTER__PRQ__SHIFT 0xf
+#define IOAPIC_VERSION_REGISTER__Max_Redirection_Entries__SHIFT 0x10
+#define IOAPIC_VERSION_REGISTER__Version_MASK 0x000000FFL
+#define IOAPIC_VERSION_REGISTER__PRQ_MASK 0x00008000L
+#define IOAPIC_VERSION_REGISTER__Max_Redirection_Entries_MASK 0x00FF0000L
+//IOAPIC_ARBITRATION_REGISTER
+#define IOAPIC_ARBITRATION_REGISTER__Arbitration_ID__SHIFT 0x18
+#define IOAPIC_ARBITRATION_REGISTER__Arbitration_ID_MASK 0x0F000000L
+//REDIRECTION_TABLE_ENTRY_LOW_0
+#define REDIRECTION_TABLE_ENTRY_LOW_0__Vector_0__SHIFT 0x0
+#define REDIRECTION_TABLE_ENTRY_LOW_0__Delivery_Mode_0__SHIFT 0x8
+#define REDIRECTION_TABLE_ENTRY_LOW_0__Destination_Mode_0__SHIFT 0xb
+#define REDIRECTION_TABLE_ENTRY_LOW_0__Delivery_status_0__SHIFT 0xc
+#define REDIRECTION_TABLE_ENTRY_LOW_0__Interrupt_Pin_Polarity_0__SHIFT 0xd
+#define REDIRECTION_TABLE_ENTRY_LOW_0__Remote_IRR_0__SHIFT 0xe
+#define REDIRECTION_TABLE_ENTRY_LOW_0__Trigger_Mode_0__SHIFT 0xf
+#define REDIRECTION_TABLE_ENTRY_LOW_0__Mask_0__SHIFT 0x10
+#define REDIRECTION_TABLE_ENTRY_LOW_0__Vector_0_MASK 0x000000FFL
+#define REDIRECTION_TABLE_ENTRY_LOW_0__Delivery_Mode_0_MASK 0x00000700L
+#define REDIRECTION_TABLE_ENTRY_LOW_0__Destination_Mode_0_MASK 0x00000800L
+#define REDIRECTION_TABLE_ENTRY_LOW_0__Delivery_status_0_MASK 0x00001000L
+#define REDIRECTION_TABLE_ENTRY_LOW_0__Interrupt_Pin_Polarity_0_MASK 0x00002000L
+#define REDIRECTION_TABLE_ENTRY_LOW_0__Remote_IRR_0_MASK 0x00004000L
+#define REDIRECTION_TABLE_ENTRY_LOW_0__Trigger_Mode_0_MASK 0x00008000L
+#define REDIRECTION_TABLE_ENTRY_LOW_0__Mask_0_MASK 0x00010000L
+//REDIRECTION_TABLE_ENTRY_HIGH_0
+#define REDIRECTION_TABLE_ENTRY_HIGH_0__Destination_id_0__SHIFT 0x18
+#define REDIRECTION_TABLE_ENTRY_HIGH_0__Destination_id_0_MASK 0xFF000000L
+//REDIRECTION_TABLE_ENTRY_LOW_1
+#define REDIRECTION_TABLE_ENTRY_LOW_1__Vector_1__SHIFT 0x0
+#define REDIRECTION_TABLE_ENTRY_LOW_1__Delivery_Mode_1__SHIFT 0x8
+#define REDIRECTION_TABLE_ENTRY_LOW_1__Destination_Mode_1__SHIFT 0xb
+#define REDIRECTION_TABLE_ENTRY_LOW_1__Delivery_status_1__SHIFT 0xc
+#define REDIRECTION_TABLE_ENTRY_LOW_1__Interrupt_Pin_Polarity_1__SHIFT 0xd
+#define REDIRECTION_TABLE_ENTRY_LOW_1__Remote_IRR_1__SHIFT 0xe
+#define REDIRECTION_TABLE_ENTRY_LOW_1__Trigger_Mode_1__SHIFT 0xf
+#define REDIRECTION_TABLE_ENTRY_LOW_1__Mask_1__SHIFT 0x10
+#define REDIRECTION_TABLE_ENTRY_LOW_1__Vector_1_MASK 0x000000FFL
+#define REDIRECTION_TABLE_ENTRY_LOW_1__Delivery_Mode_1_MASK 0x00000700L
+#define REDIRECTION_TABLE_ENTRY_LOW_1__Destination_Mode_1_MASK 0x00000800L
+#define REDIRECTION_TABLE_ENTRY_LOW_1__Delivery_status_1_MASK 0x00001000L
+#define REDIRECTION_TABLE_ENTRY_LOW_1__Interrupt_Pin_Polarity_1_MASK 0x00002000L
+#define REDIRECTION_TABLE_ENTRY_LOW_1__Remote_IRR_1_MASK 0x00004000L
+#define REDIRECTION_TABLE_ENTRY_LOW_1__Trigger_Mode_1_MASK 0x00008000L
+#define REDIRECTION_TABLE_ENTRY_LOW_1__Mask_1_MASK 0x00010000L
+//REDIRECTION_TABLE_ENTRY_HIGH_1
+#define REDIRECTION_TABLE_ENTRY_HIGH_1__Destination_id_1__SHIFT 0x18
+#define REDIRECTION_TABLE_ENTRY_HIGH_1__Destination_id_1_MASK 0xFF000000L
+//REDIRECTION_TABLE_ENTRY_LOW_2
+#define REDIRECTION_TABLE_ENTRY_LOW_2__Vector_2__SHIFT 0x0
+#define REDIRECTION_TABLE_ENTRY_LOW_2__Delivery_Mode_2__SHIFT 0x8
+#define REDIRECTION_TABLE_ENTRY_LOW_2__Destination_Mode_2__SHIFT 0xb
+#define REDIRECTION_TABLE_ENTRY_LOW_2__Delivery_status_2__SHIFT 0xc
+#define REDIRECTION_TABLE_ENTRY_LOW_2__Interrupt_Pin_Polarity_2__SHIFT 0xd
+#define REDIRECTION_TABLE_ENTRY_LOW_2__Remote_IRR_2__SHIFT 0xe
+#define REDIRECTION_TABLE_ENTRY_LOW_2__Trigger_Mode_2__SHIFT 0xf
+#define REDIRECTION_TABLE_ENTRY_LOW_2__Mask_2__SHIFT 0x10
+#define REDIRECTION_TABLE_ENTRY_LOW_2__Vector_2_MASK 0x000000FFL
+#define REDIRECTION_TABLE_ENTRY_LOW_2__Delivery_Mode_2_MASK 0x00000700L
+#define REDIRECTION_TABLE_ENTRY_LOW_2__Destination_Mode_2_MASK 0x00000800L
+#define REDIRECTION_TABLE_ENTRY_LOW_2__Delivery_status_2_MASK 0x00001000L
+#define REDIRECTION_TABLE_ENTRY_LOW_2__Interrupt_Pin_Polarity_2_MASK 0x00002000L
+#define REDIRECTION_TABLE_ENTRY_LOW_2__Remote_IRR_2_MASK 0x00004000L
+#define REDIRECTION_TABLE_ENTRY_LOW_2__Trigger_Mode_2_MASK 0x00008000L
+#define REDIRECTION_TABLE_ENTRY_LOW_2__Mask_2_MASK 0x00010000L
+//REDIRECTION_TABLE_ENTRY_HIGH_2
+#define REDIRECTION_TABLE_ENTRY_HIGH_2__Destination_id_2__SHIFT 0x18
+#define REDIRECTION_TABLE_ENTRY_HIGH_2__Destination_id_2_MASK 0xFF000000L
+//REDIRECTION_TABLE_ENTRY_LOW_3
+#define REDIRECTION_TABLE_ENTRY_LOW_3__Vector_3__SHIFT 0x0
+#define REDIRECTION_TABLE_ENTRY_LOW_3__Delivery_Mode_3__SHIFT 0x8
+#define REDIRECTION_TABLE_ENTRY_LOW_3__Destination_Mode_3__SHIFT 0xb
+#define REDIRECTION_TABLE_ENTRY_LOW_3__Delivery_status_3__SHIFT 0xc
+#define REDIRECTION_TABLE_ENTRY_LOW_3__Interrupt_Pin_Polarity_3__SHIFT 0xd
+#define REDIRECTION_TABLE_ENTRY_LOW_3__Remote_IRR_3__SHIFT 0xe
+#define REDIRECTION_TABLE_ENTRY_LOW_3__Trigger_Mode_3__SHIFT 0xf
+#define REDIRECTION_TABLE_ENTRY_LOW_3__Mask_3__SHIFT 0x10
+#define REDIRECTION_TABLE_ENTRY_LOW_3__Vector_3_MASK 0x000000FFL
+#define REDIRECTION_TABLE_ENTRY_LOW_3__Delivery_Mode_3_MASK 0x00000700L
+#define REDIRECTION_TABLE_ENTRY_LOW_3__Destination_Mode_3_MASK 0x00000800L
+#define REDIRECTION_TABLE_ENTRY_LOW_3__Delivery_status_3_MASK 0x00001000L
+#define REDIRECTION_TABLE_ENTRY_LOW_3__Interrupt_Pin_Polarity_3_MASK 0x00002000L
+#define REDIRECTION_TABLE_ENTRY_LOW_3__Remote_IRR_3_MASK 0x00004000L
+#define REDIRECTION_TABLE_ENTRY_LOW_3__Trigger_Mode_3_MASK 0x00008000L
+#define REDIRECTION_TABLE_ENTRY_LOW_3__Mask_3_MASK 0x00010000L
+//REDIRECTION_TABLE_ENTRY_HIGH_3
+#define REDIRECTION_TABLE_ENTRY_HIGH_3__Destination_id_3__SHIFT 0x18
+#define REDIRECTION_TABLE_ENTRY_HIGH_3__Destination_id_3_MASK 0xFF000000L
+//REDIRECTION_TABLE_ENTRY_LOW_4
+#define REDIRECTION_TABLE_ENTRY_LOW_4__Vector_4__SHIFT 0x0
+#define REDIRECTION_TABLE_ENTRY_LOW_4__Delivery_Mode_4__SHIFT 0x8
+#define REDIRECTION_TABLE_ENTRY_LOW_4__Destination_Mode_4__SHIFT 0xb
+#define REDIRECTION_TABLE_ENTRY_LOW_4__Delivery_status_4__SHIFT 0xc
+#define REDIRECTION_TABLE_ENTRY_LOW_4__Interrupt_Pin_Polarity_4__SHIFT 0xd
+#define REDIRECTION_TABLE_ENTRY_LOW_4__Remote_IRR_4__SHIFT 0xe
+#define REDIRECTION_TABLE_ENTRY_LOW_4__Trigger_Mode_4__SHIFT 0xf
+#define REDIRECTION_TABLE_ENTRY_LOW_4__Mask_4__SHIFT 0x10
+#define REDIRECTION_TABLE_ENTRY_LOW_4__Vector_4_MASK 0x000000FFL
+#define REDIRECTION_TABLE_ENTRY_LOW_4__Delivery_Mode_4_MASK 0x00000700L
+#define REDIRECTION_TABLE_ENTRY_LOW_4__Destination_Mode_4_MASK 0x00000800L
+#define REDIRECTION_TABLE_ENTRY_LOW_4__Delivery_status_4_MASK 0x00001000L
+#define REDIRECTION_TABLE_ENTRY_LOW_4__Interrupt_Pin_Polarity_4_MASK 0x00002000L
+#define REDIRECTION_TABLE_ENTRY_LOW_4__Remote_IRR_4_MASK 0x00004000L
+#define REDIRECTION_TABLE_ENTRY_LOW_4__Trigger_Mode_4_MASK 0x00008000L
+#define REDIRECTION_TABLE_ENTRY_LOW_4__Mask_4_MASK 0x00010000L
+//REDIRECTION_TABLE_ENTRY_HIGH_4
+#define REDIRECTION_TABLE_ENTRY_HIGH_4__Destination_id_4__SHIFT 0x18
+#define REDIRECTION_TABLE_ENTRY_HIGH_4__Destination_id_4_MASK 0xFF000000L
+//REDIRECTION_TABLE_ENTRY_LOW_5
+#define REDIRECTION_TABLE_ENTRY_LOW_5__Vector_5__SHIFT 0x0
+#define REDIRECTION_TABLE_ENTRY_LOW_5__Delivery_Mode_5__SHIFT 0x8
+#define REDIRECTION_TABLE_ENTRY_LOW_5__Destination_Mode_5__SHIFT 0xb
+#define REDIRECTION_TABLE_ENTRY_LOW_5__Delivery_status_5__SHIFT 0xc
+#define REDIRECTION_TABLE_ENTRY_LOW_5__Interrupt_Pin_Polarity_5__SHIFT 0xd
+#define REDIRECTION_TABLE_ENTRY_LOW_5__Remote_IRR_5__SHIFT 0xe
+#define REDIRECTION_TABLE_ENTRY_LOW_5__Trigger_Mode_5__SHIFT 0xf
+#define REDIRECTION_TABLE_ENTRY_LOW_5__Mask_5__SHIFT 0x10
+#define REDIRECTION_TABLE_ENTRY_LOW_5__Vector_5_MASK 0x000000FFL
+#define REDIRECTION_TABLE_ENTRY_LOW_5__Delivery_Mode_5_MASK 0x00000700L
+#define REDIRECTION_TABLE_ENTRY_LOW_5__Destination_Mode_5_MASK 0x00000800L
+#define REDIRECTION_TABLE_ENTRY_LOW_5__Delivery_status_5_MASK 0x00001000L
+#define REDIRECTION_TABLE_ENTRY_LOW_5__Interrupt_Pin_Polarity_5_MASK 0x00002000L
+#define REDIRECTION_TABLE_ENTRY_LOW_5__Remote_IRR_5_MASK 0x00004000L
+#define REDIRECTION_TABLE_ENTRY_LOW_5__Trigger_Mode_5_MASK 0x00008000L
+#define REDIRECTION_TABLE_ENTRY_LOW_5__Mask_5_MASK 0x00010000L
+//REDIRECTION_TABLE_ENTRY_HIGH_5
+#define REDIRECTION_TABLE_ENTRY_HIGH_5__Destination_id_5__SHIFT 0x18
+#define REDIRECTION_TABLE_ENTRY_HIGH_5__Destination_id_5_MASK 0xFF000000L
+//REDIRECTION_TABLE_ENTRY_LOW_6
+#define REDIRECTION_TABLE_ENTRY_LOW_6__Vector_6__SHIFT 0x0
+#define REDIRECTION_TABLE_ENTRY_LOW_6__Delivery_Mode_6__SHIFT 0x8
+#define REDIRECTION_TABLE_ENTRY_LOW_6__Destination_Mode_6__SHIFT 0xb
+#define REDIRECTION_TABLE_ENTRY_LOW_6__Delivery_status_6__SHIFT 0xc
+#define REDIRECTION_TABLE_ENTRY_LOW_6__Interrupt_Pin_Polarity_6__SHIFT 0xd
+#define REDIRECTION_TABLE_ENTRY_LOW_6__Remote_IRR_6__SHIFT 0xe
+#define REDIRECTION_TABLE_ENTRY_LOW_6__Trigger_Mode_6__SHIFT 0xf
+#define REDIRECTION_TABLE_ENTRY_LOW_6__Mask_6__SHIFT 0x10
+#define REDIRECTION_TABLE_ENTRY_LOW_6__Vector_6_MASK 0x000000FFL
+#define REDIRECTION_TABLE_ENTRY_LOW_6__Delivery_Mode_6_MASK 0x00000700L
+#define REDIRECTION_TABLE_ENTRY_LOW_6__Destination_Mode_6_MASK 0x00000800L
+#define REDIRECTION_TABLE_ENTRY_LOW_6__Delivery_status_6_MASK 0x00001000L
+#define REDIRECTION_TABLE_ENTRY_LOW_6__Interrupt_Pin_Polarity_6_MASK 0x00002000L
+#define REDIRECTION_TABLE_ENTRY_LOW_6__Remote_IRR_6_MASK 0x00004000L
+#define REDIRECTION_TABLE_ENTRY_LOW_6__Trigger_Mode_6_MASK 0x00008000L
+#define REDIRECTION_TABLE_ENTRY_LOW_6__Mask_6_MASK 0x00010000L
+//REDIRECTION_TABLE_ENTRY_HIGH_6
+#define REDIRECTION_TABLE_ENTRY_HIGH_6__Destination_id_6__SHIFT 0x18
+#define REDIRECTION_TABLE_ENTRY_HIGH_6__Destination_id_6_MASK 0xFF000000L
+//REDIRECTION_TABLE_ENTRY_LOW_7
+#define REDIRECTION_TABLE_ENTRY_LOW_7__Vector_7__SHIFT 0x0
+#define REDIRECTION_TABLE_ENTRY_LOW_7__Delivery_Mode_7__SHIFT 0x8
+#define REDIRECTION_TABLE_ENTRY_LOW_7__Destination_Mode_7__SHIFT 0xb
+#define REDIRECTION_TABLE_ENTRY_LOW_7__Delivery_status_7__SHIFT 0xc
+#define REDIRECTION_TABLE_ENTRY_LOW_7__Interrupt_Pin_Polarity_7__SHIFT 0xd
+#define REDIRECTION_TABLE_ENTRY_LOW_7__Remote_IRR_7__SHIFT 0xe
+#define REDIRECTION_TABLE_ENTRY_LOW_7__Trigger_Mode_7__SHIFT 0xf
+#define REDIRECTION_TABLE_ENTRY_LOW_7__Mask_7__SHIFT 0x10
+#define REDIRECTION_TABLE_ENTRY_LOW_7__Vector_7_MASK 0x000000FFL
+#define REDIRECTION_TABLE_ENTRY_LOW_7__Delivery_Mode_7_MASK 0x00000700L
+#define REDIRECTION_TABLE_ENTRY_LOW_7__Destination_Mode_7_MASK 0x00000800L
+#define REDIRECTION_TABLE_ENTRY_LOW_7__Delivery_status_7_MASK 0x00001000L
+#define REDIRECTION_TABLE_ENTRY_LOW_7__Interrupt_Pin_Polarity_7_MASK 0x00002000L
+#define REDIRECTION_TABLE_ENTRY_LOW_7__Remote_IRR_7_MASK 0x00004000L
+#define REDIRECTION_TABLE_ENTRY_LOW_7__Trigger_Mode_7_MASK 0x00008000L
+#define REDIRECTION_TABLE_ENTRY_LOW_7__Mask_7_MASK 0x00010000L
+//REDIRECTION_TABLE_ENTRY_HIGH_7
+#define REDIRECTION_TABLE_ENTRY_HIGH_7__Destination_id_7__SHIFT 0x18
+#define REDIRECTION_TABLE_ENTRY_HIGH_7__Destination_id_7_MASK 0xFF000000L
+//REDIRECTION_TABLE_ENTRY_LOW_8
+#define REDIRECTION_TABLE_ENTRY_LOW_8__Vector_8__SHIFT 0x0
+#define REDIRECTION_TABLE_ENTRY_LOW_8__Delivery_Mode_8__SHIFT 0x8
+#define REDIRECTION_TABLE_ENTRY_LOW_8__Destination_Mode_8__SHIFT 0xb
+#define REDIRECTION_TABLE_ENTRY_LOW_8__Delivery_status_8__SHIFT 0xc
+#define REDIRECTION_TABLE_ENTRY_LOW_8__Interrupt_Pin_Polarity_8__SHIFT 0xd
+#define REDIRECTION_TABLE_ENTRY_LOW_8__Remote_IRR_8__SHIFT 0xe
+#define REDIRECTION_TABLE_ENTRY_LOW_8__Trigger_Mode_8__SHIFT 0xf
+#define REDIRECTION_TABLE_ENTRY_LOW_8__Mask_8__SHIFT 0x10
+#define REDIRECTION_TABLE_ENTRY_LOW_8__Vector_8_MASK 0x000000FFL
+#define REDIRECTION_TABLE_ENTRY_LOW_8__Delivery_Mode_8_MASK 0x00000700L
+#define REDIRECTION_TABLE_ENTRY_LOW_8__Destination_Mode_8_MASK 0x00000800L
+#define REDIRECTION_TABLE_ENTRY_LOW_8__Delivery_status_8_MASK 0x00001000L
+#define REDIRECTION_TABLE_ENTRY_LOW_8__Interrupt_Pin_Polarity_8_MASK 0x00002000L
+#define REDIRECTION_TABLE_ENTRY_LOW_8__Remote_IRR_8_MASK 0x00004000L
+#define REDIRECTION_TABLE_ENTRY_LOW_8__Trigger_Mode_8_MASK 0x00008000L
+#define REDIRECTION_TABLE_ENTRY_LOW_8__Mask_8_MASK 0x00010000L
+//REDIRECTION_TABLE_ENTRY_HIGH_8
+#define REDIRECTION_TABLE_ENTRY_HIGH_8__Destination_id_8__SHIFT 0x18
+#define REDIRECTION_TABLE_ENTRY_HIGH_8__Destination_id_8_MASK 0xFF000000L
+//REDIRECTION_TABLE_ENTRY_LOW_9
+#define REDIRECTION_TABLE_ENTRY_LOW_9__Vector_9__SHIFT 0x0
+#define REDIRECTION_TABLE_ENTRY_LOW_9__Delivery_Mode_9__SHIFT 0x8
+#define REDIRECTION_TABLE_ENTRY_LOW_9__Destination_Mode_9__SHIFT 0xb
+#define REDIRECTION_TABLE_ENTRY_LOW_9__Delivery_status_9__SHIFT 0xc
+#define REDIRECTION_TABLE_ENTRY_LOW_9__Interrupt_Pin_Polarity_9__SHIFT 0xd
+#define REDIRECTION_TABLE_ENTRY_LOW_9__Remote_IRR_9__SHIFT 0xe
+#define REDIRECTION_TABLE_ENTRY_LOW_9__Trigger_Mode_9__SHIFT 0xf
+#define REDIRECTION_TABLE_ENTRY_LOW_9__Mask_9__SHIFT 0x10
+#define REDIRECTION_TABLE_ENTRY_LOW_9__Vector_9_MASK 0x000000FFL
+#define REDIRECTION_TABLE_ENTRY_LOW_9__Delivery_Mode_9_MASK 0x00000700L
+#define REDIRECTION_TABLE_ENTRY_LOW_9__Destination_Mode_9_MASK 0x00000800L
+#define REDIRECTION_TABLE_ENTRY_LOW_9__Delivery_status_9_MASK 0x00001000L
+#define REDIRECTION_TABLE_ENTRY_LOW_9__Interrupt_Pin_Polarity_9_MASK 0x00002000L
+#define REDIRECTION_TABLE_ENTRY_LOW_9__Remote_IRR_9_MASK 0x00004000L
+#define REDIRECTION_TABLE_ENTRY_LOW_9__Trigger_Mode_9_MASK 0x00008000L
+#define REDIRECTION_TABLE_ENTRY_LOW_9__Mask_9_MASK 0x00010000L
+//REDIRECTION_TABLE_ENTRY_HIGH_9
+#define REDIRECTION_TABLE_ENTRY_HIGH_9__Destination_id_9__SHIFT 0x18
+#define REDIRECTION_TABLE_ENTRY_HIGH_9__Destination_id_9_MASK 0xFF000000L
+//REDIRECTION_TABLE_ENTRY_LOW_10
+#define REDIRECTION_TABLE_ENTRY_LOW_10__Vector_10__SHIFT 0x0
+#define REDIRECTION_TABLE_ENTRY_LOW_10__Delivery_Mode_10__SHIFT 0x8
+#define REDIRECTION_TABLE_ENTRY_LOW_10__Destination_Mode_10__SHIFT 0xb
+#define REDIRECTION_TABLE_ENTRY_LOW_10__Delivery_status_10__SHIFT 0xc
+#define REDIRECTION_TABLE_ENTRY_LOW_10__Interrupt_Pin_Polarity_10__SHIFT 0xd
+#define REDIRECTION_TABLE_ENTRY_LOW_10__Remote_IRR_10__SHIFT 0xe
+#define REDIRECTION_TABLE_ENTRY_LOW_10__Trigger_Mode_10__SHIFT 0xf
+#define REDIRECTION_TABLE_ENTRY_LOW_10__Mask_10__SHIFT 0x10
+#define REDIRECTION_TABLE_ENTRY_LOW_10__Vector_10_MASK 0x000000FFL
+#define REDIRECTION_TABLE_ENTRY_LOW_10__Delivery_Mode_10_MASK 0x00000700L
+#define REDIRECTION_TABLE_ENTRY_LOW_10__Destination_Mode_10_MASK 0x00000800L
+#define REDIRECTION_TABLE_ENTRY_LOW_10__Delivery_status_10_MASK 0x00001000L
+#define REDIRECTION_TABLE_ENTRY_LOW_10__Interrupt_Pin_Polarity_10_MASK 0x00002000L
+#define REDIRECTION_TABLE_ENTRY_LOW_10__Remote_IRR_10_MASK 0x00004000L
+#define REDIRECTION_TABLE_ENTRY_LOW_10__Trigger_Mode_10_MASK 0x00008000L
+#define REDIRECTION_TABLE_ENTRY_LOW_10__Mask_10_MASK 0x00010000L
+//REDIRECTION_TABLE_ENTRY_HIGH_10
+#define REDIRECTION_TABLE_ENTRY_HIGH_10__Destination_id_10__SHIFT 0x18
+#define REDIRECTION_TABLE_ENTRY_HIGH_10__Destination_id_10_MASK 0xFF000000L
+//REDIRECTION_TABLE_ENTRY_LOW_11
+#define REDIRECTION_TABLE_ENTRY_LOW_11__Vector_11__SHIFT 0x0
+#define REDIRECTION_TABLE_ENTRY_LOW_11__Delivery_Mode_11__SHIFT 0x8
+#define REDIRECTION_TABLE_ENTRY_LOW_11__Destination_Mode_11__SHIFT 0xb
+#define REDIRECTION_TABLE_ENTRY_LOW_11__Delivery_status_11__SHIFT 0xc
+#define REDIRECTION_TABLE_ENTRY_LOW_11__Interrupt_Pin_Polarity_11__SHIFT 0xd
+#define REDIRECTION_TABLE_ENTRY_LOW_11__Remote_IRR_11__SHIFT 0xe
+#define REDIRECTION_TABLE_ENTRY_LOW_11__Trigger_Mode_11__SHIFT 0xf
+#define REDIRECTION_TABLE_ENTRY_LOW_11__Mask_11__SHIFT 0x10
+#define REDIRECTION_TABLE_ENTRY_LOW_11__Vector_11_MASK 0x000000FFL
+#define REDIRECTION_TABLE_ENTRY_LOW_11__Delivery_Mode_11_MASK 0x00000700L
+#define REDIRECTION_TABLE_ENTRY_LOW_11__Destination_Mode_11_MASK 0x00000800L
+#define REDIRECTION_TABLE_ENTRY_LOW_11__Delivery_status_11_MASK 0x00001000L
+#define REDIRECTION_TABLE_ENTRY_LOW_11__Interrupt_Pin_Polarity_11_MASK 0x00002000L
+#define REDIRECTION_TABLE_ENTRY_LOW_11__Remote_IRR_11_MASK 0x00004000L
+#define REDIRECTION_TABLE_ENTRY_LOW_11__Trigger_Mode_11_MASK 0x00008000L
+#define REDIRECTION_TABLE_ENTRY_LOW_11__Mask_11_MASK 0x00010000L
+//REDIRECTION_TABLE_ENTRY_HIGH_11
+#define REDIRECTION_TABLE_ENTRY_HIGH_11__Destination_id_11__SHIFT 0x18
+#define REDIRECTION_TABLE_ENTRY_HIGH_11__Destination_id_11_MASK 0xFF000000L
+//REDIRECTION_TABLE_ENTRY_LOW_12
+#define REDIRECTION_TABLE_ENTRY_LOW_12__Vector_12__SHIFT 0x0
+#define REDIRECTION_TABLE_ENTRY_LOW_12__Delivery_Mode_12__SHIFT 0x8
+#define REDIRECTION_TABLE_ENTRY_LOW_12__Destination_Mode_12__SHIFT 0xb
+#define REDIRECTION_TABLE_ENTRY_LOW_12__Delivery_status_12__SHIFT 0xc
+#define REDIRECTION_TABLE_ENTRY_LOW_12__Interrupt_Pin_Polarity_12__SHIFT 0xd
+#define REDIRECTION_TABLE_ENTRY_LOW_12__Remote_IRR_12__SHIFT 0xe
+#define REDIRECTION_TABLE_ENTRY_LOW_12__Trigger_Mode_12__SHIFT 0xf
+#define REDIRECTION_TABLE_ENTRY_LOW_12__Mask_12__SHIFT 0x10
+#define REDIRECTION_TABLE_ENTRY_LOW_12__Vector_12_MASK 0x000000FFL
+#define REDIRECTION_TABLE_ENTRY_LOW_12__Delivery_Mode_12_MASK 0x00000700L
+#define REDIRECTION_TABLE_ENTRY_LOW_12__Destination_Mode_12_MASK 0x00000800L
+#define REDIRECTION_TABLE_ENTRY_LOW_12__Delivery_status_12_MASK 0x00001000L
+#define REDIRECTION_TABLE_ENTRY_LOW_12__Interrupt_Pin_Polarity_12_MASK 0x00002000L
+#define REDIRECTION_TABLE_ENTRY_LOW_12__Remote_IRR_12_MASK 0x00004000L
+#define REDIRECTION_TABLE_ENTRY_LOW_12__Trigger_Mode_12_MASK 0x00008000L
+#define REDIRECTION_TABLE_ENTRY_LOW_12__Mask_12_MASK 0x00010000L
+//REDIRECTION_TABLE_ENTRY_HIGH_12
+#define REDIRECTION_TABLE_ENTRY_HIGH_12__Destination_id_12__SHIFT 0x18
+#define REDIRECTION_TABLE_ENTRY_HIGH_12__Destination_id_12_MASK 0xFF000000L
+//REDIRECTION_TABLE_ENTRY_LOW_13
+#define REDIRECTION_TABLE_ENTRY_LOW_13__Vector_13__SHIFT 0x0
+#define REDIRECTION_TABLE_ENTRY_LOW_13__Delivery_Mode_13__SHIFT 0x8
+#define REDIRECTION_TABLE_ENTRY_LOW_13__Destination_Mode_13__SHIFT 0xb
+#define REDIRECTION_TABLE_ENTRY_LOW_13__Delivery_status_13__SHIFT 0xc
+#define REDIRECTION_TABLE_ENTRY_LOW_13__Interrupt_Pin_Polarity_13__SHIFT 0xd
+#define REDIRECTION_TABLE_ENTRY_LOW_13__Remote_IRR_13__SHIFT 0xe
+#define REDIRECTION_TABLE_ENTRY_LOW_13__Trigger_Mode_13__SHIFT 0xf
+#define REDIRECTION_TABLE_ENTRY_LOW_13__Mask_13__SHIFT 0x10
+#define REDIRECTION_TABLE_ENTRY_LOW_13__Vector_13_MASK 0x000000FFL
+#define REDIRECTION_TABLE_ENTRY_LOW_13__Delivery_Mode_13_MASK 0x00000700L
+#define REDIRECTION_TABLE_ENTRY_LOW_13__Destination_Mode_13_MASK 0x00000800L
+#define REDIRECTION_TABLE_ENTRY_LOW_13__Delivery_status_13_MASK 0x00001000L
+#define REDIRECTION_TABLE_ENTRY_LOW_13__Interrupt_Pin_Polarity_13_MASK 0x00002000L
+#define REDIRECTION_TABLE_ENTRY_LOW_13__Remote_IRR_13_MASK 0x00004000L
+#define REDIRECTION_TABLE_ENTRY_LOW_13__Trigger_Mode_13_MASK 0x00008000L
+#define REDIRECTION_TABLE_ENTRY_LOW_13__Mask_13_MASK 0x00010000L
+//REDIRECTION_TABLE_ENTRY_HIGH_13
+#define REDIRECTION_TABLE_ENTRY_HIGH_13__Destination_id_13__SHIFT 0x18
+#define REDIRECTION_TABLE_ENTRY_HIGH_13__Destination_id_13_MASK 0xFF000000L
+//REDIRECTION_TABLE_ENTRY_LOW_14
+#define REDIRECTION_TABLE_ENTRY_LOW_14__Vector_14__SHIFT 0x0
+#define REDIRECTION_TABLE_ENTRY_LOW_14__Delivery_Mode_14__SHIFT 0x8
+#define REDIRECTION_TABLE_ENTRY_LOW_14__Destination_Mode_14__SHIFT 0xb
+#define REDIRECTION_TABLE_ENTRY_LOW_14__Delivery_status_14__SHIFT 0xc
+#define REDIRECTION_TABLE_ENTRY_LOW_14__Interrupt_Pin_Polarity_14__SHIFT 0xd
+#define REDIRECTION_TABLE_ENTRY_LOW_14__Remote_IRR_14__SHIFT 0xe
+#define REDIRECTION_TABLE_ENTRY_LOW_14__Trigger_Mode_14__SHIFT 0xf
+#define REDIRECTION_TABLE_ENTRY_LOW_14__Mask_14__SHIFT 0x10
+#define REDIRECTION_TABLE_ENTRY_LOW_14__Vector_14_MASK 0x000000FFL
+#define REDIRECTION_TABLE_ENTRY_LOW_14__Delivery_Mode_14_MASK 0x00000700L
+#define REDIRECTION_TABLE_ENTRY_LOW_14__Destination_Mode_14_MASK 0x00000800L
+#define REDIRECTION_TABLE_ENTRY_LOW_14__Delivery_status_14_MASK 0x00001000L
+#define REDIRECTION_TABLE_ENTRY_LOW_14__Interrupt_Pin_Polarity_14_MASK 0x00002000L
+#define REDIRECTION_TABLE_ENTRY_LOW_14__Remote_IRR_14_MASK 0x00004000L
+#define REDIRECTION_TABLE_ENTRY_LOW_14__Trigger_Mode_14_MASK 0x00008000L
+#define REDIRECTION_TABLE_ENTRY_LOW_14__Mask_14_MASK 0x00010000L
+//REDIRECTION_TABLE_ENTRY_HIGH_14
+#define REDIRECTION_TABLE_ENTRY_HIGH_14__Destination_id_14__SHIFT 0x18
+#define REDIRECTION_TABLE_ENTRY_HIGH_14__Destination_id_14_MASK 0xFF000000L
+//REDIRECTION_TABLE_ENTRY_LOW_15
+#define REDIRECTION_TABLE_ENTRY_LOW_15__Vector_15__SHIFT 0x0
+#define REDIRECTION_TABLE_ENTRY_LOW_15__Delivery_Mode_15__SHIFT 0x8
+#define REDIRECTION_TABLE_ENTRY_LOW_15__Destination_Mode_15__SHIFT 0xb
+#define REDIRECTION_TABLE_ENTRY_LOW_15__Delivery_status_15__SHIFT 0xc
+#define REDIRECTION_TABLE_ENTRY_LOW_15__Interrupt_Pin_Polarity_15__SHIFT 0xd
+#define REDIRECTION_TABLE_ENTRY_LOW_15__Remote_IRR_15__SHIFT 0xe
+#define REDIRECTION_TABLE_ENTRY_LOW_15__Trigger_Mode_15__SHIFT 0xf
+#define REDIRECTION_TABLE_ENTRY_LOW_15__Mask_15__SHIFT 0x10
+#define REDIRECTION_TABLE_ENTRY_LOW_15__Vector_15_MASK 0x000000FFL
+#define REDIRECTION_TABLE_ENTRY_LOW_15__Delivery_Mode_15_MASK 0x00000700L
+#define REDIRECTION_TABLE_ENTRY_LOW_15__Destination_Mode_15_MASK 0x00000800L
+#define REDIRECTION_TABLE_ENTRY_LOW_15__Delivery_status_15_MASK 0x00001000L
+#define REDIRECTION_TABLE_ENTRY_LOW_15__Interrupt_Pin_Polarity_15_MASK 0x00002000L
+#define REDIRECTION_TABLE_ENTRY_LOW_15__Remote_IRR_15_MASK 0x00004000L
+#define REDIRECTION_TABLE_ENTRY_LOW_15__Trigger_Mode_15_MASK 0x00008000L
+#define REDIRECTION_TABLE_ENTRY_LOW_15__Mask_15_MASK 0x00010000L
+//REDIRECTION_TABLE_ENTRY_HIGH_15
+#define REDIRECTION_TABLE_ENTRY_HIGH_15__Destination_id_15__SHIFT 0x18
+#define REDIRECTION_TABLE_ENTRY_HIGH_15__Destination_id_15_MASK 0xFF000000L
+//REDIRECTION_TABLE_ENTRY_LOW_16
+#define REDIRECTION_TABLE_ENTRY_LOW_16__Vector_16__SHIFT 0x0
+#define REDIRECTION_TABLE_ENTRY_LOW_16__Delivery_Mode_16__SHIFT 0x8
+#define REDIRECTION_TABLE_ENTRY_LOW_16__Destination_Mode_16__SHIFT 0xb
+#define REDIRECTION_TABLE_ENTRY_LOW_16__Delivery_status_16__SHIFT 0xc
+#define REDIRECTION_TABLE_ENTRY_LOW_16__Interrupt_Pin_Polarity_16__SHIFT 0xd
+#define REDIRECTION_TABLE_ENTRY_LOW_16__Remote_IRR_16__SHIFT 0xe
+#define REDIRECTION_TABLE_ENTRY_LOW_16__Trigger_Mode_16__SHIFT 0xf
+#define REDIRECTION_TABLE_ENTRY_LOW_16__Mask_16__SHIFT 0x10
+#define REDIRECTION_TABLE_ENTRY_LOW_16__Vector_16_MASK 0x000000FFL
+#define REDIRECTION_TABLE_ENTRY_LOW_16__Delivery_Mode_16_MASK 0x00000700L
+#define REDIRECTION_TABLE_ENTRY_LOW_16__Destination_Mode_16_MASK 0x00000800L
+#define REDIRECTION_TABLE_ENTRY_LOW_16__Delivery_status_16_MASK 0x00001000L
+#define REDIRECTION_TABLE_ENTRY_LOW_16__Interrupt_Pin_Polarity_16_MASK 0x00002000L
+#define REDIRECTION_TABLE_ENTRY_LOW_16__Remote_IRR_16_MASK 0x00004000L
+#define REDIRECTION_TABLE_ENTRY_LOW_16__Trigger_Mode_16_MASK 0x00008000L
+#define REDIRECTION_TABLE_ENTRY_LOW_16__Mask_16_MASK 0x00010000L
+//REDIRECTION_TABLE_ENTRY_HIGH_16
+#define REDIRECTION_TABLE_ENTRY_HIGH_16__Destination_id_16__SHIFT 0x18
+#define REDIRECTION_TABLE_ENTRY_HIGH_16__Destination_id_16_MASK 0xFF000000L
+//REDIRECTION_TABLE_ENTRY_LOW_17
+#define REDIRECTION_TABLE_ENTRY_LOW_17__Vector_17__SHIFT 0x0
+#define REDIRECTION_TABLE_ENTRY_LOW_17__Delivery_Mode_17__SHIFT 0x8
+#define REDIRECTION_TABLE_ENTRY_LOW_17__Destination_Mode_17__SHIFT 0xb
+#define REDIRECTION_TABLE_ENTRY_LOW_17__Delivery_status_17__SHIFT 0xc
+#define REDIRECTION_TABLE_ENTRY_LOW_17__Interrupt_Pin_Polarity_17__SHIFT 0xd
+#define REDIRECTION_TABLE_ENTRY_LOW_17__Remote_IRR_17__SHIFT 0xe
+#define REDIRECTION_TABLE_ENTRY_LOW_17__Trigger_Mode_17__SHIFT 0xf
+#define REDIRECTION_TABLE_ENTRY_LOW_17__Mask_17__SHIFT 0x10
+#define REDIRECTION_TABLE_ENTRY_LOW_17__Vector_17_MASK 0x000000FFL
+#define REDIRECTION_TABLE_ENTRY_LOW_17__Delivery_Mode_17_MASK 0x00000700L
+#define REDIRECTION_TABLE_ENTRY_LOW_17__Destination_Mode_17_MASK 0x00000800L
+#define REDIRECTION_TABLE_ENTRY_LOW_17__Delivery_status_17_MASK 0x00001000L
+#define REDIRECTION_TABLE_ENTRY_LOW_17__Interrupt_Pin_Polarity_17_MASK 0x00002000L
+#define REDIRECTION_TABLE_ENTRY_LOW_17__Remote_IRR_17_MASK 0x00004000L
+#define REDIRECTION_TABLE_ENTRY_LOW_17__Trigger_Mode_17_MASK 0x00008000L
+#define REDIRECTION_TABLE_ENTRY_LOW_17__Mask_17_MASK 0x00010000L
+//REDIRECTION_TABLE_ENTRY_HIGH_17
+#define REDIRECTION_TABLE_ENTRY_HIGH_17__Destination_id_17__SHIFT 0x18
+#define REDIRECTION_TABLE_ENTRY_HIGH_17__Destination_id_17_MASK 0xFF000000L
+//REDIRECTION_TABLE_ENTRY_LOW_18
+#define REDIRECTION_TABLE_ENTRY_LOW_18__Vector_18__SHIFT 0x0
+#define REDIRECTION_TABLE_ENTRY_LOW_18__Delivery_Mode_18__SHIFT 0x8
+#define REDIRECTION_TABLE_ENTRY_LOW_18__Destination_Mode_18__SHIFT 0xb
+#define REDIRECTION_TABLE_ENTRY_LOW_18__Delivery_status_18__SHIFT 0xc
+#define REDIRECTION_TABLE_ENTRY_LOW_18__Interrupt_Pin_Polarity_18__SHIFT 0xd
+#define REDIRECTION_TABLE_ENTRY_LOW_18__Remote_IRR_18__SHIFT 0xe
+#define REDIRECTION_TABLE_ENTRY_LOW_18__Trigger_Mode_18__SHIFT 0xf
+#define REDIRECTION_TABLE_ENTRY_LOW_18__Mask_18__SHIFT 0x10
+#define REDIRECTION_TABLE_ENTRY_LOW_18__Vector_18_MASK 0x000000FFL
+#define REDIRECTION_TABLE_ENTRY_LOW_18__Delivery_Mode_18_MASK 0x00000700L
+#define REDIRECTION_TABLE_ENTRY_LOW_18__Destination_Mode_18_MASK 0x00000800L
+#define REDIRECTION_TABLE_ENTRY_LOW_18__Delivery_status_18_MASK 0x00001000L
+#define REDIRECTION_TABLE_ENTRY_LOW_18__Interrupt_Pin_Polarity_18_MASK 0x00002000L
+#define REDIRECTION_TABLE_ENTRY_LOW_18__Remote_IRR_18_MASK 0x00004000L
+#define REDIRECTION_TABLE_ENTRY_LOW_18__Trigger_Mode_18_MASK 0x00008000L
+#define REDIRECTION_TABLE_ENTRY_LOW_18__Mask_18_MASK 0x00010000L
+//REDIRECTION_TABLE_ENTRY_HIGH_18
+#define REDIRECTION_TABLE_ENTRY_HIGH_18__Destination_id_18__SHIFT 0x18
+#define REDIRECTION_TABLE_ENTRY_HIGH_18__Destination_id_18_MASK 0xFF000000L
+//REDIRECTION_TABLE_ENTRY_LOW_19
+#define REDIRECTION_TABLE_ENTRY_LOW_19__Vector_19__SHIFT 0x0
+#define REDIRECTION_TABLE_ENTRY_LOW_19__Delivery_Mode_19__SHIFT 0x8
+#define REDIRECTION_TABLE_ENTRY_LOW_19__Destination_Mode_19__SHIFT 0xb
+#define REDIRECTION_TABLE_ENTRY_LOW_19__Delivery_status_19__SHIFT 0xc
+#define REDIRECTION_TABLE_ENTRY_LOW_19__Interrupt_Pin_Polarity_19__SHIFT 0xd
+#define REDIRECTION_TABLE_ENTRY_LOW_19__Remote_IRR_19__SHIFT 0xe
+#define REDIRECTION_TABLE_ENTRY_LOW_19__Trigger_Mode_19__SHIFT 0xf
+#define REDIRECTION_TABLE_ENTRY_LOW_19__Mask_19__SHIFT 0x10
+#define REDIRECTION_TABLE_ENTRY_LOW_19__Vector_19_MASK 0x000000FFL
+#define REDIRECTION_TABLE_ENTRY_LOW_19__Delivery_Mode_19_MASK 0x00000700L
+#define REDIRECTION_TABLE_ENTRY_LOW_19__Destination_Mode_19_MASK 0x00000800L
+#define REDIRECTION_TABLE_ENTRY_LOW_19__Delivery_status_19_MASK 0x00001000L
+#define REDIRECTION_TABLE_ENTRY_LOW_19__Interrupt_Pin_Polarity_19_MASK 0x00002000L
+#define REDIRECTION_TABLE_ENTRY_LOW_19__Remote_IRR_19_MASK 0x00004000L
+#define REDIRECTION_TABLE_ENTRY_LOW_19__Trigger_Mode_19_MASK 0x00008000L
+#define REDIRECTION_TABLE_ENTRY_LOW_19__Mask_19_MASK 0x00010000L
+//REDIRECTION_TABLE_ENTRY_HIGH_19
+#define REDIRECTION_TABLE_ENTRY_HIGH_19__Destination_id_19__SHIFT 0x18
+#define REDIRECTION_TABLE_ENTRY_HIGH_19__Destination_id_19_MASK 0xFF000000L
+//REDIRECTION_TABLE_ENTRY_LOW_20
+#define REDIRECTION_TABLE_ENTRY_LOW_20__Vector_20__SHIFT 0x0
+#define REDIRECTION_TABLE_ENTRY_LOW_20__Delivery_Mode_20__SHIFT 0x8
+#define REDIRECTION_TABLE_ENTRY_LOW_20__Destination_Mode_20__SHIFT 0xb
+#define REDIRECTION_TABLE_ENTRY_LOW_20__Delivery_status_20__SHIFT 0xc
+#define REDIRECTION_TABLE_ENTRY_LOW_20__Interrupt_Pin_Polarity_20__SHIFT 0xd
+#define REDIRECTION_TABLE_ENTRY_LOW_20__Remote_IRR_20__SHIFT 0xe
+#define REDIRECTION_TABLE_ENTRY_LOW_20__Trigger_Mode_20__SHIFT 0xf
+#define REDIRECTION_TABLE_ENTRY_LOW_20__Mask_20__SHIFT 0x10
+#define REDIRECTION_TABLE_ENTRY_LOW_20__Vector_20_MASK 0x000000FFL
+#define REDIRECTION_TABLE_ENTRY_LOW_20__Delivery_Mode_20_MASK 0x00000700L
+#define REDIRECTION_TABLE_ENTRY_LOW_20__Destination_Mode_20_MASK 0x00000800L
+#define REDIRECTION_TABLE_ENTRY_LOW_20__Delivery_status_20_MASK 0x00001000L
+#define REDIRECTION_TABLE_ENTRY_LOW_20__Interrupt_Pin_Polarity_20_MASK 0x00002000L
+#define REDIRECTION_TABLE_ENTRY_LOW_20__Remote_IRR_20_MASK 0x00004000L
+#define REDIRECTION_TABLE_ENTRY_LOW_20__Trigger_Mode_20_MASK 0x00008000L
+#define REDIRECTION_TABLE_ENTRY_LOW_20__Mask_20_MASK 0x00010000L
+//REDIRECTION_TABLE_ENTRY_HIGH_20
+#define REDIRECTION_TABLE_ENTRY_HIGH_20__Destination_id_20__SHIFT 0x18
+#define REDIRECTION_TABLE_ENTRY_HIGH_20__Destination_id_20_MASK 0xFF000000L
+//REDIRECTION_TABLE_ENTRY_LOW_21
+#define REDIRECTION_TABLE_ENTRY_LOW_21__Vector_21__SHIFT 0x0
+#define REDIRECTION_TABLE_ENTRY_LOW_21__Delivery_Mode_21__SHIFT 0x8
+#define REDIRECTION_TABLE_ENTRY_LOW_21__Destination_Mode_21__SHIFT 0xb
+#define REDIRECTION_TABLE_ENTRY_LOW_21__Delivery_status_21__SHIFT 0xc
+#define REDIRECTION_TABLE_ENTRY_LOW_21__Interrupt_Pin_Polarity_21__SHIFT 0xd
+#define REDIRECTION_TABLE_ENTRY_LOW_21__Remote_IRR_21__SHIFT 0xe
+#define REDIRECTION_TABLE_ENTRY_LOW_21__Trigger_Mode_21__SHIFT 0xf
+#define REDIRECTION_TABLE_ENTRY_LOW_21__Mask_21__SHIFT 0x10
+#define REDIRECTION_TABLE_ENTRY_LOW_21__Vector_21_MASK 0x000000FFL
+#define REDIRECTION_TABLE_ENTRY_LOW_21__Delivery_Mode_21_MASK 0x00000700L
+#define REDIRECTION_TABLE_ENTRY_LOW_21__Destination_Mode_21_MASK 0x00000800L
+#define REDIRECTION_TABLE_ENTRY_LOW_21__Delivery_status_21_MASK 0x00001000L
+#define REDIRECTION_TABLE_ENTRY_LOW_21__Interrupt_Pin_Polarity_21_MASK 0x00002000L
+#define REDIRECTION_TABLE_ENTRY_LOW_21__Remote_IRR_21_MASK 0x00004000L
+#define REDIRECTION_TABLE_ENTRY_LOW_21__Trigger_Mode_21_MASK 0x00008000L
+#define REDIRECTION_TABLE_ENTRY_LOW_21__Mask_21_MASK 0x00010000L
+//REDIRECTION_TABLE_ENTRY_HIGH_21
+#define REDIRECTION_TABLE_ENTRY_HIGH_21__Destination_id_21__SHIFT 0x18
+#define REDIRECTION_TABLE_ENTRY_HIGH_21__Destination_id_21_MASK 0xFF000000L
+//REDIRECTION_TABLE_ENTRY_LOW_22
+#define REDIRECTION_TABLE_ENTRY_LOW_22__Vector_22__SHIFT 0x0
+#define REDIRECTION_TABLE_ENTRY_LOW_22__Delivery_Mode_22__SHIFT 0x8
+#define REDIRECTION_TABLE_ENTRY_LOW_22__Destination_Mode_22__SHIFT 0xb
+#define REDIRECTION_TABLE_ENTRY_LOW_22__Delivery_status_22__SHIFT 0xc
+#define REDIRECTION_TABLE_ENTRY_LOW_22__Interrupt_Pin_Polarity_22__SHIFT 0xd
+#define REDIRECTION_TABLE_ENTRY_LOW_22__Remote_IRR_22__SHIFT 0xe
+#define REDIRECTION_TABLE_ENTRY_LOW_22__Trigger_Mode_22__SHIFT 0xf
+#define REDIRECTION_TABLE_ENTRY_LOW_22__Mask_22__SHIFT 0x10
+#define REDIRECTION_TABLE_ENTRY_LOW_22__Vector_22_MASK 0x000000FFL
+#define REDIRECTION_TABLE_ENTRY_LOW_22__Delivery_Mode_22_MASK 0x00000700L
+#define REDIRECTION_TABLE_ENTRY_LOW_22__Destination_Mode_22_MASK 0x00000800L
+#define REDIRECTION_TABLE_ENTRY_LOW_22__Delivery_status_22_MASK 0x00001000L
+#define REDIRECTION_TABLE_ENTRY_LOW_22__Interrupt_Pin_Polarity_22_MASK 0x00002000L
+#define REDIRECTION_TABLE_ENTRY_LOW_22__Remote_IRR_22_MASK 0x00004000L
+#define REDIRECTION_TABLE_ENTRY_LOW_22__Trigger_Mode_22_MASK 0x00008000L
+#define REDIRECTION_TABLE_ENTRY_LOW_22__Mask_22_MASK 0x00010000L
+//REDIRECTION_TABLE_ENTRY_HIGH_22
+#define REDIRECTION_TABLE_ENTRY_HIGH_22__Destination_id_22__SHIFT 0x18
+#define REDIRECTION_TABLE_ENTRY_HIGH_22__Destination_id_22_MASK 0xFF000000L
+//REDIRECTION_TABLE_ENTRY_LOW_23
+#define REDIRECTION_TABLE_ENTRY_LOW_23__Vector_23__SHIFT 0x0
+#define REDIRECTION_TABLE_ENTRY_LOW_23__Delivery_Mode_23__SHIFT 0x8
+#define REDIRECTION_TABLE_ENTRY_LOW_23__Destination_Mode_23__SHIFT 0xb
+#define REDIRECTION_TABLE_ENTRY_LOW_23__Delivery_status_23__SHIFT 0xc
+#define REDIRECTION_TABLE_ENTRY_LOW_23__Interrupt_Pin_Polarity_23__SHIFT 0xd
+#define REDIRECTION_TABLE_ENTRY_LOW_23__Remote_IRR_23__SHIFT 0xe
+#define REDIRECTION_TABLE_ENTRY_LOW_23__Trigger_Mode_23__SHIFT 0xf
+#define REDIRECTION_TABLE_ENTRY_LOW_23__Mask_23__SHIFT 0x10
+#define REDIRECTION_TABLE_ENTRY_LOW_23__Vector_23_MASK 0x000000FFL
+#define REDIRECTION_TABLE_ENTRY_LOW_23__Delivery_Mode_23_MASK 0x00000700L
+#define REDIRECTION_TABLE_ENTRY_LOW_23__Destination_Mode_23_MASK 0x00000800L
+#define REDIRECTION_TABLE_ENTRY_LOW_23__Delivery_status_23_MASK 0x00001000L
+#define REDIRECTION_TABLE_ENTRY_LOW_23__Interrupt_Pin_Polarity_23_MASK 0x00002000L
+#define REDIRECTION_TABLE_ENTRY_LOW_23__Remote_IRR_23_MASK 0x00004000L
+#define REDIRECTION_TABLE_ENTRY_LOW_23__Trigger_Mode_23_MASK 0x00008000L
+#define REDIRECTION_TABLE_ENTRY_LOW_23__Mask_23_MASK 0x00010000L
+//REDIRECTION_TABLE_ENTRY_HIGH_23
+#define REDIRECTION_TABLE_ENTRY_HIGH_23__Destination_id_23__SHIFT 0x18
+#define REDIRECTION_TABLE_ENTRY_HIGH_23__Destination_id_23_MASK 0xFF000000L
+//REDIRECTION_TABLE_ENTRY_LOW_24
+#define REDIRECTION_TABLE_ENTRY_LOW_24__Vector_24__SHIFT 0x0
+#define REDIRECTION_TABLE_ENTRY_LOW_24__Delivery_Mode_24__SHIFT 0x8
+#define REDIRECTION_TABLE_ENTRY_LOW_24__Destination_Mode_24__SHIFT 0xb
+#define REDIRECTION_TABLE_ENTRY_LOW_24__Delivery_status_24__SHIFT 0xc
+#define REDIRECTION_TABLE_ENTRY_LOW_24__Interrupt_Pin_Polarity_24__SHIFT 0xd
+#define REDIRECTION_TABLE_ENTRY_LOW_24__Remote_IRR_24__SHIFT 0xe
+#define REDIRECTION_TABLE_ENTRY_LOW_24__Trigger_Mode_24__SHIFT 0xf
+#define REDIRECTION_TABLE_ENTRY_LOW_24__Mask_24__SHIFT 0x10
+#define REDIRECTION_TABLE_ENTRY_LOW_24__Vector_24_MASK 0x000000FFL
+#define REDIRECTION_TABLE_ENTRY_LOW_24__Delivery_Mode_24_MASK 0x00000700L
+#define REDIRECTION_TABLE_ENTRY_LOW_24__Destination_Mode_24_MASK 0x00000800L
+#define REDIRECTION_TABLE_ENTRY_LOW_24__Delivery_status_24_MASK 0x00001000L
+#define REDIRECTION_TABLE_ENTRY_LOW_24__Interrupt_Pin_Polarity_24_MASK 0x00002000L
+#define REDIRECTION_TABLE_ENTRY_LOW_24__Remote_IRR_24_MASK 0x00004000L
+#define REDIRECTION_TABLE_ENTRY_LOW_24__Trigger_Mode_24_MASK 0x00008000L
+#define REDIRECTION_TABLE_ENTRY_LOW_24__Mask_24_MASK 0x00010000L
+//REDIRECTION_TABLE_ENTRY_HIGH_24
+#define REDIRECTION_TABLE_ENTRY_HIGH_24__Destination_id_24__SHIFT 0x18
+#define REDIRECTION_TABLE_ENTRY_HIGH_24__Destination_id_24_MASK 0xFF000000L
+//REDIRECTION_TABLE_ENTRY_LOW_25
+#define REDIRECTION_TABLE_ENTRY_LOW_25__Vector_25__SHIFT 0x0
+#define REDIRECTION_TABLE_ENTRY_LOW_25__Delivery_Mode_25__SHIFT 0x8
+#define REDIRECTION_TABLE_ENTRY_LOW_25__Destination_Mode_25__SHIFT 0xb
+#define REDIRECTION_TABLE_ENTRY_LOW_25__Delivery_status_25__SHIFT 0xc
+#define REDIRECTION_TABLE_ENTRY_LOW_25__Interrupt_Pin_Polarity_25__SHIFT 0xd
+#define REDIRECTION_TABLE_ENTRY_LOW_25__Remote_IRR_25__SHIFT 0xe
+#define REDIRECTION_TABLE_ENTRY_LOW_25__Trigger_Mode_25__SHIFT 0xf
+#define REDIRECTION_TABLE_ENTRY_LOW_25__Mask_25__SHIFT 0x10
+#define REDIRECTION_TABLE_ENTRY_LOW_25__Vector_25_MASK 0x000000FFL
+#define REDIRECTION_TABLE_ENTRY_LOW_25__Delivery_Mode_25_MASK 0x00000700L
+#define REDIRECTION_TABLE_ENTRY_LOW_25__Destination_Mode_25_MASK 0x00000800L
+#define REDIRECTION_TABLE_ENTRY_LOW_25__Delivery_status_25_MASK 0x00001000L
+#define REDIRECTION_TABLE_ENTRY_LOW_25__Interrupt_Pin_Polarity_25_MASK 0x00002000L
+#define REDIRECTION_TABLE_ENTRY_LOW_25__Remote_IRR_25_MASK 0x00004000L
+#define REDIRECTION_TABLE_ENTRY_LOW_25__Trigger_Mode_25_MASK 0x00008000L
+#define REDIRECTION_TABLE_ENTRY_LOW_25__Mask_25_MASK 0x00010000L
+//REDIRECTION_TABLE_ENTRY_HIGH_25
+#define REDIRECTION_TABLE_ENTRY_HIGH_25__Destination_id_25__SHIFT 0x18
+#define REDIRECTION_TABLE_ENTRY_HIGH_25__Destination_id_25_MASK 0xFF000000L
+//REDIRECTION_TABLE_ENTRY_LOW_26
+#define REDIRECTION_TABLE_ENTRY_LOW_26__Vector_26__SHIFT 0x0
+#define REDIRECTION_TABLE_ENTRY_LOW_26__Delivery_Mode_26__SHIFT 0x8
+#define REDIRECTION_TABLE_ENTRY_LOW_26__Destination_Mode_26__SHIFT 0xb
+#define REDIRECTION_TABLE_ENTRY_LOW_26__Delivery_status_26__SHIFT 0xc
+#define REDIRECTION_TABLE_ENTRY_LOW_26__Interrupt_Pin_Polarity_26__SHIFT 0xd
+#define REDIRECTION_TABLE_ENTRY_LOW_26__Remote_IRR_26__SHIFT 0xe
+#define REDIRECTION_TABLE_ENTRY_LOW_26__Trigger_Mode_26__SHIFT 0xf
+#define REDIRECTION_TABLE_ENTRY_LOW_26__Mask_26__SHIFT 0x10
+#define REDIRECTION_TABLE_ENTRY_LOW_26__Vector_26_MASK 0x000000FFL
+#define REDIRECTION_TABLE_ENTRY_LOW_26__Delivery_Mode_26_MASK 0x00000700L
+#define REDIRECTION_TABLE_ENTRY_LOW_26__Destination_Mode_26_MASK 0x00000800L
+#define REDIRECTION_TABLE_ENTRY_LOW_26__Delivery_status_26_MASK 0x00001000L
+#define REDIRECTION_TABLE_ENTRY_LOW_26__Interrupt_Pin_Polarity_26_MASK 0x00002000L
+#define REDIRECTION_TABLE_ENTRY_LOW_26__Remote_IRR_26_MASK 0x00004000L
+#define REDIRECTION_TABLE_ENTRY_LOW_26__Trigger_Mode_26_MASK 0x00008000L
+#define REDIRECTION_TABLE_ENTRY_LOW_26__Mask_26_MASK 0x00010000L
+//REDIRECTION_TABLE_ENTRY_HIGH_26
+#define REDIRECTION_TABLE_ENTRY_HIGH_26__Destination_id_26__SHIFT 0x18
+#define REDIRECTION_TABLE_ENTRY_HIGH_26__Destination_id_26_MASK 0xFF000000L
+//REDIRECTION_TABLE_ENTRY_LOW_27
+#define REDIRECTION_TABLE_ENTRY_LOW_27__Vector_27__SHIFT 0x0
+#define REDIRECTION_TABLE_ENTRY_LOW_27__Delivery_Mode_27__SHIFT 0x8
+#define REDIRECTION_TABLE_ENTRY_LOW_27__Destination_Mode_27__SHIFT 0xb
+#define REDIRECTION_TABLE_ENTRY_LOW_27__Delivery_status_27__SHIFT 0xc
+#define REDIRECTION_TABLE_ENTRY_LOW_27__Interrupt_Pin_Polarity_27__SHIFT 0xd
+#define REDIRECTION_TABLE_ENTRY_LOW_27__Remote_IRR_27__SHIFT 0xe
+#define REDIRECTION_TABLE_ENTRY_LOW_27__Trigger_Mode_27__SHIFT 0xf
+#define REDIRECTION_TABLE_ENTRY_LOW_27__Mask_27__SHIFT 0x10
+#define REDIRECTION_TABLE_ENTRY_LOW_27__Vector_27_MASK 0x000000FFL
+#define REDIRECTION_TABLE_ENTRY_LOW_27__Delivery_Mode_27_MASK 0x00000700L
+#define REDIRECTION_TABLE_ENTRY_LOW_27__Destination_Mode_27_MASK 0x00000800L
+#define REDIRECTION_TABLE_ENTRY_LOW_27__Delivery_status_27_MASK 0x00001000L
+#define REDIRECTION_TABLE_ENTRY_LOW_27__Interrupt_Pin_Polarity_27_MASK 0x00002000L
+#define REDIRECTION_TABLE_ENTRY_LOW_27__Remote_IRR_27_MASK 0x00004000L
+#define REDIRECTION_TABLE_ENTRY_LOW_27__Trigger_Mode_27_MASK 0x00008000L
+#define REDIRECTION_TABLE_ENTRY_LOW_27__Mask_27_MASK 0x00010000L
+//REDIRECTION_TABLE_ENTRY_HIGH_27
+#define REDIRECTION_TABLE_ENTRY_HIGH_27__Destination_id_27__SHIFT 0x18
+#define REDIRECTION_TABLE_ENTRY_HIGH_27__Destination_id_27_MASK 0xFF000000L
+//REDIRECTION_TABLE_ENTRY_LOW_28
+#define REDIRECTION_TABLE_ENTRY_LOW_28__Vector_28__SHIFT 0x0
+#define REDIRECTION_TABLE_ENTRY_LOW_28__Delivery_Mode_28__SHIFT 0x8
+#define REDIRECTION_TABLE_ENTRY_LOW_28__Destination_Mode_28__SHIFT 0xb
+#define REDIRECTION_TABLE_ENTRY_LOW_28__Delivery_status_28__SHIFT 0xc
+#define REDIRECTION_TABLE_ENTRY_LOW_28__Interrupt_Pin_Polarity_28__SHIFT 0xd
+#define REDIRECTION_TABLE_ENTRY_LOW_28__Remote_IRR_28__SHIFT 0xe
+#define REDIRECTION_TABLE_ENTRY_LOW_28__Trigger_Mode_28__SHIFT 0xf
+#define REDIRECTION_TABLE_ENTRY_LOW_28__Mask_28__SHIFT 0x10
+#define REDIRECTION_TABLE_ENTRY_LOW_28__Vector_28_MASK 0x000000FFL
+#define REDIRECTION_TABLE_ENTRY_LOW_28__Delivery_Mode_28_MASK 0x00000700L
+#define REDIRECTION_TABLE_ENTRY_LOW_28__Destination_Mode_28_MASK 0x00000800L
+#define REDIRECTION_TABLE_ENTRY_LOW_28__Delivery_status_28_MASK 0x00001000L
+#define REDIRECTION_TABLE_ENTRY_LOW_28__Interrupt_Pin_Polarity_28_MASK 0x00002000L
+#define REDIRECTION_TABLE_ENTRY_LOW_28__Remote_IRR_28_MASK 0x00004000L
+#define REDIRECTION_TABLE_ENTRY_LOW_28__Trigger_Mode_28_MASK 0x00008000L
+#define REDIRECTION_TABLE_ENTRY_LOW_28__Mask_28_MASK 0x00010000L
+//REDIRECTION_TABLE_ENTRY_HIGH_28
+#define REDIRECTION_TABLE_ENTRY_HIGH_28__Destination_id_28__SHIFT 0x18
+#define REDIRECTION_TABLE_ENTRY_HIGH_28__Destination_id_28_MASK 0xFF000000L
+//REDIRECTION_TABLE_ENTRY_LOW_29
+#define REDIRECTION_TABLE_ENTRY_LOW_29__Vector_29__SHIFT 0x0
+#define REDIRECTION_TABLE_ENTRY_LOW_29__Delivery_Mode_29__SHIFT 0x8
+#define REDIRECTION_TABLE_ENTRY_LOW_29__Destination_Mode_29__SHIFT 0xb
+#define REDIRECTION_TABLE_ENTRY_LOW_29__Delivery_status_29__SHIFT 0xc
+#define REDIRECTION_TABLE_ENTRY_LOW_29__Interrupt_Pin_Polarity_29__SHIFT 0xd
+#define REDIRECTION_TABLE_ENTRY_LOW_29__Remote_IRR_29__SHIFT 0xe
+#define REDIRECTION_TABLE_ENTRY_LOW_29__Trigger_Mode_29__SHIFT 0xf
+#define REDIRECTION_TABLE_ENTRY_LOW_29__Mask_29__SHIFT 0x10
+#define REDIRECTION_TABLE_ENTRY_LOW_29__Vector_29_MASK 0x000000FFL
+#define REDIRECTION_TABLE_ENTRY_LOW_29__Delivery_Mode_29_MASK 0x00000700L
+#define REDIRECTION_TABLE_ENTRY_LOW_29__Destination_Mode_29_MASK 0x00000800L
+#define REDIRECTION_TABLE_ENTRY_LOW_29__Delivery_status_29_MASK 0x00001000L
+#define REDIRECTION_TABLE_ENTRY_LOW_29__Interrupt_Pin_Polarity_29_MASK 0x00002000L
+#define REDIRECTION_TABLE_ENTRY_LOW_29__Remote_IRR_29_MASK 0x00004000L
+#define REDIRECTION_TABLE_ENTRY_LOW_29__Trigger_Mode_29_MASK 0x00008000L
+#define REDIRECTION_TABLE_ENTRY_LOW_29__Mask_29_MASK 0x00010000L
+//REDIRECTION_TABLE_ENTRY_HIGH_29
+#define REDIRECTION_TABLE_ENTRY_HIGH_29__Destination_id_29__SHIFT 0x18
+#define REDIRECTION_TABLE_ENTRY_HIGH_29__Destination_id_29_MASK 0xFF000000L
+//REDIRECTION_TABLE_ENTRY_LOW_30
+#define REDIRECTION_TABLE_ENTRY_LOW_30__Vector_30__SHIFT 0x0
+#define REDIRECTION_TABLE_ENTRY_LOW_30__Delivery_Mode_30__SHIFT 0x8
+#define REDIRECTION_TABLE_ENTRY_LOW_30__Destination_Mode_30__SHIFT 0xb
+#define REDIRECTION_TABLE_ENTRY_LOW_30__Delivery_status_30__SHIFT 0xc
+#define REDIRECTION_TABLE_ENTRY_LOW_30__Interrupt_Pin_Polarity_30__SHIFT 0xd
+#define REDIRECTION_TABLE_ENTRY_LOW_30__Remote_IRR_30__SHIFT 0xe
+#define REDIRECTION_TABLE_ENTRY_LOW_30__Trigger_Mode_30__SHIFT 0xf
+#define REDIRECTION_TABLE_ENTRY_LOW_30__Mask_30__SHIFT 0x10
+#define REDIRECTION_TABLE_ENTRY_LOW_30__Vector_30_MASK 0x000000FFL
+#define REDIRECTION_TABLE_ENTRY_LOW_30__Delivery_Mode_30_MASK 0x00000700L
+#define REDIRECTION_TABLE_ENTRY_LOW_30__Destination_Mode_30_MASK 0x00000800L
+#define REDIRECTION_TABLE_ENTRY_LOW_30__Delivery_status_30_MASK 0x00001000L
+#define REDIRECTION_TABLE_ENTRY_LOW_30__Interrupt_Pin_Polarity_30_MASK 0x00002000L
+#define REDIRECTION_TABLE_ENTRY_LOW_30__Remote_IRR_30_MASK 0x00004000L
+#define REDIRECTION_TABLE_ENTRY_LOW_30__Trigger_Mode_30_MASK 0x00008000L
+#define REDIRECTION_TABLE_ENTRY_LOW_30__Mask_30_MASK 0x00010000L
+//REDIRECTION_TABLE_ENTRY_HIGH_30
+#define REDIRECTION_TABLE_ENTRY_HIGH_30__Destination_id_30__SHIFT 0x18
+#define REDIRECTION_TABLE_ENTRY_HIGH_30__Destination_id_30_MASK 0xFF000000L
+//REDIRECTION_TABLE_ENTRY_LOW_31
+#define REDIRECTION_TABLE_ENTRY_LOW_31__Vector_31__SHIFT 0x0
+#define REDIRECTION_TABLE_ENTRY_LOW_31__Delivery_Mode_31__SHIFT 0x8
+#define REDIRECTION_TABLE_ENTRY_LOW_31__Destination_Mode_31__SHIFT 0xb
+#define REDIRECTION_TABLE_ENTRY_LOW_31__Delivery_status_31__SHIFT 0xc
+#define REDIRECTION_TABLE_ENTRY_LOW_31__Interrupt_Pin_Polarity_31__SHIFT 0xd
+#define REDIRECTION_TABLE_ENTRY_LOW_31__Remote_IRR_31__SHIFT 0xe
+#define REDIRECTION_TABLE_ENTRY_LOW_31__Trigger_Mode_31__SHIFT 0xf
+#define REDIRECTION_TABLE_ENTRY_LOW_31__Mask_31__SHIFT 0x10
+#define REDIRECTION_TABLE_ENTRY_LOW_31__Vector_31_MASK 0x000000FFL
+#define REDIRECTION_TABLE_ENTRY_LOW_31__Delivery_Mode_31_MASK 0x00000700L
+#define REDIRECTION_TABLE_ENTRY_LOW_31__Destination_Mode_31_MASK 0x00000800L
+#define REDIRECTION_TABLE_ENTRY_LOW_31__Delivery_status_31_MASK 0x00001000L
+#define REDIRECTION_TABLE_ENTRY_LOW_31__Interrupt_Pin_Polarity_31_MASK 0x00002000L
+#define REDIRECTION_TABLE_ENTRY_LOW_31__Remote_IRR_31_MASK 0x00004000L
+#define REDIRECTION_TABLE_ENTRY_LOW_31__Trigger_Mode_31_MASK 0x00008000L
+#define REDIRECTION_TABLE_ENTRY_LOW_31__Mask_31_MASK 0x00010000L
+//REDIRECTION_TABLE_ENTRY_HIGH_31
+#define REDIRECTION_TABLE_ENTRY_HIGH_31__Destination_id_31__SHIFT 0x18
+#define REDIRECTION_TABLE_ENTRY_HIGH_31__Destination_id_31_MASK 0xFF000000L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp
+//BIF_CFG_DEV0_RC1_VENDOR_ID
+#define BIF_CFG_DEV0_RC1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC1_DEVICE_ID
+#define BIF_CFG_DEV0_RC1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC1_COMMAND
+#define BIF_CFG_DEV0_RC1_COMMAND__IOEN_DN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_COMMAND__MEMEN_DN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_RC1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_RC1_COMMAND__IOEN_DN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC1_COMMAND__MEMEN_DN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_RC1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_RC1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_RC1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_RC1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_RC1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_RC1_STATUS
+#define BIF_CFG_DEV0_RC1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_RC1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_RC1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_RC1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_RC1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_RC1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_RC1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_RC1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_RC1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_RC1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_RC1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_RC1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_RC1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_RC1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_RC1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_RC1_REVISION_ID
+#define BIF_CFG_DEV0_RC1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_RC1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_RC1_PROG_INTERFACE
+#define BIF_CFG_DEV0_RC1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_RC1_SUB_CLASS
+#define BIF_CFG_DEV0_RC1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_RC1_BASE_CLASS
+#define BIF_CFG_DEV0_RC1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_RC1_CACHE_LINE
+#define BIF_CFG_DEV0_RC1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_RC1_LATENCY
+#define BIF_CFG_DEV0_RC1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_RC1_HEADER
+#define BIF_CFG_DEV0_RC1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_RC1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_RC1_BIST
+#define BIF_CFG_DEV0_RC1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_RC1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_RC1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_RC1_BASE_ADDR_1
+#define BIF_CFG_DEV0_RC1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY
+#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC1_IO_BASE_LIMIT
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIF_CFG_DEV0_RC1_SECONDARY_STATUS
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT
+#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT
+#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC1_PREF_BASE_UPPER
+#define BIF_CFG_DEV0_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER
+#define BIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_RC1_CAP_PTR
+#define BIF_CFG_DEV0_RC1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_RC1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_RC1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_RC1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_RC1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+//BIF_CFG_DEV0_RC1_EXT_BRIDGE_CNTL
+#define BIF_CFG_DEV0_RC1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIF_CFG_DEV0_RC1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_RC1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_RC1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_PMI_CAP
+#define BIF_CFG_DEV0_RC1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_RC1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_RC1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_RC1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_RC1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_RC1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_RC1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_RC1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_RC1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_PCIE_CAP
+#define BIF_CFG_DEV0_RC1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_RC1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_RC1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_RC1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_RC1_DEVICE_CAP
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_RC1_DEVICE_CNTL
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIF_CFG_DEV0_RC1_DEVICE_STATUS
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_RC1_LINK_CAP
+#define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_RC1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_RC1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_RC1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_RC1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_RC1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_RC1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC1_LINK_CNTL
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_RC1_LINK_STATUS
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_RC1_SLOT_CAP
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIF_CFG_DEV0_RC1_SLOT_CNTL
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+//BIF_CFG_DEV0_RC1_SLOT_STATUS
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIF_CFG_DEV0_RC1_ROOT_CNTL
+#define BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIF_CFG_DEV0_RC1_ROOT_CAP
+#define BIF_CFG_DEV0_RC1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIF_CFG_DEV0_RC1_ROOT_STATUS
+#define BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIF_CFG_DEV0_RC1_DEVICE_CAP2
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_RC1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_RC1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC1_LINK_CAP2
+#define BIF_CFG_DEV0_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_RC1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_RC1_LINK_CNTL2
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_RC1_LINK_STATUS2
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_RC1_SLOT_CAP2
+#define BIF_CFG_DEV0_RC1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_SLOT_CNTL2
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC1_SLOT_STATUS2
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_RC1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_RC1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_RC1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_RC1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_RC1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_RC1_SSID_CAP_LIST
+#define BIF_CFG_DEV0_RC1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_RC1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_SSID_CAP
+#define BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST
+#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_MSI_MAP_CAP
+#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIF_CFG_DEV0_RC1_MSI_MAP_ADDR_LO
+#define BIF_CFG_DEV0_RC1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define BIF_CFG_DEV0_RC1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC1_MSI_MAP_ADDR_HI
+#define BIF_CFG_DEV0_RC1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_RC1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID
+#define BIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp
+//BIF_CFG_DEV1_RC1_VENDOR_ID
+#define BIF_CFG_DEV1_RC1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC1_DEVICE_ID
+#define BIF_CFG_DEV1_RC1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC1_COMMAND
+#define BIF_CFG_DEV1_RC1_COMMAND__IOEN_DN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_COMMAND__MEMEN_DN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_RC1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV1_RC1_COMMAND__IOEN_DN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC1_COMMAND__MEMEN_DN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_RC1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_RC1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV1_RC1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_RC1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_RC1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV1_RC1_STATUS
+#define BIF_CFG_DEV1_RC1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV1_RC1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV1_RC1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV1_RC1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV1_RC1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV1_RC1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV1_RC1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_RC1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV1_RC1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV1_RC1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV1_RC1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV1_RC1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV1_RC1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV1_RC1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV1_RC1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV1_RC1_REVISION_ID
+#define BIF_CFG_DEV1_RC1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV1_RC1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV1_RC1_PROG_INTERFACE
+#define BIF_CFG_DEV1_RC1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV1_RC1_SUB_CLASS
+#define BIF_CFG_DEV1_RC1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_RC1_BASE_CLASS
+#define BIF_CFG_DEV1_RC1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_RC1_CACHE_LINE
+#define BIF_CFG_DEV1_RC1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV1_RC1_LATENCY
+#define BIF_CFG_DEV1_RC1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV1_RC1_HEADER
+#define BIF_CFG_DEV1_RC1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV1_RC1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV1_RC1_BIST
+#define BIF_CFG_DEV1_RC1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV1_RC1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV1_RC1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV1_RC1_BASE_ADDR_1
+#define BIF_CFG_DEV1_RC1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY
+#define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC1_IO_BASE_LIMIT
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIF_CFG_DEV1_RC1_SECONDARY_STATUS
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT
+#define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT
+#define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC1_PREF_BASE_UPPER
+#define BIF_CFG_DEV1_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PREF_LIMIT_UPPER
+#define BIF_CFG_DEV1_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_RC1_CAP_PTR
+#define BIF_CFG_DEV1_RC1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV1_RC1_INTERRUPT_LINE
+#define BIF_CFG_DEV1_RC1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV1_RC1_INTERRUPT_PIN
+#define BIF_CFG_DEV1_RC1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+//BIF_CFG_DEV1_RC1_EXT_BRIDGE_CNTL
+#define BIF_CFG_DEV1_RC1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIF_CFG_DEV1_RC1_PMI_CAP_LIST
+#define BIF_CFG_DEV1_RC1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_RC1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_PMI_CAP
+#define BIF_CFG_DEV1_RC1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV1_RC1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_RC1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV1_RC1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV1_RC1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV1_RC1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV1_RC1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV1_RC1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV1_RC1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC1_PCIE_CAP_LIST
+#define BIF_CFG_DEV1_RC1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_RC1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_PCIE_CAP
+#define BIF_CFG_DEV1_RC1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV1_RC1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV1_RC1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV1_RC1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV1_RC1_DEVICE_CAP
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV1_RC1_DEVICE_CNTL
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIF_CFG_DEV1_RC1_DEVICE_STATUS
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV1_RC1_LINK_CAP
+#define BIF_CFG_DEV1_RC1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_RC1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV1_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV1_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV1_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV1_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV1_RC1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV1_RC1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_RC1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV1_RC1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV1_RC1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV1_RC1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV1_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV1_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV1_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV1_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV1_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV1_RC1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC1_LINK_CNTL
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV1_RC1_LINK_STATUS
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV1_RC1_SLOT_CAP
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIF_CFG_DEV1_RC1_SLOT_CNTL
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+//BIF_CFG_DEV1_RC1_SLOT_STATUS
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIF_CFG_DEV1_RC1_ROOT_CNTL
+#define BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIF_CFG_DEV1_RC1_ROOT_CAP
+#define BIF_CFG_DEV1_RC1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIF_CFG_DEV1_RC1_ROOT_STATUS
+#define BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIF_CFG_DEV1_RC1_DEVICE_CAP2
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV1_RC1_DEVICE_CNTL2
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV1_RC1_DEVICE_STATUS2
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC1_LINK_CAP2
+#define BIF_CFG_DEV1_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV1_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV1_RC1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV1_RC1_LINK_CNTL2
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV1_RC1_LINK_STATUS2
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV1_RC1_SLOT_CAP2
+#define BIF_CFG_DEV1_RC1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_SLOT_CNTL2
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC1_SLOT_STATUS2
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC1_MSI_CAP_LIST
+#define BIF_CFG_DEV1_RC1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_RC1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_MSI_MSG_CNTL
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_MSI_MSG_DATA
+#define BIF_CFG_DEV1_RC1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_RC1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV1_RC1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_RC1_SSID_CAP_LIST
+#define BIF_CFG_DEV1_RC1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_RC1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_SSID_CAP
+#define BIF_CFG_DEV1_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST
+#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_MSI_MAP_CAP
+#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIF_CFG_DEV1_RC1_MSI_MAP_ADDR_LO
+#define BIF_CFG_DEV1_RC1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define BIF_CFG_DEV1_RC1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC1_MSI_MAP_ADDR_HI
+#define BIF_CFG_DEV1_RC1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV1_RC1_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV1_RC1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID
+#define BIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV1_RC1_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC1_PCIE_ACS_CAP
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC
+//BIF_BX_PF0_MM_INDEX
+#define BIF_BX_PF0_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_PF0_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_PF0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_PF0_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_PF0_MM_DATA
+#define BIF_BX_PF0_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_PF0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_MM_INDEX_HI
+#define BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_SYSDEC
+//BIF_BX_PF0_SYSHUB_INDEX_OVLP
+#define BIF_BX_PF0_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__SHIFT 0x0
+#define BIF_BX_PF0_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET_MASK 0x003FFFFFL
+//BIF_BX_PF0_SYSHUB_DATA_OVLP
+#define BIF_BX_PF0_SYSHUB_DATA_OVLP__SYSHUB_DATA__SHIFT 0x0
+#define BIF_BX_PF0_SYSHUB_DATA_OVLP__SYSHUB_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_PCIE_INDEX
+#define BIF_BX_PF0_PCIE_INDEX__PCIE_INDEX__SHIFT 0x0
+#define BIF_BX_PF0_PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_PCIE_DATA
+#define BIF_BX_PF0_PCIE_DATA__PCIE_DATA__SHIFT 0x0
+#define BIF_BX_PF0_PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_PCIE_INDEX2
+#define BIF_BX_PF0_PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0
+#define BIF_BX_PF0_PCIE_INDEX2__PCIE_INDEX2_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_PCIE_DATA2
+#define BIF_BX_PF0_PCIE_DATA2__PCIE_DATA2__SHIFT 0x0
+#define BIF_BX_PF0_PCIE_DATA2__PCIE_DATA2_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_SBIOS_SCRATCH_0
+#define BIF_BX_PF0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define BIF_BX_PF0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_SBIOS_SCRATCH_1
+#define BIF_BX_PF0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define BIF_BX_PF0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_SBIOS_SCRATCH_2
+#define BIF_BX_PF0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define BIF_BX_PF0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_SBIOS_SCRATCH_3
+#define BIF_BX_PF0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define BIF_BX_PF0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_BIOS_SCRATCH_0
+#define BIF_BX_PF0_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0
+#define BIF_BX_PF0_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_BIOS_SCRATCH_1
+#define BIF_BX_PF0_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0
+#define BIF_BX_PF0_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_BIOS_SCRATCH_2
+#define BIF_BX_PF0_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0
+#define BIF_BX_PF0_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_BIOS_SCRATCH_3
+#define BIF_BX_PF0_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0
+#define BIF_BX_PF0_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_BIOS_SCRATCH_4
+#define BIF_BX_PF0_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0
+#define BIF_BX_PF0_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_BIOS_SCRATCH_5
+#define BIF_BX_PF0_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0
+#define BIF_BX_PF0_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_BIOS_SCRATCH_6
+#define BIF_BX_PF0_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0
+#define BIF_BX_PF0_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_BIOS_SCRATCH_7
+#define BIF_BX_PF0_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0
+#define BIF_BX_PF0_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_BIOS_SCRATCH_8
+#define BIF_BX_PF0_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0
+#define BIF_BX_PF0_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_BIOS_SCRATCH_9
+#define BIF_BX_PF0_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0
+#define BIF_BX_PF0_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_BIOS_SCRATCH_10
+#define BIF_BX_PF0_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0
+#define BIF_BX_PF0_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_BIOS_SCRATCH_11
+#define BIF_BX_PF0_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0
+#define BIF_BX_PF0_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_BIOS_SCRATCH_12
+#define BIF_BX_PF0_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0
+#define BIF_BX_PF0_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_BIOS_SCRATCH_13
+#define BIF_BX_PF0_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0
+#define BIF_BX_PF0_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_BIOS_SCRATCH_14
+#define BIF_BX_PF0_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0
+#define BIF_BX_PF0_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_BIOS_SCRATCH_15
+#define BIF_BX_PF0_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0
+#define BIF_BX_PF0_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_BIF_RLC_INTR_CNTL
+#define BIF_BX_PF0_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT 0x0
+#define BIF_BX_PF0_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT 0x1
+#define BIF_BX_PF0_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT 0x2
+#define BIF_BX_PF0_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT 0x3
+#define BIF_BX_PF0_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE_MASK 0x00000001L
+#define BIF_BX_PF0_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED_MASK 0x00000002L
+#define BIF_BX_PF0_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR_MASK 0x00000004L
+#define BIF_BX_PF0_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION_MASK 0x00000008L
+//BIF_BX_PF0_BIF_VCE_INTR_CNTL
+#define BIF_BX_PF0_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT 0x0
+#define BIF_BX_PF0_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT 0x1
+#define BIF_BX_PF0_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT 0x2
+#define BIF_BX_PF0_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT 0x3
+#define BIF_BX_PF0_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE_MASK 0x00000001L
+#define BIF_BX_PF0_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED_MASK 0x00000002L
+#define BIF_BX_PF0_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR_MASK 0x00000004L
+#define BIF_BX_PF0_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION_MASK 0x00000008L
+//BIF_BX_PF0_BIF_UVD_INTR_CNTL
+#define BIF_BX_PF0_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT 0x0
+#define BIF_BX_PF0_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT 0x1
+#define BIF_BX_PF0_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT 0x2
+#define BIF_BX_PF0_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT 0x3
+#define BIF_BX_PF0_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE_MASK 0x00000001L
+#define BIF_BX_PF0_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED_MASK 0x00000002L
+#define BIF_BX_PF0_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR_MASK 0x00000004L
+#define BIF_BX_PF0_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION_MASK 0x00000008L
+//BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR0
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000FFFFFL
+//BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR0
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000FFFFFL
+//BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR1
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000FFFFFL
+//BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR1
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000FFFFFL
+//BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR2
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000FFFFFL
+//BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR2
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000FFFFFL
+//BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR3
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000FFFFFL
+//BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR3
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000FFFFFL
+//BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR4
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000FFFFFL
+//BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR4
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000FFFFFL
+//BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR5
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000FFFFFL
+//BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR5
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000FFFFFL
+//BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR6
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000FFFFFL
+//BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR6
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000FFFFFL
+//BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR7
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000FFFFFL
+//BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR7
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000FFFFFL
+//BIF_BX_PF0_GFX_MMIOREG_CAM_CNTL
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000FFL
+//BIF_BX_PF0_GFX_MMIOREG_CAM_ZERO_CPL
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_GFX_MMIOREG_CAM_ONE_CPL
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0
+#define BIF_BX_PF0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1
+//RCC_EP_DEV0_0_EP_PCIE_SCRATCH
+#define RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//RCC_EP_DEV0_0_EP_PCIE_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//RCC_EP_DEV0_0_EP_PCIE_INT_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L
+//RCC_EP_DEV0_0_EP_PCIE_INT_STATUS
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L
+//RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L
+//RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+//RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+//RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL
+#define RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL
+//RCC_EP_DEV0_0_EP_PCIEP_RESERVED
+#define RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL
+//RCC_EP_DEV0_0_EP_PCIE_TX_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L
+//RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L
+//RCC_EP_DEV0_0_EP_PCIE_RX_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+//RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+
+
+// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1
+//RCC_DWN_DEV0_0_DN_PCIE_RESERVED
+#define RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
+#define RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DWN_DEV0_0_DN_PCIE_SCRATCH
+#define RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//RCC_DWN_DEV0_0_DN_PCIE_CNTL
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL
+#define RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
+#define RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L
+//RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2
+#define RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
+#define RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L
+//RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL
+#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8
+#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L
+//RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1
+//RCC_DWNP_DEV0_0_PCIE_ERR_CNTL
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+//RCC_DWNP_DEV0_0_PCIE_RX_CNTL
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+//RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+//RCC_DWNP_DEV0_0_PCIE_LC_CNTL2
+#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+//RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC
+#define RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa
+#define RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L
+//RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP
+#define RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0
+#define RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_BIFDEC1
+//BIF_BX_PF0_BIF_MM_INDACCESS_CNTL
+#define BIF_BX_PF0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
+#define BIF_BX_PF0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L
+//BIF_BX_PF0_BUS_CNTL
+#define BIF_BX_PF0_BUS_CNTL__PMI_INT_DIS_EP__SHIFT 0x3
+#define BIF_BX_PF0_BUS_CNTL__PMI_INT_DIS_DN__SHIFT 0x4
+#define BIF_BX_PF0_BUS_CNTL__PMI_INT_DIS_SWUS__SHIFT 0x5
+#define BIF_BX_PF0_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6
+#define BIF_BX_PF0_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7
+#define BIF_BX_PF0_BUS_CNTL__SET_AZ_TC__SHIFT 0xa
+#define BIF_BX_PF0_BUS_CNTL__SET_MC_TC__SHIFT 0xd
+#define BIF_BX_PF0_BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10
+#define BIF_BX_PF0_BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11
+#define BIF_BX_PF0_BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12
+#define BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT 0x13
+#define BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT 0x14
+#define BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT 0x15
+#define BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT 0x16
+#define BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT 0x17
+#define BIF_BX_PF0_BUS_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT 0x18
+#define BIF_BX_PF0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT 0x19
+#define BIF_BX_PF0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT 0x1a
+#define BIF_BX_PF0_BUS_CNTL__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT 0x1b
+#define BIF_BX_PF0_BUS_CNTL__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT 0x1c
+#define BIF_BX_PF0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT 0x1d
+#define BIF_BX_PF0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT 0x1e
+#define BIF_BX_PF0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT 0x1f
+#define BIF_BX_PF0_BUS_CNTL__PMI_INT_DIS_EP_MASK 0x00000008L
+#define BIF_BX_PF0_BUS_CNTL__PMI_INT_DIS_DN_MASK 0x00000010L
+#define BIF_BX_PF0_BUS_CNTL__PMI_INT_DIS_SWUS_MASK 0x00000020L
+#define BIF_BX_PF0_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L
+#define BIF_BX_PF0_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L
+#define BIF_BX_PF0_BUS_CNTL__SET_AZ_TC_MASK 0x00001C00L
+#define BIF_BX_PF0_BUS_CNTL__SET_MC_TC_MASK 0x0000E000L
+#define BIF_BX_PF0_BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L
+#define BIF_BX_PF0_BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L
+#define BIF_BX_PF0_BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L
+#define BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK 0x00080000L
+#define BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK 0x00100000L
+#define BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK 0x00200000L
+#define BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK 0x00400000L
+#define BIF_BX_PF0_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK 0x00800000L
+#define BIF_BX_PF0_BUS_CNTL__UR_OVRD_FOR_ECRC_EN_MASK 0x01000000L
+#define BIF_BX_PF0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK 0x02000000L
+#define BIF_BX_PF0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK 0x04000000L
+#define BIF_BX_PF0_BUS_CNTL__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK 0x08000000L
+#define BIF_BX_PF0_BUS_CNTL__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK 0x10000000L
+#define BIF_BX_PF0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK 0x20000000L
+#define BIF_BX_PF0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK 0x40000000L
+#define BIF_BX_PF0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK 0x80000000L
+//BIF_BX_PF0_BIF_SCRATCH0
+#define BIF_BX_PF0_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0
+#define BIF_BX_PF0_BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_BIF_SCRATCH1
+#define BIF_BX_PF0_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0
+#define BIF_BX_PF0_BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_BX_RESET_EN
+#define BIF_BX_PF0_BX_RESET_EN__COR_RESET_EN__SHIFT 0x0
+#define BIF_BX_PF0_BX_RESET_EN__REG_RESET_EN__SHIFT 0x1
+#define BIF_BX_PF0_BX_RESET_EN__STY_RESET_EN__SHIFT 0x2
+#define BIF_BX_PF0_BX_RESET_EN__FLR_TWICE_EN__SHIFT 0x8
+#define BIF_BX_PF0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10
+#define BIF_BX_PF0_BX_RESET_EN__COR_RESET_EN_MASK 0x00000001L
+#define BIF_BX_PF0_BX_RESET_EN__REG_RESET_EN_MASK 0x00000002L
+#define BIF_BX_PF0_BX_RESET_EN__STY_RESET_EN_MASK 0x00000004L
+#define BIF_BX_PF0_BX_RESET_EN__FLR_TWICE_EN_MASK 0x00000100L
+#define BIF_BX_PF0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L
+//BIF_BX_PF0_MM_CFGREGS_CNTL
+#define BIF_BX_PF0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0
+#define BIF_BX_PF0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6
+#define BIF_BX_PF0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f
+#define BIF_BX_PF0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L
+#define BIF_BX_PF0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000C0L
+#define BIF_BX_PF0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L
+//BIF_BX_PF0_BX_RESET_CNTL
+#define BIF_BX_PF0_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0
+#define BIF_BX_PF0_BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L
+//BIF_BX_PF0_INTERRUPT_CNTL
+#define BIF_BX_PF0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0
+#define BIF_BX_PF0_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1
+#define BIF_BX_PF0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3
+#define BIF_BX_PF0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4
+#define BIF_BX_PF0_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8
+#define BIF_BX_PF0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf
+#define BIF_BX_PF0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10
+#define BIF_BX_PF0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11
+#define BIF_BX_PF0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L
+#define BIF_BX_PF0_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L
+#define BIF_BX_PF0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L
+#define BIF_BX_PF0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L
+#define BIF_BX_PF0_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L
+#define BIF_BX_PF0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L
+#define BIF_BX_PF0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L
+#define BIF_BX_PF0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L
+//BIF_BX_PF0_INTERRUPT_CNTL2
+#define BIF_BX_PF0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0
+#define BIF_BX_PF0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_CLKREQB_PAD_CNTL
+#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0
+#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1
+#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2
+#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3
+#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5
+#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6
+#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7
+#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8
+#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9
+#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa
+#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb
+#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc
+#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd
+#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L
+#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L
+#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L
+#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L
+#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L
+#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L
+#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L
+#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L
+#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L
+#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L
+#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L
+#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L
+#define BIF_BX_PF0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L
+//BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC
+#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0
+#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1
+#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2
+#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3
+#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc
+#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd
+#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf
+#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__SHIFT 0x11
+#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__SHIFT 0x12
+#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x18
+#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L
+#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L
+#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L
+#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L
+#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L
+#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L
+#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L
+#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS_MASK 0x00020000L
+#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS_MASK 0x00040000L
+#define BIF_BX_PF0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK 0x01000000L
+//BIF_BX_PF0_BIF_DOORBELL_CNTL
+#define BIF_BX_PF0_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0
+#define BIF_BX_PF0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1
+#define BIF_BX_PF0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2
+#define BIF_BX_PF0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3
+#define BIF_BX_PF0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4
+#define BIF_BX_PF0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18
+#define BIF_BX_PF0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19
+#define BIF_BX_PF0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a
+#define BIF_BX_PF0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b
+#define BIF_BX_PF0_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L
+#define BIF_BX_PF0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L
+#define BIF_BX_PF0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L
+#define BIF_BX_PF0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L
+#define BIF_BX_PF0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L
+#define BIF_BX_PF0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L
+#define BIF_BX_PF0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L
+#define BIF_BX_PF0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L
+#define BIF_BX_PF0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L
+//BIF_BX_PF0_BIF_DOORBELL_INT_CNTL
+#define BIF_BX_PF0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0
+#define BIF_BX_PF0_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS__SHIFT 0x1
+#define BIF_BX_PF0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10
+#define BIF_BX_PF0_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR__SHIFT 0x11
+#define BIF_BX_PF0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L
+#define BIF_BX_PF0_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS_MASK 0x00000002L
+#define BIF_BX_PF0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L
+#define BIF_BX_PF0_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR_MASK 0x00020000L
+//BIF_BX_PF0_BIF_FB_EN
+#define BIF_BX_PF0_BIF_FB_EN__FB_READ_EN__SHIFT 0x0
+#define BIF_BX_PF0_BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1
+#define BIF_BX_PF0_BIF_FB_EN__FB_READ_EN_MASK 0x00000001L
+#define BIF_BX_PF0_BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L
+//BIF_BX_PF0_BIF_BUSY_DELAY_CNTR
+#define BIF_BX_PF0_BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0
+#define BIF_BX_PF0_BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x0000003FL
+//BIF_BX_PF0_BIF_MST_TRANS_PENDING_VF
+#define BIF_BX_PF0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_PF0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x0000FFFFL
+//BIF_BX_PF0_BIF_SLV_TRANS_PENDING_VF
+#define BIF_BX_PF0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_PF0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x0000FFFFL
+//BIF_BX_PF0_BACO_CNTL
+#define BIF_BX_PF0_BACO_CNTL__BACO_EN__SHIFT 0x0
+#define BIF_BX_PF0_BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT 0x1
+#define BIF_BX_PF0_BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2
+#define BIF_BX_PF0_BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3
+#define BIF_BX_PF0_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5
+#define BIF_BX_PF0_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6
+#define BIF_BX_PF0_BACO_CNTL__BACO_MODE__SHIFT 0x8
+#define BIF_BX_PF0_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9
+#define BIF_BX_PF0_BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f
+#define BIF_BX_PF0_BACO_CNTL__BACO_EN_MASK 0x00000001L
+#define BIF_BX_PF0_BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK 0x00000002L
+#define BIF_BX_PF0_BACO_CNTL__BACO_DUMMY_EN_MASK 0x00000004L
+#define BIF_BX_PF0_BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L
+#define BIF_BX_PF0_BACO_CNTL__BACO_DSTATE_BYPASS_MASK 0x00000020L
+#define BIF_BX_PF0_BACO_CNTL__BACO_RST_INTR_MASK_MASK 0x00000040L
+#define BIF_BX_PF0_BACO_CNTL__BACO_MODE_MASK 0x00000100L
+#define BIF_BX_PF0_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000200L
+#define BIF_BX_PF0_BACO_CNTL__BACO_AUTO_EXIT_MASK 0x80000000L
+//BIF_BX_PF0_BIF_BACO_EXIT_TIME0
+#define BIF_BX_PF0_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0
+#define BIF_BX_PF0_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK 0x000FFFFFL
+//BIF_BX_PF0_BIF_BACO_EXIT_TIMER1
+#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0
+#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT 0x18
+#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR__SHIFT 0x19
+#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a
+#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b
+#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c
+#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d
+#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f
+#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK 0x000FFFFFL
+#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK 0x01000000L
+#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR_MASK 0x02000000L
+#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK 0x04000000L
+#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK 0x08000000L
+#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK 0x10000000L
+#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK 0x60000000L
+#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK 0x80000000L
+//BIF_BX_PF0_BIF_BACO_EXIT_TIMER2
+#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0
+#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK 0x000FFFFFL
+//BIF_BX_PF0_BIF_BACO_EXIT_TIMER3
+#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0
+#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK 0x000FFFFFL
+//BIF_BX_PF0_BIF_BACO_EXIT_TIMER4
+#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0
+#define BIF_BX_PF0_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK 0x000FFFFFL
+//BIF_BX_PF0_MEM_TYPE_CNTL
+#define BIF_BX_PF0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0
+#define BIF_BX_PF0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L
+//BIF_BX_PF0_SMU_BIF_VDDGFX_PWR_STATUS
+#define BIF_BX_PF0_SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT 0x0
+#define BIF_BX_PF0_SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF_MASK 0x00000001L
+//BIF_BX_PF0_BIF_VDDGFX_GFX0_LOWER
+#define BIF_BX_PF0_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2
+#define BIF_BX_PF0_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e
+#define BIF_BX_PF0_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f
+#define BIF_BX_PF0_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_BX_PF0_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN_MASK 0x40000000L
+#define BIF_BX_PF0_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN_MASK 0x80000000L
+//BIF_BX_PF0_BIF_VDDGFX_GFX0_UPPER
+#define BIF_BX_PF0_BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2
+#define BIF_BX_PF0_BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER_MASK 0x0003FFFCL
+//BIF_BX_PF0_BIF_VDDGFX_GFX1_LOWER
+#define BIF_BX_PF0_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2
+#define BIF_BX_PF0_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e
+#define BIF_BX_PF0_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f
+#define BIF_BX_PF0_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_BX_PF0_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN_MASK 0x40000000L
+#define BIF_BX_PF0_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN_MASK 0x80000000L
+//BIF_BX_PF0_BIF_VDDGFX_GFX1_UPPER
+#define BIF_BX_PF0_BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2
+#define BIF_BX_PF0_BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER_MASK 0x0003FFFCL
+//BIF_BX_PF0_BIF_VDDGFX_GFX2_LOWER
+#define BIF_BX_PF0_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2
+#define BIF_BX_PF0_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e
+#define BIF_BX_PF0_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f
+#define BIF_BX_PF0_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_BX_PF0_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN_MASK 0x40000000L
+#define BIF_BX_PF0_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN_MASK 0x80000000L
+//BIF_BX_PF0_BIF_VDDGFX_GFX2_UPPER
+#define BIF_BX_PF0_BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2
+#define BIF_BX_PF0_BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER_MASK 0x0003FFFCL
+//BIF_BX_PF0_BIF_VDDGFX_GFX3_LOWER
+#define BIF_BX_PF0_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2
+#define BIF_BX_PF0_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e
+#define BIF_BX_PF0_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f
+#define BIF_BX_PF0_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_BX_PF0_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN_MASK 0x40000000L
+#define BIF_BX_PF0_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN_MASK 0x80000000L
+//BIF_BX_PF0_BIF_VDDGFX_GFX3_UPPER
+#define BIF_BX_PF0_BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2
+#define BIF_BX_PF0_BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER_MASK 0x0003FFFCL
+//BIF_BX_PF0_BIF_VDDGFX_GFX4_LOWER
+#define BIF_BX_PF0_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2
+#define BIF_BX_PF0_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e
+#define BIF_BX_PF0_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f
+#define BIF_BX_PF0_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_BX_PF0_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN_MASK 0x40000000L
+#define BIF_BX_PF0_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN_MASK 0x80000000L
+//BIF_BX_PF0_BIF_VDDGFX_GFX4_UPPER
+#define BIF_BX_PF0_BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2
+#define BIF_BX_PF0_BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER_MASK 0x0003FFFCL
+//BIF_BX_PF0_BIF_VDDGFX_GFX5_LOWER
+#define BIF_BX_PF0_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2
+#define BIF_BX_PF0_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e
+#define BIF_BX_PF0_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f
+#define BIF_BX_PF0_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_BX_PF0_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK 0x40000000L
+#define BIF_BX_PF0_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN_MASK 0x80000000L
+//BIF_BX_PF0_BIF_VDDGFX_GFX5_UPPER
+#define BIF_BX_PF0_BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2
+#define BIF_BX_PF0_BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER_MASK 0x0003FFFCL
+//BIF_BX_PF0_BIF_VDDGFX_RSV1_LOWER
+#define BIF_BX_PF0_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2
+#define BIF_BX_PF0_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e
+#define BIF_BX_PF0_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f
+#define BIF_BX_PF0_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_BX_PF0_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN_MASK 0x40000000L
+#define BIF_BX_PF0_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN_MASK 0x80000000L
+//BIF_BX_PF0_BIF_VDDGFX_RSV1_UPPER
+#define BIF_BX_PF0_BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2
+#define BIF_BX_PF0_BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER_MASK 0x0003FFFCL
+//BIF_BX_PF0_BIF_VDDGFX_RSV2_LOWER
+#define BIF_BX_PF0_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2
+#define BIF_BX_PF0_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e
+#define BIF_BX_PF0_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f
+#define BIF_BX_PF0_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_BX_PF0_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN_MASK 0x40000000L
+#define BIF_BX_PF0_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN_MASK 0x80000000L
+//BIF_BX_PF0_BIF_VDDGFX_RSV2_UPPER
+#define BIF_BX_PF0_BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2
+#define BIF_BX_PF0_BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER_MASK 0x0003FFFCL
+//BIF_BX_PF0_BIF_VDDGFX_RSV3_LOWER
+#define BIF_BX_PF0_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2
+#define BIF_BX_PF0_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e
+#define BIF_BX_PF0_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f
+#define BIF_BX_PF0_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_BX_PF0_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN_MASK 0x40000000L
+#define BIF_BX_PF0_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN_MASK 0x80000000L
+//BIF_BX_PF0_BIF_VDDGFX_RSV3_UPPER
+#define BIF_BX_PF0_BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2
+#define BIF_BX_PF0_BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER_MASK 0x0003FFFCL
+//BIF_BX_PF0_BIF_VDDGFX_RSV4_LOWER
+#define BIF_BX_PF0_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2
+#define BIF_BX_PF0_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e
+#define BIF_BX_PF0_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f
+#define BIF_BX_PF0_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_BX_PF0_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN_MASK 0x40000000L
+#define BIF_BX_PF0_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN_MASK 0x80000000L
+//BIF_BX_PF0_BIF_VDDGFX_RSV4_UPPER
+#define BIF_BX_PF0_BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2
+#define BIF_BX_PF0_BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER_MASK 0x0003FFFCL
+//BIF_BX_PF0_BIF_VDDGFX_FB_CMP
+#define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0
+#define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1
+#define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2
+#define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3
+#define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4
+#define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5
+#define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN_MASK 0x00000001L
+#define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN_MASK 0x00000002L
+#define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN_MASK 0x00000004L
+#define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN_MASK 0x00000008L
+#define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN_MASK 0x00000010L
+#define BIF_BX_PF0_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN_MASK 0x00000020L
+//BIF_BX_PF0_BIF_DOORBELL_GBLAPER1_LOWER
+#define BIF_BX_PF0_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2
+#define BIF_BX_PF0_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT 0x1f
+#define BIF_BX_PF0_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER_MASK 0x00000FFCL
+#define BIF_BX_PF0_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN_MASK 0x80000000L
+//BIF_BX_PF0_BIF_DOORBELL_GBLAPER1_UPPER
+#define BIF_BX_PF0_BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2
+#define BIF_BX_PF0_BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER_MASK 0x00000FFCL
+//BIF_BX_PF0_BIF_DOORBELL_GBLAPER2_LOWER
+#define BIF_BX_PF0_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2
+#define BIF_BX_PF0_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT 0x1f
+#define BIF_BX_PF0_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER_MASK 0x00000FFCL
+#define BIF_BX_PF0_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN_MASK 0x80000000L
+//BIF_BX_PF0_BIF_DOORBELL_GBLAPER2_UPPER
+#define BIF_BX_PF0_BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2
+#define BIF_BX_PF0_BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER_MASK 0x00000FFCL
+//BIF_BX_PF0_REMAP_HDP_MEM_FLUSH_CNTL
+#define BIF_BX_PF0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2
+#define BIF_BX_PF0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL
+//BIF_BX_PF0_REMAP_HDP_REG_FLUSH_CNTL
+#define BIF_BX_PF0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2
+#define BIF_BX_PF0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL
+//BIF_BX_PF0_BIF_RB_CNTL
+#define BIF_BX_PF0_BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define BIF_BX_PF0_BIF_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define BIF_BX_PF0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
+#define BIF_BX_PF0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9
+#define BIF_BX_PF0_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11
+#define BIF_BX_PF0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
+#define BIF_BX_PF0_BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define BIF_BX_PF0_BIF_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define BIF_BX_PF0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L
+#define BIF_BX_PF0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003E00L
+#define BIF_BX_PF0_BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L
+#define BIF_BX_PF0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L
+//BIF_BX_PF0_BIF_RB_BASE
+#define BIF_BX_PF0_BIF_RB_BASE__ADDR__SHIFT 0x0
+#define BIF_BX_PF0_BIF_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_BIF_RB_RPTR
+#define BIF_BX_PF0_BIF_RB_RPTR__OFFSET__SHIFT 0x2
+#define BIF_BX_PF0_BIF_RB_RPTR__OFFSET_MASK 0x0003FFFCL
+//BIF_BX_PF0_BIF_RB_WPTR
+#define BIF_BX_PF0_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0
+#define BIF_BX_PF0_BIF_RB_WPTR__OFFSET__SHIFT 0x2
+#define BIF_BX_PF0_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L
+#define BIF_BX_PF0_BIF_RB_WPTR__OFFSET_MASK 0x0003FFFCL
+//BIF_BX_PF0_BIF_RB_WPTR_ADDR_HI
+#define BIF_BX_PF0_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define BIF_BX_PF0_BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000FFL
+//BIF_BX_PF0_BIF_RB_WPTR_ADDR_LO
+#define BIF_BX_PF0_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define BIF_BX_PF0_BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//BIF_BX_PF0_MAILBOX_INDEX
+#define BIF_BX_PF0_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0
+#define BIF_BX_PF0_MAILBOX_INDEX__MAILBOX_INDEX_MASK 0x0000001FL
+//BIF_BX_PF0_BIF_UVD_GPUIOV_CFG_SIZE
+#define BIF_BX_PF0_BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE__SHIFT 0x0
+#define BIF_BX_PF0_BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE_MASK 0x0000000FL
+//BIF_BX_PF0_BIF_VCE_GPUIOV_CFG_SIZE
+#define BIF_BX_PF0_BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE__SHIFT 0x0
+#define BIF_BX_PF0_BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE_MASK 0x0000000FL
+//BIF_BX_PF0_BIF_GFX_SDMA_GPUIOV_CFG_SIZE
+#define BIF_BX_PF0_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT 0x0
+#define BIF_BX_PF0_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK 0x0000000FL
+//BIF_BX_PF0_BIF_PERSTB_PAD_CNTL
+#define BIF_BX_PF0_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0
+#define BIF_BX_PF0_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK 0x0000FFFFL
+//BIF_BX_PF0_BIF_PX_EN_PAD_CNTL
+#define BIF_BX_PF0_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0
+#define BIF_BX_PF0_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK 0x000000FFL
+//BIF_BX_PF0_BIF_REFPADKIN_PAD_CNTL
+#define BIF_BX_PF0_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0
+#define BIF_BX_PF0_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK 0x000000FFL
+//BIF_BX_PF0_BIF_CLKREQB_PAD_CNTL
+#define BIF_BX_PF0_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0
+#define BIF_BX_PF0_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK 0x00FFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1
+//BIF_BX_PF0_BIF_BME_STATUS
+#define BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_PF0_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_PF0_GPU_HDP_FLUSH_REQ
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_PF0_GPU_HDP_FLUSH_DONE
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_PF0_BIF_TRANS_PENDING
+#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_MAILBOX_CONTROL
+#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_PF0_MAILBOX_INT_CNTL
+#define BIF_BX_PF0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_PF0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_PF0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_PF0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_PF0_BIF_VMHV_MAILBOX
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_shadow_reg_shadowdec
+//SHADOW_COMMAND
+#define SHADOW_COMMAND__IOEN_UP__SHIFT 0x0
+#define SHADOW_COMMAND__MEMEN_UP__SHIFT 0x1
+#define SHADOW_COMMAND__IOEN_UP_MASK 0x0001L
+#define SHADOW_COMMAND__MEMEN_UP_MASK 0x0002L
+//SHADOW_BASE_ADDR_1
+#define SHADOW_BASE_ADDR_1__BAR1_UP__SHIFT 0x0
+#define SHADOW_BASE_ADDR_1__BAR1_UP_MASK 0xFFFFFFFFL
+//SHADOW_BASE_ADDR_2
+#define SHADOW_BASE_ADDR_2__BAR2_UP__SHIFT 0x0
+#define SHADOW_BASE_ADDR_2__BAR2_UP_MASK 0xFFFFFFFFL
+//SHADOW_SUB_BUS_NUMBER_LATENCY
+#define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP__SHIFT 0x8
+#define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP__SHIFT 0x10
+#define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP_MASK 0x0000FF00L
+#define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP_MASK 0x00FF0000L
+//SHADOW_IO_BASE_LIMIT
+#define SHADOW_IO_BASE_LIMIT__IO_BASE_UP__SHIFT 0x4
+#define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP__SHIFT 0xc
+#define SHADOW_IO_BASE_LIMIT__IO_BASE_UP_MASK 0x00F0L
+#define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP_MASK 0xF000L
+//SHADOW_MEM_BASE_LIMIT
+#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP__SHIFT 0x4
+#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP__SHIFT 0x14
+#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP_MASK 0x0000FFF0L
+#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP_MASK 0xFFF00000L
+//SHADOW_PREF_BASE_LIMIT
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP__SHIFT 0x4
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP__SHIFT 0x14
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP_MASK 0x0000FFF0L
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP_MASK 0xFFF00000L
+//SHADOW_PREF_BASE_UPPER
+#define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP__SHIFT 0x0
+#define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP_MASK 0xFFFFFFFFL
+//SHADOW_PREF_LIMIT_UPPER
+#define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP__SHIFT 0x0
+#define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP_MASK 0xFFFFFFFFL
+//SHADOW_IO_BASE_LIMIT_HI
+#define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP__SHIFT 0x0
+#define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP__SHIFT 0x10
+#define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP_MASK 0x0000FFFFL
+#define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP_MASK 0xFFFF0000L
+//SHADOW_IRQ_BRIDGE_CNTL
+#define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP__SHIFT 0x2
+#define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP__SHIFT 0x3
+#define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP__SHIFT 0x4
+#define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP__SHIFT 0x6
+#define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP_MASK 0x0004L
+#define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP_MASK 0x0008L
+#define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP_MASK 0x0010L
+#define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP_MASK 0x0040L
+//SUC_INDEX
+#define SUC_INDEX__SUC_INDEX__SHIFT 0x0
+#define SUC_INDEX__SUC_INDEX_MASK 0xFFFFFFFFL
+//SUC_DATA
+#define SUC_DATA__SUC_DATA__SHIFT 0x0
+#define SUC_DATA__SUC_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_ep_dev0_RCCPORTDEC
+//RCC_EP_DEV0_1_EP_PCIE_SCRATCH
+#define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//RCC_EP_DEV0_1_EP_PCIE_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//RCC_EP_DEV0_1_EP_PCIE_INT_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L
+//RCC_EP_DEV0_1_EP_PCIE_INT_STATUS
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L
+//RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L
+//RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+//RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+//RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L
+//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL
+#define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL
+//RCC_EP_DEV0_1_EP_PCIEP_RESERVED
+#define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL
+//RCC_EP_DEV0_1_EP_PCIE_TX_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L
+//RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L
+//RCC_EP_DEV0_1_EP_PCIE_RX_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+//RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+
+
+// addressBlock: nbio_nbif0_rcc_dwn_dev0_RCCPORTDEC
+//RCC_DWN_DEV0_1_DN_PCIE_RESERVED
+#define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DWN_DEV0_1_DN_PCIE_SCRATCH
+#define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//RCC_DWN_DEV0_1_DN_PCIE_CNTL
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL
+#define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
+#define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L
+//RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2
+#define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
+#define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L
+//RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL
+#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8
+#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L
+//RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwnp_dev0_RCCPORTDEC
+//RCC_DWNP_DEV0_1_PCIE_ERR_CNTL
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+//RCC_DWNP_DEV0_1_PCIE_RX_CNTL
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+//RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+//RCC_DWNP_DEV0_1_PCIE_LC_CNTL2
+#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+//RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC
+#define RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa
+#define RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L
+//RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP
+#define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0
+#define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_ep_dev1_RCCPORTDEC
+//RCC_EP_DEV1_EP_PCIE_SCRATCH
+#define RCC_EP_DEV1_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define RCC_EP_DEV1_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//RCC_EP_DEV1_EP_PCIE_CNTL
+#define RCC_EP_DEV1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
+#define RCC_EP_DEV1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
+#define RCC_EP_DEV1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define RCC_EP_DEV1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L
+#define RCC_EP_DEV1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L
+#define RCC_EP_DEV1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//RCC_EP_DEV1_EP_PCIE_INT_CNTL
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L
+//RCC_EP_DEV1_EP_PCIE_INT_STATUS
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L
+//RCC_EP_DEV1_EP_PCIE_RX_CNTL2
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L
+//RCC_EP_DEV1_EP_PCIE_BUS_CNTL
+#define RCC_EP_DEV1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define RCC_EP_DEV1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+//RCC_EP_DEV1_EP_PCIE_CFG_CNTL
+#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+//RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L
+//RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//RCC_EP_DEV1_EP_PCIE_F0_DPA_LATENCY_INDICATOR
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L
+//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV1_EP_PCIE_PME_CONTROL
+#define RCC_EP_DEV1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0
+#define RCC_EP_DEV1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL
+//RCC_EP_DEV1_EP_PCIEP_RESERVED
+#define RCC_EP_DEV1_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define RCC_EP_DEV1_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL
+//RCC_EP_DEV1_EP_PCIE_TX_CNTL
+#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18
+#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19
+#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a
+#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L
+#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L
+#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L
+//RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID
+#define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//RCC_EP_DEV1_EP_PCIE_ERR_CNTL
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L
+//RCC_EP_DEV1_EP_PCIE_RX_CNTL
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+//RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL
+#define RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+
+
+// addressBlock: nbio_nbif0_rcc_dwn_dev1_RCCPORTDEC
+//RCC_DWN_DEV1_DN_PCIE_RESERVED
+#define RCC_DWN_DEV1_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
+#define RCC_DWN_DEV1_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DWN_DEV1_DN_PCIE_SCRATCH
+#define RCC_DWN_DEV1_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define RCC_DWN_DEV1_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//RCC_DWN_DEV1_DN_PCIE_CNTL
+#define RCC_DWN_DEV1_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
+#define RCC_DWN_DEV1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7
+#define RCC_DWN_DEV1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define RCC_DWN_DEV1_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L
+#define RCC_DWN_DEV1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L
+#define RCC_DWN_DEV1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//RCC_DWN_DEV1_DN_PCIE_CONFIG_CNTL
+#define RCC_DWN_DEV1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
+#define RCC_DWN_DEV1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L
+//RCC_DWN_DEV1_DN_PCIE_RX_CNTL2
+#define RCC_DWN_DEV1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
+#define RCC_DWN_DEV1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L
+//RCC_DWN_DEV1_DN_PCIE_BUS_CNTL
+#define RCC_DWN_DEV1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define RCC_DWN_DEV1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8
+#define RCC_DWN_DEV1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+#define RCC_DWN_DEV1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L
+//RCC_DWN_DEV1_DN_PCIE_CFG_CNTL
+#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwnp_dev1_RCCPORTDEC
+//RCC_DWNP_DEV1_PCIE_ERR_CNTL
+#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+//RCC_DWNP_DEV1_PCIE_RX_CNTL
+#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9
+#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15
+#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L
+#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L
+#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+//RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL
+#define RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+//RCC_DWNP_DEV1_PCIE_LC_CNTL2
+#define RCC_DWNP_DEV1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define RCC_DWNP_DEV1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+//RCC_DWNP_DEV1_PCIEP_STRAP_MISC
+#define RCC_DWNP_DEV1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa
+#define RCC_DWNP_DEV1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L
+//RCC_DWNP_DEV1_LTR_MSG_INFO_FROM_EP
+#define RCC_DWNP_DEV1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0
+#define RCC_DWNP_DEV1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_strap_rcc_strap_internal
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_SUMDEC
+//SUM_INDEX
+#define SUM_INDEX__SUM_INDEX__SHIFT 0x0
+#define SUM_INDEX__SUM_INDEX_MASK 0xFFFFFFFFL
+//SUM_DATA
+#define SUM_DATA__SUM_DATA__SHIFT 0x0
+#define SUM_DATA__SUM_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_misc_bif_misc_regblk
+//MISC_SCRATCH
+#define MISC_SCRATCH__MISC_SCRATCH0__SHIFT 0x0
+#define MISC_SCRATCH__MISC_SCRATCH0_MASK 0xFFFFFFFFL
+//INTR_LINE_POLARITY
+#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__SHIFT 0x0
+#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV1__SHIFT 0x8
+#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0_MASK 0x000000FFL
+#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV1_MASK 0x0000FF00L
+//INTR_LINE_ENABLE
+#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__SHIFT 0x0
+#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV1__SHIFT 0x8
+#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0_MASK 0x000000FFL
+#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV1_MASK 0x0000FF00L
+//OUTSTANDING_VC_ALLOC
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__SHIFT 0x0
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__SHIFT 0x2
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__SHIFT 0x4
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__SHIFT 0x6
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__SHIFT 0x8
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__SHIFT 0xa
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__SHIFT 0xc
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__SHIFT 0xe
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__SHIFT 0x10
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__SHIFT 0x18
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__SHIFT 0x1a
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__SHIFT 0x1c
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC_MASK 0x00000003L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC_MASK 0x0000000CL
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC_MASK 0x00000030L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC_MASK 0x000000C0L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC_MASK 0x00000300L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC_MASK 0x00000C00L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC_MASK 0x00003000L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC_MASK 0x0000C000L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD_MASK 0x000F0000L
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC_MASK 0x03000000L
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC_MASK 0x0C000000L
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD_MASK 0xF0000000L
+//BIFC_MISC_CTRL0
+#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN__SHIFT 0x0
+#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN__SHIFT 0x1
+#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__SHIFT 0x8
+#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK__SHIFT 0x9
+#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__SHIFT 0xa
+#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__SHIFT 0x10
+#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__SHIFT 0x11
+#define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW__SHIFT 0x12
+#define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH__SHIFT 0x13
+#define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO__SHIFT 0x14
+#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__SHIFT 0x18
+#define BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS__SHIFT 0x19
+#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__SHIFT 0x1a
+#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__SHIFT 0x1b
+#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE__SHIFT 0x1c
+#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION__SHIFT 0x1f
+#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN_MASK 0x00000001L
+#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN_MASK 0x00000006L
+#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE_MASK 0x00000100L
+#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_MASK 0x00000200L
+#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK_MASK 0x00000400L
+#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS_MASK 0x00010000L
+#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL_MASK 0x00020000L
+#define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW_MASK 0x00040000L
+#define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH_MASK 0x00080000L
+#define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO_MASK 0x00100000L
+#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS_MASK 0x01000000L
+#define BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS_MASK 0x02000000L
+#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS_MASK 0x04000000L
+#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE_MASK 0x08000000L
+#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE_MASK 0x10000000L
+#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION_MASK 0x80000000L
+//BIFC_MISC_CTRL1
+#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__SHIFT 0x0
+#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__SHIFT 0x1
+#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__SHIFT 0x2
+#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__SHIFT 0x3
+#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__SHIFT 0x4
+#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__SHIFT 0x5
+#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__SHIFT 0x6
+#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__SHIFT 0x7
+#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__SHIFT 0x8
+#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__SHIFT 0xa
+#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__SHIFT 0xc
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__SHIFT 0xd
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__SHIFT 0xe
+#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__SHIFT 0xf
+#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__SHIFT 0x10
+#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__SHIFT 0x11
+#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__SHIFT 0x12
+#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__SHIFT 0x13
+#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR__SHIFT 0x14
+#define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK__SHIFT 0x18
+#define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK__SHIFT 0x19
+#define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK__SHIFT 0x1a
+#define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK__SHIFT 0x1b
+#define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT__SHIFT 0x1c
+#define BIFC_MISC_CTRL1__GMI_CPLBUF_EN__SHIFT 0x1d
+#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP__SHIFT 0x1f
+#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT_MASK 0x00000001L
+#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT_MASK 0x00000002L
+#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT_MASK 0x00000004L
+#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT_MASK 0x00000008L
+#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS_MASK 0x00000010L
+#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR_MASK 0x00000020L
+#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS_MASK 0x00000040L
+#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL_MASK 0x00000080L
+#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS_MASK 0x00000300L
+#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS_MASK 0x00000C00L
+#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ_MASK 0x00001000L
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_MASK 0x00002000L
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE_MASK 0x00004000L
+#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1_MASK 0x00008000L
+#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS_MASK 0x00010000L
+#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS_MASK 0x00020000L
+#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS_MASK 0x00040000L
+#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS_MASK 0x00080000L
+#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR_MASK 0x00100000L
+#define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK_MASK 0x01000000L
+#define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK_MASK 0x02000000L
+#define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK_MASK 0x04000000L
+#define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK_MASK 0x08000000L
+#define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT_MASK 0x10000000L
+#define BIFC_MISC_CTRL1__GMI_CPLBUF_EN_MASK 0x20000000L
+#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP_MASK 0x80000000L
+//BIFC_BME_ERR_LOG
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x0
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x1
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2__SHIFT 0x2
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3__SHIFT 0x3
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4__SHIFT 0x4
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5__SHIFT 0x5
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6__SHIFT 0x6
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7__SHIFT 0x7
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F0__SHIFT 0x8
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F1__SHIFT 0x9
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F2__SHIFT 0xa
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F3__SHIFT 0xb
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F4__SHIFT 0xc
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F5__SHIFT 0xd
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F6__SHIFT 0xe
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F7__SHIFT 0xf
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x10
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x11
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2__SHIFT 0x12
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3__SHIFT 0x13
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4__SHIFT 0x14
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5__SHIFT 0x15
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6__SHIFT 0x16
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7__SHIFT 0x17
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F0__SHIFT 0x18
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F1__SHIFT 0x19
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F2__SHIFT 0x1a
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F3__SHIFT 0x1b
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F4__SHIFT 0x1c
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F5__SHIFT 0x1d
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F6__SHIFT 0x1e
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F7__SHIFT 0x1f
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0_MASK 0x00000001L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1_MASK 0x00000002L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2_MASK 0x00000004L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3_MASK 0x00000008L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4_MASK 0x00000010L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5_MASK 0x00000020L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6_MASK 0x00000040L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7_MASK 0x00000080L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F0_MASK 0x00000100L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F1_MASK 0x00000200L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F2_MASK 0x00000400L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F3_MASK 0x00000800L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F4_MASK 0x00001000L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F5_MASK 0x00002000L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F6_MASK 0x00004000L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F7_MASK 0x00008000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0_MASK 0x00010000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1_MASK 0x00020000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2_MASK 0x00040000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3_MASK 0x00080000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4_MASK 0x00100000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5_MASK 0x00200000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6_MASK 0x00400000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7_MASK 0x00800000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F0_MASK 0x01000000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F1_MASK 0x02000000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F2_MASK 0x04000000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F3_MASK 0x08000000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F4_MASK 0x10000000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F5_MASK 0x20000000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F6_MASK 0x40000000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F7_MASK 0x80000000L
+//BIFC_RCCBIH_BME_ERR_LOG
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x0
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x1
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x2
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x3
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT 0x4
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT 0x5
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT 0x6
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT 0x7
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F0__SHIFT 0x8
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F1__SHIFT 0x9
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F2__SHIFT 0xa
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F3__SHIFT 0xb
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F4__SHIFT 0xc
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F5__SHIFT 0xd
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F6__SHIFT 0xe
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F7__SHIFT 0xf
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x10
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x11
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x12
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x13
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT 0x14
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT 0x15
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT 0x16
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT 0x17
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F0__SHIFT 0x18
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F1__SHIFT 0x19
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F2__SHIFT 0x1a
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F3__SHIFT 0x1b
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F4__SHIFT 0x1c
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F5__SHIFT 0x1d
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F6__SHIFT 0x1e
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F7__SHIFT 0x1f
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F0_MASK 0x00000001L
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F1_MASK 0x00000002L
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F2_MASK 0x00000004L
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F3_MASK 0x00000008L
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F4_MASK 0x00000010L
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F5_MASK 0x00000020L
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F6_MASK 0x00000040L
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F7_MASK 0x00000080L
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F0_MASK 0x00000100L
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F1_MASK 0x00000200L
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F2_MASK 0x00000400L
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F3_MASK 0x00000800L
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F4_MASK 0x00001000L
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F5_MASK 0x00002000L
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F6_MASK 0x00004000L
+#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV1_F7_MASK 0x00008000L
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0_MASK 0x00010000L
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1_MASK 0x00020000L
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2_MASK 0x00040000L
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3_MASK 0x00080000L
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4_MASK 0x00100000L
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5_MASK 0x00200000L
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6_MASK 0x00400000L
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7_MASK 0x00800000L
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F0_MASK 0x01000000L
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F1_MASK 0x02000000L
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F2_MASK 0x04000000L
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F3_MASK 0x08000000L
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F4_MASK 0x10000000L
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F5_MASK 0x20000000L
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F6_MASK 0x40000000L
+#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F7_MASK 0x80000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__SHIFT 0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0_MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0_MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0_MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0_MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0_MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0_MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1_MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1_MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1_MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1_MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1_MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1_MASK 0x30000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__SHIFT 0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2_MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2_MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2_MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2_MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2_MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2_MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3_MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3_MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3_MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3_MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3_MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3_MASK 0x30000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__SHIFT 0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4_MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4_MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4_MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4_MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4_MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4_MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5_MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5_MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5_MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5_MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5_MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5_MASK 0x30000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__SHIFT 0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6_MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6_MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6_MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6_MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6_MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6_MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7_MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7_MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7_MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7_MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7_MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7_MASK 0x30000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_P_DEV1_F0__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_NP_DEV1_F0__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_P_DEV1_F0__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_NP_DEV1_F0__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_P_DEV1_F0__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_NP_DEV1_F0__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_P_DEV1_F1__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_NP_DEV1_F1__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_P_DEV1_F1__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_NP_DEV1_F1__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_P_DEV1_F1__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_NP_DEV1_F1__SHIFT 0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_P_DEV1_F0_MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_NP_DEV1_F0_MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_P_DEV1_F0_MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_NP_DEV1_F0_MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_P_DEV1_F0_MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_NP_DEV1_F0_MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_P_DEV1_F1_MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_NP_DEV1_F1_MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_P_DEV1_F1_MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_NP_DEV1_F1_MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_P_DEV1_F1_MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_NP_DEV1_F1_MASK 0x30000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_P_DEV1_F2__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_NP_DEV1_F2__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_P_DEV1_F2__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_NP_DEV1_F2__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_P_DEV1_F2__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_NP_DEV1_F2__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_P_DEV1_F3__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_NP_DEV1_F3__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_P_DEV1_F3__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_NP_DEV1_F3__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_P_DEV1_F3__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_NP_DEV1_F3__SHIFT 0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_P_DEV1_F2_MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_NP_DEV1_F2_MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_P_DEV1_F2_MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_NP_DEV1_F2_MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_P_DEV1_F2_MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_NP_DEV1_F2_MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_P_DEV1_F3_MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_NP_DEV1_F3_MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_P_DEV1_F3_MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_NP_DEV1_F3_MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_P_DEV1_F3_MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_NP_DEV1_F3_MASK 0x30000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_P_DEV1_F4__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_NP_DEV1_F4__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_P_DEV1_F4__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_NP_DEV1_F4__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_P_DEV1_F4__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_NP_DEV1_F4__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_P_DEV1_F5__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_NP_DEV1_F5__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_P_DEV1_F5__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_NP_DEV1_F5__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_P_DEV1_F5__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_NP_DEV1_F5__SHIFT 0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_P_DEV1_F4_MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_NP_DEV1_F4_MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_P_DEV1_F4_MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_NP_DEV1_F4_MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_P_DEV1_F4_MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_NP_DEV1_F4_MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_P_DEV1_F5_MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_NP_DEV1_F5_MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_P_DEV1_F5_MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_NP_DEV1_F5_MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_P_DEV1_F5_MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_NP_DEV1_F5_MASK 0x30000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_P_DEV1_F6__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_NP_DEV1_F6__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_P_DEV1_F6__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_NP_DEV1_F6__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_P_DEV1_F6__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_NP_DEV1_F6__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_P_DEV1_F7__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_NP_DEV1_F7__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_P_DEV1_F7__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_NP_DEV1_F7__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_P_DEV1_F7__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_NP_DEV1_F7__SHIFT 0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_P_DEV1_F6_MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_NP_DEV1_F6_MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_P_DEV1_F6_MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_NP_DEV1_F6_MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_P_DEV1_F6_MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_NP_DEV1_F6_MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_P_DEV1_F7_MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_NP_DEV1_F7_MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_P_DEV1_F7_MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_NP_DEV1_F7_MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_P_DEV1_F7_MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_NP_DEV1_F7_MASK 0x30000000L
+//NBIF_VWIRE_CTRL
+#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__SHIFT 0x4
+#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED__SHIFT 0x8
+#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__SHIFT 0x14
+#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__SHIFT 0x1a
+#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT_MASK 0x000000F0L
+#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED_MASK 0x00000100L
+#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT_MASK 0x00F00000L
+#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL_MASK 0x0C000000L
+//NBIF_SMN_VWR_VCHG_DIS_CTRL
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS__SHIFT 0x0
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS__SHIFT 0x1
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS__SHIFT 0x2
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS__SHIFT 0x3
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS__SHIFT 0x4
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS__SHIFT 0x5
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS__SHIFT 0x6
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET7_DIS__SHIFT 0x7
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET8_DIS__SHIFT 0x8
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET9_DIS__SHIFT 0x9
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET10_DIS__SHIFT 0xa
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET11_DIS__SHIFT 0xb
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET12_DIS__SHIFT 0xc
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET13_DIS__SHIFT 0xd
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET14_DIS__SHIFT 0xe
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET15_DIS__SHIFT 0xf
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET16_DIS__SHIFT 0x10
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET17_DIS__SHIFT 0x11
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS_MASK 0x00000001L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS_MASK 0x00000002L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS_MASK 0x00000004L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS_MASK 0x00000008L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS_MASK 0x00000010L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS_MASK 0x00000020L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS_MASK 0x00000040L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET7_DIS_MASK 0x00000080L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET8_DIS_MASK 0x00000100L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET9_DIS_MASK 0x00000200L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET10_DIS_MASK 0x00000400L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET11_DIS_MASK 0x00000800L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET12_DIS_MASK 0x00001000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET13_DIS_MASK 0x00002000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET14_DIS_MASK 0x00004000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET15_DIS_MASK 0x00008000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET16_DIS_MASK 0x00010000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET17_DIS_MASK 0x00020000L
+//NBIF_SMN_VWR_VCHG_RST_CTRL0
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV__SHIFT 0x0
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV__SHIFT 0x1
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV__SHIFT 0x2
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV__SHIFT 0x3
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV__SHIFT 0x4
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV__SHIFT 0x5
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV__SHIFT 0x6
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET7_RST_DEF_REV__SHIFT 0x7
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET8_RST_DEF_REV__SHIFT 0x8
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET9_RST_DEF_REV__SHIFT 0x9
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET10_RST_DEF_REV__SHIFT 0xa
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET11_RST_DEF_REV__SHIFT 0xb
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET12_RST_DEF_REV__SHIFT 0xc
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET13_RST_DEF_REV__SHIFT 0xd
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET14_RST_DEF_REV__SHIFT 0xe
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET15_RST_DEF_REV__SHIFT 0xf
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET16_RST_DEF_REV__SHIFT 0x10
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET17_RST_DEF_REV__SHIFT 0x11
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV_MASK 0x00000001L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV_MASK 0x00000002L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV_MASK 0x00000004L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV_MASK 0x00000008L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV_MASK 0x00000010L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV_MASK 0x00000020L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV_MASK 0x00000040L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET7_RST_DEF_REV_MASK 0x00000080L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET8_RST_DEF_REV_MASK 0x00000100L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET9_RST_DEF_REV_MASK 0x00000200L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET10_RST_DEF_REV_MASK 0x00000400L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET11_RST_DEF_REV_MASK 0x00000800L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET12_RST_DEF_REV_MASK 0x00001000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET13_RST_DEF_REV_MASK 0x00002000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET14_RST_DEF_REV_MASK 0x00004000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET15_RST_DEF_REV_MASK 0x00008000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET16_RST_DEF_REV_MASK 0x00010000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET17_RST_DEF_REV_MASK 0x00020000L
+//NBIF_SMN_VWR_VCHG_TRIG
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG__SHIFT 0x0
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG__SHIFT 0x1
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG__SHIFT 0x2
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG__SHIFT 0x3
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG__SHIFT 0x4
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG__SHIFT 0x5
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG__SHIFT 0x6
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET7_TRIG__SHIFT 0x7
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET8_TRIG__SHIFT 0x8
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET9_TRIG__SHIFT 0x9
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET10_TRIG__SHIFT 0xa
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET11_TRIG__SHIFT 0xb
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET12_TRIG__SHIFT 0xc
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET13_TRIG__SHIFT 0xd
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET14_TRIG__SHIFT 0xe
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET15_TRIG__SHIFT 0xf
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET16_TRIG__SHIFT 0x10
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET17_TRIG__SHIFT 0x11
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG_MASK 0x00000001L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG_MASK 0x00000002L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG_MASK 0x00000004L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG_MASK 0x00000008L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG_MASK 0x00000010L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG_MASK 0x00000020L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG_MASK 0x00000040L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET7_TRIG_MASK 0x00000080L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET8_TRIG_MASK 0x00000100L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET9_TRIG_MASK 0x00000200L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET10_TRIG_MASK 0x00000400L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET11_TRIG_MASK 0x00000800L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET12_TRIG_MASK 0x00001000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET13_TRIG_MASK 0x00002000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET14_TRIG_MASK 0x00004000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET15_TRIG_MASK 0x00008000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET16_TRIG_MASK 0x00010000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET17_TRIG_MASK 0x00020000L
+//NBIF_SMN_VWR_WTRIG_CNTL
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS__SHIFT 0x0
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS__SHIFT 0x1
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS__SHIFT 0x2
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS__SHIFT 0x3
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS__SHIFT 0x4
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS__SHIFT 0x5
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS__SHIFT 0x6
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET7_DIS__SHIFT 0x7
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET8_DIS__SHIFT 0x8
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET9_DIS__SHIFT 0x9
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET10_DIS__SHIFT 0xa
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET11_DIS__SHIFT 0xb
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET12_DIS__SHIFT 0xc
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET13_DIS__SHIFT 0xd
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET14_DIS__SHIFT 0xe
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET15_DIS__SHIFT 0xf
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET16_DIS__SHIFT 0x10
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET17_DIS__SHIFT 0x11
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS_MASK 0x00000001L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS_MASK 0x00000002L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS_MASK 0x00000004L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS_MASK 0x00000008L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS_MASK 0x00000010L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS_MASK 0x00000020L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS_MASK 0x00000040L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET7_DIS_MASK 0x00000080L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET8_DIS_MASK 0x00000100L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET9_DIS_MASK 0x00000200L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET10_DIS_MASK 0x00000400L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET11_DIS_MASK 0x00000800L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET12_DIS_MASK 0x00001000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET13_DIS_MASK 0x00002000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET14_DIS_MASK 0x00004000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET15_DIS_MASK 0x00008000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET16_DIS_MASK 0x00010000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET17_DIS_MASK 0x00020000L
+//NBIF_SMN_VWR_VCHG_DIS_CTRL_1
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV__SHIFT 0x0
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV__SHIFT 0x1
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV__SHIFT 0x2
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV__SHIFT 0x3
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV__SHIFT 0x4
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV__SHIFT 0x5
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV__SHIFT 0x6
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET7_DIFFDET_DEF_REV__SHIFT 0x7
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET8_DIFFDET_DEF_REV__SHIFT 0x8
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET9_DIFFDET_DEF_REV__SHIFT 0x9
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET10_DIFFDET_DEF_REV__SHIFT 0xa
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET11_DIFFDET_DEF_REV__SHIFT 0xb
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET12_DIFFDET_DEF_REV__SHIFT 0xc
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET13_DIFFDET_DEF_REV__SHIFT 0xd
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET14_DIFFDET_DEF_REV__SHIFT 0xe
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET15_DIFFDET_DEF_REV__SHIFT 0xf
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET16_DIFFDET_DEF_REV__SHIFT 0x10
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET17_DIFFDET_DEF_REV__SHIFT 0x11
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV_MASK 0x00000001L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV_MASK 0x00000002L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV_MASK 0x00000004L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV_MASK 0x00000008L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV_MASK 0x00000010L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV_MASK 0x00000020L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV_MASK 0x00000040L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET7_DIFFDET_DEF_REV_MASK 0x00000080L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET8_DIFFDET_DEF_REV_MASK 0x00000100L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET9_DIFFDET_DEF_REV_MASK 0x00000200L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET10_DIFFDET_DEF_REV_MASK 0x00000400L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET11_DIFFDET_DEF_REV_MASK 0x00000800L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET12_DIFFDET_DEF_REV_MASK 0x00001000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET13_DIFFDET_DEF_REV_MASK 0x00002000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET14_DIFFDET_DEF_REV_MASK 0x00004000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET15_DIFFDET_DEF_REV_MASK 0x00008000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET16_DIFFDET_DEF_REV_MASK 0x00010000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET17_DIFFDET_DEF_REV_MASK 0x00020000L
+//NBIF_MGCG_CTRL_LCLK
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK__SHIFT 0x0
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK__SHIFT 0x1
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK__SHIFT 0x2
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK__SHIFT 0xa
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK__SHIFT 0xb
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REGS_DIS_LCLK__SHIFT 0xc
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK__SHIFT 0xd
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK 0x00000001L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK_MASK 0x00000002L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK_MASK 0x000003FCL
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK_MASK 0x00000400L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK_MASK 0x00000800L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REGS_DIS_LCLK_MASK 0x00001000L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK_MASK 0x00002000L
+//NBIF_DS_CTRL_LCLK
+#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__SHIFT 0x0
+#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__SHIFT 0x10
+#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN_MASK 0x00000001L
+#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER_MASK 0xFFFF0000L
+//SMN_MST_CNTL0
+#define SMN_MST_CNTL0__SMN_ARB_MODE__SHIFT 0x0
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__SHIFT 0x8
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__SHIFT 0x9
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__SHIFT 0xa
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__SHIFT 0xb
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__SHIFT 0x10
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV1__SHIFT 0x11
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__SHIFT 0x14
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV1__SHIFT 0x15
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__SHIFT 0x18
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV1__SHIFT 0x19
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__SHIFT 0x1c
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV1__SHIFT 0x1d
+#define SMN_MST_CNTL0__SMN_ARB_MODE_MASK 0x00000003L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS_MASK 0x00000100L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS_MASK 0x00000200L
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS_MASK 0x00000400L
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS_MASK 0x00000800L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0_MASK 0x00010000L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV1_MASK 0x00020000L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0_MASK 0x00100000L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV1_MASK 0x00200000L
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0_MASK 0x01000000L
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV1_MASK 0x02000000L
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0_MASK 0x10000000L
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV1_MASK 0x20000000L
+//SMN_MST_EP_CNTL1
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__SHIFT 0x0
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__SHIFT 0x1
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__SHIFT 0x2
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__SHIFT 0x3
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__SHIFT 0x4
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__SHIFT 0x5
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__SHIFT 0x6
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__SHIFT 0x7
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF0__SHIFT 0x8
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF1__SHIFT 0x9
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF2__SHIFT 0xa
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF3__SHIFT 0xb
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF4__SHIFT 0xc
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF5__SHIFT 0xd
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF6__SHIFT 0xe
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF7__SHIFT 0xf
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0_MASK 0x00000001L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1_MASK 0x00000002L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2_MASK 0x00000004L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3_MASK 0x00000008L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4_MASK 0x00000010L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5_MASK 0x00000020L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6_MASK 0x00000040L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7_MASK 0x00000080L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF0_MASK 0x00000100L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF1_MASK 0x00000200L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF2_MASK 0x00000400L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF3_MASK 0x00000800L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF4_MASK 0x00001000L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF5_MASK 0x00002000L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF6_MASK 0x00004000L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF7_MASK 0x00008000L
+//SMN_MST_EP_CNTL2
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__SHIFT 0x0
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__SHIFT 0x1
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__SHIFT 0x2
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__SHIFT 0x3
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__SHIFT 0x4
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__SHIFT 0x5
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__SHIFT 0x6
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__SHIFT 0x7
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF0__SHIFT 0x8
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF1__SHIFT 0x9
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF2__SHIFT 0xa
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF3__SHIFT 0xb
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF4__SHIFT 0xc
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF5__SHIFT 0xd
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF6__SHIFT 0xe
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF7__SHIFT 0xf
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0_MASK 0x00000001L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1_MASK 0x00000002L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2_MASK 0x00000004L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3_MASK 0x00000008L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4_MASK 0x00000010L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5_MASK 0x00000020L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6_MASK 0x00000040L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7_MASK 0x00000080L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF0_MASK 0x00000100L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF1_MASK 0x00000200L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF2_MASK 0x00000400L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF3_MASK 0x00000800L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF4_MASK 0x00001000L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF5_MASK 0x00002000L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF6_MASK 0x00004000L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF7_MASK 0x00008000L
+//NBIF_SDP_VWR_VCHG_DIS_CTRL
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__SHIFT 0x0
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__SHIFT 0x1
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__SHIFT 0x2
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__SHIFT 0x3
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__SHIFT 0x4
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__SHIFT 0x5
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__SHIFT 0x6
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__SHIFT 0x7
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__SHIFT 0x18
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS_MASK 0x00000001L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS_MASK 0x00000002L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS_MASK 0x00000004L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS_MASK 0x00000008L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS_MASK 0x00000010L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS_MASK 0x00000020L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS_MASK 0x00000040L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS_MASK 0x00000080L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS_MASK 0x01000000L
+//NBIF_SDP_VWR_VCHG_RST_CTRL0
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__SHIFT 0x0
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__SHIFT 0x1
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__SHIFT 0x2
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__SHIFT 0x3
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__SHIFT 0x4
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__SHIFT 0x5
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__SHIFT 0x6
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__SHIFT 0x7
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__SHIFT 0x18
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN_MASK 0x00000001L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN_MASK 0x00000002L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN_MASK 0x00000004L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN_MASK 0x00000008L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN_MASK 0x00000010L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN_MASK 0x00000020L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN_MASK 0x00000040L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN_MASK 0x00000080L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN_MASK 0x01000000L
+//NBIF_SDP_VWR_VCHG_RST_CTRL1
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__SHIFT 0x0
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__SHIFT 0x1
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__SHIFT 0x2
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__SHIFT 0x3
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__SHIFT 0x4
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__SHIFT 0x5
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__SHIFT 0x6
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__SHIFT 0x7
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__SHIFT 0x18
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL_MASK 0x00000001L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL_MASK 0x00000002L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL_MASK 0x00000004L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL_MASK 0x00000008L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL_MASK 0x00000010L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL_MASK 0x00000020L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL_MASK 0x00000040L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL_MASK 0x00000080L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL_MASK 0x01000000L
+//NBIF_SDP_VWR_VCHG_TRIG
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__SHIFT 0x0
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__SHIFT 0x1
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__SHIFT 0x2
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__SHIFT 0x3
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__SHIFT 0x4
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__SHIFT 0x5
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__SHIFT 0x6
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__SHIFT 0x7
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__SHIFT 0x18
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG_MASK 0x00000001L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG_MASK 0x00000002L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG_MASK 0x00000004L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG_MASK 0x00000008L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG_MASK 0x00000010L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG_MASK 0x00000020L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG_MASK 0x00000040L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG_MASK 0x00000080L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG_MASK 0x01000000L
+//BME_DUMMY_CNTL_0
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__SHIFT 0x0
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__SHIFT 0x2
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__SHIFT 0x4
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__SHIFT 0x6
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__SHIFT 0x8
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__SHIFT 0xa
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__SHIFT 0xc
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__SHIFT 0xe
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F0__SHIFT 0x10
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F1__SHIFT 0x12
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F2__SHIFT 0x14
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F3__SHIFT 0x16
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F4__SHIFT 0x18
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F5__SHIFT 0x1a
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F6__SHIFT 0x1c
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F7__SHIFT 0x1e
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0_MASK 0x00000003L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1_MASK 0x0000000CL
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2_MASK 0x00000030L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3_MASK 0x000000C0L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4_MASK 0x00000300L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5_MASK 0x00000C00L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6_MASK 0x00003000L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7_MASK 0x0000C000L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F0_MASK 0x00030000L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F1_MASK 0x000C0000L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F2_MASK 0x00300000L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F3_MASK 0x00C00000L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F4_MASK 0x03000000L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F5_MASK 0x0C000000L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F6_MASK 0x30000000L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F7_MASK 0xC0000000L
+//BIFC_THT_CNTL
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0__SHIFT 0x0
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0__SHIFT 0x4
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1__SHIFT 0x8
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0_MASK 0x0000000FL
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0_MASK 0x000000F0L
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1_MASK 0x00000F00L
+//BIFC_HSTARB_CNTL
+#define BIFC_HSTARB_CNTL__SLVARB_MODE__SHIFT 0x0
+#define BIFC_HSTARB_CNTL__SLVARB_MODE_MASK 0x00000003L
+//BIFC_GSI_CNTL
+#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__SHIFT 0x0
+#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__SHIFT 0x2
+#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__SHIFT 0x5
+#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__SHIFT 0x6
+#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__SHIFT 0x7
+#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__SHIFT 0x8
+#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__SHIFT 0x9
+#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__SHIFT 0xa
+#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__SHIFT 0xc
+#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE_MASK 0x00000003L
+#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE_MASK 0x0000001CL
+#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN_MASK 0x00000020L
+#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN_MASK 0x00000040L
+#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN_MASK 0x00000080L
+#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN_MASK 0x00000100L
+#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN_MASK 0x00000200L
+#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE_MASK 0x00000C00L
+#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE_MASK 0x00003000L
+//BIFC_PCIEFUNC_CNTL
+#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__SHIFT 0x0
+#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__SHIFT 0x10
+#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC_MASK 0x0000FFFFL
+#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC_MASK 0x00010000L
+//BIFC_SDP_CNTL_0
+#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__SHIFT 0x0
+#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__SHIFT 0x8
+#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__SHIFT 0x10
+#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__SHIFT 0x18
+#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS_MASK 0x000000FFL
+#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS_MASK 0x0000FF00L
+#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS_MASK 0x00FF0000L
+#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS_MASK 0xFF000000L
+//BIFC_SDP_CNTL_1
+#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS__SHIFT 0x0
+#define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS__SHIFT 0x1
+#define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS__SHIFT 0x2
+#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS__SHIFT 0x3
+#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT 0x4
+#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT 0x7
+#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS_MASK 0x00000001L
+#define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS_MASK 0x00000002L
+#define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS_MASK 0x00000004L
+#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS_MASK 0x00000008L
+#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY_MASK 0x00000010L
+#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY_MASK 0x00000080L
+//BIFC_PERF_CNTL_0
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__SHIFT 0x0
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__SHIFT 0x1
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__SHIFT 0x8
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__SHIFT 0x9
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__SHIFT 0x10
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__SHIFT 0x18
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN_MASK 0x00000001L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN_MASK 0x00000002L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET_MASK 0x00000100L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET_MASK 0x00000200L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL_MASK 0x001F0000L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL_MASK 0x1F000000L
+//BIFC_PERF_CNTL_1
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__SHIFT 0x0
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__SHIFT 0x1
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__SHIFT 0x8
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__SHIFT 0x9
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__SHIFT 0x10
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__SHIFT 0x18
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN_MASK 0x00000001L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN_MASK 0x00000002L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET_MASK 0x00000100L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET_MASK 0x00000200L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL_MASK 0x003F0000L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL_MASK 0x7F000000L
+//BIFC_PERF_CNT_MMIO_RD
+#define BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE__SHIFT 0x0
+#define BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE_MASK 0xFFFFFFFFL
+//BIFC_PERF_CNT_MMIO_WR
+#define BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE__SHIFT 0x0
+#define BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE_MASK 0xFFFFFFFFL
+//BIFC_PERF_CNT_DMA_RD
+#define BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE__SHIFT 0x0
+#define BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE_MASK 0xFFFFFFFFL
+//BIFC_PERF_CNT_DMA_WR
+#define BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE__SHIFT 0x0
+#define BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE_MASK 0xFFFFFFFFL
+//NBIF_REGIF_ERRSET_CTRL
+#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0
+#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L
+//NBIF_PGMST_CTRL
+#define NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS__SHIFT 0x0
+#define NBIF_PGMST_CTRL__NBIF_CFG_PG_EN__SHIFT 0x8
+#define NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN__SHIFT 0xa
+#define NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN__SHIFT 0xe
+#define NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS_MASK 0x000000FFL
+#define NBIF_PGMST_CTRL__NBIF_CFG_PG_EN_MASK 0x00000100L
+#define NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L
+#define NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN_MASK 0x0000C000L
+//NBIF_PGSLV_CTRL
+#define NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS__SHIFT 0x0
+#define NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS_MASK 0x0000001FL
+//NBIF_PG_MISC_CTRL
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT 0x0
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT 0x5
+#define NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY__SHIFT 0xa
+#define NBIF_PG_MISC_CTRL__NBIF_PG_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT 0xb
+#define NBIF_PG_MISC_CTRL__NBIF_PG_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT 0xc
+#define NBIF_PG_MISC_CTRL__NBIF_PG_SHUB_CLK_PERM__SHIFT 0xd
+#define NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS__SHIFT 0xe
+#define NBIF_PG_MISC_CTRL__NBIF_PG_RESET_SELECT_COLD_RESET__SHIFT 0x10
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT 0x18
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE__SHIFT 0x1f
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK 0x0000001FL
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK 0x000003E0L
+#define NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY_MASK 0x00000400L
+#define NBIF_PG_MISC_CTRL__NBIF_PG_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK 0x00000800L
+#define NBIF_PG_MISC_CTRL__NBIF_PG_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK 0x00001000L
+#define NBIF_PG_MISC_CTRL__NBIF_PG_SHUB_CLK_PERM_MASK 0x00002000L
+#define NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS_MASK 0x00004000L
+#define NBIF_PG_MISC_CTRL__NBIF_PG_RESET_SELECT_COLD_RESET_MASK 0x00010000L
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS_MASK 0x3F000000L
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE_MASK 0x80000000L
+//SMN_MST_EP_CNTL3
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__SHIFT 0x0
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__SHIFT 0x1
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__SHIFT 0x2
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__SHIFT 0x3
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__SHIFT 0x4
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__SHIFT 0x5
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__SHIFT 0x6
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__SHIFT 0x7
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF0__SHIFT 0x8
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF1__SHIFT 0x9
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF2__SHIFT 0xa
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF3__SHIFT 0xb
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF4__SHIFT 0xc
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF5__SHIFT 0xd
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF6__SHIFT 0xe
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF7__SHIFT 0xf
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0_MASK 0x00000001L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1_MASK 0x00000002L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2_MASK 0x00000004L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3_MASK 0x00000008L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4_MASK 0x00000010L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5_MASK 0x00000020L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6_MASK 0x00000040L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7_MASK 0x00000080L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF0_MASK 0x00000100L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF1_MASK 0x00000200L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF2_MASK 0x00000400L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF3_MASK 0x00000800L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF4_MASK 0x00001000L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF5_MASK 0x00002000L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF6_MASK 0x00004000L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF7_MASK 0x00008000L
+//SMN_MST_EP_CNTL4
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__SHIFT 0x0
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__SHIFT 0x1
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__SHIFT 0x2
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__SHIFT 0x3
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__SHIFT 0x4
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__SHIFT 0x5
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__SHIFT 0x6
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__SHIFT 0x7
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF0__SHIFT 0x8
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF1__SHIFT 0x9
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF2__SHIFT 0xa
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF3__SHIFT 0xb
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF4__SHIFT 0xc
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF5__SHIFT 0xd
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF6__SHIFT 0xe
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF7__SHIFT 0xf
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0_MASK 0x00000001L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1_MASK 0x00000002L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2_MASK 0x00000004L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3_MASK 0x00000008L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4_MASK 0x00000010L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5_MASK 0x00000020L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6_MASK 0x00000040L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7_MASK 0x00000080L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF0_MASK 0x00000100L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF1_MASK 0x00000200L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF2_MASK 0x00000400L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF3_MASK 0x00000800L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF4_MASK 0x00001000L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF5_MASK 0x00002000L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF6_MASK 0x00004000L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF7_MASK 0x00008000L
+//SMN_MST_CNTL1
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS__SHIFT 0x0
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0__SHIFT 0x10
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV1__SHIFT 0x11
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS_MASK 0x00000001L
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0_MASK 0x00010000L
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV1_MASK 0x00020000L
+//SMN_MST_EP_CNTL5
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0__SHIFT 0x0
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1__SHIFT 0x1
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2__SHIFT 0x2
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3__SHIFT 0x3
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4__SHIFT 0x4
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5__SHIFT 0x5
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6__SHIFT 0x6
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7__SHIFT 0x7
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF0__SHIFT 0x8
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF1__SHIFT 0x9
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF2__SHIFT 0xa
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF3__SHIFT 0xb
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF4__SHIFT 0xc
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF5__SHIFT 0xd
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF6__SHIFT 0xe
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF7__SHIFT 0xf
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0_MASK 0x00000001L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1_MASK 0x00000002L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2_MASK 0x00000004L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3_MASK 0x00000008L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4_MASK 0x00000010L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5_MASK 0x00000020L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6_MASK 0x00000040L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7_MASK 0x00000080L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF0_MASK 0x00000100L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF1_MASK 0x00000200L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF2_MASK 0x00000400L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF3_MASK 0x00000800L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF4_MASK 0x00001000L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF5_MASK 0x00002000L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF6_MASK 0x00004000L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF7_MASK 0x00008000L
+//BIF_SELFRING_BUFFER_VID
+#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__SHIFT 0x0
+#define BIF_SELFRING_BUFFER_VID__IOHUB_RAS_INTR_CID__SHIFT 0x8
+#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID_MASK 0x000000FFL
+#define BIF_SELFRING_BUFFER_VID__IOHUB_RAS_INTR_CID_MASK 0x0000FF00L
+//BIF_SELFRING_VECTOR_CNTL
+#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__SHIFT 0x0
+#define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM__SHIFT 0x1
+#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS_MASK 0x00000001L
+#define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM_MASK 0x00000002L
+//BIF_GMI_WRR_WEIGHT
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_REALTIME_WEIGHT__SHIFT 0x0
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_P_WEIGHT__SHIFT 0x8
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_NP_WEIGHT__SHIFT 0x10
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_MODE__SHIFT 0x1f
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_REALTIME_WEIGHT_MASK 0x000000FFL
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_P_WEIGHT_MASK 0x0000FF00L
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_NP_WEIGHT_MASK 0x00FF0000L
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_MODE_MASK 0x80000000L
+//BIF_GMI_CPLBUF_WR_CTRL
+#define BIF_GMI_CPLBUF_WR_CTRL__GMI_CPLBUF_WR_VC0_RSV__SHIFT 0x0
+#define BIF_GMI_CPLBUF_WR_CTRL__GMI_CPLBUF_WR_VC1_RSV__SHIFT 0x4
+#define BIF_GMI_CPLBUF_WR_CTRL__GMI_CPLBUF_WR_VC3_RSV__SHIFT 0x8
+#define BIF_GMI_CPLBUF_WR_CTRL__GMI_CPLBUF_WR_VC7_RSV__SHIFT 0xc
+#define BIF_GMI_CPLBUF_WR_CTRL__GMI_CPLBUF_WR_VC0_RSV_MASK 0x0000000FL
+#define BIF_GMI_CPLBUF_WR_CTRL__GMI_CPLBUF_WR_VC1_RSV_MASK 0x000000F0L
+#define BIF_GMI_CPLBUF_WR_CTRL__GMI_CPLBUF_WR_VC3_RSV_MASK 0x00000F00L
+#define BIF_GMI_CPLBUF_WR_CTRL__GMI_CPLBUF_WR_VC7_RSV_MASK 0x0000F000L
+//BIF_GMI_CPLBUF_RD_CTRL
+#define BIF_GMI_CPLBUF_RD_CTRL__GMI_CPLBUF_RD_VC0_RSV__SHIFT 0x0
+#define BIF_GMI_CPLBUF_RD_CTRL__GMI_CPLBUF_RD_VC1_RSV__SHIFT 0x4
+#define BIF_GMI_CPLBUF_RD_CTRL__GMI_CPLBUF_RD_VC3_RSV__SHIFT 0x8
+#define BIF_GMI_CPLBUF_RD_CTRL__GMI_CPLBUF_RD_VC7_RSV__SHIFT 0xc
+#define BIF_GMI_CPLBUF_RD_CTRL__GMI_CPLBUF_RD_VC0_RSV_MASK 0x0000000FL
+#define BIF_GMI_CPLBUF_RD_CTRL__GMI_CPLBUF_RD_VC1_RSV_MASK 0x000000F0L
+#define BIF_GMI_CPLBUF_RD_CTRL__GMI_CPLBUF_RD_VC3_RSV_MASK 0x00000F00L
+#define BIF_GMI_CPLBUF_RD_CTRL__GMI_CPLBUF_RD_VC7_RSV_MASK 0x0000F000L
+
+
+// addressBlock: nbio_nbif0_rcc_pfc_amdgfx_RCCPFCDEC
+//RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L
+//RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE
+#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8
+#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L
+#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L
+//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L
+//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL
+#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3
+#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L
+#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_rcc_pfc_amdgfxaz_RCCPFCDEC
+//RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L
+//RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L
+//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L
+//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_rcc_pfc_psp_RCCPFCDEC
+//RCC_PFC_PSP_RCC_PFC_LTR_CNTL
+#define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0
+#define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa
+#define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf
+#define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10
+#define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a
+#define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f
+#define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL
+#define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L
+#define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L
+#define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L
+#define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L
+#define RCC_PFC_PSP_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L
+//RCC_PFC_PSP_RCC_PFC_PME_RESTORE
+#define RCC_PFC_PSP_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0
+#define RCC_PFC_PSP_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8
+#define RCC_PFC_PSP_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L
+#define RCC_PFC_PSP_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L
+//RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0
+#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0
+#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1
+#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2
+#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3
+#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4
+#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5
+#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6
+#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7
+#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L
+#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L
+#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L
+#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L
+#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L
+#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L
+#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L
+#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L
+//RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_1
+#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0
+#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL
+//RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_2
+#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0
+#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL
+//RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_3
+#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0
+#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL
+//RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_4
+#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0
+#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL
+//RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_5
+#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0
+#define RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL
+//RCC_PFC_PSP_RCC_PFC_AUXPWR_CNTL
+#define RCC_PFC_PSP_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0
+#define RCC_PFC_PSP_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3
+#define RCC_PFC_PSP_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L
+#define RCC_PFC_PSP_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_rcc_pfc_usb3_0_RCCPFCDEC
+//RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL
+#define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0
+#define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa
+#define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf
+#define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10
+#define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a
+#define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f
+#define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL
+#define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L
+#define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L
+#define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L
+#define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L
+#define RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L
+//RCC_PFC_USB3_0_RCC_PFC_PME_RESTORE
+#define RCC_PFC_USB3_0_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0
+#define RCC_PFC_USB3_0_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8
+#define RCC_PFC_USB3_0_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L
+#define RCC_PFC_USB3_0_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L
+//RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0
+#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0
+#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1
+#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2
+#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3
+#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4
+#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5
+#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6
+#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7
+#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L
+#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L
+#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L
+#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L
+#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L
+#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L
+#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L
+#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L
+//RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_1
+#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0
+#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL
+//RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_2
+#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0
+#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL
+//RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_3
+#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0
+#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL
+//RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_4
+#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0
+#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL
+//RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_5
+#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0
+#define RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL
+//RCC_PFC_USB3_0_RCC_PFC_AUXPWR_CNTL
+#define RCC_PFC_USB3_0_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0
+#define RCC_PFC_USB3_0_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3
+#define RCC_PFC_USB3_0_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L
+#define RCC_PFC_USB3_0_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_rcc_pfc_usb3_1_RCCPFCDEC
+//RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL
+#define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0
+#define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa
+#define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf
+#define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10
+#define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a
+#define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f
+#define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL
+#define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L
+#define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L
+#define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L
+#define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L
+#define RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L
+//RCC_PFC_USB3_1_RCC_PFC_PME_RESTORE
+#define RCC_PFC_USB3_1_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0
+#define RCC_PFC_USB3_1_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8
+#define RCC_PFC_USB3_1_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L
+#define RCC_PFC_USB3_1_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L
+//RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0
+#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0
+#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1
+#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2
+#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3
+#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4
+#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5
+#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6
+#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7
+#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L
+#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L
+#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L
+#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L
+#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L
+#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L
+#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L
+#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L
+//RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_1
+#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0
+#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL
+//RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_2
+#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0
+#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL
+//RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_3
+#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0
+#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL
+//RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_4
+#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0
+#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL
+//RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_5
+#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0
+#define RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL
+//RCC_PFC_USB3_1_RCC_PFC_AUXPWR_CNTL
+#define RCC_PFC_USB3_1_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0
+#define RCC_PFC_USB3_1_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3
+#define RCC_PFC_USB3_1_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L
+#define RCC_PFC_USB3_1_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_rcc_pfc_acp_RCCPFCDEC
+//RCC_PFC_ACP_RCC_PFC_LTR_CNTL
+#define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0
+#define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa
+#define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf
+#define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10
+#define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a
+#define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f
+#define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL
+#define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L
+#define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L
+#define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L
+#define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L
+#define RCC_PFC_ACP_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L
+//RCC_PFC_ACP_RCC_PFC_PME_RESTORE
+#define RCC_PFC_ACP_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0
+#define RCC_PFC_ACP_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8
+#define RCC_PFC_ACP_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L
+#define RCC_PFC_ACP_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L
+//RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0
+#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0
+#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1
+#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2
+#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3
+#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4
+#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5
+#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6
+#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7
+#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L
+#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L
+#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L
+#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L
+#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L
+#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L
+#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L
+#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L
+//RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_1
+#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0
+#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL
+//RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_2
+#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0
+#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL
+//RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_3
+#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0
+#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL
+//RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_4
+#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0
+#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL
+//RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_5
+#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0
+#define RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL
+//RCC_PFC_ACP_RCC_PFC_AUXPWR_CNTL
+#define RCC_PFC_ACP_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0
+#define RCC_PFC_ACP_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3
+#define RCC_PFC_ACP_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L
+#define RCC_PFC_ACP_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_rcc_pfc_az_RCCPFCDEC
+//RCC_PFC_AZ_RCC_PFC_LTR_CNTL
+#define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0
+#define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa
+#define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf
+#define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10
+#define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a
+#define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f
+#define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL
+#define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L
+#define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L
+#define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L
+#define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L
+#define RCC_PFC_AZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L
+//RCC_PFC_AZ_RCC_PFC_PME_RESTORE
+#define RCC_PFC_AZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0
+#define RCC_PFC_AZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8
+#define RCC_PFC_AZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L
+#define RCC_PFC_AZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L
+//RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0
+#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0
+#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1
+#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2
+#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3
+#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4
+#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5
+#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6
+#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7
+#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L
+#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L
+#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L
+#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L
+#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L
+#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L
+#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L
+#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L
+//RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_1
+#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0
+#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL
+//RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_2
+#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0
+#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL
+//RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_3
+#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0
+#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL
+//RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_4
+#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0
+#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL
+//RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_5
+#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0
+#define RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL
+//RCC_PFC_AZ_RCC_PFC_AUXPWR_CNTL
+#define RCC_PFC_AZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0
+#define RCC_PFC_AZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3
+#define RCC_PFC_AZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L
+#define RCC_PFC_AZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_rcc_pfc_mp2_RCCPFCDEC
+//RCC_PFC_MP2_RCC_PFC_LTR_CNTL
+#define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0
+#define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa
+#define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf
+#define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10
+#define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a
+#define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f
+#define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL
+#define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L
+#define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L
+#define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L
+#define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L
+#define RCC_PFC_MP2_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L
+//RCC_PFC_MP2_RCC_PFC_PME_RESTORE
+#define RCC_PFC_MP2_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0
+#define RCC_PFC_MP2_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8
+#define RCC_PFC_MP2_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L
+#define RCC_PFC_MP2_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L
+//RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0
+#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0
+#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1
+#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2
+#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3
+#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4
+#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5
+#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6
+#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7
+#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L
+#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L
+#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L
+#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L
+#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L
+#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L
+#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L
+#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L
+//RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_1
+#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0
+#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL
+//RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_2
+#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0
+#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL
+//RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_3
+#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0
+#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL
+//RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_4
+#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0
+#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL
+//RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_5
+#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0
+#define RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL
+//RCC_PFC_MP2_RCC_PFC_AUXPWR_CNTL
+#define RCC_PFC_MP2_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0
+#define RCC_PFC_MP2_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3
+#define RCC_PFC_MP2_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L
+#define RCC_PFC_MP2_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_rcc_pfc_sata_RCCPFCDEC
+//RCC_PFC_SATA_RCC_PFC_LTR_CNTL
+#define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0
+#define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa
+#define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf
+#define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10
+#define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a
+#define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f
+#define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL
+#define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L
+#define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L
+#define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L
+#define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L
+#define RCC_PFC_SATA_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L
+//RCC_PFC_SATA_RCC_PFC_PME_RESTORE
+#define RCC_PFC_SATA_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0
+#define RCC_PFC_SATA_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8
+#define RCC_PFC_SATA_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L
+#define RCC_PFC_SATA_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L
+//RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0
+#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0
+#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1
+#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2
+#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3
+#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4
+#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5
+#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6
+#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7
+#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L
+#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L
+#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L
+#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L
+#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L
+#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L
+#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L
+#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L
+//RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_1
+#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0
+#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL
+//RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_2
+#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0
+#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL
+//RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_3
+#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0
+#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL
+//RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_4
+#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0
+#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL
+//RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_5
+#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0
+#define RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL
+//RCC_PFC_SATA_RCC_PFC_AUXPWR_CNTL
+#define RCC_PFC_SATA_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0
+#define RCC_PFC_SATA_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3
+#define RCC_PFC_SATA_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L
+#define RCC_PFC_SATA_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_rcc_pfc_gbe0_RCCPFCDEC
+//RCC_PFC_GBE0_RCC_PFC_LTR_CNTL
+#define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0
+#define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa
+#define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf
+#define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10
+#define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a
+#define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f
+#define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL
+#define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L
+#define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L
+#define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L
+#define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L
+#define RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L
+//RCC_PFC_GBE0_RCC_PFC_PME_RESTORE
+#define RCC_PFC_GBE0_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0
+#define RCC_PFC_GBE0_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8
+#define RCC_PFC_GBE0_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L
+#define RCC_PFC_GBE0_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L
+//RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0
+#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0
+#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1
+#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2
+#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3
+#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4
+#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5
+#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6
+#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7
+#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L
+#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L
+#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L
+#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L
+#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L
+#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L
+#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L
+#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L
+//RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_1
+#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0
+#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL
+//RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_2
+#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0
+#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL
+//RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_3
+#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0
+#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL
+//RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_4
+#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0
+#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL
+//RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_5
+#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0
+#define RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL
+//RCC_PFC_GBE0_RCC_PFC_AUXPWR_CNTL
+#define RCC_PFC_GBE0_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0
+#define RCC_PFC_GBE0_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3
+#define RCC_PFC_GBE0_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L
+#define RCC_PFC_GBE0_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_rcc_pfc_gbe1_RCCPFCDEC
+//RCC_PFC_GBE1_RCC_PFC_LTR_CNTL
+#define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0
+#define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa
+#define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf
+#define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10
+#define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a
+#define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f
+#define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL
+#define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L
+#define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L
+#define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L
+#define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L
+#define RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L
+//RCC_PFC_GBE1_RCC_PFC_PME_RESTORE
+#define RCC_PFC_GBE1_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0
+#define RCC_PFC_GBE1_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8
+#define RCC_PFC_GBE1_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L
+#define RCC_PFC_GBE1_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L
+//RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0
+#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0
+#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1
+#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2
+#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3
+#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4
+#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5
+#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6
+#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7
+#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L
+#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L
+#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L
+#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L
+#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L
+#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L
+#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L
+#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L
+//RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_1
+#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0
+#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL
+//RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_2
+#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0
+#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL
+//RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_3
+#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0
+#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL
+//RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_4
+#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0
+#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL
+//RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_5
+#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0
+#define RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL
+//RCC_PFC_GBE1_RCC_PFC_AUXPWR_CNTL
+#define RCC_PFC_GBE1_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0
+#define RCC_PFC_GBE1_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3
+#define RCC_PFC_GBE1_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L
+#define RCC_PFC_GBE1_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_rst_bif_rst_regblk
+//HARD_RST_CTRL
+#define HARD_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x0
+#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x1
+#define HARD_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x2
+#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x3
+#define HARD_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x4
+#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x5
+#define HARD_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x6
+#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x7
+#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT 0x1c
+#define HARD_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x1d
+#define HARD_RST_CTRL__RELOAD_STRAP_EN__SHIFT 0x1e
+#define HARD_RST_CTRL__CORE_RST_EN__SHIFT 0x1f
+#define HARD_RST_CTRL__DSPT_CFG_RST_EN_MASK 0x00000001L
+#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN_MASK 0x00000002L
+#define HARD_RST_CTRL__DSPT_PRV_RST_EN_MASK 0x00000004L
+#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN_MASK 0x00000008L
+#define HARD_RST_CTRL__EP_CFG_RST_EN_MASK 0x00000010L
+#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN_MASK 0x00000020L
+#define HARD_RST_CTRL__EP_PRV_RST_EN_MASK 0x00000040L
+#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN_MASK 0x00000080L
+#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN_MASK 0x10000000L
+#define HARD_RST_CTRL__CORE_STICKY_RST_EN_MASK 0x20000000L
+#define HARD_RST_CTRL__RELOAD_STRAP_EN_MASK 0x40000000L
+#define HARD_RST_CTRL__CORE_RST_EN_MASK 0x80000000L
+//RSMU_SOFT_RST_CTRL
+#define RSMU_SOFT_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x0
+#define RSMU_SOFT_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x1
+#define RSMU_SOFT_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x2
+#define RSMU_SOFT_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x3
+#define RSMU_SOFT_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x4
+#define RSMU_SOFT_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x5
+#define RSMU_SOFT_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x6
+#define RSMU_SOFT_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x7
+#define RSMU_SOFT_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT 0x1c
+#define RSMU_SOFT_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x1d
+#define RSMU_SOFT_RST_CTRL__RELOAD_STRAP_EN__SHIFT 0x1e
+#define RSMU_SOFT_RST_CTRL__CORE_RST_EN__SHIFT 0x1f
+#define RSMU_SOFT_RST_CTRL__DSPT_CFG_RST_EN_MASK 0x00000001L
+#define RSMU_SOFT_RST_CTRL__DSPT_CFG_STICKY_RST_EN_MASK 0x00000002L
+#define RSMU_SOFT_RST_CTRL__DSPT_PRV_RST_EN_MASK 0x00000004L
+#define RSMU_SOFT_RST_CTRL__DSPT_PRV_STICKY_RST_EN_MASK 0x00000008L
+#define RSMU_SOFT_RST_CTRL__EP_CFG_RST_EN_MASK 0x00000010L
+#define RSMU_SOFT_RST_CTRL__EP_CFG_STICKY_RST_EN_MASK 0x00000020L
+#define RSMU_SOFT_RST_CTRL__EP_PRV_RST_EN_MASK 0x00000040L
+#define RSMU_SOFT_RST_CTRL__EP_PRV_STICKY_RST_EN_MASK 0x00000080L
+#define RSMU_SOFT_RST_CTRL__SWUS_SHADOW_RST_EN_MASK 0x10000000L
+#define RSMU_SOFT_RST_CTRL__CORE_STICKY_RST_EN_MASK 0x20000000L
+#define RSMU_SOFT_RST_CTRL__RELOAD_STRAP_EN_MASK 0x40000000L
+#define RSMU_SOFT_RST_CTRL__CORE_RST_EN_MASK 0x80000000L
+//SELF_SOFT_RST
+#define SELF_SOFT_RST__DSPT0_CFG_RST__SHIFT 0x0
+#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__SHIFT 0x1
+#define SELF_SOFT_RST__DSPT0_PRV_RST__SHIFT 0x2
+#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__SHIFT 0x3
+#define SELF_SOFT_RST__EP0_CFG_RST__SHIFT 0x4
+#define SELF_SOFT_RST__EP0_CFG_STICKY_RST__SHIFT 0x5
+#define SELF_SOFT_RST__EP0_PRV_RST__SHIFT 0x6
+#define SELF_SOFT_RST__EP0_PRV_STICKY_RST__SHIFT 0x7
+#define SELF_SOFT_RST__DSPT1_CFG_RST__SHIFT 0x8
+#define SELF_SOFT_RST__DSPT1_CFG_STICKY_RST__SHIFT 0x9
+#define SELF_SOFT_RST__DSPT1_PRV_RST__SHIFT 0xa
+#define SELF_SOFT_RST__DSPT1_PRV_STICKY_RST__SHIFT 0xb
+#define SELF_SOFT_RST__EP1_CFG_RST__SHIFT 0xc
+#define SELF_SOFT_RST__EP1_CFG_STICKY_RST__SHIFT 0xd
+#define SELF_SOFT_RST__EP1_PRV_RST__SHIFT 0xe
+#define SELF_SOFT_RST__EP1_PRV_STICKY_RST__SHIFT 0xf
+#define SELF_SOFT_RST__HRPU_SDP_PORT_RST__SHIFT 0x18
+#define SELF_SOFT_RST__GSID_SDP_PORT_RST__SHIFT 0x19
+#define SELF_SOFT_RST__GMIU_SDP_PORT_RST__SHIFT 0x1a
+#define SELF_SOFT_RST__GMID_SDP_PORT_RST__SHIFT 0x1b
+#define SELF_SOFT_RST__SWUS_SHADOW_RST__SHIFT 0x1c
+#define SELF_SOFT_RST__CORE_STICKY_RST__SHIFT 0x1d
+#define SELF_SOFT_RST__RELOAD_STRAP__SHIFT 0x1e
+#define SELF_SOFT_RST__CORE_RST__SHIFT 0x1f
+#define SELF_SOFT_RST__DSPT0_CFG_RST_MASK 0x00000001L
+#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST_MASK 0x00000002L
+#define SELF_SOFT_RST__DSPT0_PRV_RST_MASK 0x00000004L
+#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST_MASK 0x00000008L
+#define SELF_SOFT_RST__EP0_CFG_RST_MASK 0x00000010L
+#define SELF_SOFT_RST__EP0_CFG_STICKY_RST_MASK 0x00000020L
+#define SELF_SOFT_RST__EP0_PRV_RST_MASK 0x00000040L
+#define SELF_SOFT_RST__EP0_PRV_STICKY_RST_MASK 0x00000080L
+#define SELF_SOFT_RST__DSPT1_CFG_RST_MASK 0x00000100L
+#define SELF_SOFT_RST__DSPT1_CFG_STICKY_RST_MASK 0x00000200L
+#define SELF_SOFT_RST__DSPT1_PRV_RST_MASK 0x00000400L
+#define SELF_SOFT_RST__DSPT1_PRV_STICKY_RST_MASK 0x00000800L
+#define SELF_SOFT_RST__EP1_CFG_RST_MASK 0x00001000L
+#define SELF_SOFT_RST__EP1_CFG_STICKY_RST_MASK 0x00002000L
+#define SELF_SOFT_RST__EP1_PRV_RST_MASK 0x00004000L
+#define SELF_SOFT_RST__EP1_PRV_STICKY_RST_MASK 0x00008000L
+#define SELF_SOFT_RST__HRPU_SDP_PORT_RST_MASK 0x01000000L
+#define SELF_SOFT_RST__GSID_SDP_PORT_RST_MASK 0x02000000L
+#define SELF_SOFT_RST__GMIU_SDP_PORT_RST_MASK 0x04000000L
+#define SELF_SOFT_RST__GMID_SDP_PORT_RST_MASK 0x08000000L
+#define SELF_SOFT_RST__SWUS_SHADOW_RST_MASK 0x10000000L
+#define SELF_SOFT_RST__CORE_STICKY_RST_MASK 0x20000000L
+#define SELF_SOFT_RST__RELOAD_STRAP_MASK 0x40000000L
+#define SELF_SOFT_RST__CORE_RST_MASK 0x80000000L
+//BIF_GFX_DRV_VPU_RST
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST__SHIFT 0x0
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST__SHIFT 0x1
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST__SHIFT 0x2
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST__SHIFT 0x3
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST__SHIFT 0x4
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST__SHIFT 0x5
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST__SHIFT 0x6
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST__SHIFT 0x7
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST_MASK 0x00000001L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST_MASK 0x00000002L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST_MASK 0x00000004L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST_MASK 0x00000008L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST_MASK 0x00000010L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST_MASK 0x00000020L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST_MASK 0x00000040L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST_MASK 0x00000080L
+//BIF_RST_MISC_CTRL
+#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__SHIFT 0x0
+#define BIF_RST_MISC_CTRL__DRV_RST_MODE__SHIFT 0x2
+#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__SHIFT 0x4
+#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__SHIFT 0x5
+#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__SHIFT 0x6
+#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__SHIFT 0x8
+#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__SHIFT 0x9
+#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__SHIFT 0xa
+#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__SHIFT 0xd
+#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__SHIFT 0xf
+#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT 0x11
+#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__SHIFT 0x17
+#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__SHIFT 0x18
+#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB_MASK 0x00000001L
+#define BIF_RST_MISC_CTRL__DRV_RST_MODE_MASK 0x0000000CL
+#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK_MASK 0x00000010L
+#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR_MASK 0x00000020L
+#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR_MASK 0x00000040L
+#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN_MASK 0x00000100L
+#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE_MASK 0x00000200L
+#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT_MASK 0x00001C00L
+#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL_MASK 0x00006000L
+#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL_MASK 0x00018000L
+#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK 0x000E0000L
+#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS_MASK 0x00800000L
+#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS_MASK 0x03000000L
+//BIF_RST_MISC_CTRL2
+#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__SHIFT 0x10
+#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__SHIFT 0x11
+#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__SHIFT 0x12
+#define BIF_RST_MISC_CTRL2__ENDP1_LNK_RST_TRANS_IDLE__SHIFT 0x13
+#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__SHIFT 0x1f
+#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE_MASK 0x00010000L
+#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE_MASK 0x00020000L
+#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE_MASK 0x00040000L
+#define BIF_RST_MISC_CTRL2__ENDP1_LNK_RST_TRANS_IDLE_MASK 0x00080000L
+#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE_MASK 0x80000000L
+//BIF_RST_MISC_CTRL3
+#define BIF_RST_MISC_CTRL3__TIMER_SCALE__SHIFT 0x0
+#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__SHIFT 0x4
+#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__SHIFT 0x6
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__SHIFT 0x7
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__SHIFT 0xa
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__SHIFT 0xd
+#define BIF_RST_MISC_CTRL3__RSMU_SOFT_RST_CYCLE__SHIFT 0x10
+#define BIF_RST_MISC_CTRL3__TIMER_SCALE_MASK 0x0000000FL
+#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT_MASK 0x00000030L
+#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE_MASK 0x00000040L
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD_MASK 0x00000380L
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT_MASK 0x00001C00L
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF_MASK 0x0000E000L
+#define BIF_RST_MISC_CTRL3__RSMU_SOFT_RST_CYCLE_MASK 0x00FF0000L
+//DEV0_PF0_FLR_RST_CTRL
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN__SHIFT 0x5
+#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN__SHIFT 0x6
+#define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN__SHIFT 0x7
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__SHIFT 0x8
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__SHIFT 0x9
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__SHIFT 0xa
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__SHIFT 0xb
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__SHIFT 0xc
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN__SHIFT 0xd
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__SHIFT 0xe
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__SHIFT 0xf
+#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT 0x10
+#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN__SHIFT 0x1f
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN_MASK 0x00000020L
+#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN_MASK 0x00000040L
+#define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN_MASK 0x00000080L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN_MASK 0x00000100L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN_MASK 0x00000200L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN_MASK 0x00000400L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN_MASK 0x00000800L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN_MASK 0x00001000L
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN_MASK 0x00002000L
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN_MASK 0x00004000L
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN_MASK 0x00008000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN_MASK 0x00010000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN_MASK 0x80000000L
+//DEV0_PF1_FLR_RST_CTRL
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV0_PF2_FLR_RST_CTRL
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV0_PF3_FLR_RST_CTRL
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV0_PF4_FLR_RST_CTRL
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV0_PF5_FLR_RST_CTRL
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV0_PF6_FLR_RST_CTRL
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV0_PF7_FLR_RST_CTRL
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//BIF_INST_RESET_INTR_STS
+#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__SHIFT 0x0
+#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT 0x1
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__SHIFT 0x2
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__SHIFT 0x3
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__SHIFT 0x4
+#define BIF_INST_RESET_INTR_STS__EP1_LINK_RESET_INTR_STS__SHIFT 0x8
+#define BIF_INST_RESET_INTR_STS__EP1_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT 0x9
+#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS_MASK 0x00000001L
+#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS_MASK 0x00000002L
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS_MASK 0x00000004L
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS_MASK 0x00000008L
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS_MASK 0x00000010L
+#define BIF_INST_RESET_INTR_STS__EP1_LINK_RESET_INTR_STS_MASK 0x00000100L
+#define BIF_INST_RESET_INTR_STS__EP1_LINK_RESET_CFG_ONLY_INTR_STS_MASK 0x00000200L
+//BIF_PF_FLR_INTR_STS
+#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__SHIFT 0x0
+#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__SHIFT 0x1
+#define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS__SHIFT 0x2
+#define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS__SHIFT 0x3
+#define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS__SHIFT 0x4
+#define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS__SHIFT 0x5
+#define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS__SHIFT 0x6
+#define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS__SHIFT 0x7
+#define BIF_PF_FLR_INTR_STS__DEV1_PF0_FLR_INTR_STS__SHIFT 0x8
+#define BIF_PF_FLR_INTR_STS__DEV1_PF1_FLR_INTR_STS__SHIFT 0x9
+#define BIF_PF_FLR_INTR_STS__DEV1_PF2_FLR_INTR_STS__SHIFT 0xa
+#define BIF_PF_FLR_INTR_STS__DEV1_PF3_FLR_INTR_STS__SHIFT 0xb
+#define BIF_PF_FLR_INTR_STS__DEV1_PF4_FLR_INTR_STS__SHIFT 0xc
+#define BIF_PF_FLR_INTR_STS__DEV1_PF5_FLR_INTR_STS__SHIFT 0xd
+#define BIF_PF_FLR_INTR_STS__DEV1_PF6_FLR_INTR_STS__SHIFT 0xe
+#define BIF_PF_FLR_INTR_STS__DEV1_PF7_FLR_INTR_STS__SHIFT 0xf
+#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS_MASK 0x00000001L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS_MASK 0x00000002L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS_MASK 0x00000004L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS_MASK 0x00000008L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS_MASK 0x00000010L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS_MASK 0x00000020L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS_MASK 0x00000040L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS_MASK 0x00000080L
+#define BIF_PF_FLR_INTR_STS__DEV1_PF0_FLR_INTR_STS_MASK 0x00000100L
+#define BIF_PF_FLR_INTR_STS__DEV1_PF1_FLR_INTR_STS_MASK 0x00000200L
+#define BIF_PF_FLR_INTR_STS__DEV1_PF2_FLR_INTR_STS_MASK 0x00000400L
+#define BIF_PF_FLR_INTR_STS__DEV1_PF3_FLR_INTR_STS_MASK 0x00000800L
+#define BIF_PF_FLR_INTR_STS__DEV1_PF4_FLR_INTR_STS_MASK 0x00001000L
+#define BIF_PF_FLR_INTR_STS__DEV1_PF5_FLR_INTR_STS_MASK 0x00002000L
+#define BIF_PF_FLR_INTR_STS__DEV1_PF6_FLR_INTR_STS_MASK 0x00004000L
+#define BIF_PF_FLR_INTR_STS__DEV1_PF7_FLR_INTR_STS_MASK 0x00008000L
+//BIF_D3HOTD0_INTR_STS
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__SHIFT 0x0
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__SHIFT 0x1
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS__SHIFT 0x2
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS__SHIFT 0x3
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS__SHIFT 0x4
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS__SHIFT 0x5
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS__SHIFT 0x6
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS__SHIFT 0x7
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF0_D3HOTD0_INTR_STS__SHIFT 0x8
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF1_D3HOTD0_INTR_STS__SHIFT 0x9
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF2_D3HOTD0_INTR_STS__SHIFT 0xa
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF3_D3HOTD0_INTR_STS__SHIFT 0xb
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF4_D3HOTD0_INTR_STS__SHIFT 0xc
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF5_D3HOTD0_INTR_STS__SHIFT 0xd
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF6_D3HOTD0_INTR_STS__SHIFT 0xe
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF7_D3HOTD0_INTR_STS__SHIFT 0xf
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS_MASK 0x00000001L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS_MASK 0x00000002L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS_MASK 0x00000004L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS_MASK 0x00000008L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS_MASK 0x00000010L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS_MASK 0x00000020L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS_MASK 0x00000040L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS_MASK 0x00000080L
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF0_D3HOTD0_INTR_STS_MASK 0x00000100L
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF1_D3HOTD0_INTR_STS_MASK 0x00000200L
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF2_D3HOTD0_INTR_STS_MASK 0x00000400L
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF3_D3HOTD0_INTR_STS_MASK 0x00000800L
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF4_D3HOTD0_INTR_STS_MASK 0x00001000L
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF5_D3HOTD0_INTR_STS_MASK 0x00002000L
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF6_D3HOTD0_INTR_STS_MASK 0x00004000L
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF7_D3HOTD0_INTR_STS_MASK 0x00008000L
+//BIF_POWER_INTR_STS
+#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__SHIFT 0x0
+#define BIF_POWER_INTR_STS__DEV1_PME_TURN_OFF_INTR_STS__SHIFT 0x1
+#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__SHIFT 0x10
+#define BIF_POWER_INTR_STS__PORT1_DSTATE_INTR_STS__SHIFT 0x11
+#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS_MASK 0x00000001L
+#define BIF_POWER_INTR_STS__DEV1_PME_TURN_OFF_INTR_STS_MASK 0x00000002L
+#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS_MASK 0x00010000L
+#define BIF_POWER_INTR_STS__PORT1_DSTATE_INTR_STS_MASK 0x00020000L
+//BIF_PF_DSTATE_INTR_STS
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__SHIFT 0x0
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__SHIFT 0x1
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__SHIFT 0x2
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__SHIFT 0x3
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__SHIFT 0x4
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__SHIFT 0x5
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__SHIFT 0x6
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__SHIFT 0x7
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF0_DSTATE_INTR_STS__SHIFT 0x8
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF1_DSTATE_INTR_STS__SHIFT 0x9
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF2_DSTATE_INTR_STS__SHIFT 0xa
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF3_DSTATE_INTR_STS__SHIFT 0xb
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF4_DSTATE_INTR_STS__SHIFT 0xc
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF5_DSTATE_INTR_STS__SHIFT 0xd
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF6_DSTATE_INTR_STS__SHIFT 0xe
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF7_DSTATE_INTR_STS__SHIFT 0xf
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS_MASK 0x00000001L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS_MASK 0x00000002L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS_MASK 0x00000004L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS_MASK 0x00000008L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS_MASK 0x00000010L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS_MASK 0x00000020L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS_MASK 0x00000040L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS_MASK 0x00000080L
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF0_DSTATE_INTR_STS_MASK 0x00000100L
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF1_DSTATE_INTR_STS_MASK 0x00000200L
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF2_DSTATE_INTR_STS_MASK 0x00000400L
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF3_DSTATE_INTR_STS_MASK 0x00000800L
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF4_DSTATE_INTR_STS_MASK 0x00001000L
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF5_DSTATE_INTR_STS_MASK 0x00002000L
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF6_DSTATE_INTR_STS_MASK 0x00004000L
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF7_DSTATE_INTR_STS_MASK 0x00008000L
+//BIF_INST_RESET_INTR_MASK
+#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__SHIFT 0x0
+#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT 0x1
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__SHIFT 0x2
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__SHIFT 0x3
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__SHIFT 0x4
+#define BIF_INST_RESET_INTR_MASK__EP1_LINK_RESET_INTR_MASK__SHIFT 0x8
+#define BIF_INST_RESET_INTR_MASK__EP1_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT 0x9
+#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK_MASK 0x00000001L
+#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK_MASK 0x00000002L
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK_MASK 0x00000004L
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK_MASK 0x00000008L
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK_MASK 0x00000010L
+#define BIF_INST_RESET_INTR_MASK__EP1_LINK_RESET_INTR_MASK_MASK 0x00000100L
+#define BIF_INST_RESET_INTR_MASK__EP1_LINK_RESET_CFG_ONLY_INTR_MASK_MASK 0x00000200L
+//BIF_PF_FLR_INTR_MASK
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__SHIFT 0x0
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__SHIFT 0x1
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK__SHIFT 0x2
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK__SHIFT 0x3
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK__SHIFT 0x4
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK__SHIFT 0x5
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK__SHIFT 0x6
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK__SHIFT 0x7
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF0_FLR_INTR_MASK__SHIFT 0x8
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF1_FLR_INTR_MASK__SHIFT 0x9
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF2_FLR_INTR_MASK__SHIFT 0xa
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF3_FLR_INTR_MASK__SHIFT 0xb
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF4_FLR_INTR_MASK__SHIFT 0xc
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF5_FLR_INTR_MASK__SHIFT 0xd
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF6_FLR_INTR_MASK__SHIFT 0xe
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF7_FLR_INTR_MASK__SHIFT 0xf
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK_MASK 0x00000001L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK_MASK 0x00000002L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK_MASK 0x00000004L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK_MASK 0x00000008L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK_MASK 0x00000010L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK_MASK 0x00000020L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK_MASK 0x00000040L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK_MASK 0x00000080L
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF0_FLR_INTR_MASK_MASK 0x00000100L
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF1_FLR_INTR_MASK_MASK 0x00000200L
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF2_FLR_INTR_MASK_MASK 0x00000400L
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF3_FLR_INTR_MASK_MASK 0x00000800L
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF4_FLR_INTR_MASK_MASK 0x00001000L
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF5_FLR_INTR_MASK_MASK 0x00002000L
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF6_FLR_INTR_MASK_MASK 0x00004000L
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF7_FLR_INTR_MASK_MASK 0x00008000L
+//BIF_D3HOTD0_INTR_MASK
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__SHIFT 0x0
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__SHIFT 0x1
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK__SHIFT 0x2
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK__SHIFT 0x3
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK__SHIFT 0x4
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK__SHIFT 0x5
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK__SHIFT 0x6
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK__SHIFT 0x7
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF0_D3HOTD0_INTR_MASK__SHIFT 0x8
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF1_D3HOTD0_INTR_MASK__SHIFT 0x9
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF2_D3HOTD0_INTR_MASK__SHIFT 0xa
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF3_D3HOTD0_INTR_MASK__SHIFT 0xb
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF4_D3HOTD0_INTR_MASK__SHIFT 0xc
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF5_D3HOTD0_INTR_MASK__SHIFT 0xd
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF6_D3HOTD0_INTR_MASK__SHIFT 0xe
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF7_D3HOTD0_INTR_MASK__SHIFT 0xf
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK_MASK 0x00000001L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK_MASK 0x00000002L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK_MASK 0x00000004L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK_MASK 0x00000008L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK_MASK 0x00000010L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK_MASK 0x00000020L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK_MASK 0x00000040L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK_MASK 0x00000080L
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF0_D3HOTD0_INTR_MASK_MASK 0x00000100L
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF1_D3HOTD0_INTR_MASK_MASK 0x00000200L
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF2_D3HOTD0_INTR_MASK_MASK 0x00000400L
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF3_D3HOTD0_INTR_MASK_MASK 0x00000800L
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF4_D3HOTD0_INTR_MASK_MASK 0x00001000L
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF5_D3HOTD0_INTR_MASK_MASK 0x00002000L
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF6_D3HOTD0_INTR_MASK_MASK 0x00004000L
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF7_D3HOTD0_INTR_MASK_MASK 0x00008000L
+//BIF_POWER_INTR_MASK
+#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__SHIFT 0x0
+#define BIF_POWER_INTR_MASK__DEV1_PME_TURN_OFF_INTR_MASK__SHIFT 0x1
+#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT 0x10
+#define BIF_POWER_INTR_MASK__PORT1_DSTATE_INTR_MASK__SHIFT 0x11
+#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK_MASK 0x00000001L
+#define BIF_POWER_INTR_MASK__DEV1_PME_TURN_OFF_INTR_MASK_MASK 0x00000002L
+#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK_MASK 0x00010000L
+#define BIF_POWER_INTR_MASK__PORT1_DSTATE_INTR_MASK_MASK 0x00020000L
+//BIF_PF_DSTATE_INTR_MASK
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__SHIFT 0x0
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__SHIFT 0x1
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__SHIFT 0x2
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__SHIFT 0x3
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__SHIFT 0x4
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__SHIFT 0x5
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__SHIFT 0x6
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__SHIFT 0x7
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF0_DSTATE_INTR_MASK__SHIFT 0x8
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF1_DSTATE_INTR_MASK__SHIFT 0x9
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF2_DSTATE_INTR_MASK__SHIFT 0xa
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF3_DSTATE_INTR_MASK__SHIFT 0xb
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF4_DSTATE_INTR_MASK__SHIFT 0xc
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF5_DSTATE_INTR_MASK__SHIFT 0xd
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF6_DSTATE_INTR_MASK__SHIFT 0xe
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF7_DSTATE_INTR_MASK__SHIFT 0xf
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK_MASK 0x00000001L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK_MASK 0x00000002L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK_MASK 0x00000004L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK_MASK 0x00000008L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK_MASK 0x00000010L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK_MASK 0x00000020L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK_MASK 0x00000040L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK_MASK 0x00000080L
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF0_DSTATE_INTR_MASK_MASK 0x00000100L
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF1_DSTATE_INTR_MASK_MASK 0x00000200L
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF2_DSTATE_INTR_MASK_MASK 0x00000400L
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF3_DSTATE_INTR_MASK_MASK 0x00000800L
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF4_DSTATE_INTR_MASK_MASK 0x00001000L
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF5_DSTATE_INTR_MASK_MASK 0x00002000L
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF6_DSTATE_INTR_MASK_MASK 0x00004000L
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF7_DSTATE_INTR_MASK_MASK 0x00008000L
+//BIF_PF_FLR_RST
+#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0
+#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1
+#define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT 0x2
+#define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT 0x3
+#define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST__SHIFT 0x4
+#define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST__SHIFT 0x5
+#define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST__SHIFT 0x6
+#define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST__SHIFT 0x7
+#define BIF_PF_FLR_RST__DEV1_PF0_FLR_RST__SHIFT 0x8
+#define BIF_PF_FLR_RST__DEV1_PF1_FLR_RST__SHIFT 0x9
+#define BIF_PF_FLR_RST__DEV1_PF2_FLR_RST__SHIFT 0xa
+#define BIF_PF_FLR_RST__DEV1_PF3_FLR_RST__SHIFT 0xb
+#define BIF_PF_FLR_RST__DEV1_PF4_FLR_RST__SHIFT 0xc
+#define BIF_PF_FLR_RST__DEV1_PF5_FLR_RST__SHIFT 0xd
+#define BIF_PF_FLR_RST__DEV1_PF6_FLR_RST__SHIFT 0xe
+#define BIF_PF_FLR_RST__DEV1_PF7_FLR_RST__SHIFT 0xf
+#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK 0x00000001L
+#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK 0x00000002L
+#define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST_MASK 0x00000004L
+#define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST_MASK 0x00000008L
+#define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST_MASK 0x00000010L
+#define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST_MASK 0x00000020L
+#define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST_MASK 0x00000040L
+#define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST_MASK 0x00000080L
+#define BIF_PF_FLR_RST__DEV1_PF0_FLR_RST_MASK 0x00000100L
+#define BIF_PF_FLR_RST__DEV1_PF1_FLR_RST_MASK 0x00000200L
+#define BIF_PF_FLR_RST__DEV1_PF2_FLR_RST_MASK 0x00000400L
+#define BIF_PF_FLR_RST__DEV1_PF3_FLR_RST_MASK 0x00000800L
+#define BIF_PF_FLR_RST__DEV1_PF4_FLR_RST_MASK 0x00001000L
+#define BIF_PF_FLR_RST__DEV1_PF5_FLR_RST_MASK 0x00002000L
+#define BIF_PF_FLR_RST__DEV1_PF6_FLR_RST_MASK 0x00004000L
+#define BIF_PF_FLR_RST__DEV1_PF7_FLR_RST_MASK 0x00008000L
+//BIF_DEV0_PF0_DSTATE_VALUE
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF1_DSTATE_VALUE
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF2_DSTATE_VALUE
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF3_DSTATE_VALUE
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF4_DSTATE_VALUE
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF5_DSTATE_VALUE
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF6_DSTATE_VALUE
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF7_DSTATE_VALUE
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE_MASK 0x00030000L
+//DEV0_PF0_D3HOTD0_RST_CTRL
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF1_D3HOTD0_RST_CTRL
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF2_D3HOTD0_RST_CTRL
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF3_D3HOTD0_RST_CTRL
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF4_D3HOTD0_RST_CTRL
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF5_D3HOTD0_RST_CTRL
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF6_D3HOTD0_RST_CTRL
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF7_D3HOTD0_RST_CTRL
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV1_PF0_FLR_RST_CTRL
+#define DEV1_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV1_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV1_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV1_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV1_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV1_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV1_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV1_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV1_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV1_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV1_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV1_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV1_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV1_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV1_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV1_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV1_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV1_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV1_PF1_FLR_RST_CTRL
+#define DEV1_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV1_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV1_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV1_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV1_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV1_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV1_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV1_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV1_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV1_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV1_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV1_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV1_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV1_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV1_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV1_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV1_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV1_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV1_PF2_FLR_RST_CTRL
+#define DEV1_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV1_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV1_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV1_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV1_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV1_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV1_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV1_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV1_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV1_PF2_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV1_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV1_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV1_PF2_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV1_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV1_PF2_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV1_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV1_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV1_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV1_PF3_FLR_RST_CTRL
+#define DEV1_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV1_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV1_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV1_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV1_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV1_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV1_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV1_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV1_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV1_PF3_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV1_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV1_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV1_PF3_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV1_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV1_PF3_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV1_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV1_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV1_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV1_PF4_FLR_RST_CTRL
+#define DEV1_PF4_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV1_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV1_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV1_PF4_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV1_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV1_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV1_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV1_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV1_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV1_PF4_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV1_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV1_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV1_PF4_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV1_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV1_PF4_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV1_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV1_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV1_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV1_PF5_FLR_RST_CTRL
+#define DEV1_PF5_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV1_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV1_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV1_PF5_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV1_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV1_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV1_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV1_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV1_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV1_PF5_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV1_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV1_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV1_PF5_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV1_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV1_PF5_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV1_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV1_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV1_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV1_PF6_FLR_RST_CTRL
+#define DEV1_PF6_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV1_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV1_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV1_PF6_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV1_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV1_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV1_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV1_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV1_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV1_PF6_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV1_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV1_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV1_PF6_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV1_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV1_PF6_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV1_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV1_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV1_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV1_PF7_FLR_RST_CTRL
+#define DEV1_PF7_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV1_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV1_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV1_PF7_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV1_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV1_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV1_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV1_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV1_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV1_PF7_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV1_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV1_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV1_PF7_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV1_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV1_PF7_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV1_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV1_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV1_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//BIF_DEV1_PF0_DSTATE_VALUE
+#define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV1_PF1_DSTATE_VALUE
+#define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV1_PF2_DSTATE_VALUE
+#define BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV1_PF3_DSTATE_VALUE
+#define BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV1_PF4_DSTATE_VALUE
+#define BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV1_PF5_DSTATE_VALUE
+#define BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV1_PF6_DSTATE_VALUE
+#define BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV1_PF7_DSTATE_VALUE
+#define BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_ACK_VALUE_MASK 0x00030000L
+//DEV1_PF0_D3HOTD0_RST_CTRL
+#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV1_PF1_D3HOTD0_RST_CTRL
+#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV1_PF2_D3HOTD0_RST_CTRL
+#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV1_PF3_D3HOTD0_RST_CTRL
+#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV1_PF4_D3HOTD0_RST_CTRL
+#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV1_PF5_D3HOTD0_RST_CTRL
+#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV1_PF6_D3HOTD0_RST_CTRL
+#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV1_PF7_D3HOTD0_RST_CTRL
+#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//BIF_PORT0_DSTATE_VALUE
+#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_PORT1_DSTATE_VALUE
+#define BIF_PORT1_DSTATE_VALUE__PORT1_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_PORT1_DSTATE_VALUE__PORT1_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_PORT1_DSTATE_VALUE__PORT1_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_PORT1_DSTATE_VALUE__PORT1_DSTATE_ACK_VALUE_MASK 0x00030000L
+
+
+// addressBlock: nbio_nbif0_bif_ras_bif_ras_regblk
+//BIF_RAS_LEAF0_CTRL
+#define BIF_RAS_LEAF0_CTRL__POISON_DET_EN__SHIFT 0x0
+#define BIF_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define BIF_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define BIF_RAS_LEAF0_CTRL__PARITY_DET_EN__SHIFT 0x4
+#define BIF_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
+#define BIF_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT 0x6
+#define BIF_RAS_LEAF0_CTRL__LOCAL_ERR_REPORT_EN__SHIFT 0x7
+#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_RECV__SHIFT 0x10
+#define BIF_RAS_LEAF0_CTRL__LINK_DIS_RECV__SHIFT 0x11
+#define BIF_RAS_LEAF0_CTRL__POISON_ERR_DET__SHIFT 0x12
+#define BIF_RAS_LEAF0_CTRL__PARITY_ERR_DET__SHIFT 0x13
+#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_SENT__SHIFT 0x14
+#define BIF_RAS_LEAF0_CTRL__EGRESS_STALLED__SHIFT 0x15
+#define BIF_RAS_LEAF0_CTRL__POISON_DET_EN_MASK 0x00000001L
+#define BIF_RAS_LEAF0_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L
+#define BIF_RAS_LEAF0_CTRL__POISON_STALL_EN_MASK 0x00000004L
+#define BIF_RAS_LEAF0_CTRL__PARITY_DET_EN_MASK 0x00000010L
+#define BIF_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L
+#define BIF_RAS_LEAF0_CTRL__PARITY_STALL_EN_MASK 0x00000040L
+#define BIF_RAS_LEAF0_CTRL__LOCAL_ERR_REPORT_EN_MASK 0x00000080L
+#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_RECV_MASK 0x00010000L
+#define BIF_RAS_LEAF0_CTRL__LINK_DIS_RECV_MASK 0x00020000L
+#define BIF_RAS_LEAF0_CTRL__POISON_ERR_DET_MASK 0x00040000L
+#define BIF_RAS_LEAF0_CTRL__PARITY_ERR_DET_MASK 0x00080000L
+#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_SENT_MASK 0x00100000L
+#define BIF_RAS_LEAF0_CTRL__EGRESS_STALLED_MASK 0x00200000L
+//BIF_RAS_LEAF1_CTRL
+#define BIF_RAS_LEAF1_CTRL__POISON_DET_EN__SHIFT 0x0
+#define BIF_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define BIF_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define BIF_RAS_LEAF1_CTRL__PARITY_DET_EN__SHIFT 0x4
+#define BIF_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
+#define BIF_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT 0x6
+#define BIF_RAS_LEAF1_CTRL__LOCAL_ERR_REPORT_EN__SHIFT 0x7
+#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_RECV__SHIFT 0x10
+#define BIF_RAS_LEAF1_CTRL__LINK_DIS_RECV__SHIFT 0x11
+#define BIF_RAS_LEAF1_CTRL__POISON_ERR_DET__SHIFT 0x12
+#define BIF_RAS_LEAF1_CTRL__PARITY_ERR_DET__SHIFT 0x13
+#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_SENT__SHIFT 0x14
+#define BIF_RAS_LEAF1_CTRL__EGRESS_STALLED__SHIFT 0x15
+#define BIF_RAS_LEAF1_CTRL__POISON_DET_EN_MASK 0x00000001L
+#define BIF_RAS_LEAF1_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L
+#define BIF_RAS_LEAF1_CTRL__POISON_STALL_EN_MASK 0x00000004L
+#define BIF_RAS_LEAF1_CTRL__PARITY_DET_EN_MASK 0x00000010L
+#define BIF_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L
+#define BIF_RAS_LEAF1_CTRL__PARITY_STALL_EN_MASK 0x00000040L
+#define BIF_RAS_LEAF1_CTRL__LOCAL_ERR_REPORT_EN_MASK 0x00000080L
+#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_RECV_MASK 0x00010000L
+#define BIF_RAS_LEAF1_CTRL__LINK_DIS_RECV_MASK 0x00020000L
+#define BIF_RAS_LEAF1_CTRL__POISON_ERR_DET_MASK 0x00040000L
+#define BIF_RAS_LEAF1_CTRL__PARITY_ERR_DET_MASK 0x00080000L
+#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_SENT_MASK 0x00100000L
+#define BIF_RAS_LEAF1_CTRL__EGRESS_STALLED_MASK 0x00200000L
+//BIF_RAS_LEAF2_CTRL
+#define BIF_RAS_LEAF2_CTRL__POISON_DET_EN__SHIFT 0x0
+#define BIF_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define BIF_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define BIF_RAS_LEAF2_CTRL__PARITY_DET_EN__SHIFT 0x4
+#define BIF_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
+#define BIF_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT 0x6
+#define BIF_RAS_LEAF2_CTRL__LOCAL_ERR_REPORT_EN__SHIFT 0x7
+#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_RECV__SHIFT 0x10
+#define BIF_RAS_LEAF2_CTRL__LINK_DIS_RECV__SHIFT 0x11
+#define BIF_RAS_LEAF2_CTRL__POISON_ERR_DET__SHIFT 0x12
+#define BIF_RAS_LEAF2_CTRL__PARITY_ERR_DET__SHIFT 0x13
+#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_SENT__SHIFT 0x14
+#define BIF_RAS_LEAF2_CTRL__EGRESS_STALLED__SHIFT 0x15
+#define BIF_RAS_LEAF2_CTRL__POISON_DET_EN_MASK 0x00000001L
+#define BIF_RAS_LEAF2_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L
+#define BIF_RAS_LEAF2_CTRL__POISON_STALL_EN_MASK 0x00000004L
+#define BIF_RAS_LEAF2_CTRL__PARITY_DET_EN_MASK 0x00000010L
+#define BIF_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN_MASK 0x00000020L
+#define BIF_RAS_LEAF2_CTRL__PARITY_STALL_EN_MASK 0x00000040L
+#define BIF_RAS_LEAF2_CTRL__LOCAL_ERR_REPORT_EN_MASK 0x00000080L
+#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_RECV_MASK 0x00010000L
+#define BIF_RAS_LEAF2_CTRL__LINK_DIS_RECV_MASK 0x00020000L
+#define BIF_RAS_LEAF2_CTRL__POISON_ERR_DET_MASK 0x00040000L
+#define BIF_RAS_LEAF2_CTRL__PARITY_ERR_DET_MASK 0x00080000L
+#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_SENT_MASK 0x00100000L
+#define BIF_RAS_LEAF2_CTRL__EGRESS_STALLED_MASK 0x00200000L
+//BIF_RAS_MISC_CTRL
+#define BIF_RAS_MISC_CTRL__LINKDIS_TRIG_ERREVENT_EN__SHIFT 0x0
+#define BIF_RAS_MISC_CTRL__LINKDIS_TRIG_ERREVENT_EN_MASK 0x00000001L
+//BIF_IOHUB_RAS_IH_CNTL
+#define BIF_IOHUB_RAS_IH_CNTL__RAS_IH_INTR_EN__SHIFT 0x0
+#define BIF_IOHUB_RAS_IH_CNTL__RAS_IH_INTR_EN_MASK 0x00000001L
+//BIF_RAS_VWR_FROM_IOHUB
+#define BIF_RAS_VWR_FROM_IOHUB__RAS_IH_INTR_TRIG__SHIFT 0x0
+#define BIF_RAS_VWR_FROM_IOHUB__RAS_IH_INTR_TRIG_MASK 0x00000001L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_2_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_2_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_2_COMMAND
+#define BIF_CFG_DEV0_EPF0_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_2_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_2_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_2_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_2_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_2_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_2_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_2_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_2_STATUS
+#define BIF_CFG_DEV0_EPF0_2_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_2_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_2_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_2_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_2_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_2_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_2_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_2_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_2_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_2_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_2_LATENCY
+#define BIF_CFG_DEV0_EPF0_2_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_2_HEADER
+#define BIF_CFG_DEV0_EPF0_2_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_2_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_2_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_2_BIST
+#define BIF_CFG_DEV0_EPF0_2_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_2_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_2_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_2_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_2_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_2_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_2_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_2_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_2_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_2_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_2_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_2_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_2_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_2_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF0_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF0_2_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF0_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_2_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_2_PMI_CAP
+#define BIF_CFG_DEV0_EPF0_2_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_2_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_2_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF0_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_2_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_2_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_2_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_2_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_2_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_2_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_2_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_2_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_2_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_2_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_2_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_2_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_2_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_2_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_2_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_2_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_2_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_2_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_2_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_2_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_2_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_2_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF0_2_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_2_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
+#define BIF_CFG_DEV0_EPF0_2_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define BIF_CFG_DEV0_EPF0_2_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF0_2_PCIE_MC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_MC_CAP
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_MC_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_MC_RCV0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_MC_RCV1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_ALL0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_ALL1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CAP
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L
+//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_STATUS
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_INITIAL_VFS
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_TOTAL_VFS
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_NUM_VFS
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_FUNC_DEP_LINK
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0x00FFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_FIRST_VF_OFFSET
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_STRIDE
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x00000002L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp
+//BIF_CFG_DEV0_EPF1_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_COMMAND
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF1_1_STATUS
+#define BIF_CFG_DEV0_EPF1_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF1_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF1_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_LATENCY
+#define BIF_CFG_DEV0_EPF1_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_HEADER
+#define BIF_CFG_DEV0_EPF1_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF1_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF1_1_BIST
+#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF1_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF1_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF1_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_PMI_CAP
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF1_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF1_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF1_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF1_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF1_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF1_1_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF1_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF1_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF1_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF1_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF1_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF1_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
+#define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0x00FFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x00000002L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp
+//BIF_CFG_DEV0_EPF2_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF2_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_1_COMMAND
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF2_1_STATUS
+#define BIF_CFG_DEV0_EPF2_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF2_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF2_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF2_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF2_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF2_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF2_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_LATENCY
+#define BIF_CFG_DEV0_EPF2_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_HEADER
+#define BIF_CFG_DEV0_EPF2_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF2_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF2_1_BIST
+#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF2_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF2_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF2_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PMI_CAP
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_1_SBRN
+#define BIF_CFG_DEV0_EPF2_1_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_FLADJ
+#define BIF_CFG_DEV0_EPF2_1_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_FLADJ__FLADJ_MASK 0x3FL
+//BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF2_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF2_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF2_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF2_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF2_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF2_1_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF2_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF2_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_1_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF2_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF2_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF2_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF2_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF2_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF2_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF2_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF2_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF2_1_SATA_CAP_0
+#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_1_SATA_CAP_1
+#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX
+#define BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF2_1_SATA_IDP_DATA
+#define BIF_CFG_DEV0_EPF2_1_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp
+//BIF_CFG_DEV0_EPF3_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF3_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_1_COMMAND
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF3_1_STATUS
+#define BIF_CFG_DEV0_EPF3_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF3_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF3_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF3_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF3_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF3_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF3_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF3_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_LATENCY
+#define BIF_CFG_DEV0_EPF3_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_HEADER
+#define BIF_CFG_DEV0_EPF3_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF3_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF3_1_BIST
+#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF3_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF3_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF3_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PMI_CAP
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_1_SBRN
+#define BIF_CFG_DEV0_EPF3_1_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_FLADJ
+#define BIF_CFG_DEV0_EPF3_1_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_FLADJ__FLADJ_MASK 0x3FL
+//BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF3_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF3_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF3_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF3_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF3_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF3_1_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF3_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF3_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_1_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF3_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF3_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF3_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF3_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF3_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF3_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF3_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF3_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF3_1_SATA_CAP_0
+#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_1_SATA_CAP_1
+#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX
+#define BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF3_1_SATA_IDP_DATA
+#define BIF_CFG_DEV0_EPF3_1_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp
+//BIF_CFG_DEV0_EPF4_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF4_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_1_COMMAND
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF4_1_STATUS
+#define BIF_CFG_DEV0_EPF4_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF4_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF4_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF4_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF4_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF4_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF4_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF4_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF4_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF4_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF4_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF4_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF4_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_LATENCY
+#define BIF_CFG_DEV0_EPF4_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_HEADER
+#define BIF_CFG_DEV0_EPF4_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF4_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF4_1_BIST
+#define BIF_CFG_DEV0_EPF4_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF4_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF4_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF4_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF4_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF4_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF4_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF4_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF4_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF4_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF4_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PMI_CAP
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF4_1_SBRN
+#define BIF_CFG_DEV0_EPF4_1_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_FLADJ
+#define BIF_CFG_DEV0_EPF4_1_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_FLADJ__FLADJ_MASK 0x3FL
+//BIF_CFG_DEV0_EPF4_1_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF4_1_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF4_1_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF4_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF4_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF4_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF4_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF4_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF4_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF4_1_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF4_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF4_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_1_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF4_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF4_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF4_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF4_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF4_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF4_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF4_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF4_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF4_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF4_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF4_1_SATA_CAP_0
+#define BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV0_EPF4_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF4_1_SATA_CAP_1
+#define BIF_CFG_DEV0_EPF4_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF4_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV0_EPF4_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF4_1_SATA_IDP_INDEX
+#define BIF_CFG_DEV0_EPF4_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF4_1_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV0_EPF4_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF4_1_SATA_IDP_DATA
+#define BIF_CFG_DEV0_EPF4_1_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp
+//BIF_CFG_DEV0_EPF5_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF5_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_1_COMMAND
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF5_1_STATUS
+#define BIF_CFG_DEV0_EPF5_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF5_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF5_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF5_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF5_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF5_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF5_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF5_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF5_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF5_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF5_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF5_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF5_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_LATENCY
+#define BIF_CFG_DEV0_EPF5_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_HEADER
+#define BIF_CFG_DEV0_EPF5_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF5_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF5_1_BIST
+#define BIF_CFG_DEV0_EPF5_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF5_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF5_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF5_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF5_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF5_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF5_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF5_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF5_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF5_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF5_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PMI_CAP
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF5_1_SBRN
+#define BIF_CFG_DEV0_EPF5_1_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_FLADJ
+#define BIF_CFG_DEV0_EPF5_1_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_FLADJ__FLADJ_MASK 0x3FL
+//BIF_CFG_DEV0_EPF5_1_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF5_1_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF5_1_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF5_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF5_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF5_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF5_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF5_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF5_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF5_1_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF5_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF5_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_1_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF5_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF5_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF5_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF5_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF5_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF5_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF5_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF5_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF5_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF5_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF5_1_SATA_CAP_0
+#define BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV0_EPF5_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF5_1_SATA_CAP_1
+#define BIF_CFG_DEV0_EPF5_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF5_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV0_EPF5_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF5_1_SATA_IDP_INDEX
+#define BIF_CFG_DEV0_EPF5_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF5_1_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV0_EPF5_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF5_1_SATA_IDP_DATA
+#define BIF_CFG_DEV0_EPF5_1_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp
+//BIF_CFG_DEV0_EPF6_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF6_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_1_COMMAND
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF6_1_STATUS
+#define BIF_CFG_DEV0_EPF6_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF6_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF6_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF6_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF6_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF6_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF6_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF6_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF6_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF6_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF6_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF6_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF6_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_LATENCY
+#define BIF_CFG_DEV0_EPF6_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_HEADER
+#define BIF_CFG_DEV0_EPF6_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF6_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF6_1_BIST
+#define BIF_CFG_DEV0_EPF6_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF6_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF6_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF6_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF6_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF6_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF6_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF6_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF6_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF6_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF6_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PMI_CAP
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF6_1_SBRN
+#define BIF_CFG_DEV0_EPF6_1_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_FLADJ
+#define BIF_CFG_DEV0_EPF6_1_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_FLADJ__FLADJ_MASK 0x3FL
+//BIF_CFG_DEV0_EPF6_1_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF6_1_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF6_1_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF6_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF6_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF6_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF6_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF6_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF6_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF6_1_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF6_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF6_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_1_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF6_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF6_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF6_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF6_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF6_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF6_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF6_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF6_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF6_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF6_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF6_1_SATA_CAP_0
+#define BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV0_EPF6_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF6_1_SATA_CAP_1
+#define BIF_CFG_DEV0_EPF6_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF6_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV0_EPF6_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF6_1_SATA_IDP_INDEX
+#define BIF_CFG_DEV0_EPF6_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF6_1_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV0_EPF6_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF6_1_SATA_IDP_DATA
+#define BIF_CFG_DEV0_EPF6_1_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf7_bifcfgdecp
+//BIF_CFG_DEV0_EPF7_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF7_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF7_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF7_1_COMMAND
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF7_1_STATUS
+#define BIF_CFG_DEV0_EPF7_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF7_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF7_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF7_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF7_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF7_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF7_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF7_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF7_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF7_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF7_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF7_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF7_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF7_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF7_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF7_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_LATENCY
+#define BIF_CFG_DEV0_EPF7_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_HEADER
+#define BIF_CFG_DEV0_EPF7_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF7_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF7_1_BIST
+#define BIF_CFG_DEV0_EPF7_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF7_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF7_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF7_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF7_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF7_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF7_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF7_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF7_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF7_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF7_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PMI_CAP
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF7_1_SBRN
+#define BIF_CFG_DEV0_EPF7_1_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_FLADJ
+#define BIF_CFG_DEV0_EPF7_1_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_FLADJ__FLADJ_MASK 0x3FL
+//BIF_CFG_DEV0_EPF7_1_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF7_1_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF7_1_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF7_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF7_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF7_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF7_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF7_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF7_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF7_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF7_1_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF7_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF7_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF7_1_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF7_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF7_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF7_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF7_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF7_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF7_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF7_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF7_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF7_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF7_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF7_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF7_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF7_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF7_1_SATA_CAP_0
+#define BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV0_EPF7_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF7_1_SATA_CAP_1
+#define BIF_CFG_DEV0_EPF7_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF7_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV0_EPF7_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF7_1_SATA_IDP_INDEX
+#define BIF_CFG_DEV0_EPF7_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF7_1_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV0_EPF7_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF7_1_SATA_IDP_DATA
+#define BIF_CFG_DEV0_EPF7_1_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_epf0_bifcfgdecp
+//BIF_CFG_DEV1_EPF0_1_VENDOR_ID
+#define BIF_CFG_DEV1_EPF0_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF0_1_DEVICE_ID
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF0_1_COMMAND
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV1_EPF0_1_STATUS
+#define BIF_CFG_DEV1_EPF0_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF0_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV1_EPF0_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF0_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV1_EPF0_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV1_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF0_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_1_REVISION_ID
+#define BIF_CFG_DEV1_EPF0_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_1_PROG_INTERFACE
+#define BIF_CFG_DEV1_EPF0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_SUB_CLASS
+#define BIF_CFG_DEV1_EPF0_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_BASE_CLASS
+#define BIF_CFG_DEV1_EPF0_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_CACHE_LINE
+#define BIF_CFG_DEV1_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_LATENCY
+#define BIF_CFG_DEV1_EPF0_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_HEADER
+#define BIF_CFG_DEV1_EPF0_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV1_EPF0_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV1_EPF0_1_BIST
+#define BIF_CFG_DEV1_EPF0_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV1_EPF0_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV1_EPF0_1_BASE_ADDR_1
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_BASE_ADDR_2
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_BASE_ADDR_3
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_BASE_ADDR_4
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_BASE_ADDR_5
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_BASE_ADDR_6
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_ADAPTER_ID
+#define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV1_EPF0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_CAP_PTR
+#define BIF_CFG_DEV1_EPF0_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV1_EPF0_1_INTERRUPT_LINE
+#define BIF_CFG_DEV1_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_INTERRUPT_PIN
+#define BIF_CFG_DEV1_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_MIN_GRANT
+#define BIF_CFG_DEV1_EPF0_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_MAX_LATENCY
+#define BIF_CFG_DEV1_EPF0_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W
+#define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PMI_CAP
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV1_EPF0_1_DEVICE_CAP
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV1_EPF0_1_LINK_CAP
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_1_LINK_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV1_EPF0_1_LINK_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS2
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF0_1_LINK_CAP2
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV1_EPF0_1_LINK_CNTL2
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV1_EPF0_1_LINK_STATUS2
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV1_EPF0_1_SLOT_CAP2
+#define BIF_CFG_DEV1_EPF0_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_SLOT_CNTL2
+#define BIF_CFG_DEV1_EPF0_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF0_1_SLOT_STATUS2
+#define BIF_CFG_DEV1_EPF0_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_EPF0_1_MSI_MASK
+#define BIF_CFG_DEV1_EPF0_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_EPF0_1_MSI_MASK_64
+#define BIF_CFG_DEV1_EPF0_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_MSI_PENDING
+#define BIF_CFG_DEV1_EPF0_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_MSI_PENDING_64
+#define BIF_CFG_DEV1_EPF0_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_1_MSIX_TABLE
+#define BIF_CFG_DEV1_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF0_1_MSIX_PBA
+#define BIF_CFG_DEV1_EPF0_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF0_1_SATA_CAP_0
+#define BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV1_EPF0_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_1_SATA_CAP_1
+#define BIF_CFG_DEV1_EPF0_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF0_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV1_EPF0_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_1_SATA_IDP_INDEX
+#define BIF_CFG_DEV1_EPF0_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV1_EPF0_1_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV1_EPF0_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV1_EPF0_1_SATA_IDP_DATA
+#define BIF_CFG_DEV1_EPF0_1_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_epf1_bifcfgdecp
+//BIF_CFG_DEV1_EPF1_1_VENDOR_ID
+#define BIF_CFG_DEV1_EPF1_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF1_1_DEVICE_ID
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF1_1_COMMAND
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV1_EPF1_1_STATUS
+#define BIF_CFG_DEV1_EPF1_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF1_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV1_EPF1_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF1_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV1_EPF1_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV1_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF1_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF1_1_REVISION_ID
+#define BIF_CFG_DEV1_EPF1_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF1_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV1_EPF1_1_PROG_INTERFACE
+#define BIF_CFG_DEV1_EPF1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_SUB_CLASS
+#define BIF_CFG_DEV1_EPF1_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_BASE_CLASS
+#define BIF_CFG_DEV1_EPF1_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_CACHE_LINE
+#define BIF_CFG_DEV1_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_LATENCY
+#define BIF_CFG_DEV1_EPF1_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_HEADER
+#define BIF_CFG_DEV1_EPF1_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV1_EPF1_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV1_EPF1_1_BIST
+#define BIF_CFG_DEV1_EPF1_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF1_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV1_EPF1_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV1_EPF1_1_BASE_ADDR_1
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_BASE_ADDR_2
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_BASE_ADDR_3
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_BASE_ADDR_4
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_BASE_ADDR_5
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_BASE_ADDR_6
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_ADAPTER_ID
+#define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV1_EPF1_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_CAP_PTR
+#define BIF_CFG_DEV1_EPF1_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV1_EPF1_1_INTERRUPT_LINE
+#define BIF_CFG_DEV1_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_INTERRUPT_PIN
+#define BIF_CFG_DEV1_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_MIN_GRANT
+#define BIF_CFG_DEV1_EPF1_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_MAX_LATENCY
+#define BIF_CFG_DEV1_EPF1_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W
+#define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PMI_CAP
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF1_1_SBRN
+#define BIF_CFG_DEV1_EPF1_1_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_FLADJ
+#define BIF_CFG_DEV1_EPF1_1_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_FLADJ__FLADJ_MASK 0x3FL
+//BIF_CFG_DEV1_EPF1_1_DBESL_DBESLD
+#define BIF_CFG_DEV1_EPF1_1_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF1_1_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV1_EPF1_1_DEVICE_CAP
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV1_EPF1_1_LINK_CAP
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF1_1_LINK_CNTL
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV1_EPF1_1_LINK_STATUS
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS2
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF1_1_LINK_CAP2
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV1_EPF1_1_LINK_CNTL2
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV1_EPF1_1_LINK_STATUS2
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV1_EPF1_1_SLOT_CAP2
+#define BIF_CFG_DEV1_EPF1_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_SLOT_CNTL2
+#define BIF_CFG_DEV1_EPF1_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF1_1_SLOT_STATUS2
+#define BIF_CFG_DEV1_EPF1_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_EPF1_1_MSI_MASK
+#define BIF_CFG_DEV1_EPF1_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_EPF1_1_MSI_MASK_64
+#define BIF_CFG_DEV1_EPF1_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_MSI_PENDING
+#define BIF_CFG_DEV1_EPF1_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_MSI_PENDING_64
+#define BIF_CFG_DEV1_EPF1_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV1_EPF1_1_MSIX_TABLE
+#define BIF_CFG_DEV1_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF1_1_MSIX_PBA
+#define BIF_CFG_DEV1_EPF1_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF1_1_SATA_CAP_0
+#define BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV1_EPF1_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF1_1_SATA_CAP_1
+#define BIF_CFG_DEV1_EPF1_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF1_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV1_EPF1_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF1_1_SATA_IDP_INDEX
+#define BIF_CFG_DEV1_EPF1_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV1_EPF1_1_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV1_EPF1_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV1_EPF1_1_SATA_IDP_DATA
+#define BIF_CFG_DEV1_EPF1_1_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_epf2_bifcfgdecp
+//BIF_CFG_DEV1_EPF2_1_VENDOR_ID
+#define BIF_CFG_DEV1_EPF2_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF2_1_DEVICE_ID
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF2_1_COMMAND
+#define BIF_CFG_DEV1_EPF2_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF2_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF2_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF2_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF2_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF2_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF2_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF2_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF2_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF2_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF2_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF2_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV1_EPF2_1_STATUS
+#define BIF_CFG_DEV1_EPF2_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF2_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF2_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF2_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF2_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF2_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF2_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV1_EPF2_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF2_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV1_EPF2_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV1_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF2_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF2_1_REVISION_ID
+#define BIF_CFG_DEV1_EPF2_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF2_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV1_EPF2_1_PROG_INTERFACE
+#define BIF_CFG_DEV1_EPF2_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_1_SUB_CLASS
+#define BIF_CFG_DEV1_EPF2_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_1_BASE_CLASS
+#define BIF_CFG_DEV1_EPF2_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_1_CACHE_LINE
+#define BIF_CFG_DEV1_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_1_LATENCY
+#define BIF_CFG_DEV1_EPF2_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_1_HEADER
+#define BIF_CFG_DEV1_EPF2_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV1_EPF2_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV1_EPF2_1_BIST
+#define BIF_CFG_DEV1_EPF2_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF2_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV1_EPF2_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV1_EPF2_1_BASE_ADDR_1
+#define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_1_BASE_ADDR_2
+#define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_1_BASE_ADDR_3
+#define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_1_BASE_ADDR_4
+#define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_1_BASE_ADDR_5
+#define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_1_BASE_ADDR_6
+#define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_1_ADAPTER_ID
+#define BIF_CFG_DEV1_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF2_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV1_EPF2_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_1_CAP_PTR
+#define BIF_CFG_DEV1_EPF2_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV1_EPF2_1_INTERRUPT_LINE
+#define BIF_CFG_DEV1_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_1_INTERRUPT_PIN
+#define BIF_CFG_DEV1_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_1_MIN_GRANT
+#define BIF_CFG_DEV1_EPF2_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_1_MAX_LATENCY
+#define BIF_CFG_DEV1_EPF2_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV1_EPF2_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV1_EPF2_1_ADAPTER_ID_W
+#define BIF_CFG_DEV1_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF2_1_PMI_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF2_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF2_1_PMI_CAP
+#define BIF_CFG_DEV1_EPF2_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF2_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF2_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF2_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF2_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV1_EPF2_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF2_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF2_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF2_1_SBRN
+#define BIF_CFG_DEV1_EPF2_1_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_1_FLADJ
+#define BIF_CFG_DEV1_EPF2_1_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_FLADJ__FLADJ_MASK 0x3FL
+//BIF_CFG_DEV1_EPF2_1_DBESL_DBESLD
+#define BIF_CFG_DEV1_EPF2_1_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_1_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF2_1_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV1_EPF2_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF2_1_PCIE_CAP
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV1_EPF2_1_DEVICE_CAP
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV1_EPF2_1_LINK_CAP
+#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF2_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF2_1_LINK_CNTL
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV1_EPF2_1_LINK_STATUS
+#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS2
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF2_1_LINK_CAP2
+#define BIF_CFG_DEV1_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV1_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF2_1_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV1_EPF2_1_LINK_CNTL2
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV1_EPF2_1_LINK_STATUS2
+#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV1_EPF2_1_SLOT_CAP2
+#define BIF_CFG_DEV1_EPF2_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_1_SLOT_CNTL2
+#define BIF_CFG_DEV1_EPF2_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF2_1_SLOT_STATUS2
+#define BIF_CFG_DEV1_EPF2_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF2_1_MSI_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF2_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV1_EPF2_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV1_EPF2_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_1_MSI_MSG_DATA
+#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_EPF2_1_MSI_MASK
+#define BIF_CFG_DEV1_EPF2_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_EPF2_1_MSI_MASK_64
+#define BIF_CFG_DEV1_EPF2_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_1_MSI_PENDING
+#define BIF_CFG_DEV1_EPF2_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_1_MSI_PENDING_64
+#define BIF_CFG_DEV1_EPF2_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF2_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF2_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV1_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF2_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV1_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF2_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV1_EPF2_1_MSIX_TABLE
+#define BIF_CFG_DEV1_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF2_1_MSIX_PBA
+#define BIF_CFG_DEV1_EPF2_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF2_1_SATA_CAP_0
+#define BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV1_EPF2_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF2_1_SATA_CAP_1
+#define BIF_CFG_DEV1_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV1_EPF2_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF2_1_SATA_IDP_INDEX
+#define BIF_CFG_DEV1_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV1_EPF2_1_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV1_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV1_EPF2_1_SATA_IDP_DATA
+#define BIF_CFG_DEV1_EPF2_1_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV1_EPF2_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF2_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV1_EPF2_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_pciemsix_amdgfx_MSIXTDEC
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_ADDR_LO
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_ADDR_HI
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_MSG_DATA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_CONTROL
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_ADDR_LO
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_ADDR_HI
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_MSG_DATA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_CONTROL
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_ADDR_LO
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_ADDR_HI
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_MSG_DATA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_CONTROL
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_ADDR_LO
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_ADDR_HI
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_MSG_DATA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_CONTROL
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_ADDR_LO
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_ADDR_HI
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_MSG_DATA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_CONTROL
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_ADDR_LO
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_ADDR_HI
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_MSG_DATA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_CONTROL
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_ADDR_LO
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_ADDR_HI
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_MSG_DATA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_CONTROL
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_ADDR_LO
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_ADDR_HI
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_MSG_DATA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_CONTROL
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_ADDR_LO
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_ADDR_HI
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_MSG_DATA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_CONTROL
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_ADDR_LO
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_ADDR_HI
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_MSG_DATA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_CONTROL
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_ADDR_LO
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_ADDR_HI
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_MSG_DATA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_CONTROL
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_ADDR_LO
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_ADDR_HI
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_MSG_DATA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_CONTROL
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_ADDR_LO
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_ADDR_HI
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_MSG_DATA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_CONTROL
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_ADDR_LO
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_ADDR_HI
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_MSG_DATA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_CONTROL
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_ADDR_LO
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_ADDR_HI
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_MSG_DATA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_CONTROL
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_ADDR_LO
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_ADDR_HI
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_MSG_DATA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_CONTROL
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_ADDR_LO
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_ADDR_HI
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_MSG_DATA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_CONTROL
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_ADDR_LO
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_ADDR_HI
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_MSG_DATA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_CONTROL
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_ADDR_LO
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_ADDR_HI
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_MSG_DATA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_CONTROL
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_ADDR_LO
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_ADDR_HI
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_MSG_DATA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_CONTROL
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_ADDR_LO
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_ADDR_HI
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_MSG_DATA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_CONTROL
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_ADDR_LO
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_ADDR_HI
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_MSG_DATA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_CONTROL
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_ADDR_LO
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_ADDR_HI
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_MSG_DATA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_CONTROL
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_ADDR_LO
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_ADDR_HI
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_MSG_DATA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_CONTROL
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_ADDR_LO
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_ADDR_HI
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_MSG_DATA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_CONTROL
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_ADDR_LO
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_ADDR_HI
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_MSG_DATA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_CONTROL
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_ADDR_LO
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_ADDR_HI
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_MSG_DATA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_CONTROL
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_ADDR_LO
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_ADDR_HI
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_MSG_DATA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_CONTROL
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_ADDR_LO
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_ADDR_HI
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_MSG_DATA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_CONTROL
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_ADDR_LO
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_ADDR_HI
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_MSG_DATA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_CONTROL
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_ADDR_LO
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_ADDR_HI
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_MSG_DATA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_CONTROL
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_ADDR_LO
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_ADDR_HI
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_MSG_DATA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_CONTROL
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK 0x00000001L
+
+
+// addressBlock: nbio_nbif0_pciemsix_psp_MSIXTDEC
+//PCIEMSIX_PSP_PCIEMSIX_VECT0_ADDR_LO
+#define PCIEMSIX_PSP_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_PSP_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_PSP_PCIEMSIX_VECT0_ADDR_HI
+#define PCIEMSIX_PSP_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT0_MSG_DATA
+#define PCIEMSIX_PSP_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT0_CONTROL
+#define PCIEMSIX_PSP_PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_PSP_PCIEMSIX_VECT1_ADDR_LO
+#define PCIEMSIX_PSP_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_PSP_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_PSP_PCIEMSIX_VECT1_ADDR_HI
+#define PCIEMSIX_PSP_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT1_MSG_DATA
+#define PCIEMSIX_PSP_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT1_CONTROL
+#define PCIEMSIX_PSP_PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_PSP_PCIEMSIX_VECT2_ADDR_LO
+#define PCIEMSIX_PSP_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_PSP_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_PSP_PCIEMSIX_VECT2_ADDR_HI
+#define PCIEMSIX_PSP_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT2_MSG_DATA
+#define PCIEMSIX_PSP_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT2_CONTROL
+#define PCIEMSIX_PSP_PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_PSP_PCIEMSIX_VECT3_ADDR_LO
+#define PCIEMSIX_PSP_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_PSP_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_PSP_PCIEMSIX_VECT3_ADDR_HI
+#define PCIEMSIX_PSP_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT3_MSG_DATA
+#define PCIEMSIX_PSP_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT3_CONTROL
+#define PCIEMSIX_PSP_PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_PSP_PCIEMSIX_VECT4_ADDR_LO
+#define PCIEMSIX_PSP_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_PSP_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_PSP_PCIEMSIX_VECT4_ADDR_HI
+#define PCIEMSIX_PSP_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT4_MSG_DATA
+#define PCIEMSIX_PSP_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT4_CONTROL
+#define PCIEMSIX_PSP_PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_PSP_PCIEMSIX_VECT5_ADDR_LO
+#define PCIEMSIX_PSP_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_PSP_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_PSP_PCIEMSIX_VECT5_ADDR_HI
+#define PCIEMSIX_PSP_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT5_MSG_DATA
+#define PCIEMSIX_PSP_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT5_CONTROL
+#define PCIEMSIX_PSP_PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_PSP_PCIEMSIX_VECT6_ADDR_LO
+#define PCIEMSIX_PSP_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_PSP_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_PSP_PCIEMSIX_VECT6_ADDR_HI
+#define PCIEMSIX_PSP_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT6_MSG_DATA
+#define PCIEMSIX_PSP_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT6_CONTROL
+#define PCIEMSIX_PSP_PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_PSP_PCIEMSIX_VECT7_ADDR_LO
+#define PCIEMSIX_PSP_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_PSP_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_PSP_PCIEMSIX_VECT7_ADDR_HI
+#define PCIEMSIX_PSP_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT7_MSG_DATA
+#define PCIEMSIX_PSP_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT7_CONTROL
+#define PCIEMSIX_PSP_PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_PSP_PCIEMSIX_VECT8_ADDR_LO
+#define PCIEMSIX_PSP_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_PSP_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_PSP_PCIEMSIX_VECT8_ADDR_HI
+#define PCIEMSIX_PSP_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT8_MSG_DATA
+#define PCIEMSIX_PSP_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT8_CONTROL
+#define PCIEMSIX_PSP_PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_PSP_PCIEMSIX_VECT9_ADDR_LO
+#define PCIEMSIX_PSP_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_PSP_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_PSP_PCIEMSIX_VECT9_ADDR_HI
+#define PCIEMSIX_PSP_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT9_MSG_DATA
+#define PCIEMSIX_PSP_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT9_CONTROL
+#define PCIEMSIX_PSP_PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_PSP_PCIEMSIX_VECT10_ADDR_LO
+#define PCIEMSIX_PSP_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_PSP_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_PSP_PCIEMSIX_VECT10_ADDR_HI
+#define PCIEMSIX_PSP_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT10_MSG_DATA
+#define PCIEMSIX_PSP_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT10_CONTROL
+#define PCIEMSIX_PSP_PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_PSP_PCIEMSIX_VECT11_ADDR_LO
+#define PCIEMSIX_PSP_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_PSP_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_PSP_PCIEMSIX_VECT11_ADDR_HI
+#define PCIEMSIX_PSP_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT11_MSG_DATA
+#define PCIEMSIX_PSP_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT11_CONTROL
+#define PCIEMSIX_PSP_PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_PSP_PCIEMSIX_VECT12_ADDR_LO
+#define PCIEMSIX_PSP_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_PSP_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_PSP_PCIEMSIX_VECT12_ADDR_HI
+#define PCIEMSIX_PSP_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT12_MSG_DATA
+#define PCIEMSIX_PSP_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT12_CONTROL
+#define PCIEMSIX_PSP_PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_PSP_PCIEMSIX_VECT13_ADDR_LO
+#define PCIEMSIX_PSP_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_PSP_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_PSP_PCIEMSIX_VECT13_ADDR_HI
+#define PCIEMSIX_PSP_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT13_MSG_DATA
+#define PCIEMSIX_PSP_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT13_CONTROL
+#define PCIEMSIX_PSP_PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_PSP_PCIEMSIX_VECT14_ADDR_LO
+#define PCIEMSIX_PSP_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_PSP_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_PSP_PCIEMSIX_VECT14_ADDR_HI
+#define PCIEMSIX_PSP_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT14_MSG_DATA
+#define PCIEMSIX_PSP_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT14_CONTROL
+#define PCIEMSIX_PSP_PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_PSP_PCIEMSIX_VECT15_ADDR_LO
+#define PCIEMSIX_PSP_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_PSP_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_PSP_PCIEMSIX_VECT15_ADDR_HI
+#define PCIEMSIX_PSP_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT15_MSG_DATA
+#define PCIEMSIX_PSP_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT15_CONTROL
+#define PCIEMSIX_PSP_PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_PSP_PCIEMSIX_VECT16_ADDR_LO
+#define PCIEMSIX_PSP_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_PSP_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_PSP_PCIEMSIX_VECT16_ADDR_HI
+#define PCIEMSIX_PSP_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT16_MSG_DATA
+#define PCIEMSIX_PSP_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT16_CONTROL
+#define PCIEMSIX_PSP_PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_PSP_PCIEMSIX_VECT17_ADDR_LO
+#define PCIEMSIX_PSP_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_PSP_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_PSP_PCIEMSIX_VECT17_ADDR_HI
+#define PCIEMSIX_PSP_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT17_MSG_DATA
+#define PCIEMSIX_PSP_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT17_CONTROL
+#define PCIEMSIX_PSP_PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_PSP_PCIEMSIX_VECT18_ADDR_LO
+#define PCIEMSIX_PSP_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_PSP_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_PSP_PCIEMSIX_VECT18_ADDR_HI
+#define PCIEMSIX_PSP_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT18_MSG_DATA
+#define PCIEMSIX_PSP_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT18_CONTROL
+#define PCIEMSIX_PSP_PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_PSP_PCIEMSIX_VECT19_ADDR_LO
+#define PCIEMSIX_PSP_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_PSP_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_PSP_PCIEMSIX_VECT19_ADDR_HI
+#define PCIEMSIX_PSP_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT19_MSG_DATA
+#define PCIEMSIX_PSP_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT19_CONTROL
+#define PCIEMSIX_PSP_PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_PSP_PCIEMSIX_VECT20_ADDR_LO
+#define PCIEMSIX_PSP_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_PSP_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_PSP_PCIEMSIX_VECT20_ADDR_HI
+#define PCIEMSIX_PSP_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT20_MSG_DATA
+#define PCIEMSIX_PSP_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT20_CONTROL
+#define PCIEMSIX_PSP_PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_PSP_PCIEMSIX_VECT21_ADDR_LO
+#define PCIEMSIX_PSP_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_PSP_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_PSP_PCIEMSIX_VECT21_ADDR_HI
+#define PCIEMSIX_PSP_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT21_MSG_DATA
+#define PCIEMSIX_PSP_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT21_CONTROL
+#define PCIEMSIX_PSP_PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_PSP_PCIEMSIX_VECT22_ADDR_LO
+#define PCIEMSIX_PSP_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_PSP_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_PSP_PCIEMSIX_VECT22_ADDR_HI
+#define PCIEMSIX_PSP_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT22_MSG_DATA
+#define PCIEMSIX_PSP_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT22_CONTROL
+#define PCIEMSIX_PSP_PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_PSP_PCIEMSIX_VECT23_ADDR_LO
+#define PCIEMSIX_PSP_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_PSP_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_PSP_PCIEMSIX_VECT23_ADDR_HI
+#define PCIEMSIX_PSP_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT23_MSG_DATA
+#define PCIEMSIX_PSP_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT23_CONTROL
+#define PCIEMSIX_PSP_PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_PSP_PCIEMSIX_VECT24_ADDR_LO
+#define PCIEMSIX_PSP_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_PSP_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_PSP_PCIEMSIX_VECT24_ADDR_HI
+#define PCIEMSIX_PSP_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT24_MSG_DATA
+#define PCIEMSIX_PSP_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT24_CONTROL
+#define PCIEMSIX_PSP_PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_PSP_PCIEMSIX_VECT25_ADDR_LO
+#define PCIEMSIX_PSP_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_PSP_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_PSP_PCIEMSIX_VECT25_ADDR_HI
+#define PCIEMSIX_PSP_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT25_MSG_DATA
+#define PCIEMSIX_PSP_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT25_CONTROL
+#define PCIEMSIX_PSP_PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_PSP_PCIEMSIX_VECT26_ADDR_LO
+#define PCIEMSIX_PSP_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_PSP_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_PSP_PCIEMSIX_VECT26_ADDR_HI
+#define PCIEMSIX_PSP_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT26_MSG_DATA
+#define PCIEMSIX_PSP_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT26_CONTROL
+#define PCIEMSIX_PSP_PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_PSP_PCIEMSIX_VECT27_ADDR_LO
+#define PCIEMSIX_PSP_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_PSP_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_PSP_PCIEMSIX_VECT27_ADDR_HI
+#define PCIEMSIX_PSP_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT27_MSG_DATA
+#define PCIEMSIX_PSP_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT27_CONTROL
+#define PCIEMSIX_PSP_PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_PSP_PCIEMSIX_VECT28_ADDR_LO
+#define PCIEMSIX_PSP_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_PSP_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_PSP_PCIEMSIX_VECT28_ADDR_HI
+#define PCIEMSIX_PSP_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT28_MSG_DATA
+#define PCIEMSIX_PSP_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT28_CONTROL
+#define PCIEMSIX_PSP_PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_PSP_PCIEMSIX_VECT29_ADDR_LO
+#define PCIEMSIX_PSP_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_PSP_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_PSP_PCIEMSIX_VECT29_ADDR_HI
+#define PCIEMSIX_PSP_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT29_MSG_DATA
+#define PCIEMSIX_PSP_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT29_CONTROL
+#define PCIEMSIX_PSP_PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_PSP_PCIEMSIX_VECT30_ADDR_LO
+#define PCIEMSIX_PSP_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_PSP_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_PSP_PCIEMSIX_VECT30_ADDR_HI
+#define PCIEMSIX_PSP_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT30_MSG_DATA
+#define PCIEMSIX_PSP_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT30_CONTROL
+#define PCIEMSIX_PSP_PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_PSP_PCIEMSIX_VECT31_ADDR_LO
+#define PCIEMSIX_PSP_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_PSP_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_PSP_PCIEMSIX_VECT31_ADDR_HI
+#define PCIEMSIX_PSP_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT31_MSG_DATA
+#define PCIEMSIX_PSP_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_PSP_PCIEMSIX_VECT31_CONTROL
+#define PCIEMSIX_PSP_PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK 0x00000001L
+
+
+// addressBlock: nbio_nbif0_pciemsix_usb3_0_MSIXTDEC
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT0_ADDR_LO
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT0_ADDR_HI
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT0_MSG_DATA
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT0_CONTROL
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT1_ADDR_LO
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT1_ADDR_HI
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT1_MSG_DATA
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT1_CONTROL
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT2_ADDR_LO
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT2_ADDR_HI
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT2_MSG_DATA
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT2_CONTROL
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT3_ADDR_LO
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT3_ADDR_HI
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT3_MSG_DATA
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT3_CONTROL
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT4_ADDR_LO
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT4_ADDR_HI
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT4_MSG_DATA
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT4_CONTROL
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT5_ADDR_LO
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT5_ADDR_HI
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT5_MSG_DATA
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT5_CONTROL
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT6_ADDR_LO
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT6_ADDR_HI
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT6_MSG_DATA
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT6_CONTROL
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT7_ADDR_LO
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT7_ADDR_HI
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT7_MSG_DATA
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT7_CONTROL
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT8_ADDR_LO
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT8_ADDR_HI
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT8_MSG_DATA
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT8_CONTROL
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT9_ADDR_LO
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT9_ADDR_HI
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT9_MSG_DATA
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT9_CONTROL
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT10_ADDR_LO
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT10_ADDR_HI
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT10_MSG_DATA
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT10_CONTROL
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT11_ADDR_LO
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT11_ADDR_HI
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT11_MSG_DATA
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT11_CONTROL
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT12_ADDR_LO
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT12_ADDR_HI
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT12_MSG_DATA
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT12_CONTROL
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT13_ADDR_LO
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT13_ADDR_HI
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT13_MSG_DATA
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT13_CONTROL
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT14_ADDR_LO
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT14_ADDR_HI
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT14_MSG_DATA
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT14_CONTROL
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT15_ADDR_LO
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT15_ADDR_HI
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT15_MSG_DATA
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT15_CONTROL
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT16_ADDR_LO
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT16_ADDR_HI
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT16_MSG_DATA
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT16_CONTROL
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT17_ADDR_LO
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT17_ADDR_HI
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT17_MSG_DATA
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT17_CONTROL
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT18_ADDR_LO
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT18_ADDR_HI
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT18_MSG_DATA
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT18_CONTROL
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT19_ADDR_LO
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT19_ADDR_HI
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT19_MSG_DATA
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT19_CONTROL
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT20_ADDR_LO
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT20_ADDR_HI
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT20_MSG_DATA
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT20_CONTROL
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT21_ADDR_LO
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT21_ADDR_HI
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT21_MSG_DATA
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT21_CONTROL
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT22_ADDR_LO
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT22_ADDR_HI
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT22_MSG_DATA
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT22_CONTROL
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT23_ADDR_LO
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT23_ADDR_HI
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT23_MSG_DATA
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT23_CONTROL
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT24_ADDR_LO
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT24_ADDR_HI
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT24_MSG_DATA
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT24_CONTROL
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT25_ADDR_LO
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT25_ADDR_HI
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT25_MSG_DATA
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT25_CONTROL
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT26_ADDR_LO
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT26_ADDR_HI
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT26_MSG_DATA
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT26_CONTROL
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT27_ADDR_LO
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT27_ADDR_HI
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT27_MSG_DATA
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT27_CONTROL
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT28_ADDR_LO
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT28_ADDR_HI
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT28_MSG_DATA
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT28_CONTROL
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT29_ADDR_LO
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT29_ADDR_HI
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT29_MSG_DATA
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT29_CONTROL
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT30_ADDR_LO
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT30_ADDR_HI
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT30_MSG_DATA
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT30_CONTROL
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT31_ADDR_LO
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT31_ADDR_HI
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT31_MSG_DATA
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_0_PCIEMSIX_VECT31_CONTROL
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK 0x00000001L
+
+
+// addressBlock: nbio_nbif0_pciemsix_usb3_1_MSIXTDEC
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT0_ADDR_LO
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT0_ADDR_HI
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT0_MSG_DATA
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT0_CONTROL
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT1_ADDR_LO
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT1_ADDR_HI
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT1_MSG_DATA
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT1_CONTROL
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT2_ADDR_LO
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT2_ADDR_HI
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT2_MSG_DATA
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT2_CONTROL
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT3_ADDR_LO
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT3_ADDR_HI
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT3_MSG_DATA
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT3_CONTROL
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT4_ADDR_LO
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT4_ADDR_HI
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT4_MSG_DATA
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT4_CONTROL
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT5_ADDR_LO
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT5_ADDR_HI
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT5_MSG_DATA
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT5_CONTROL
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT6_ADDR_LO
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT6_ADDR_HI
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT6_MSG_DATA
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT6_CONTROL
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT7_ADDR_LO
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT7_ADDR_HI
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT7_MSG_DATA
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT7_CONTROL
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT8_ADDR_LO
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT8_ADDR_HI
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT8_MSG_DATA
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT8_CONTROL
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT9_ADDR_LO
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT9_ADDR_HI
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT9_MSG_DATA
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT9_CONTROL
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT10_ADDR_LO
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT10_ADDR_HI
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT10_MSG_DATA
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT10_CONTROL
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT11_ADDR_LO
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT11_ADDR_HI
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT11_MSG_DATA
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT11_CONTROL
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT12_ADDR_LO
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT12_ADDR_HI
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT12_MSG_DATA
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT12_CONTROL
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT13_ADDR_LO
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT13_ADDR_HI
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT13_MSG_DATA
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT13_CONTROL
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT14_ADDR_LO
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT14_ADDR_HI
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT14_MSG_DATA
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT14_CONTROL
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT15_ADDR_LO
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT15_ADDR_HI
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT15_MSG_DATA
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT15_CONTROL
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT16_ADDR_LO
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT16_ADDR_HI
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT16_MSG_DATA
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT16_CONTROL
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT17_ADDR_LO
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT17_ADDR_HI
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT17_MSG_DATA
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT17_CONTROL
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT18_ADDR_LO
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT18_ADDR_HI
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT18_MSG_DATA
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT18_CONTROL
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT19_ADDR_LO
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT19_ADDR_HI
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT19_MSG_DATA
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT19_CONTROL
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT20_ADDR_LO
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT20_ADDR_HI
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT20_MSG_DATA
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT20_CONTROL
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT21_ADDR_LO
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT21_ADDR_HI
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT21_MSG_DATA
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT21_CONTROL
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT22_ADDR_LO
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT22_ADDR_HI
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT22_MSG_DATA
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT22_CONTROL
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT23_ADDR_LO
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT23_ADDR_HI
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT23_MSG_DATA
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT23_CONTROL
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT24_ADDR_LO
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT24_ADDR_HI
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT24_MSG_DATA
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT24_CONTROL
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT25_ADDR_LO
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT25_ADDR_HI
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT25_MSG_DATA
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT25_CONTROL
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT26_ADDR_LO
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT26_ADDR_HI
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT26_MSG_DATA
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT26_CONTROL
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT27_ADDR_LO
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT27_ADDR_HI
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT27_MSG_DATA
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT27_CONTROL
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT28_ADDR_LO
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT28_ADDR_HI
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT28_MSG_DATA
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT28_CONTROL
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT29_ADDR_LO
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT29_ADDR_HI
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT29_MSG_DATA
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT29_CONTROL
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT30_ADDR_LO
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT30_ADDR_HI
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT30_MSG_DATA
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT30_CONTROL
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT31_ADDR_LO
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT31_ADDR_HI
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT31_MSG_DATA
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_USB3_1_PCIEMSIX_VECT31_CONTROL
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK 0x00000001L
+
+
+// addressBlock: nbio_nbif0_pciemsix_mp2_MSIXTDEC
+//PCIEMSIX_MP2_PCIEMSIX_VECT0_ADDR_LO
+#define PCIEMSIX_MP2_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_MP2_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_MP2_PCIEMSIX_VECT0_ADDR_HI
+#define PCIEMSIX_MP2_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT0_MSG_DATA
+#define PCIEMSIX_MP2_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT0_CONTROL
+#define PCIEMSIX_MP2_PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_MP2_PCIEMSIX_VECT1_ADDR_LO
+#define PCIEMSIX_MP2_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_MP2_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_MP2_PCIEMSIX_VECT1_ADDR_HI
+#define PCIEMSIX_MP2_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT1_MSG_DATA
+#define PCIEMSIX_MP2_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT1_CONTROL
+#define PCIEMSIX_MP2_PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_MP2_PCIEMSIX_VECT2_ADDR_LO
+#define PCIEMSIX_MP2_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_MP2_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_MP2_PCIEMSIX_VECT2_ADDR_HI
+#define PCIEMSIX_MP2_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT2_MSG_DATA
+#define PCIEMSIX_MP2_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT2_CONTROL
+#define PCIEMSIX_MP2_PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_MP2_PCIEMSIX_VECT3_ADDR_LO
+#define PCIEMSIX_MP2_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_MP2_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_MP2_PCIEMSIX_VECT3_ADDR_HI
+#define PCIEMSIX_MP2_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT3_MSG_DATA
+#define PCIEMSIX_MP2_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT3_CONTROL
+#define PCIEMSIX_MP2_PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_MP2_PCIEMSIX_VECT4_ADDR_LO
+#define PCIEMSIX_MP2_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_MP2_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_MP2_PCIEMSIX_VECT4_ADDR_HI
+#define PCIEMSIX_MP2_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT4_MSG_DATA
+#define PCIEMSIX_MP2_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT4_CONTROL
+#define PCIEMSIX_MP2_PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_MP2_PCIEMSIX_VECT5_ADDR_LO
+#define PCIEMSIX_MP2_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_MP2_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_MP2_PCIEMSIX_VECT5_ADDR_HI
+#define PCIEMSIX_MP2_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT5_MSG_DATA
+#define PCIEMSIX_MP2_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT5_CONTROL
+#define PCIEMSIX_MP2_PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_MP2_PCIEMSIX_VECT6_ADDR_LO
+#define PCIEMSIX_MP2_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_MP2_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_MP2_PCIEMSIX_VECT6_ADDR_HI
+#define PCIEMSIX_MP2_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT6_MSG_DATA
+#define PCIEMSIX_MP2_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT6_CONTROL
+#define PCIEMSIX_MP2_PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_MP2_PCIEMSIX_VECT7_ADDR_LO
+#define PCIEMSIX_MP2_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_MP2_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_MP2_PCIEMSIX_VECT7_ADDR_HI
+#define PCIEMSIX_MP2_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT7_MSG_DATA
+#define PCIEMSIX_MP2_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT7_CONTROL
+#define PCIEMSIX_MP2_PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_MP2_PCIEMSIX_VECT8_ADDR_LO
+#define PCIEMSIX_MP2_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_MP2_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_MP2_PCIEMSIX_VECT8_ADDR_HI
+#define PCIEMSIX_MP2_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT8_MSG_DATA
+#define PCIEMSIX_MP2_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT8_CONTROL
+#define PCIEMSIX_MP2_PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_MP2_PCIEMSIX_VECT9_ADDR_LO
+#define PCIEMSIX_MP2_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_MP2_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_MP2_PCIEMSIX_VECT9_ADDR_HI
+#define PCIEMSIX_MP2_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT9_MSG_DATA
+#define PCIEMSIX_MP2_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT9_CONTROL
+#define PCIEMSIX_MP2_PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_MP2_PCIEMSIX_VECT10_ADDR_LO
+#define PCIEMSIX_MP2_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_MP2_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_MP2_PCIEMSIX_VECT10_ADDR_HI
+#define PCIEMSIX_MP2_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT10_MSG_DATA
+#define PCIEMSIX_MP2_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT10_CONTROL
+#define PCIEMSIX_MP2_PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_MP2_PCIEMSIX_VECT11_ADDR_LO
+#define PCIEMSIX_MP2_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_MP2_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_MP2_PCIEMSIX_VECT11_ADDR_HI
+#define PCIEMSIX_MP2_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT11_MSG_DATA
+#define PCIEMSIX_MP2_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT11_CONTROL
+#define PCIEMSIX_MP2_PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_MP2_PCIEMSIX_VECT12_ADDR_LO
+#define PCIEMSIX_MP2_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_MP2_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_MP2_PCIEMSIX_VECT12_ADDR_HI
+#define PCIEMSIX_MP2_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT12_MSG_DATA
+#define PCIEMSIX_MP2_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT12_CONTROL
+#define PCIEMSIX_MP2_PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_MP2_PCIEMSIX_VECT13_ADDR_LO
+#define PCIEMSIX_MP2_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_MP2_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_MP2_PCIEMSIX_VECT13_ADDR_HI
+#define PCIEMSIX_MP2_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT13_MSG_DATA
+#define PCIEMSIX_MP2_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT13_CONTROL
+#define PCIEMSIX_MP2_PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_MP2_PCIEMSIX_VECT14_ADDR_LO
+#define PCIEMSIX_MP2_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_MP2_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_MP2_PCIEMSIX_VECT14_ADDR_HI
+#define PCIEMSIX_MP2_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT14_MSG_DATA
+#define PCIEMSIX_MP2_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT14_CONTROL
+#define PCIEMSIX_MP2_PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_MP2_PCIEMSIX_VECT15_ADDR_LO
+#define PCIEMSIX_MP2_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_MP2_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_MP2_PCIEMSIX_VECT15_ADDR_HI
+#define PCIEMSIX_MP2_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT15_MSG_DATA
+#define PCIEMSIX_MP2_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT15_CONTROL
+#define PCIEMSIX_MP2_PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_MP2_PCIEMSIX_VECT16_ADDR_LO
+#define PCIEMSIX_MP2_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_MP2_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_MP2_PCIEMSIX_VECT16_ADDR_HI
+#define PCIEMSIX_MP2_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT16_MSG_DATA
+#define PCIEMSIX_MP2_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT16_CONTROL
+#define PCIEMSIX_MP2_PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_MP2_PCIEMSIX_VECT17_ADDR_LO
+#define PCIEMSIX_MP2_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_MP2_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_MP2_PCIEMSIX_VECT17_ADDR_HI
+#define PCIEMSIX_MP2_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT17_MSG_DATA
+#define PCIEMSIX_MP2_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT17_CONTROL
+#define PCIEMSIX_MP2_PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_MP2_PCIEMSIX_VECT18_ADDR_LO
+#define PCIEMSIX_MP2_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_MP2_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_MP2_PCIEMSIX_VECT18_ADDR_HI
+#define PCIEMSIX_MP2_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT18_MSG_DATA
+#define PCIEMSIX_MP2_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT18_CONTROL
+#define PCIEMSIX_MP2_PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_MP2_PCIEMSIX_VECT19_ADDR_LO
+#define PCIEMSIX_MP2_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_MP2_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_MP2_PCIEMSIX_VECT19_ADDR_HI
+#define PCIEMSIX_MP2_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT19_MSG_DATA
+#define PCIEMSIX_MP2_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT19_CONTROL
+#define PCIEMSIX_MP2_PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_MP2_PCIEMSIX_VECT20_ADDR_LO
+#define PCIEMSIX_MP2_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_MP2_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_MP2_PCIEMSIX_VECT20_ADDR_HI
+#define PCIEMSIX_MP2_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT20_MSG_DATA
+#define PCIEMSIX_MP2_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT20_CONTROL
+#define PCIEMSIX_MP2_PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_MP2_PCIEMSIX_VECT21_ADDR_LO
+#define PCIEMSIX_MP2_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_MP2_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_MP2_PCIEMSIX_VECT21_ADDR_HI
+#define PCIEMSIX_MP2_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT21_MSG_DATA
+#define PCIEMSIX_MP2_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT21_CONTROL
+#define PCIEMSIX_MP2_PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_MP2_PCIEMSIX_VECT22_ADDR_LO
+#define PCIEMSIX_MP2_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_MP2_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_MP2_PCIEMSIX_VECT22_ADDR_HI
+#define PCIEMSIX_MP2_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT22_MSG_DATA
+#define PCIEMSIX_MP2_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT22_CONTROL
+#define PCIEMSIX_MP2_PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_MP2_PCIEMSIX_VECT23_ADDR_LO
+#define PCIEMSIX_MP2_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_MP2_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_MP2_PCIEMSIX_VECT23_ADDR_HI
+#define PCIEMSIX_MP2_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT23_MSG_DATA
+#define PCIEMSIX_MP2_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT23_CONTROL
+#define PCIEMSIX_MP2_PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_MP2_PCIEMSIX_VECT24_ADDR_LO
+#define PCIEMSIX_MP2_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_MP2_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_MP2_PCIEMSIX_VECT24_ADDR_HI
+#define PCIEMSIX_MP2_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT24_MSG_DATA
+#define PCIEMSIX_MP2_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT24_CONTROL
+#define PCIEMSIX_MP2_PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_MP2_PCIEMSIX_VECT25_ADDR_LO
+#define PCIEMSIX_MP2_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_MP2_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_MP2_PCIEMSIX_VECT25_ADDR_HI
+#define PCIEMSIX_MP2_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT25_MSG_DATA
+#define PCIEMSIX_MP2_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT25_CONTROL
+#define PCIEMSIX_MP2_PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_MP2_PCIEMSIX_VECT26_ADDR_LO
+#define PCIEMSIX_MP2_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_MP2_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_MP2_PCIEMSIX_VECT26_ADDR_HI
+#define PCIEMSIX_MP2_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT26_MSG_DATA
+#define PCIEMSIX_MP2_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT26_CONTROL
+#define PCIEMSIX_MP2_PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_MP2_PCIEMSIX_VECT27_ADDR_LO
+#define PCIEMSIX_MP2_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_MP2_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_MP2_PCIEMSIX_VECT27_ADDR_HI
+#define PCIEMSIX_MP2_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT27_MSG_DATA
+#define PCIEMSIX_MP2_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT27_CONTROL
+#define PCIEMSIX_MP2_PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_MP2_PCIEMSIX_VECT28_ADDR_LO
+#define PCIEMSIX_MP2_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_MP2_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_MP2_PCIEMSIX_VECT28_ADDR_HI
+#define PCIEMSIX_MP2_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT28_MSG_DATA
+#define PCIEMSIX_MP2_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT28_CONTROL
+#define PCIEMSIX_MP2_PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_MP2_PCIEMSIX_VECT29_ADDR_LO
+#define PCIEMSIX_MP2_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_MP2_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_MP2_PCIEMSIX_VECT29_ADDR_HI
+#define PCIEMSIX_MP2_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT29_MSG_DATA
+#define PCIEMSIX_MP2_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT29_CONTROL
+#define PCIEMSIX_MP2_PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_MP2_PCIEMSIX_VECT30_ADDR_LO
+#define PCIEMSIX_MP2_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_MP2_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_MP2_PCIEMSIX_VECT30_ADDR_HI
+#define PCIEMSIX_MP2_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT30_MSG_DATA
+#define PCIEMSIX_MP2_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT30_CONTROL
+#define PCIEMSIX_MP2_PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_MP2_PCIEMSIX_VECT31_ADDR_LO
+#define PCIEMSIX_MP2_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_MP2_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_MP2_PCIEMSIX_VECT31_ADDR_HI
+#define PCIEMSIX_MP2_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT31_MSG_DATA
+#define PCIEMSIX_MP2_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_MP2_PCIEMSIX_VECT31_CONTROL
+#define PCIEMSIX_MP2_PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK 0x00000001L
+
+
+// addressBlock: nbio_nbif0_pciemsix_gbe0_MSIXTDEC
+//PCIEMSIX_GBE0_PCIEMSIX_VECT0_ADDR_LO
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT0_ADDR_HI
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT0_MSG_DATA
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT0_CONTROL
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE0_PCIEMSIX_VECT1_ADDR_LO
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT1_ADDR_HI
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT1_MSG_DATA
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT1_CONTROL
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE0_PCIEMSIX_VECT2_ADDR_LO
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT2_ADDR_HI
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT2_MSG_DATA
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT2_CONTROL
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE0_PCIEMSIX_VECT3_ADDR_LO
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT3_ADDR_HI
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT3_MSG_DATA
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT3_CONTROL
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE0_PCIEMSIX_VECT4_ADDR_LO
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT4_ADDR_HI
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT4_MSG_DATA
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT4_CONTROL
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE0_PCIEMSIX_VECT5_ADDR_LO
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT5_ADDR_HI
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT5_MSG_DATA
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT5_CONTROL
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE0_PCIEMSIX_VECT6_ADDR_LO
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT6_ADDR_HI
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT6_MSG_DATA
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT6_CONTROL
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE0_PCIEMSIX_VECT7_ADDR_LO
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT7_ADDR_HI
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT7_MSG_DATA
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT7_CONTROL
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE0_PCIEMSIX_VECT8_ADDR_LO
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT8_ADDR_HI
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT8_MSG_DATA
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT8_CONTROL
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE0_PCIEMSIX_VECT9_ADDR_LO
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT9_ADDR_HI
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT9_MSG_DATA
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT9_CONTROL
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE0_PCIEMSIX_VECT10_ADDR_LO
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT10_ADDR_HI
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT10_MSG_DATA
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT10_CONTROL
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE0_PCIEMSIX_VECT11_ADDR_LO
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT11_ADDR_HI
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT11_MSG_DATA
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT11_CONTROL
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE0_PCIEMSIX_VECT12_ADDR_LO
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT12_ADDR_HI
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT12_MSG_DATA
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT12_CONTROL
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE0_PCIEMSIX_VECT13_ADDR_LO
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT13_ADDR_HI
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT13_MSG_DATA
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT13_CONTROL
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE0_PCIEMSIX_VECT14_ADDR_LO
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT14_ADDR_HI
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT14_MSG_DATA
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT14_CONTROL
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE0_PCIEMSIX_VECT15_ADDR_LO
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT15_ADDR_HI
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT15_MSG_DATA
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT15_CONTROL
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE0_PCIEMSIX_VECT16_ADDR_LO
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT16_ADDR_HI
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT16_MSG_DATA
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT16_CONTROL
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE0_PCIEMSIX_VECT17_ADDR_LO
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT17_ADDR_HI
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT17_MSG_DATA
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT17_CONTROL
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE0_PCIEMSIX_VECT18_ADDR_LO
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT18_ADDR_HI
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT18_MSG_DATA
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT18_CONTROL
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE0_PCIEMSIX_VECT19_ADDR_LO
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT19_ADDR_HI
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT19_MSG_DATA
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT19_CONTROL
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE0_PCIEMSIX_VECT20_ADDR_LO
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT20_ADDR_HI
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT20_MSG_DATA
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT20_CONTROL
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE0_PCIEMSIX_VECT21_ADDR_LO
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT21_ADDR_HI
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT21_MSG_DATA
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT21_CONTROL
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE0_PCIEMSIX_VECT22_ADDR_LO
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT22_ADDR_HI
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT22_MSG_DATA
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT22_CONTROL
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE0_PCIEMSIX_VECT23_ADDR_LO
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT23_ADDR_HI
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT23_MSG_DATA
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT23_CONTROL
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE0_PCIEMSIX_VECT24_ADDR_LO
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT24_ADDR_HI
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT24_MSG_DATA
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT24_CONTROL
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE0_PCIEMSIX_VECT25_ADDR_LO
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT25_ADDR_HI
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT25_MSG_DATA
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT25_CONTROL
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE0_PCIEMSIX_VECT26_ADDR_LO
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT26_ADDR_HI
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT26_MSG_DATA
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT26_CONTROL
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE0_PCIEMSIX_VECT27_ADDR_LO
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT27_ADDR_HI
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT27_MSG_DATA
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT27_CONTROL
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE0_PCIEMSIX_VECT28_ADDR_LO
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT28_ADDR_HI
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT28_MSG_DATA
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT28_CONTROL
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE0_PCIEMSIX_VECT29_ADDR_LO
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT29_ADDR_HI
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT29_MSG_DATA
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT29_CONTROL
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE0_PCIEMSIX_VECT30_ADDR_LO
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT30_ADDR_HI
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT30_MSG_DATA
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT30_CONTROL
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE0_PCIEMSIX_VECT31_ADDR_LO
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT31_ADDR_HI
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT31_MSG_DATA
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE0_PCIEMSIX_VECT31_CONTROL
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK 0x00000001L
+
+
+// addressBlock: nbio_nbif0_pciemsix_gbe1_MSIXTDEC
+//PCIEMSIX_GBE1_PCIEMSIX_VECT0_ADDR_LO
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT0_ADDR_HI
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT0_MSG_DATA
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT0_CONTROL
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE1_PCIEMSIX_VECT1_ADDR_LO
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT1_ADDR_HI
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT1_MSG_DATA
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT1_CONTROL
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE1_PCIEMSIX_VECT2_ADDR_LO
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT2_ADDR_HI
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT2_MSG_DATA
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT2_CONTROL
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE1_PCIEMSIX_VECT3_ADDR_LO
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT3_ADDR_HI
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT3_MSG_DATA
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT3_CONTROL
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE1_PCIEMSIX_VECT4_ADDR_LO
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT4_ADDR_HI
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT4_MSG_DATA
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT4_CONTROL
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE1_PCIEMSIX_VECT5_ADDR_LO
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT5_ADDR_HI
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT5_MSG_DATA
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT5_CONTROL
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE1_PCIEMSIX_VECT6_ADDR_LO
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT6_ADDR_HI
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT6_MSG_DATA
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT6_CONTROL
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE1_PCIEMSIX_VECT7_ADDR_LO
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT7_ADDR_HI
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT7_MSG_DATA
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT7_CONTROL
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE1_PCIEMSIX_VECT8_ADDR_LO
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT8_ADDR_HI
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT8_MSG_DATA
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT8_CONTROL
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE1_PCIEMSIX_VECT9_ADDR_LO
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT9_ADDR_HI
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT9_MSG_DATA
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT9_CONTROL
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE1_PCIEMSIX_VECT10_ADDR_LO
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT10_ADDR_HI
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT10_MSG_DATA
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT10_CONTROL
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE1_PCIEMSIX_VECT11_ADDR_LO
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT11_ADDR_HI
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT11_MSG_DATA
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT11_CONTROL
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE1_PCIEMSIX_VECT12_ADDR_LO
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT12_ADDR_HI
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT12_MSG_DATA
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT12_CONTROL
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE1_PCIEMSIX_VECT13_ADDR_LO
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT13_ADDR_HI
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT13_MSG_DATA
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT13_CONTROL
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE1_PCIEMSIX_VECT14_ADDR_LO
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT14_ADDR_HI
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT14_MSG_DATA
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT14_CONTROL
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE1_PCIEMSIX_VECT15_ADDR_LO
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT15_ADDR_HI
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT15_MSG_DATA
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT15_CONTROL
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE1_PCIEMSIX_VECT16_ADDR_LO
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT16_ADDR_HI
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT16_MSG_DATA
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT16_CONTROL
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE1_PCIEMSIX_VECT17_ADDR_LO
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT17_ADDR_HI
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT17_MSG_DATA
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT17_CONTROL
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE1_PCIEMSIX_VECT18_ADDR_LO
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT18_ADDR_HI
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT18_MSG_DATA
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT18_CONTROL
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE1_PCIEMSIX_VECT19_ADDR_LO
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT19_ADDR_HI
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT19_MSG_DATA
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT19_CONTROL
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE1_PCIEMSIX_VECT20_ADDR_LO
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT20_ADDR_HI
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT20_MSG_DATA
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT20_CONTROL
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE1_PCIEMSIX_VECT21_ADDR_LO
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT21_ADDR_HI
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT21_MSG_DATA
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT21_CONTROL
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE1_PCIEMSIX_VECT22_ADDR_LO
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT22_ADDR_HI
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT22_MSG_DATA
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT22_CONTROL
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE1_PCIEMSIX_VECT23_ADDR_LO
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT23_ADDR_HI
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT23_MSG_DATA
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT23_CONTROL
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE1_PCIEMSIX_VECT24_ADDR_LO
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT24_ADDR_HI
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT24_MSG_DATA
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT24_CONTROL
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE1_PCIEMSIX_VECT25_ADDR_LO
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT25_ADDR_HI
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT25_MSG_DATA
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT25_CONTROL
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE1_PCIEMSIX_VECT26_ADDR_LO
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT26_ADDR_HI
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT26_MSG_DATA
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT26_CONTROL
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE1_PCIEMSIX_VECT27_ADDR_LO
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT27_ADDR_HI
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT27_MSG_DATA
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT27_CONTROL
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE1_PCIEMSIX_VECT28_ADDR_LO
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT28_ADDR_HI
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT28_MSG_DATA
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT28_CONTROL
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE1_PCIEMSIX_VECT29_ADDR_LO
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT29_ADDR_HI
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT29_MSG_DATA
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT29_CONTROL
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE1_PCIEMSIX_VECT30_ADDR_LO
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT30_ADDR_HI
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT30_MSG_DATA
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT30_CONTROL
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_GBE1_PCIEMSIX_VECT31_ADDR_LO
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT31_ADDR_HI
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT31_MSG_DATA
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_GBE1_PCIEMSIX_VECT31_CONTROL
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK 0x00000001L
+
+
+// addressBlock: nbio_nbif0_pciemsix_amdgfx_MSIXPDEC
+//PCIEMSIX_AMDGFX_PCIEMSIX_PBA
+#define PCIEMSIX_AMDGFX_PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x0
+#define PCIEMSIX_AMDGFX_PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_pciemsix_psp_MSIXPDEC
+//PCIEMSIX_PSP_PCIEMSIX_PBA
+#define PCIEMSIX_PSP_PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x0
+#define PCIEMSIX_PSP_PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_pciemsix_usb3_0_MSIXPDEC
+//PCIEMSIX_USB3_0_PCIEMSIX_PBA
+#define PCIEMSIX_USB3_0_PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x0
+#define PCIEMSIX_USB3_0_PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_pciemsix_usb3_1_MSIXPDEC
+//PCIEMSIX_USB3_1_PCIEMSIX_PBA
+#define PCIEMSIX_USB3_1_PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x0
+#define PCIEMSIX_USB3_1_PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_pciemsix_mp2_MSIXPDEC
+//PCIEMSIX_MP2_PCIEMSIX_PBA
+#define PCIEMSIX_MP2_PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x0
+#define PCIEMSIX_MP2_PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_pciemsix_gbe0_MSIXPDEC
+//PCIEMSIX_GBE0_PCIEMSIX_PBA
+#define PCIEMSIX_GBE0_PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x0
+#define PCIEMSIX_GBE0_PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_pciemsix_gbe1_MSIXPDEC
+//PCIEMSIX_GBE1_PCIEMSIX_PBA
+#define PCIEMSIX_GBE1_PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x0
+#define PCIEMSIX_GBE1_PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_pcie0_bifplr0_cfgdecp
+//BIFPLR0_1_VENDOR_ID
+#define BIFPLR0_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR0_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR0_1_DEVICE_ID
+#define BIFPLR0_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR0_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR0_1_COMMAND
+#define BIFPLR0_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR0_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR0_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR0_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR0_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR0_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR0_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR0_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR0_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR0_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR0_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR0_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR0_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR0_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR0_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR0_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR0_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR0_1_STATUS
+#define BIFPLR0_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR0_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR0_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR0_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR0_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR0_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR0_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR0_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR0_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR0_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR0_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR0_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR0_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR0_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR0_1_REVISION_ID
+#define BIFPLR0_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR0_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR0_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR0_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR0_1_PROG_INTERFACE
+#define BIFPLR0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR0_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR0_1_SUB_CLASS
+#define BIFPLR0_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR0_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR0_1_BASE_CLASS
+#define BIFPLR0_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR0_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR0_1_CACHE_LINE
+#define BIFPLR0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR0_1_LATENCY
+#define BIFPLR0_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR0_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR0_1_HEADER
+#define BIFPLR0_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR0_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR0_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR0_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR0_1_BIST
+#define BIFPLR0_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR0_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR0_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR0_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR0_1_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR0_1_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR0_1_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR0_1_IO_BASE_LIMIT
+#define BIFPLR0_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR0_1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR0_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR0_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR0_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR0_1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR0_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR0_1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR0_1_SECONDARY_STATUS
+#define BIFPLR0_1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR0_1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR0_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR0_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR0_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR0_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR0_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR0_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR0_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR0_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR0_1_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR0_1_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR0_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR0_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR0_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR0_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR0_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR0_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR0_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR0_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR0_1_MEM_BASE_LIMIT
+#define BIFPLR0_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR0_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR0_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR0_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR0_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR0_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR0_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR0_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR0_1_PREF_BASE_LIMIT
+#define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR0_1_PREF_BASE_UPPER
+#define BIFPLR0_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR0_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PREF_LIMIT_UPPER
+#define BIFPLR0_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR0_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR0_1_IO_BASE_LIMIT_HI
+#define BIFPLR0_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR0_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR0_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR0_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR0_1_CAP_PTR
+#define BIFPLR0_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR0_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIFPLR0_1_INTERRUPT_LINE
+#define BIFPLR0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR0_1_INTERRUPT_PIN
+#define BIFPLR0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR0_1_IRQ_BRIDGE_CNTL
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+//BIFPLR0_1_EXT_BRIDGE_CNTL
+#define BIFPLR0_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR0_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR0_1_PMI_CAP_LIST
+#define BIFPLR0_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR0_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR0_1_PMI_CAP
+#define BIFPLR0_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR0_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR0_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR0_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR0_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR0_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR0_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR0_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR0_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR0_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR0_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR0_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR0_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR0_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR0_1_PMI_STATUS_CNTL
+#define BIFPLR0_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR0_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR0_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR0_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR0_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR0_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR0_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR0_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR0_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR0_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR0_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR0_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR0_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR0_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR0_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR0_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR0_1_PCIE_CAP_LIST
+#define BIFPLR0_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR0_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR0_1_PCIE_CAP
+#define BIFPLR0_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR0_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR0_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR0_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR0_1_DEVICE_CAP
+#define BIFPLR0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR0_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR0_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR0_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR0_1_DEVICE_CNTL
+#define BIFPLR0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR0_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR0_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR0_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR0_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR0_1_DEVICE_STATUS
+#define BIFPLR0_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR0_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR0_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR0_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR0_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR0_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR0_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR0_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIFPLR0_1_LINK_CAP
+#define BIFPLR0_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR0_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR0_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR0_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR0_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR0_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR0_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR0_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR0_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR0_1_LINK_CNTL
+#define BIFPLR0_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR0_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR0_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR0_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR0_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR0_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR0_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIFPLR0_1_LINK_STATUS
+#define BIFPLR0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR0_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR0_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR0_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR0_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR0_1_SLOT_CAP
+#define BIFPLR0_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR0_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR0_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR0_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR0_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR0_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR0_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR0_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR0_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR0_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR0_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR0_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR0_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR0_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR0_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR0_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR0_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR0_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR0_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR0_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR0_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR0_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR0_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR0_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR0_1_SLOT_CNTL
+#define BIFPLR0_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR0_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR0_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR0_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR0_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR0_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR0_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR0_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR0_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR0_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR0_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR0_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR0_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR0_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR0_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR0_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR0_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR0_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR0_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR0_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR0_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR0_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR0_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR0_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR0_1_SLOT_STATUS
+#define BIFPLR0_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR0_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR0_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR0_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR0_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR0_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR0_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR0_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR0_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR0_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR0_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR0_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR0_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR0_1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR0_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR0_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR0_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR0_1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR0_1_ROOT_CNTL
+#define BIFPLR0_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR0_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR0_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR0_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR0_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR0_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR0_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR0_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR0_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR0_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR0_1_ROOT_CAP
+#define BIFPLR0_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR0_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR0_1_ROOT_STATUS
+#define BIFPLR0_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR0_1_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR0_1_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR0_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR0_1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR0_1_DEVICE_CAP2
+#define BIFPLR0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIFPLR0_1_DEVICE_CNTL2
+#define BIFPLR0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR0_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR0_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR0_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR0_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR0_1_DEVICE_STATUS2
+#define BIFPLR0_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR0_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR0_1_LINK_CAP2
+#define BIFPLR0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIFPLR0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR0_1_LINK_CAP2__RESERVED__SHIFT 0x13
+#define BIFPLR0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L
+#define BIFPLR0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L
+#define BIFPLR0_1_LINK_CAP2__RESERVED_MASK 0xFFF80000L
+//BIFPLR0_1_LINK_CNTL2
+#define BIFPLR0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR0_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR0_1_LINK_STATUS2
+#define BIFPLR0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIFPLR0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIFPLR0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIFPLR0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIFPLR0_1_SLOT_CAP2
+#define BIFPLR0_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR0_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR0_1_SLOT_CNTL2
+#define BIFPLR0_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR0_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR0_1_SLOT_STATUS2
+#define BIFPLR0_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR0_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR0_1_MSI_CAP_LIST
+#define BIFPLR0_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR0_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR0_1_MSI_MSG_CNTL
+#define BIFPLR0_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR0_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR0_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR0_1_MSI_MSG_ADDR_LO
+#define BIFPLR0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR0_1_MSI_MSG_ADDR_HI
+#define BIFPLR0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR0_1_MSI_MSG_DATA
+#define BIFPLR0_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR0_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIFPLR0_1_MSI_MSG_DATA_64
+#define BIFPLR0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR0_1_SSID_CAP_LIST
+#define BIFPLR0_1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR0_1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR0_1_SSID_CAP
+#define BIFPLR0_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR0_1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR0_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR0_1_MSI_MAP_CAP_LIST
+#define BIFPLR0_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR0_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR0_1_MSI_MAP_CAP
+#define BIFPLR0_1_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR0_1_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR0_1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR0_1_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR0_1_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR0_1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR0_1_MSI_MAP_ADDR_LO
+#define BIFPLR0_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define BIFPLR0_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L
+//BIFPLR0_1_MSI_MAP_ADDR_HI
+#define BIFPLR0_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define BIFPLR0_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR0_1_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_1_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR0_1_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR0_1_PCIE_PORT_VC_CNTL
+#define BIFPLR0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR0_1_PCIE_PORT_VC_STATUS
+#define BIFPLR0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR0_1_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR0_1_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR0_1_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR0_1_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_1_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR0_1_PCIE_UNCORR_ERR_MASK
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR0_1_PCIE_CORR_ERR_STATUS
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR0_1_PCIE_CORR_ERR_MASK
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIFPLR0_1_PCIE_HDR_LOG0
+#define BIFPLR0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_HDR_LOG1
+#define BIFPLR0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_HDR_LOG2
+#define BIFPLR0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_HDR_LOG3
+#define BIFPLR0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_ROOT_ERR_CMD
+#define BIFPLR0_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR0_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR0_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR0_1_PCIE_ROOT_ERR_STATUS
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR0_1_PCIE_ERR_SRC_ID
+#define BIFPLR0_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR0_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR0_1_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_1_PCIE_LINK_CNTL3
+#define BIFPLR0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR0_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define BIFPLR0_1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10
+#define BIFPLR0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+#define BIFPLR0_1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L
+//BIFPLR0_1_PCIE_LANE_ERROR_STATUS
+#define BIFPLR0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIFPLR0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIFPLR0_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_1_PCIE_ACS_CAP
+#define BIFPLR0_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR0_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR0_1_PCIE_ACS_CNTL
+#define BIFPLR0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR0_1_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_1_PCIE_MC_CAP
+#define BIFPLR0_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR0_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR0_1_PCIE_MC_CNTL
+#define BIFPLR0_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR0_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR0_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR0_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR0_1_PCIE_MC_ADDR0
+#define BIFPLR0_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR0_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR0_1_PCIE_MC_ADDR1
+#define BIFPLR0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_MC_RCV0
+#define BIFPLR0_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR0_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_MC_RCV1
+#define BIFPLR0_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR0_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_MC_BLOCK_ALL0
+#define BIFPLR0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_MC_BLOCK_ALL1
+#define BIFPLR0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR0_1_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR0_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR0_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_1_PCIE_L1_PM_SUB_CAP
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR0_1_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR0_1_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_1_PCIE_DPC_CAP_LIST
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR0_1_PCIE_DPC_CNTL
+#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR0_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR0_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR0_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR0_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR0_1_PCIE_DPC_STATUS
+#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR0_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR0_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR0_1_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR0_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR0_1_PCIE_RP_PIO_STATUS
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR0_1_PCIE_RP_PIO_MASK
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR0_1_PCIE_RP_PIO_SEVERITY
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR0_1_PCIE_RP_PIO_SYSERROR
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR0_1_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR0_1_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_RP_PIO_IMPSPEC_LOG
+#define BIFPLR0_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_ESM_CAP_LIST
+#define BIFPLR0_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_1_PCIE_ESM_HEADER_1
+#define BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR0_1_PCIE_ESM_HEADER_2
+#define BIFPLR0_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR0_1_PCIE_ESM_STATUS
+#define BIFPLR0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR0_1_PCIE_ESM_CTRL
+#define BIFPLR0_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8
+#define BIFPLR0_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR0_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL
+#define BIFPLR0_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L
+#define BIFPLR0_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR0_1_PCIE_ESM_CAP_1
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR0_1_PCIE_ESM_CAP_2
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR0_1_PCIE_ESM_CAP_3
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR0_1_PCIE_ESM_CAP_4
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR0_1_PCIE_ESM_CAP_5
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR0_1_PCIE_ESM_CAP_6
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR0_1_PCIE_ESM_CAP_7
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+
+
+// addressBlock: nbio_pcie0_bifplr1_cfgdecp
+//BIFPLR1_1_VENDOR_ID
+#define BIFPLR1_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR1_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR1_1_DEVICE_ID
+#define BIFPLR1_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR1_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR1_1_COMMAND
+#define BIFPLR1_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR1_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR1_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR1_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR1_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR1_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR1_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR1_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR1_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR1_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR1_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR1_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR1_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR1_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR1_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR1_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR1_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR1_1_STATUS
+#define BIFPLR1_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR1_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR1_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR1_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR1_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR1_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR1_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR1_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR1_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR1_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR1_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR1_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR1_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR1_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR1_1_REVISION_ID
+#define BIFPLR1_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR1_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR1_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR1_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR1_1_PROG_INTERFACE
+#define BIFPLR1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR1_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR1_1_SUB_CLASS
+#define BIFPLR1_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR1_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR1_1_BASE_CLASS
+#define BIFPLR1_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR1_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR1_1_CACHE_LINE
+#define BIFPLR1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR1_1_LATENCY
+#define BIFPLR1_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR1_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR1_1_HEADER
+#define BIFPLR1_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR1_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR1_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR1_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR1_1_BIST
+#define BIFPLR1_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR1_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR1_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR1_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR1_1_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR1_1_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR1_1_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR1_1_IO_BASE_LIMIT
+#define BIFPLR1_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR1_1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR1_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR1_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR1_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR1_1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR1_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR1_1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR1_1_SECONDARY_STATUS
+#define BIFPLR1_1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR1_1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR1_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR1_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR1_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR1_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR1_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR1_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR1_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR1_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR1_1_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR1_1_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR1_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR1_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR1_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR1_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR1_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR1_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR1_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR1_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR1_1_MEM_BASE_LIMIT
+#define BIFPLR1_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR1_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR1_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR1_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR1_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR1_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR1_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR1_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR1_1_PREF_BASE_LIMIT
+#define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR1_1_PREF_BASE_UPPER
+#define BIFPLR1_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR1_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PREF_LIMIT_UPPER
+#define BIFPLR1_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR1_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR1_1_IO_BASE_LIMIT_HI
+#define BIFPLR1_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR1_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR1_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR1_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR1_1_CAP_PTR
+#define BIFPLR1_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR1_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIFPLR1_1_INTERRUPT_LINE
+#define BIFPLR1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR1_1_INTERRUPT_PIN
+#define BIFPLR1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR1_1_IRQ_BRIDGE_CNTL
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+//BIFPLR1_1_EXT_BRIDGE_CNTL
+#define BIFPLR1_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR1_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR1_1_PMI_CAP_LIST
+#define BIFPLR1_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR1_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR1_1_PMI_CAP
+#define BIFPLR1_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR1_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR1_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR1_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR1_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR1_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR1_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR1_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR1_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR1_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR1_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR1_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR1_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR1_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR1_1_PMI_STATUS_CNTL
+#define BIFPLR1_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR1_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR1_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR1_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR1_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR1_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR1_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR1_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR1_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR1_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR1_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR1_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR1_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR1_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR1_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR1_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR1_1_PCIE_CAP_LIST
+#define BIFPLR1_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR1_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR1_1_PCIE_CAP
+#define BIFPLR1_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR1_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR1_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR1_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR1_1_DEVICE_CAP
+#define BIFPLR1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR1_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR1_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR1_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR1_1_DEVICE_CNTL
+#define BIFPLR1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR1_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR1_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR1_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR1_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR1_1_DEVICE_STATUS
+#define BIFPLR1_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR1_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR1_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR1_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR1_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR1_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR1_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR1_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIFPLR1_1_LINK_CAP
+#define BIFPLR1_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR1_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR1_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR1_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR1_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR1_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR1_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR1_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR1_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR1_1_LINK_CNTL
+#define BIFPLR1_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR1_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR1_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR1_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR1_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR1_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR1_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIFPLR1_1_LINK_STATUS
+#define BIFPLR1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR1_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR1_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR1_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR1_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR1_1_SLOT_CAP
+#define BIFPLR1_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR1_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR1_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR1_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR1_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR1_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR1_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR1_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR1_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR1_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR1_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR1_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR1_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR1_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR1_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR1_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR1_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR1_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR1_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR1_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR1_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR1_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR1_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR1_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR1_1_SLOT_CNTL
+#define BIFPLR1_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR1_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR1_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR1_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR1_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR1_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR1_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR1_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR1_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR1_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR1_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR1_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR1_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR1_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR1_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR1_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR1_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR1_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR1_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR1_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR1_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR1_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR1_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR1_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR1_1_SLOT_STATUS
+#define BIFPLR1_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR1_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR1_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR1_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR1_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR1_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR1_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR1_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR1_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR1_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR1_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR1_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR1_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR1_1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR1_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR1_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR1_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR1_1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR1_1_ROOT_CNTL
+#define BIFPLR1_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR1_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR1_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR1_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR1_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR1_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR1_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR1_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR1_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR1_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR1_1_ROOT_CAP
+#define BIFPLR1_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR1_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR1_1_ROOT_STATUS
+#define BIFPLR1_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR1_1_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR1_1_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR1_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR1_1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR1_1_DEVICE_CAP2
+#define BIFPLR1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIFPLR1_1_DEVICE_CNTL2
+#define BIFPLR1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR1_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR1_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR1_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR1_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR1_1_DEVICE_STATUS2
+#define BIFPLR1_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR1_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR1_1_LINK_CAP2
+#define BIFPLR1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR1_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIFPLR1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR1_1_LINK_CAP2__RESERVED__SHIFT 0x13
+#define BIFPLR1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR1_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L
+#define BIFPLR1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L
+#define BIFPLR1_1_LINK_CAP2__RESERVED_MASK 0xFFF80000L
+//BIFPLR1_1_LINK_CNTL2
+#define BIFPLR1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR1_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR1_1_LINK_STATUS2
+#define BIFPLR1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIFPLR1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIFPLR1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIFPLR1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIFPLR1_1_SLOT_CAP2
+#define BIFPLR1_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR1_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR1_1_SLOT_CNTL2
+#define BIFPLR1_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR1_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR1_1_SLOT_STATUS2
+#define BIFPLR1_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR1_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR1_1_MSI_CAP_LIST
+#define BIFPLR1_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR1_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR1_1_MSI_MSG_CNTL
+#define BIFPLR1_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR1_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR1_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR1_1_MSI_MSG_ADDR_LO
+#define BIFPLR1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR1_1_MSI_MSG_ADDR_HI
+#define BIFPLR1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR1_1_MSI_MSG_DATA
+#define BIFPLR1_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR1_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIFPLR1_1_MSI_MSG_DATA_64
+#define BIFPLR1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR1_1_SSID_CAP_LIST
+#define BIFPLR1_1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR1_1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR1_1_SSID_CAP
+#define BIFPLR1_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR1_1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR1_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR1_1_MSI_MAP_CAP_LIST
+#define BIFPLR1_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR1_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR1_1_MSI_MAP_CAP
+#define BIFPLR1_1_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR1_1_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR1_1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR1_1_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR1_1_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR1_1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR1_1_MSI_MAP_ADDR_LO
+#define BIFPLR1_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define BIFPLR1_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L
+//BIFPLR1_1_MSI_MAP_ADDR_HI
+#define BIFPLR1_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define BIFPLR1_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR1_1_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_1_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR1_1_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR1_1_PCIE_PORT_VC_CNTL
+#define BIFPLR1_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR1_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR1_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR1_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR1_1_PCIE_PORT_VC_STATUS
+#define BIFPLR1_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR1_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR1_1_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR1_1_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR1_1_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR1_1_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_1_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR1_1_PCIE_UNCORR_ERR_MASK
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR1_1_PCIE_CORR_ERR_STATUS
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR1_1_PCIE_CORR_ERR_MASK
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIFPLR1_1_PCIE_HDR_LOG0
+#define BIFPLR1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_HDR_LOG1
+#define BIFPLR1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_HDR_LOG2
+#define BIFPLR1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_HDR_LOG3
+#define BIFPLR1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_ROOT_ERR_CMD
+#define BIFPLR1_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR1_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR1_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR1_1_PCIE_ROOT_ERR_STATUS
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR1_1_PCIE_ERR_SRC_ID
+#define BIFPLR1_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR1_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR1_1_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_1_PCIE_LINK_CNTL3
+#define BIFPLR1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR1_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define BIFPLR1_1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10
+#define BIFPLR1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+#define BIFPLR1_1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L
+//BIFPLR1_1_PCIE_LANE_ERROR_STATUS
+#define BIFPLR1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIFPLR1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIFPLR1_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_1_PCIE_ACS_CAP
+#define BIFPLR1_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR1_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR1_1_PCIE_ACS_CNTL
+#define BIFPLR1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR1_1_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_1_PCIE_MC_CAP
+#define BIFPLR1_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR1_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR1_1_PCIE_MC_CNTL
+#define BIFPLR1_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR1_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR1_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR1_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR1_1_PCIE_MC_ADDR0
+#define BIFPLR1_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR1_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR1_1_PCIE_MC_ADDR1
+#define BIFPLR1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_MC_RCV0
+#define BIFPLR1_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR1_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_MC_RCV1
+#define BIFPLR1_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR1_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_MC_BLOCK_ALL0
+#define BIFPLR1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_MC_BLOCK_ALL1
+#define BIFPLR1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR1_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR1_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR1_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR1_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR1_1_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR1_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR1_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_1_PCIE_L1_PM_SUB_CAP
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR1_1_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR1_1_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_1_PCIE_DPC_CAP_LIST
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR1_1_PCIE_DPC_CNTL
+#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR1_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR1_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR1_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR1_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR1_1_PCIE_DPC_STATUS
+#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR1_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR1_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR1_1_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR1_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR1_1_PCIE_RP_PIO_STATUS
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR1_1_PCIE_RP_PIO_MASK
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR1_1_PCIE_RP_PIO_SEVERITY
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR1_1_PCIE_RP_PIO_SYSERROR
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR1_1_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR1_1_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_RP_PIO_IMPSPEC_LOG
+#define BIFPLR1_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_ESM_CAP_LIST
+#define BIFPLR1_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_1_PCIE_ESM_HEADER_1
+#define BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR1_1_PCIE_ESM_HEADER_2
+#define BIFPLR1_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR1_1_PCIE_ESM_STATUS
+#define BIFPLR1_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR1_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR1_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR1_1_PCIE_ESM_CTRL
+#define BIFPLR1_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8
+#define BIFPLR1_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR1_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL
+#define BIFPLR1_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L
+#define BIFPLR1_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR1_1_PCIE_ESM_CAP_1
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR1_1_PCIE_ESM_CAP_2
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR1_1_PCIE_ESM_CAP_3
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR1_1_PCIE_ESM_CAP_4
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR1_1_PCIE_ESM_CAP_5
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR1_1_PCIE_ESM_CAP_6
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR1_1_PCIE_ESM_CAP_7
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+
+
+// addressBlock: nbio_pcie0_bifplr2_cfgdecp
+//BIFPLR2_1_VENDOR_ID
+#define BIFPLR2_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR2_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR2_1_DEVICE_ID
+#define BIFPLR2_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR2_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR2_1_COMMAND
+#define BIFPLR2_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR2_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR2_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR2_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR2_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR2_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR2_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR2_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR2_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR2_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR2_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR2_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR2_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR2_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR2_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR2_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR2_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR2_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR2_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR2_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR2_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR2_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR2_1_STATUS
+#define BIFPLR2_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR2_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR2_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR2_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR2_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR2_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR2_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR2_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR2_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR2_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR2_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR2_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR2_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR2_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR2_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR2_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR2_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR2_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR2_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR2_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR2_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR2_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR2_1_REVISION_ID
+#define BIFPLR2_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR2_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR2_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR2_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR2_1_PROG_INTERFACE
+#define BIFPLR2_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR2_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR2_1_SUB_CLASS
+#define BIFPLR2_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR2_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR2_1_BASE_CLASS
+#define BIFPLR2_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR2_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR2_1_CACHE_LINE
+#define BIFPLR2_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR2_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR2_1_LATENCY
+#define BIFPLR2_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR2_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR2_1_HEADER
+#define BIFPLR2_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR2_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR2_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR2_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR2_1_BIST
+#define BIFPLR2_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR2_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR2_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR2_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR2_1_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR2_1_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR2_1_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR2_1_IO_BASE_LIMIT
+#define BIFPLR2_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR2_1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR2_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR2_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR2_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR2_1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR2_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR2_1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR2_1_SECONDARY_STATUS
+#define BIFPLR2_1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR2_1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR2_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR2_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR2_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR2_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR2_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR2_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR2_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR2_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR2_1_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR2_1_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR2_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR2_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR2_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR2_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR2_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR2_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR2_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR2_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR2_1_MEM_BASE_LIMIT
+#define BIFPLR2_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR2_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR2_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR2_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR2_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR2_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR2_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR2_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR2_1_PREF_BASE_LIMIT
+#define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR2_1_PREF_BASE_UPPER
+#define BIFPLR2_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR2_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PREF_LIMIT_UPPER
+#define BIFPLR2_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR2_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR2_1_IO_BASE_LIMIT_HI
+#define BIFPLR2_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR2_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR2_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR2_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR2_1_CAP_PTR
+#define BIFPLR2_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR2_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIFPLR2_1_INTERRUPT_LINE
+#define BIFPLR2_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR2_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR2_1_INTERRUPT_PIN
+#define BIFPLR2_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR2_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR2_1_IRQ_BRIDGE_CNTL
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+//BIFPLR2_1_EXT_BRIDGE_CNTL
+#define BIFPLR2_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR2_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR2_1_PMI_CAP_LIST
+#define BIFPLR2_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR2_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR2_1_PMI_CAP
+#define BIFPLR2_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR2_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR2_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR2_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR2_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR2_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR2_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR2_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR2_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR2_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR2_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR2_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR2_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR2_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR2_1_PMI_STATUS_CNTL
+#define BIFPLR2_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR2_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR2_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR2_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR2_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR2_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR2_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR2_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR2_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR2_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR2_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR2_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR2_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR2_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR2_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR2_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR2_1_PCIE_CAP_LIST
+#define BIFPLR2_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR2_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR2_1_PCIE_CAP
+#define BIFPLR2_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR2_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR2_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR2_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR2_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR2_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR2_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR2_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR2_1_DEVICE_CAP
+#define BIFPLR2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR2_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR2_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR2_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR2_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR2_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR2_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR2_1_DEVICE_CNTL
+#define BIFPLR2_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR2_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR2_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR2_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR2_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR2_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR2_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR2_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR2_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR2_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR2_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR2_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR2_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR2_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR2_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR2_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR2_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR2_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR2_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR2_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR2_1_DEVICE_STATUS
+#define BIFPLR2_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR2_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR2_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR2_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR2_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR2_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR2_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR2_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR2_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR2_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR2_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR2_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIFPLR2_1_LINK_CAP
+#define BIFPLR2_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR2_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR2_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR2_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR2_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR2_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR2_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR2_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR2_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR2_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR2_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR2_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR2_1_LINK_CNTL
+#define BIFPLR2_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR2_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR2_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR2_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR2_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR2_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR2_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR2_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR2_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR2_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR2_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR2_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIFPLR2_1_LINK_STATUS
+#define BIFPLR2_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR2_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR2_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR2_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR2_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR2_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR2_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR2_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR2_1_SLOT_CAP
+#define BIFPLR2_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR2_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR2_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR2_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR2_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR2_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR2_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR2_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR2_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR2_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR2_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR2_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR2_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR2_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR2_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR2_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR2_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR2_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR2_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR2_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR2_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR2_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR2_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR2_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR2_1_SLOT_CNTL
+#define BIFPLR2_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR2_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR2_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR2_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR2_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR2_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR2_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR2_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR2_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR2_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR2_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR2_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR2_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR2_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR2_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR2_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR2_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR2_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR2_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR2_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR2_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR2_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR2_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR2_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR2_1_SLOT_STATUS
+#define BIFPLR2_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR2_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR2_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR2_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR2_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR2_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR2_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR2_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR2_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR2_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR2_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR2_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR2_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR2_1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR2_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR2_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR2_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR2_1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR2_1_ROOT_CNTL
+#define BIFPLR2_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR2_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR2_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR2_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR2_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR2_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR2_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR2_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR2_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR2_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR2_1_ROOT_CAP
+#define BIFPLR2_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR2_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR2_1_ROOT_STATUS
+#define BIFPLR2_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR2_1_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR2_1_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR2_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR2_1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR2_1_DEVICE_CAP2
+#define BIFPLR2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR2_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR2_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR2_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR2_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIFPLR2_1_DEVICE_CNTL2
+#define BIFPLR2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR2_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR2_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR2_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR2_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR2_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR2_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR2_1_DEVICE_STATUS2
+#define BIFPLR2_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR2_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR2_1_LINK_CAP2
+#define BIFPLR2_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR2_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR2_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIFPLR2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR2_1_LINK_CAP2__RESERVED__SHIFT 0x13
+#define BIFPLR2_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR2_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR2_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L
+#define BIFPLR2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L
+#define BIFPLR2_1_LINK_CAP2__RESERVED_MASK 0xFFF80000L
+//BIFPLR2_1_LINK_CNTL2
+#define BIFPLR2_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR2_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR2_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR2_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR2_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR2_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR2_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR2_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR2_1_LINK_STATUS2
+#define BIFPLR2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIFPLR2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIFPLR2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIFPLR2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIFPLR2_1_SLOT_CAP2
+#define BIFPLR2_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR2_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR2_1_SLOT_CNTL2
+#define BIFPLR2_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR2_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR2_1_SLOT_STATUS2
+#define BIFPLR2_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR2_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR2_1_MSI_CAP_LIST
+#define BIFPLR2_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR2_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR2_1_MSI_MSG_CNTL
+#define BIFPLR2_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR2_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR2_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR2_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR2_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR2_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR2_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR2_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR2_1_MSI_MSG_ADDR_LO
+#define BIFPLR2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR2_1_MSI_MSG_ADDR_HI
+#define BIFPLR2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR2_1_MSI_MSG_DATA
+#define BIFPLR2_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR2_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIFPLR2_1_MSI_MSG_DATA_64
+#define BIFPLR2_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR2_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR2_1_SSID_CAP_LIST
+#define BIFPLR2_1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR2_1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR2_1_SSID_CAP
+#define BIFPLR2_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR2_1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR2_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR2_1_MSI_MAP_CAP_LIST
+#define BIFPLR2_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR2_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR2_1_MSI_MAP_CAP
+#define BIFPLR2_1_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR2_1_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR2_1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR2_1_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR2_1_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR2_1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR2_1_MSI_MAP_ADDR_LO
+#define BIFPLR2_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define BIFPLR2_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L
+//BIFPLR2_1_MSI_MAP_ADDR_HI
+#define BIFPLR2_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define BIFPLR2_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR2_1_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_1_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR2_1_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR2_1_PCIE_PORT_VC_CNTL
+#define BIFPLR2_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR2_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR2_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR2_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR2_1_PCIE_PORT_VC_STATUS
+#define BIFPLR2_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR2_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR2_1_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR2_1_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR2_1_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR2_1_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_1_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR2_1_PCIE_UNCORR_ERR_MASK
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR2_1_PCIE_CORR_ERR_STATUS
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR2_1_PCIE_CORR_ERR_MASK
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIFPLR2_1_PCIE_HDR_LOG0
+#define BIFPLR2_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_HDR_LOG1
+#define BIFPLR2_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_HDR_LOG2
+#define BIFPLR2_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_HDR_LOG3
+#define BIFPLR2_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_ROOT_ERR_CMD
+#define BIFPLR2_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR2_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR2_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR2_1_PCIE_ROOT_ERR_STATUS
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR2_1_PCIE_ERR_SRC_ID
+#define BIFPLR2_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR2_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR2_1_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_1_PCIE_LINK_CNTL3
+#define BIFPLR2_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR2_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define BIFPLR2_1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10
+#define BIFPLR2_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+#define BIFPLR2_1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L
+//BIFPLR2_1_PCIE_LANE_ERROR_STATUS
+#define BIFPLR2_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIFPLR2_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIFPLR2_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_1_PCIE_ACS_CAP
+#define BIFPLR2_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR2_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR2_1_PCIE_ACS_CNTL
+#define BIFPLR2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR2_1_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_1_PCIE_MC_CAP
+#define BIFPLR2_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR2_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR2_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR2_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR2_1_PCIE_MC_CNTL
+#define BIFPLR2_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR2_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR2_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR2_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR2_1_PCIE_MC_ADDR0
+#define BIFPLR2_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR2_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR2_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR2_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR2_1_PCIE_MC_ADDR1
+#define BIFPLR2_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR2_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_MC_RCV0
+#define BIFPLR2_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR2_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_MC_RCV1
+#define BIFPLR2_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR2_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_MC_BLOCK_ALL0
+#define BIFPLR2_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR2_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_MC_BLOCK_ALL1
+#define BIFPLR2_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR2_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR2_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR2_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR2_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR2_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR2_1_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR2_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR2_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_1_PCIE_L1_PM_SUB_CAP
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR2_1_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR2_1_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_1_PCIE_DPC_CAP_LIST
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR2_1_PCIE_DPC_CNTL
+#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR2_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR2_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR2_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR2_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR2_1_PCIE_DPC_STATUS
+#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR2_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR2_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR2_1_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR2_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR2_1_PCIE_RP_PIO_STATUS
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR2_1_PCIE_RP_PIO_MASK
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR2_1_PCIE_RP_PIO_SEVERITY
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR2_1_PCIE_RP_PIO_SYSERROR
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR2_1_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR2_1_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_RP_PIO_IMPSPEC_LOG
+#define BIFPLR2_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_ESM_CAP_LIST
+#define BIFPLR2_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_1_PCIE_ESM_HEADER_1
+#define BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR2_1_PCIE_ESM_HEADER_2
+#define BIFPLR2_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR2_1_PCIE_ESM_STATUS
+#define BIFPLR2_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR2_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR2_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR2_1_PCIE_ESM_CTRL
+#define BIFPLR2_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8
+#define BIFPLR2_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR2_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL
+#define BIFPLR2_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L
+#define BIFPLR2_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR2_1_PCIE_ESM_CAP_1
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR2_1_PCIE_ESM_CAP_2
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR2_1_PCIE_ESM_CAP_3
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR2_1_PCIE_ESM_CAP_4
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR2_1_PCIE_ESM_CAP_5
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR2_1_PCIE_ESM_CAP_6
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR2_1_PCIE_ESM_CAP_7
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+
+
+// addressBlock: nbio_pcie0_bifplr3_cfgdecp
+//BIFPLR3_1_VENDOR_ID
+#define BIFPLR3_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR3_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR3_1_DEVICE_ID
+#define BIFPLR3_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR3_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR3_1_COMMAND
+#define BIFPLR3_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR3_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR3_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR3_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR3_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR3_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR3_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR3_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR3_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR3_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR3_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR3_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR3_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR3_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR3_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR3_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR3_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR3_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR3_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR3_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR3_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR3_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR3_1_STATUS
+#define BIFPLR3_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR3_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR3_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR3_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR3_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR3_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR3_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR3_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR3_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR3_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR3_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR3_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR3_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR3_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR3_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR3_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR3_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR3_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR3_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR3_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR3_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR3_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR3_1_REVISION_ID
+#define BIFPLR3_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR3_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR3_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR3_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR3_1_PROG_INTERFACE
+#define BIFPLR3_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR3_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR3_1_SUB_CLASS
+#define BIFPLR3_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR3_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR3_1_BASE_CLASS
+#define BIFPLR3_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR3_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR3_1_CACHE_LINE
+#define BIFPLR3_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR3_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR3_1_LATENCY
+#define BIFPLR3_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR3_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR3_1_HEADER
+#define BIFPLR3_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR3_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR3_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR3_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR3_1_BIST
+#define BIFPLR3_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR3_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR3_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR3_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR3_1_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR3_1_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR3_1_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR3_1_IO_BASE_LIMIT
+#define BIFPLR3_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR3_1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR3_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR3_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR3_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR3_1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR3_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR3_1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR3_1_SECONDARY_STATUS
+#define BIFPLR3_1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR3_1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR3_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR3_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR3_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR3_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR3_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR3_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR3_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR3_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR3_1_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR3_1_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR3_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR3_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR3_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR3_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR3_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR3_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR3_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR3_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR3_1_MEM_BASE_LIMIT
+#define BIFPLR3_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR3_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR3_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR3_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR3_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR3_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR3_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR3_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR3_1_PREF_BASE_LIMIT
+#define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR3_1_PREF_BASE_UPPER
+#define BIFPLR3_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR3_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PREF_LIMIT_UPPER
+#define BIFPLR3_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR3_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR3_1_IO_BASE_LIMIT_HI
+#define BIFPLR3_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR3_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR3_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR3_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR3_1_CAP_PTR
+#define BIFPLR3_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR3_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIFPLR3_1_INTERRUPT_LINE
+#define BIFPLR3_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR3_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR3_1_INTERRUPT_PIN
+#define BIFPLR3_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR3_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR3_1_IRQ_BRIDGE_CNTL
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+//BIFPLR3_1_EXT_BRIDGE_CNTL
+#define BIFPLR3_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR3_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR3_1_PMI_CAP_LIST
+#define BIFPLR3_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR3_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR3_1_PMI_CAP
+#define BIFPLR3_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR3_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR3_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR3_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR3_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR3_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR3_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR3_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR3_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR3_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR3_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR3_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR3_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR3_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR3_1_PMI_STATUS_CNTL
+#define BIFPLR3_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR3_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR3_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR3_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR3_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR3_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR3_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR3_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR3_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR3_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR3_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR3_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR3_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR3_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR3_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR3_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR3_1_PCIE_CAP_LIST
+#define BIFPLR3_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR3_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR3_1_PCIE_CAP
+#define BIFPLR3_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR3_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR3_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR3_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR3_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR3_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR3_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR3_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR3_1_DEVICE_CAP
+#define BIFPLR3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR3_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR3_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR3_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR3_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR3_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR3_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR3_1_DEVICE_CNTL
+#define BIFPLR3_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR3_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR3_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR3_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR3_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR3_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR3_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR3_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR3_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR3_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR3_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR3_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR3_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR3_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR3_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR3_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR3_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR3_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR3_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR3_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR3_1_DEVICE_STATUS
+#define BIFPLR3_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR3_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR3_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR3_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR3_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR3_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR3_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR3_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR3_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR3_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR3_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR3_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIFPLR3_1_LINK_CAP
+#define BIFPLR3_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR3_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR3_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR3_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR3_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR3_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR3_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR3_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR3_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR3_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR3_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR3_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR3_1_LINK_CNTL
+#define BIFPLR3_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR3_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR3_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR3_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR3_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR3_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR3_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR3_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR3_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR3_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR3_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR3_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIFPLR3_1_LINK_STATUS
+#define BIFPLR3_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR3_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR3_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR3_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR3_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR3_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR3_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR3_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR3_1_SLOT_CAP
+#define BIFPLR3_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR3_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR3_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR3_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR3_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR3_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR3_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR3_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR3_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR3_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR3_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR3_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR3_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR3_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR3_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR3_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR3_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR3_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR3_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR3_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR3_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR3_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR3_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR3_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR3_1_SLOT_CNTL
+#define BIFPLR3_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR3_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR3_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR3_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR3_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR3_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR3_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR3_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR3_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR3_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR3_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR3_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR3_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR3_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR3_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR3_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR3_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR3_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR3_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR3_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR3_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR3_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR3_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR3_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR3_1_SLOT_STATUS
+#define BIFPLR3_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR3_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR3_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR3_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR3_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR3_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR3_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR3_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR3_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR3_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR3_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR3_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR3_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR3_1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR3_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR3_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR3_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR3_1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR3_1_ROOT_CNTL
+#define BIFPLR3_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR3_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR3_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR3_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR3_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR3_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR3_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR3_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR3_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR3_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR3_1_ROOT_CAP
+#define BIFPLR3_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR3_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR3_1_ROOT_STATUS
+#define BIFPLR3_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR3_1_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR3_1_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR3_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR3_1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR3_1_DEVICE_CAP2
+#define BIFPLR3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR3_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR3_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR3_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR3_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIFPLR3_1_DEVICE_CNTL2
+#define BIFPLR3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR3_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR3_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR3_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR3_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR3_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR3_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR3_1_DEVICE_STATUS2
+#define BIFPLR3_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR3_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR3_1_LINK_CAP2
+#define BIFPLR3_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR3_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR3_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIFPLR3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR3_1_LINK_CAP2__RESERVED__SHIFT 0x13
+#define BIFPLR3_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR3_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR3_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L
+#define BIFPLR3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L
+#define BIFPLR3_1_LINK_CAP2__RESERVED_MASK 0xFFF80000L
+//BIFPLR3_1_LINK_CNTL2
+#define BIFPLR3_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR3_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR3_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR3_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR3_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR3_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR3_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR3_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR3_1_LINK_STATUS2
+#define BIFPLR3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIFPLR3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIFPLR3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIFPLR3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIFPLR3_1_SLOT_CAP2
+#define BIFPLR3_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR3_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR3_1_SLOT_CNTL2
+#define BIFPLR3_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR3_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR3_1_SLOT_STATUS2
+#define BIFPLR3_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR3_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR3_1_MSI_CAP_LIST
+#define BIFPLR3_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR3_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR3_1_MSI_MSG_CNTL
+#define BIFPLR3_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR3_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR3_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR3_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR3_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR3_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR3_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR3_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR3_1_MSI_MSG_ADDR_LO
+#define BIFPLR3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR3_1_MSI_MSG_ADDR_HI
+#define BIFPLR3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR3_1_MSI_MSG_DATA
+#define BIFPLR3_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR3_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIFPLR3_1_MSI_MSG_DATA_64
+#define BIFPLR3_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR3_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR3_1_SSID_CAP_LIST
+#define BIFPLR3_1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR3_1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR3_1_SSID_CAP
+#define BIFPLR3_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR3_1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR3_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR3_1_MSI_MAP_CAP_LIST
+#define BIFPLR3_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR3_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR3_1_MSI_MAP_CAP
+#define BIFPLR3_1_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR3_1_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR3_1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR3_1_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR3_1_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR3_1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR3_1_MSI_MAP_ADDR_LO
+#define BIFPLR3_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define BIFPLR3_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L
+//BIFPLR3_1_MSI_MAP_ADDR_HI
+#define BIFPLR3_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define BIFPLR3_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR3_1_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_1_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR3_1_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR3_1_PCIE_PORT_VC_CNTL
+#define BIFPLR3_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR3_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR3_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR3_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR3_1_PCIE_PORT_VC_STATUS
+#define BIFPLR3_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR3_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR3_1_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR3_1_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR3_1_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR3_1_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_1_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR3_1_PCIE_UNCORR_ERR_MASK
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR3_1_PCIE_CORR_ERR_STATUS
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR3_1_PCIE_CORR_ERR_MASK
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIFPLR3_1_PCIE_HDR_LOG0
+#define BIFPLR3_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_HDR_LOG1
+#define BIFPLR3_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_HDR_LOG2
+#define BIFPLR3_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_HDR_LOG3
+#define BIFPLR3_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_ROOT_ERR_CMD
+#define BIFPLR3_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR3_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR3_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR3_1_PCIE_ROOT_ERR_STATUS
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR3_1_PCIE_ERR_SRC_ID
+#define BIFPLR3_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR3_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR3_1_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_1_PCIE_LINK_CNTL3
+#define BIFPLR3_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR3_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define BIFPLR3_1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10
+#define BIFPLR3_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+#define BIFPLR3_1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L
+//BIFPLR3_1_PCIE_LANE_ERROR_STATUS
+#define BIFPLR3_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIFPLR3_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIFPLR3_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_1_PCIE_ACS_CAP
+#define BIFPLR3_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR3_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR3_1_PCIE_ACS_CNTL
+#define BIFPLR3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR3_1_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_1_PCIE_MC_CAP
+#define BIFPLR3_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR3_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR3_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR3_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR3_1_PCIE_MC_CNTL
+#define BIFPLR3_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR3_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR3_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR3_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR3_1_PCIE_MC_ADDR0
+#define BIFPLR3_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR3_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR3_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR3_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR3_1_PCIE_MC_ADDR1
+#define BIFPLR3_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR3_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_MC_RCV0
+#define BIFPLR3_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR3_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_MC_RCV1
+#define BIFPLR3_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR3_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_MC_BLOCK_ALL0
+#define BIFPLR3_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR3_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_MC_BLOCK_ALL1
+#define BIFPLR3_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR3_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR3_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR3_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR3_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR3_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR3_1_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR3_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR3_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_1_PCIE_L1_PM_SUB_CAP
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR3_1_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR3_1_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_1_PCIE_DPC_CAP_LIST
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR3_1_PCIE_DPC_CNTL
+#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR3_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR3_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR3_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR3_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR3_1_PCIE_DPC_STATUS
+#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR3_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR3_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR3_1_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR3_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR3_1_PCIE_RP_PIO_STATUS
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR3_1_PCIE_RP_PIO_MASK
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR3_1_PCIE_RP_PIO_SEVERITY
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR3_1_PCIE_RP_PIO_SYSERROR
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR3_1_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR3_1_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_RP_PIO_IMPSPEC_LOG
+#define BIFPLR3_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_ESM_CAP_LIST
+#define BIFPLR3_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_1_PCIE_ESM_HEADER_1
+#define BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR3_1_PCIE_ESM_HEADER_2
+#define BIFPLR3_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR3_1_PCIE_ESM_STATUS
+#define BIFPLR3_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR3_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR3_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR3_1_PCIE_ESM_CTRL
+#define BIFPLR3_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8
+#define BIFPLR3_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR3_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL
+#define BIFPLR3_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L
+#define BIFPLR3_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR3_1_PCIE_ESM_CAP_1
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR3_1_PCIE_ESM_CAP_2
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR3_1_PCIE_ESM_CAP_3
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR3_1_PCIE_ESM_CAP_4
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR3_1_PCIE_ESM_CAP_5
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR3_1_PCIE_ESM_CAP_6
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR3_1_PCIE_ESM_CAP_7
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+
+
+// addressBlock: nbio_pcie0_bifplr4_cfgdecp
+//BIFPLR4_1_VENDOR_ID
+#define BIFPLR4_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR4_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR4_1_DEVICE_ID
+#define BIFPLR4_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR4_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR4_1_COMMAND
+#define BIFPLR4_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR4_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR4_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR4_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR4_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR4_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR4_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR4_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR4_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR4_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR4_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR4_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR4_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR4_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR4_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR4_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR4_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR4_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR4_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR4_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR4_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR4_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR4_1_STATUS
+#define BIFPLR4_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR4_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR4_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR4_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR4_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR4_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR4_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR4_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR4_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR4_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR4_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR4_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR4_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR4_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR4_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR4_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR4_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR4_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR4_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR4_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR4_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR4_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR4_1_REVISION_ID
+#define BIFPLR4_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR4_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR4_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR4_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR4_1_PROG_INTERFACE
+#define BIFPLR4_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR4_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR4_1_SUB_CLASS
+#define BIFPLR4_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR4_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR4_1_BASE_CLASS
+#define BIFPLR4_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR4_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR4_1_CACHE_LINE
+#define BIFPLR4_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR4_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR4_1_LATENCY
+#define BIFPLR4_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR4_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR4_1_HEADER
+#define BIFPLR4_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR4_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR4_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR4_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR4_1_BIST
+#define BIFPLR4_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR4_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR4_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR4_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR4_1_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR4_1_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR4_1_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR4_1_IO_BASE_LIMIT
+#define BIFPLR4_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR4_1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR4_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR4_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR4_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR4_1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR4_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR4_1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR4_1_SECONDARY_STATUS
+#define BIFPLR4_1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR4_1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR4_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR4_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR4_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR4_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR4_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR4_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR4_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR4_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR4_1_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR4_1_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR4_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR4_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR4_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR4_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR4_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR4_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR4_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR4_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR4_1_MEM_BASE_LIMIT
+#define BIFPLR4_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR4_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR4_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR4_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR4_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR4_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR4_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR4_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR4_1_PREF_BASE_LIMIT
+#define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR4_1_PREF_BASE_UPPER
+#define BIFPLR4_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR4_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PREF_LIMIT_UPPER
+#define BIFPLR4_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR4_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR4_1_IO_BASE_LIMIT_HI
+#define BIFPLR4_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR4_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR4_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR4_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR4_1_CAP_PTR
+#define BIFPLR4_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR4_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIFPLR4_1_INTERRUPT_LINE
+#define BIFPLR4_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR4_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR4_1_INTERRUPT_PIN
+#define BIFPLR4_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR4_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR4_1_IRQ_BRIDGE_CNTL
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+//BIFPLR4_1_EXT_BRIDGE_CNTL
+#define BIFPLR4_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR4_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR4_1_PMI_CAP_LIST
+#define BIFPLR4_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR4_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR4_1_PMI_CAP
+#define BIFPLR4_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR4_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR4_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR4_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR4_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR4_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR4_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR4_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR4_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR4_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR4_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR4_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR4_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR4_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR4_1_PMI_STATUS_CNTL
+#define BIFPLR4_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR4_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR4_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR4_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR4_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR4_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR4_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR4_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR4_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR4_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR4_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR4_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR4_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR4_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR4_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR4_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR4_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR4_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR4_1_PCIE_CAP_LIST
+#define BIFPLR4_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR4_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR4_1_PCIE_CAP
+#define BIFPLR4_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR4_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR4_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR4_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR4_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR4_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR4_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR4_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR4_1_DEVICE_CAP
+#define BIFPLR4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR4_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR4_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR4_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR4_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR4_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR4_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR4_1_DEVICE_CNTL
+#define BIFPLR4_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR4_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR4_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR4_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR4_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR4_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR4_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR4_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR4_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR4_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR4_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR4_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR4_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR4_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR4_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR4_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR4_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR4_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR4_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR4_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR4_1_DEVICE_STATUS
+#define BIFPLR4_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR4_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR4_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR4_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR4_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR4_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR4_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR4_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR4_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR4_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR4_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR4_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIFPLR4_1_LINK_CAP
+#define BIFPLR4_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR4_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR4_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR4_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR4_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR4_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR4_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR4_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR4_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR4_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR4_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR4_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR4_1_LINK_CNTL
+#define BIFPLR4_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR4_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR4_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR4_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR4_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR4_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR4_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR4_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR4_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR4_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR4_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR4_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIFPLR4_1_LINK_STATUS
+#define BIFPLR4_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR4_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR4_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR4_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR4_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR4_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR4_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR4_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR4_1_SLOT_CAP
+#define BIFPLR4_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR4_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR4_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR4_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR4_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR4_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR4_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR4_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR4_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR4_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR4_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR4_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR4_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR4_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR4_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR4_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR4_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR4_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR4_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR4_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR4_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR4_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR4_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR4_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR4_1_SLOT_CNTL
+#define BIFPLR4_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR4_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR4_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR4_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR4_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR4_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR4_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR4_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR4_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR4_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR4_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR4_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR4_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR4_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR4_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR4_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR4_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR4_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR4_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR4_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR4_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR4_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR4_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR4_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR4_1_SLOT_STATUS
+#define BIFPLR4_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR4_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR4_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR4_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR4_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR4_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR4_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR4_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR4_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR4_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR4_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR4_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR4_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR4_1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR4_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR4_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR4_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR4_1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR4_1_ROOT_CNTL
+#define BIFPLR4_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR4_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR4_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR4_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR4_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR4_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR4_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR4_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR4_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR4_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR4_1_ROOT_CAP
+#define BIFPLR4_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR4_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR4_1_ROOT_STATUS
+#define BIFPLR4_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR4_1_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR4_1_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR4_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR4_1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR4_1_DEVICE_CAP2
+#define BIFPLR4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR4_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR4_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR4_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR4_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIFPLR4_1_DEVICE_CNTL2
+#define BIFPLR4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR4_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR4_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR4_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR4_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR4_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR4_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR4_1_DEVICE_STATUS2
+#define BIFPLR4_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR4_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR4_1_LINK_CAP2
+#define BIFPLR4_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR4_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR4_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIFPLR4_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR4_1_LINK_CAP2__RESERVED__SHIFT 0x13
+#define BIFPLR4_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR4_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR4_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L
+#define BIFPLR4_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L
+#define BIFPLR4_1_LINK_CAP2__RESERVED_MASK 0xFFF80000L
+//BIFPLR4_1_LINK_CNTL2
+#define BIFPLR4_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR4_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR4_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR4_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR4_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR4_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR4_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR4_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR4_1_LINK_STATUS2
+#define BIFPLR4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIFPLR4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIFPLR4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIFPLR4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIFPLR4_1_SLOT_CAP2
+#define BIFPLR4_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR4_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR4_1_SLOT_CNTL2
+#define BIFPLR4_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR4_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR4_1_SLOT_STATUS2
+#define BIFPLR4_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR4_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR4_1_MSI_CAP_LIST
+#define BIFPLR4_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR4_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR4_1_MSI_MSG_CNTL
+#define BIFPLR4_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR4_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR4_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR4_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR4_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR4_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR4_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR4_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR4_1_MSI_MSG_ADDR_LO
+#define BIFPLR4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR4_1_MSI_MSG_ADDR_HI
+#define BIFPLR4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR4_1_MSI_MSG_DATA
+#define BIFPLR4_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR4_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIFPLR4_1_MSI_MSG_DATA_64
+#define BIFPLR4_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR4_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR4_1_SSID_CAP_LIST
+#define BIFPLR4_1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR4_1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR4_1_SSID_CAP
+#define BIFPLR4_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR4_1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR4_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR4_1_MSI_MAP_CAP_LIST
+#define BIFPLR4_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR4_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR4_1_MSI_MAP_CAP
+#define BIFPLR4_1_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR4_1_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR4_1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR4_1_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR4_1_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR4_1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR4_1_MSI_MAP_ADDR_LO
+#define BIFPLR4_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define BIFPLR4_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L
+//BIFPLR4_1_MSI_MAP_ADDR_HI
+#define BIFPLR4_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define BIFPLR4_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR4_1_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_1_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR4_1_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR4_1_PCIE_PORT_VC_CNTL
+#define BIFPLR4_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR4_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR4_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR4_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR4_1_PCIE_PORT_VC_STATUS
+#define BIFPLR4_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR4_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR4_1_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR4_1_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR4_1_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR4_1_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_1_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR4_1_PCIE_UNCORR_ERR_MASK
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR4_1_PCIE_CORR_ERR_STATUS
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR4_1_PCIE_CORR_ERR_MASK
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIFPLR4_1_PCIE_HDR_LOG0
+#define BIFPLR4_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_HDR_LOG1
+#define BIFPLR4_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_HDR_LOG2
+#define BIFPLR4_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_HDR_LOG3
+#define BIFPLR4_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_ROOT_ERR_CMD
+#define BIFPLR4_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR4_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR4_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR4_1_PCIE_ROOT_ERR_STATUS
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR4_1_PCIE_ERR_SRC_ID
+#define BIFPLR4_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR4_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR4_1_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_1_PCIE_LINK_CNTL3
+#define BIFPLR4_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR4_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define BIFPLR4_1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10
+#define BIFPLR4_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+#define BIFPLR4_1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L
+//BIFPLR4_1_PCIE_LANE_ERROR_STATUS
+#define BIFPLR4_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIFPLR4_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIFPLR4_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_1_PCIE_ACS_CAP
+#define BIFPLR4_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR4_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR4_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR4_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR4_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR4_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR4_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR4_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR4_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR4_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR4_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR4_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR4_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR4_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR4_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR4_1_PCIE_ACS_CNTL
+#define BIFPLR4_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR4_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR4_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR4_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR4_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR4_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR4_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR4_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR4_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR4_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR4_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR4_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR4_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR4_1_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_1_PCIE_MC_CAP
+#define BIFPLR4_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR4_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR4_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR4_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR4_1_PCIE_MC_CNTL
+#define BIFPLR4_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR4_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR4_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR4_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR4_1_PCIE_MC_ADDR0
+#define BIFPLR4_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR4_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR4_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR4_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR4_1_PCIE_MC_ADDR1
+#define BIFPLR4_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR4_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_MC_RCV0
+#define BIFPLR4_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR4_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_MC_RCV1
+#define BIFPLR4_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR4_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_MC_BLOCK_ALL0
+#define BIFPLR4_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR4_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_MC_BLOCK_ALL1
+#define BIFPLR4_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR4_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR4_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR4_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR4_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR4_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR4_1_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR4_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR4_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_1_PCIE_L1_PM_SUB_CAP
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR4_1_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR4_1_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_1_PCIE_DPC_CAP_LIST
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR4_1_PCIE_DPC_CNTL
+#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR4_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR4_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR4_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR4_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR4_1_PCIE_DPC_STATUS
+#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR4_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR4_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR4_1_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR4_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR4_1_PCIE_RP_PIO_STATUS
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR4_1_PCIE_RP_PIO_MASK
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR4_1_PCIE_RP_PIO_SEVERITY
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR4_1_PCIE_RP_PIO_SYSERROR
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR4_1_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR4_1_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_RP_PIO_IMPSPEC_LOG
+#define BIFPLR4_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_ESM_CAP_LIST
+#define BIFPLR4_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_1_PCIE_ESM_HEADER_1
+#define BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR4_1_PCIE_ESM_HEADER_2
+#define BIFPLR4_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR4_1_PCIE_ESM_STATUS
+#define BIFPLR4_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR4_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR4_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR4_1_PCIE_ESM_CTRL
+#define BIFPLR4_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8
+#define BIFPLR4_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR4_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL
+#define BIFPLR4_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L
+#define BIFPLR4_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR4_1_PCIE_ESM_CAP_1
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR4_1_PCIE_ESM_CAP_2
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR4_1_PCIE_ESM_CAP_3
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR4_1_PCIE_ESM_CAP_4
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR4_1_PCIE_ESM_CAP_5
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR4_1_PCIE_ESM_CAP_6
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR4_1_PCIE_ESM_CAP_7
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+
+
+// addressBlock: nbio_pcie0_bifplr5_cfgdecp
+//BIFPLR5_1_VENDOR_ID
+#define BIFPLR5_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR5_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR5_1_DEVICE_ID
+#define BIFPLR5_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR5_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR5_1_COMMAND
+#define BIFPLR5_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR5_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR5_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR5_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR5_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR5_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR5_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR5_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR5_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR5_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR5_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR5_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR5_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR5_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR5_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR5_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR5_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR5_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR5_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR5_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR5_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR5_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR5_1_STATUS
+#define BIFPLR5_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR5_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR5_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR5_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR5_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR5_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR5_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR5_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR5_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR5_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR5_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR5_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR5_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR5_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR5_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR5_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR5_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR5_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR5_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR5_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR5_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR5_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR5_1_REVISION_ID
+#define BIFPLR5_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR5_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR5_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR5_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR5_1_PROG_INTERFACE
+#define BIFPLR5_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR5_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR5_1_SUB_CLASS
+#define BIFPLR5_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR5_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR5_1_BASE_CLASS
+#define BIFPLR5_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR5_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR5_1_CACHE_LINE
+#define BIFPLR5_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR5_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR5_1_LATENCY
+#define BIFPLR5_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR5_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR5_1_HEADER
+#define BIFPLR5_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR5_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR5_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR5_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR5_1_BIST
+#define BIFPLR5_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR5_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR5_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR5_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR5_1_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR5_1_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR5_1_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR5_1_IO_BASE_LIMIT
+#define BIFPLR5_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR5_1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR5_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR5_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR5_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR5_1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR5_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR5_1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR5_1_SECONDARY_STATUS
+#define BIFPLR5_1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR5_1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR5_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR5_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR5_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR5_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR5_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR5_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR5_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR5_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR5_1_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR5_1_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR5_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR5_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR5_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR5_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR5_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR5_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR5_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR5_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR5_1_MEM_BASE_LIMIT
+#define BIFPLR5_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR5_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR5_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR5_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR5_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR5_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR5_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR5_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR5_1_PREF_BASE_LIMIT
+#define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR5_1_PREF_BASE_UPPER
+#define BIFPLR5_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR5_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PREF_LIMIT_UPPER
+#define BIFPLR5_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR5_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR5_1_IO_BASE_LIMIT_HI
+#define BIFPLR5_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR5_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR5_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR5_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR5_1_CAP_PTR
+#define BIFPLR5_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR5_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIFPLR5_1_INTERRUPT_LINE
+#define BIFPLR5_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR5_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR5_1_INTERRUPT_PIN
+#define BIFPLR5_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR5_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR5_1_IRQ_BRIDGE_CNTL
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+//BIFPLR5_1_EXT_BRIDGE_CNTL
+#define BIFPLR5_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR5_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR5_1_PMI_CAP_LIST
+#define BIFPLR5_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR5_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR5_1_PMI_CAP
+#define BIFPLR5_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR5_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR5_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR5_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR5_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR5_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR5_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR5_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR5_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR5_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR5_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR5_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR5_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR5_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR5_1_PMI_STATUS_CNTL
+#define BIFPLR5_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR5_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR5_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR5_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR5_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR5_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR5_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR5_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR5_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR5_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR5_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR5_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR5_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR5_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR5_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR5_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR5_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR5_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR5_1_PCIE_CAP_LIST
+#define BIFPLR5_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR5_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR5_1_PCIE_CAP
+#define BIFPLR5_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR5_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR5_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR5_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR5_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR5_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR5_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR5_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR5_1_DEVICE_CAP
+#define BIFPLR5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR5_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR5_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR5_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR5_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR5_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR5_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR5_1_DEVICE_CNTL
+#define BIFPLR5_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR5_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR5_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR5_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR5_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR5_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR5_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR5_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR5_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR5_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR5_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR5_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR5_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR5_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR5_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR5_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR5_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR5_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR5_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR5_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR5_1_DEVICE_STATUS
+#define BIFPLR5_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR5_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR5_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR5_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR5_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR5_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR5_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR5_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR5_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR5_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR5_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR5_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIFPLR5_1_LINK_CAP
+#define BIFPLR5_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR5_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR5_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR5_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR5_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR5_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR5_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR5_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR5_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR5_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR5_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR5_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR5_1_LINK_CNTL
+#define BIFPLR5_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR5_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR5_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR5_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR5_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR5_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR5_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR5_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR5_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR5_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR5_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR5_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIFPLR5_1_LINK_STATUS
+#define BIFPLR5_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR5_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR5_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR5_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR5_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR5_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR5_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR5_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR5_1_SLOT_CAP
+#define BIFPLR5_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR5_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR5_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR5_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR5_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR5_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR5_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR5_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR5_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR5_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR5_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR5_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR5_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR5_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR5_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR5_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR5_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR5_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR5_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR5_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR5_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR5_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR5_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR5_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR5_1_SLOT_CNTL
+#define BIFPLR5_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR5_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR5_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR5_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR5_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR5_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR5_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR5_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR5_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR5_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR5_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR5_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR5_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR5_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR5_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR5_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR5_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR5_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR5_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR5_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR5_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR5_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR5_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR5_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR5_1_SLOT_STATUS
+#define BIFPLR5_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR5_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR5_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR5_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR5_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR5_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR5_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR5_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR5_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR5_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR5_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR5_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR5_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR5_1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR5_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR5_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR5_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR5_1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR5_1_ROOT_CNTL
+#define BIFPLR5_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR5_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR5_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR5_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR5_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR5_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR5_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR5_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR5_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR5_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR5_1_ROOT_CAP
+#define BIFPLR5_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR5_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR5_1_ROOT_STATUS
+#define BIFPLR5_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR5_1_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR5_1_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR5_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR5_1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR5_1_DEVICE_CAP2
+#define BIFPLR5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR5_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR5_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR5_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR5_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIFPLR5_1_DEVICE_CNTL2
+#define BIFPLR5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR5_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR5_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR5_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR5_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR5_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR5_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR5_1_DEVICE_STATUS2
+#define BIFPLR5_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR5_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR5_1_LINK_CAP2
+#define BIFPLR5_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR5_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR5_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIFPLR5_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR5_1_LINK_CAP2__RESERVED__SHIFT 0x13
+#define BIFPLR5_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR5_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR5_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L
+#define BIFPLR5_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L
+#define BIFPLR5_1_LINK_CAP2__RESERVED_MASK 0xFFF80000L
+//BIFPLR5_1_LINK_CNTL2
+#define BIFPLR5_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR5_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR5_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR5_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR5_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR5_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR5_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR5_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR5_1_LINK_STATUS2
+#define BIFPLR5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIFPLR5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIFPLR5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIFPLR5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIFPLR5_1_SLOT_CAP2
+#define BIFPLR5_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR5_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR5_1_SLOT_CNTL2
+#define BIFPLR5_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR5_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR5_1_SLOT_STATUS2
+#define BIFPLR5_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR5_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR5_1_MSI_CAP_LIST
+#define BIFPLR5_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR5_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR5_1_MSI_MSG_CNTL
+#define BIFPLR5_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR5_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR5_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR5_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR5_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR5_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR5_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR5_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR5_1_MSI_MSG_ADDR_LO
+#define BIFPLR5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR5_1_MSI_MSG_ADDR_HI
+#define BIFPLR5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR5_1_MSI_MSG_DATA
+#define BIFPLR5_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR5_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIFPLR5_1_MSI_MSG_DATA_64
+#define BIFPLR5_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR5_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR5_1_SSID_CAP_LIST
+#define BIFPLR5_1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR5_1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR5_1_SSID_CAP
+#define BIFPLR5_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR5_1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR5_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR5_1_MSI_MAP_CAP_LIST
+#define BIFPLR5_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR5_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR5_1_MSI_MAP_CAP
+#define BIFPLR5_1_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR5_1_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR5_1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR5_1_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR5_1_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR5_1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR5_1_MSI_MAP_ADDR_LO
+#define BIFPLR5_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define BIFPLR5_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L
+//BIFPLR5_1_MSI_MAP_ADDR_HI
+#define BIFPLR5_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define BIFPLR5_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR5_1_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_1_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR5_1_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR5_1_PCIE_PORT_VC_CNTL
+#define BIFPLR5_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR5_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR5_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR5_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR5_1_PCIE_PORT_VC_STATUS
+#define BIFPLR5_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR5_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR5_1_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR5_1_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR5_1_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR5_1_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_1_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR5_1_PCIE_UNCORR_ERR_MASK
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR5_1_PCIE_CORR_ERR_STATUS
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR5_1_PCIE_CORR_ERR_MASK
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIFPLR5_1_PCIE_HDR_LOG0
+#define BIFPLR5_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_HDR_LOG1
+#define BIFPLR5_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_HDR_LOG2
+#define BIFPLR5_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_HDR_LOG3
+#define BIFPLR5_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_ROOT_ERR_CMD
+#define BIFPLR5_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR5_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR5_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR5_1_PCIE_ROOT_ERR_STATUS
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR5_1_PCIE_ERR_SRC_ID
+#define BIFPLR5_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR5_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR5_1_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_1_PCIE_LINK_CNTL3
+#define BIFPLR5_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR5_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define BIFPLR5_1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10
+#define BIFPLR5_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+#define BIFPLR5_1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L
+//BIFPLR5_1_PCIE_LANE_ERROR_STATUS
+#define BIFPLR5_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIFPLR5_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIFPLR5_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_1_PCIE_ACS_CAP
+#define BIFPLR5_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR5_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR5_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR5_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR5_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR5_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR5_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR5_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR5_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR5_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR5_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR5_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR5_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR5_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR5_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR5_1_PCIE_ACS_CNTL
+#define BIFPLR5_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR5_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR5_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR5_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR5_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR5_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR5_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR5_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR5_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR5_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR5_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR5_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR5_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR5_1_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_1_PCIE_MC_CAP
+#define BIFPLR5_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR5_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR5_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR5_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR5_1_PCIE_MC_CNTL
+#define BIFPLR5_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR5_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR5_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR5_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR5_1_PCIE_MC_ADDR0
+#define BIFPLR5_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR5_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR5_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR5_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR5_1_PCIE_MC_ADDR1
+#define BIFPLR5_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR5_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_MC_RCV0
+#define BIFPLR5_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR5_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_MC_RCV1
+#define BIFPLR5_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR5_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_MC_BLOCK_ALL0
+#define BIFPLR5_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR5_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_MC_BLOCK_ALL1
+#define BIFPLR5_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR5_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR5_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR5_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR5_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR5_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR5_1_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR5_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR5_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_1_PCIE_L1_PM_SUB_CAP
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR5_1_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR5_1_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_1_PCIE_DPC_CAP_LIST
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR5_1_PCIE_DPC_CNTL
+#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR5_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR5_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR5_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR5_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR5_1_PCIE_DPC_STATUS
+#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR5_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR5_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR5_1_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR5_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR5_1_PCIE_RP_PIO_STATUS
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR5_1_PCIE_RP_PIO_MASK
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR5_1_PCIE_RP_PIO_SEVERITY
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR5_1_PCIE_RP_PIO_SYSERROR
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR5_1_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR5_1_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_RP_PIO_IMPSPEC_LOG
+#define BIFPLR5_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_ESM_CAP_LIST
+#define BIFPLR5_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_1_PCIE_ESM_HEADER_1
+#define BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR5_1_PCIE_ESM_HEADER_2
+#define BIFPLR5_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR5_1_PCIE_ESM_STATUS
+#define BIFPLR5_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR5_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR5_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR5_1_PCIE_ESM_CTRL
+#define BIFPLR5_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8
+#define BIFPLR5_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR5_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL
+#define BIFPLR5_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L
+#define BIFPLR5_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR5_1_PCIE_ESM_CAP_1
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR5_1_PCIE_ESM_CAP_2
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR5_1_PCIE_ESM_CAP_3
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR5_1_PCIE_ESM_CAP_4
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR5_1_PCIE_ESM_CAP_5
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR5_1_PCIE_ESM_CAP_6
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR5_1_PCIE_ESM_CAP_7
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+
+
+// addressBlock: nbio_pcie0_bifplr6_cfgdecp
+//BIFPLR6_1_VENDOR_ID
+#define BIFPLR6_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR6_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR6_1_DEVICE_ID
+#define BIFPLR6_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR6_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR6_1_COMMAND
+#define BIFPLR6_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR6_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR6_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR6_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR6_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR6_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR6_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR6_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR6_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR6_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR6_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR6_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR6_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR6_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR6_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR6_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR6_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR6_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR6_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR6_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR6_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR6_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR6_1_STATUS
+#define BIFPLR6_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR6_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR6_1_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR6_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR6_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR6_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR6_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR6_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR6_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR6_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR6_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR6_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR6_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR6_1_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR6_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR6_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR6_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR6_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR6_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR6_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR6_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR6_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR6_1_REVISION_ID
+#define BIFPLR6_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR6_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR6_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR6_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR6_1_PROG_INTERFACE
+#define BIFPLR6_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR6_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR6_1_SUB_CLASS
+#define BIFPLR6_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR6_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR6_1_BASE_CLASS
+#define BIFPLR6_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR6_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR6_1_CACHE_LINE
+#define BIFPLR6_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR6_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR6_1_LATENCY
+#define BIFPLR6_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR6_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR6_1_HEADER
+#define BIFPLR6_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR6_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR6_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR6_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR6_1_BIST
+#define BIFPLR6_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR6_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR6_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR6_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR6_1_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR6_1_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR6_1_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR6_1_IO_BASE_LIMIT
+#define BIFPLR6_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR6_1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR6_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR6_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR6_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR6_1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR6_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR6_1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR6_1_SECONDARY_STATUS
+#define BIFPLR6_1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR6_1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR6_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR6_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR6_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR6_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR6_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR6_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR6_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR6_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR6_1_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR6_1_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR6_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR6_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR6_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR6_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR6_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR6_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR6_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR6_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR6_1_MEM_BASE_LIMIT
+#define BIFPLR6_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR6_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR6_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR6_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR6_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR6_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR6_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR6_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR6_1_PREF_BASE_LIMIT
+#define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR6_1_PREF_BASE_UPPER
+#define BIFPLR6_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR6_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PREF_LIMIT_UPPER
+#define BIFPLR6_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR6_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR6_1_IO_BASE_LIMIT_HI
+#define BIFPLR6_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR6_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR6_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR6_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR6_1_CAP_PTR
+#define BIFPLR6_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR6_1_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIFPLR6_1_INTERRUPT_LINE
+#define BIFPLR6_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR6_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR6_1_INTERRUPT_PIN
+#define BIFPLR6_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR6_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR6_1_IRQ_BRIDGE_CNTL
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+//BIFPLR6_1_EXT_BRIDGE_CNTL
+#define BIFPLR6_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR6_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR6_1_PMI_CAP_LIST
+#define BIFPLR6_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR6_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR6_1_PMI_CAP
+#define BIFPLR6_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR6_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR6_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR6_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR6_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR6_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR6_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR6_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR6_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR6_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR6_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR6_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR6_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR6_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR6_1_PMI_STATUS_CNTL
+#define BIFPLR6_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR6_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR6_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR6_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR6_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR6_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR6_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR6_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR6_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR6_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR6_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR6_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR6_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR6_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR6_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR6_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR6_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR6_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR6_1_PCIE_CAP_LIST
+#define BIFPLR6_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR6_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR6_1_PCIE_CAP
+#define BIFPLR6_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR6_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR6_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR6_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR6_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR6_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR6_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR6_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR6_1_DEVICE_CAP
+#define BIFPLR6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR6_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR6_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR6_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR6_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR6_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR6_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR6_1_DEVICE_CNTL
+#define BIFPLR6_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR6_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR6_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR6_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR6_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR6_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR6_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR6_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR6_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR6_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR6_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR6_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR6_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR6_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR6_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR6_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR6_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR6_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR6_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR6_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR6_1_DEVICE_STATUS
+#define BIFPLR6_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR6_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR6_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR6_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR6_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR6_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR6_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR6_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR6_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR6_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR6_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR6_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIFPLR6_1_LINK_CAP
+#define BIFPLR6_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR6_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR6_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR6_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR6_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR6_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR6_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR6_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR6_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR6_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR6_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR6_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR6_1_LINK_CNTL
+#define BIFPLR6_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR6_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR6_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR6_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR6_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR6_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR6_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR6_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR6_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR6_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR6_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR6_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIFPLR6_1_LINK_STATUS
+#define BIFPLR6_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR6_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR6_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR6_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR6_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR6_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR6_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR6_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR6_1_SLOT_CAP
+#define BIFPLR6_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR6_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR6_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR6_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR6_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR6_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR6_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR6_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR6_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR6_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR6_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR6_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR6_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR6_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR6_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR6_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR6_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR6_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR6_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR6_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR6_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR6_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR6_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR6_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR6_1_SLOT_CNTL
+#define BIFPLR6_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR6_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR6_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR6_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR6_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR6_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR6_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR6_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR6_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR6_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR6_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR6_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR6_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR6_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR6_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR6_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR6_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR6_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR6_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR6_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR6_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR6_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR6_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR6_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR6_1_SLOT_STATUS
+#define BIFPLR6_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR6_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR6_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR6_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR6_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR6_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR6_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR6_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR6_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR6_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR6_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR6_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR6_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR6_1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR6_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR6_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR6_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR6_1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR6_1_ROOT_CNTL
+#define BIFPLR6_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR6_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR6_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR6_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR6_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR6_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR6_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR6_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR6_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR6_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR6_1_ROOT_CAP
+#define BIFPLR6_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR6_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR6_1_ROOT_STATUS
+#define BIFPLR6_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR6_1_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR6_1_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR6_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR6_1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR6_1_DEVICE_CAP2
+#define BIFPLR6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR6_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR6_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR6_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR6_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIFPLR6_1_DEVICE_CNTL2
+#define BIFPLR6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR6_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR6_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR6_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR6_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR6_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR6_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR6_1_DEVICE_STATUS2
+#define BIFPLR6_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR6_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR6_1_LINK_CAP2
+#define BIFPLR6_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR6_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR6_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIFPLR6_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR6_1_LINK_CAP2__RESERVED__SHIFT 0x13
+#define BIFPLR6_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR6_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR6_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L
+#define BIFPLR6_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L
+#define BIFPLR6_1_LINK_CAP2__RESERVED_MASK 0xFFF80000L
+//BIFPLR6_1_LINK_CNTL2
+#define BIFPLR6_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR6_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR6_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR6_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR6_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR6_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR6_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR6_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR6_1_LINK_STATUS2
+#define BIFPLR6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIFPLR6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIFPLR6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIFPLR6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIFPLR6_1_SLOT_CAP2
+#define BIFPLR6_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR6_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR6_1_SLOT_CNTL2
+#define BIFPLR6_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR6_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR6_1_SLOT_STATUS2
+#define BIFPLR6_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR6_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR6_1_MSI_CAP_LIST
+#define BIFPLR6_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR6_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR6_1_MSI_MSG_CNTL
+#define BIFPLR6_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR6_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR6_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR6_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR6_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR6_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR6_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR6_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR6_1_MSI_MSG_ADDR_LO
+#define BIFPLR6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR6_1_MSI_MSG_ADDR_HI
+#define BIFPLR6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR6_1_MSI_MSG_DATA
+#define BIFPLR6_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR6_1_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIFPLR6_1_MSI_MSG_DATA_64
+#define BIFPLR6_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR6_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR6_1_SSID_CAP_LIST
+#define BIFPLR6_1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR6_1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR6_1_SSID_CAP
+#define BIFPLR6_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR6_1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR6_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR6_1_MSI_MAP_CAP_LIST
+#define BIFPLR6_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR6_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR6_1_MSI_MAP_CAP
+#define BIFPLR6_1_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR6_1_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR6_1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR6_1_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR6_1_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR6_1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR6_1_MSI_MAP_ADDR_LO
+#define BIFPLR6_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define BIFPLR6_1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L
+//BIFPLR6_1_MSI_MAP_ADDR_HI
+#define BIFPLR6_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define BIFPLR6_1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR6_1_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_1_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR6_1_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR6_1_PCIE_PORT_VC_CNTL
+#define BIFPLR6_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR6_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR6_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR6_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR6_1_PCIE_PORT_VC_STATUS
+#define BIFPLR6_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR6_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR6_1_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR6_1_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR6_1_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR6_1_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_1_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR6_1_PCIE_UNCORR_ERR_MASK
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR6_1_PCIE_CORR_ERR_STATUS
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR6_1_PCIE_CORR_ERR_MASK
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIFPLR6_1_PCIE_HDR_LOG0
+#define BIFPLR6_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_HDR_LOG1
+#define BIFPLR6_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_HDR_LOG2
+#define BIFPLR6_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_HDR_LOG3
+#define BIFPLR6_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_ROOT_ERR_CMD
+#define BIFPLR6_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR6_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR6_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR6_1_PCIE_ROOT_ERR_STATUS
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR6_1_PCIE_ERR_SRC_ID
+#define BIFPLR6_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR6_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR6_1_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_1_PCIE_LINK_CNTL3
+#define BIFPLR6_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR6_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define BIFPLR6_1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10
+#define BIFPLR6_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+#define BIFPLR6_1_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L
+//BIFPLR6_1_PCIE_LANE_ERROR_STATUS
+#define BIFPLR6_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIFPLR6_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIFPLR6_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_1_PCIE_ACS_CAP
+#define BIFPLR6_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR6_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR6_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR6_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR6_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR6_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR6_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR6_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR6_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR6_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR6_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR6_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR6_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR6_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR6_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR6_1_PCIE_ACS_CNTL
+#define BIFPLR6_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR6_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR6_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR6_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR6_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR6_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR6_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR6_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR6_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR6_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR6_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR6_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR6_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR6_1_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_1_PCIE_MC_CAP
+#define BIFPLR6_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR6_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR6_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR6_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR6_1_PCIE_MC_CNTL
+#define BIFPLR6_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR6_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR6_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR6_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR6_1_PCIE_MC_ADDR0
+#define BIFPLR6_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR6_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR6_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR6_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR6_1_PCIE_MC_ADDR1
+#define BIFPLR6_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR6_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_MC_RCV0
+#define BIFPLR6_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR6_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_MC_RCV1
+#define BIFPLR6_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR6_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_MC_BLOCK_ALL0
+#define BIFPLR6_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR6_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_MC_BLOCK_ALL1
+#define BIFPLR6_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR6_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR6_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR6_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR6_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR6_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR6_1_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR6_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR6_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_1_PCIE_L1_PM_SUB_CAP
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR6_1_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR6_1_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_1_PCIE_DPC_CAP_LIST
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR6_1_PCIE_DPC_CNTL
+#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR6_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR6_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR6_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR6_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR6_1_PCIE_DPC_STATUS
+#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR6_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR6_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR6_1_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR6_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR6_1_PCIE_RP_PIO_STATUS
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR6_1_PCIE_RP_PIO_MASK
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR6_1_PCIE_RP_PIO_SEVERITY
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR6_1_PCIE_RP_PIO_SYSERROR
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR6_1_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR6_1_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_RP_PIO_IMPSPEC_LOG
+#define BIFPLR6_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_1_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_ESM_CAP_LIST
+#define BIFPLR6_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_1_PCIE_ESM_HEADER_1
+#define BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR6_1_PCIE_ESM_HEADER_2
+#define BIFPLR6_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR6_1_PCIE_ESM_STATUS
+#define BIFPLR6_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR6_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR6_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR6_1_PCIE_ESM_CTRL
+#define BIFPLR6_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8
+#define BIFPLR6_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR6_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL
+#define BIFPLR6_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L
+#define BIFPLR6_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR6_1_PCIE_ESM_CAP_1
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR6_1_PCIE_ESM_CAP_2
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR6_1_PCIE_ESM_CAP_3
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR6_1_PCIE_ESM_CAP_4
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR6_1_PCIE_ESM_CAP_5
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR6_1_PCIE_ESM_CAP_6
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR6_1_PCIE_ESM_CAP_7
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+
+
+// addressBlock: nbio_pcie0_bifp0_pciedir_p
+//BIFP0_PCIEP_RESERVED
+#define BIFP0_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define BIFP0_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL
+//BIFP0_PCIEP_SCRATCH
+#define BIFP0_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
+#define BIFP0_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xFFFFFFFFL
+//BIFP0_PCIEP_PORT_CNTL
+#define BIFP0_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
+#define BIFP0_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
+#define BIFP0_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
+#define BIFP0_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
+#define BIFP0_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
+#define BIFP0_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
+#define BIFP0_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
+#define BIFP0_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
+#define BIFP0_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
+#define BIFP0_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT 0x18
+#define BIFP0_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L
+#define BIFP0_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L
+#define BIFP0_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L
+#define BIFP0_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L
+#define BIFP0_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L
+#define BIFP0_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L
+#define BIFP0_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x00007F00L
+#define BIFP0_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x00030000L
+#define BIFP0_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x001C0000L
+#define BIFP0_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK 0x03000000L
+//BIFP0_PCIE_TX_CNTL
+#define BIFP0_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define BIFP0_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define BIFP0_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
+#define BIFP0_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
+#define BIFP0_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
+#define BIFP0_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
+#define BIFP0_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
+#define BIFP0_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
+#define BIFP0_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define BIFP0_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define BIFP0_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L
+#define BIFP0_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L
+#define BIFP0_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L
+#define BIFP0_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L
+#define BIFP0_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L
+#define BIFP0_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L
+//BIFP0_PCIE_TX_REQUESTER_ID
+#define BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//BIFP0_PCIE_TX_VENDOR_SPECIFIC
+#define BIFP0_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
+#define BIFP0_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00FFFFFFL
+//BIFP0_PCIE_TX_REQUEST_NUM_CNTL
+#define BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
+#define BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
+#define BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
+#define BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3F000000L
+#define BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L
+#define BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L
+//BIFP0_PCIE_TX_SEQ
+#define BIFP0_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
+#define BIFP0_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
+#define BIFP0_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000FFFL
+#define BIFP0_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0FFF0000L
+//BIFP0_PCIE_TX_REPLAY
+#define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
+#define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
+#define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
+#define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L
+#define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L
+#define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xFFFF0000L
+//BIFP0_PCIE_TX_ACK_LATENCY_LIMIT
+#define BIFP0_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
+#define BIFP0_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
+#define BIFP0_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000FFFL
+#define BIFP0_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L
+//BIFP0_PCIE_TX_CREDITS_ADVT_P
+#define BIFP0_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
+#define BIFP0_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
+#define BIFP0_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00000FFFL
+#define BIFP0_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x00FF0000L
+//BIFP0_PCIE_TX_CREDITS_ADVT_NP
+#define BIFP0_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
+#define BIFP0_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
+#define BIFP0_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00000FFFL
+#define BIFP0_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x00FF0000L
+//BIFP0_PCIE_TX_CREDITS_ADVT_CPL
+#define BIFP0_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
+#define BIFP0_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
+#define BIFP0_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00000FFFL
+#define BIFP0_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x00FF0000L
+//BIFP0_PCIE_TX_CREDITS_INIT_P
+#define BIFP0_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
+#define BIFP0_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
+#define BIFP0_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000FFFL
+#define BIFP0_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00FF0000L
+//BIFP0_PCIE_TX_CREDITS_INIT_NP
+#define BIFP0_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
+#define BIFP0_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
+#define BIFP0_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000FFFL
+#define BIFP0_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00FF0000L
+//BIFP0_PCIE_TX_CREDITS_INIT_CPL
+#define BIFP0_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
+#define BIFP0_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
+#define BIFP0_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000FFFL
+#define BIFP0_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00FF0000L
+//BIFP0_PCIE_TX_CREDITS_STATUS
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L
+//BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L
+//BIFP0_PCIE_P_PORT_LANE_STATUS
+#define BIFP0_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
+#define BIFP0_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
+#define BIFP0_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L
+#define BIFP0_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007EL
+//BIFP0_PCIE_FC_P
+#define BIFP0_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
+#define BIFP0_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
+#define BIFP0_PCIE_FC_P__PD_CREDITS_MASK 0x000000FFL
+#define BIFP0_PCIE_FC_P__PH_CREDITS_MASK 0x0000FF00L
+//BIFP0_PCIE_FC_NP
+#define BIFP0_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
+#define BIFP0_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
+#define BIFP0_PCIE_FC_NP__NPD_CREDITS_MASK 0x000000FFL
+#define BIFP0_PCIE_FC_NP__NPH_CREDITS_MASK 0x0000FF00L
+//BIFP0_PCIE_FC_CPL
+#define BIFP0_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
+#define BIFP0_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
+#define BIFP0_PCIE_FC_CPL__CPLD_CREDITS_MASK 0x000000FFL
+#define BIFP0_PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0000FF00L
+//BIFP0_PCIE_ERR_CNTL
+#define BIFP0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define BIFP0_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
+#define BIFP0_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
+#define BIFP0_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
+#define BIFP0_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
+#define BIFP0_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
+#define BIFP0_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
+#define BIFP0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define BIFP0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define BIFP0_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
+#define BIFP0_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
+#define BIFP0_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
+#define BIFP0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define BIFP0_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define BIFP0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define BIFP0_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L
+#define BIFP0_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x00000004L
+#define BIFP0_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L
+#define BIFP0_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L
+#define BIFP0_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L
+#define BIFP0_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L
+#define BIFP0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define BIFP0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define BIFP0_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L
+#define BIFP0_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L
+#define BIFP0_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L
+#define BIFP0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define BIFP0_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+//BIFP0_PCIE_RX_CNTL
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
+#define BIFP0_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
+#define BIFP0_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
+#define BIFP0_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
+#define BIFP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
+#define BIFP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
+#define BIFP0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define BIFP0_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define BIFP0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L
+#define BIFP0_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L
+#define BIFP0_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x00004000L
+#define BIFP0_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L
+#define BIFP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L
+#define BIFP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L
+#define BIFP0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define BIFP0_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+#define BIFP0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+//BIFP0_PCIE_RX_EXPECTED_SEQNUM
+#define BIFP0_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
+#define BIFP0_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000FFFL
+//BIFP0_PCIE_RX_VENDOR_SPECIFIC
+#define BIFP0_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
+#define BIFP0_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
+#define BIFP0_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00FFFFFFL
+#define BIFP0_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L
+//BIFP0_PCIE_RX_CNTL3
+#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
+#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
+#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
+#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
+#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
+#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L
+#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L
+#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L
+#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L
+#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L
+//BIFP0_PCIE_RX_CREDITS_ALLOCATED_P
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000FFFL
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00FF0000L
+//BIFP0_PCIE_RX_CREDITS_ALLOCATED_NP
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000FFFL
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00FF0000L
+//BIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000FFFL
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00FF0000L
+//BIFP0_PCIEP_ERROR_INJECT_PHYSICAL
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x00000003L
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0x0000000CL
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x00000030L
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0x000000C0L
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x00000300L
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0x00000C00L
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x00003000L
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0x0000C000L
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x00030000L
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0x000C0000L
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x00300000L
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0x00C00000L
+//BIFP0_PCIEP_ERROR_INJECT_TRANSACTION
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x00000003L
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0x0000000CL
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x00000030L
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0x000000C0L
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x00000300L
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0x00000C00L
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x00003000L
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0x0000C000L
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x00030000L
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0x000C0000L
+//BIFP0_PCIEP_NAK_COUNTER
+#define BIFP0_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT 0x0
+#define BIFP0_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT 0x10
+#define BIFP0_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK 0x0000FFFFL
+#define BIFP0_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK 0xFFFF0000L
+//BIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS__SHIFT 0x0
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK__SHIFT 0x8
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK__SHIFT 0x9
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS_MASK 0x00000001L
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK_MASK 0x00000100L
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK_MASK 0x00000200L
+//BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT 0x0
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT 0xa
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT 0xf
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT 0x1a
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT 0x1f
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK 0x000003FFL
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK 0x00001C00L
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK 0x00008000L
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK 0x1C000000L
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK 0x80000000L
+//BIFP0_PCIE_LC_CNTL
+#define BIFP0_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
+#define BIFP0_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
+#define BIFP0_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
+#define BIFP0_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
+#define BIFP0_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
+#define BIFP0_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
+#define BIFP0_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
+#define BIFP0_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
+#define BIFP0_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
+#define BIFP0_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
+#define BIFP0_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
+#define BIFP0_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
+#define BIFP0_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
+#define BIFP0_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
+#define BIFP0_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
+#define BIFP0_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
+#define BIFP0_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
+#define BIFP0_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
+#define BIFP0_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
+#define BIFP0_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
+#define BIFP0_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L
+#define BIFP0_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L
+#define BIFP0_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L
+#define BIFP0_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000F0L
+#define BIFP0_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000F00L
+#define BIFP0_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000F000L
+#define BIFP0_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L
+#define BIFP0_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L
+#define BIFP0_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000C0000L
+#define BIFP0_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L
+#define BIFP0_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L
+#define BIFP0_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L
+#define BIFP0_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L
+#define BIFP0_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L
+#define BIFP0_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L
+#define BIFP0_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L
+#define BIFP0_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L
+#define BIFP0_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L
+#define BIFP0_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L
+#define BIFP0_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L
+//BIFP0_PCIE_LC_TRAINING_CNTL
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000FL
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x00004000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x00008000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00C00000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xC0000000L
+//BIFP0_PCIE_LC_LINK_WIDTH_CNTL
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT 0x1e
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT 0x1f
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x00010000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x01000000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x02000000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x04000000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x08000000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK 0x40000000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK 0x80000000L
+//BIFP0_PCIE_LC_N_FTS_CNTL
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT 0xf
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000FFL
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK 0x00008000L
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00FF0000L
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xFF000000L
+//BIFP0_PCIE_LC_SPEED_CNTL
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000004L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000018L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000020L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000040L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000080L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000100L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000200L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00000C00L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00001000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x00006000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00008000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00010000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00020000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00040000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00080000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00100000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00200000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x00400000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x00800000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x03000000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x04000000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x08000000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000L
+//BIFP0_PCIE_LC_STATE0
+#define BIFP0_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
+#define BIFP0_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
+#define BIFP0_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
+#define BIFP0_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
+#define BIFP0_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003FL
+#define BIFP0_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003F00L
+#define BIFP0_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003F0000L
+#define BIFP0_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3F000000L
+//BIFP0_PCIE_LC_STATE1
+#define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
+#define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
+#define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
+#define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
+#define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003FL
+#define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003F00L
+#define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003F0000L
+#define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3F000000L
+//BIFP0_PCIE_LC_STATE2
+#define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
+#define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
+#define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
+#define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
+#define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003FL
+#define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003F00L
+#define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003F0000L
+#define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3F000000L
+//BIFP0_PCIE_LC_STATE3
+#define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
+#define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
+#define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
+#define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
+#define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003FL
+#define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003F00L
+#define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003F0000L
+#define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3F000000L
+//BIFP0_PCIE_LC_STATE4
+#define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
+#define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
+#define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
+#define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
+#define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003FL
+#define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003F00L
+#define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003F0000L
+#define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3F000000L
+//BIFP0_PCIE_LC_STATE5
+#define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
+#define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
+#define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
+#define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
+#define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003FL
+#define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003F00L
+#define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003F0000L
+#define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3F000000L
+//BIFP0_PCIE_LINK_MANAGEMENT_CNTL2
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT 0x0
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT 0x1
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT 0x2
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT 0x3
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT 0x4
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT 0x7
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT 0xb
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT 0xf
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT 0x13
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK 0x00000001L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK 0x00000002L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK 0x00000004L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK 0x00000008L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK 0x00000070L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK 0x00000780L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK 0x00007800L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK 0x00078000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK 0x00780000L
+//BIFP0_PCIE_LC_CNTL2
+#define BIFP0_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
+#define BIFP0_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
+#define BIFP0_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
+#define BIFP0_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
+#define BIFP0_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
+#define BIFP0_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
+#define BIFP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
+#define BIFP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
+#define BIFP0_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
+#define BIFP0_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
+#define BIFP0_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
+#define BIFP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
+#define BIFP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
+#define BIFP0_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
+#define BIFP0_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
+#define BIFP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
+#define BIFP0_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
+#define BIFP0_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
+#define BIFP0_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
+#define BIFP0_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
+#define BIFP0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define BIFP0_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
+#define BIFP0_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
+#define BIFP0_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
+#define BIFP0_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003FL
+#define BIFP0_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L
+#define BIFP0_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L
+#define BIFP0_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L
+#define BIFP0_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L
+#define BIFP0_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L
+#define BIFP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L
+#define BIFP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L
+#define BIFP0_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L
+#define BIFP0_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000C000L
+#define BIFP0_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L
+#define BIFP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L
+#define BIFP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L
+#define BIFP0_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x00080000L
+#define BIFP0_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L
+#define BIFP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L
+#define BIFP0_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L
+#define BIFP0_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L
+#define BIFP0_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L
+#define BIFP0_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L
+#define BIFP0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+#define BIFP0_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L
+#define BIFP0_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L
+#define BIFP0_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L
+//BIFP0_PCIE_LC_BW_CHANGE_CNTL
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT 0xb
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK 0x00000800L
+//BIFP0_PCIE_LC_CDR_CNTL
+#define BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
+#define BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
+#define BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
+#define BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000FFFL
+#define BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00FFF000L
+#define BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L
+//BIFP0_PCIE_LC_LANE_CNTL
+#define BIFP0_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
+#define BIFP0_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
+#define BIFP0_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000FFFFL
+#define BIFP0_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xFFFF0000L
+//BIFP0_PCIE_LC_CNTL3
+#define BIFP0_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
+#define BIFP0_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
+#define BIFP0_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
+#define BIFP0_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
+#define BIFP0_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
+#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
+#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
+#define BIFP0_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
+#define BIFP0_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
+#define BIFP0_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
+#define BIFP0_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
+#define BIFP0_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
+#define BIFP0_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
+#define BIFP0_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
+#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
+#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
+#define BIFP0_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
+#define BIFP0_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
+#define BIFP0_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
+#define BIFP0_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
+#define BIFP0_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
+#define BIFP0_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
+#define BIFP0_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
+#define BIFP0_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L
+#define BIFP0_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L
+#define BIFP0_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L
+#define BIFP0_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L
+#define BIFP0_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L
+#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000C0L
+#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L
+#define BIFP0_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L
+#define BIFP0_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L
+#define BIFP0_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L
+#define BIFP0_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x00003000L
+#define BIFP0_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0x0000C000L
+#define BIFP0_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x00010000L
+#define BIFP0_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L
+#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L
+#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L
+#define BIFP0_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L
+#define BIFP0_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x00400000L
+#define BIFP0_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L
+#define BIFP0_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L
+#define BIFP0_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3C000000L
+#define BIFP0_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L
+#define BIFP0_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000L
+//BIFP0_PCIE_LC_CNTL4
+#define BIFP0_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
+#define BIFP0_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
+#define BIFP0_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
+#define BIFP0_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
+#define BIFP0_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
+#define BIFP0_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
+#define BIFP0_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
+#define BIFP0_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
+#define BIFP0_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
+#define BIFP0_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
+#define BIFP0_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
+#define BIFP0_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
+#define BIFP0_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
+#define BIFP0_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
+#define BIFP0_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
+#define BIFP0_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
+#define BIFP0_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
+#define BIFP0_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
+#define BIFP0_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT 0x17
+#define BIFP0_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
+#define BIFP0_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
+#define BIFP0_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
+#define BIFP0_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L
+#define BIFP0_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x00000004L
+#define BIFP0_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x00000008L
+#define BIFP0_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x00000010L
+#define BIFP0_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x00000020L
+#define BIFP0_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L
+#define BIFP0_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L
+#define BIFP0_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x00000300L
+#define BIFP0_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L
+#define BIFP0_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x00000800L
+#define BIFP0_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x00001000L
+#define BIFP0_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L
+#define BIFP0_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L
+#define BIFP0_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x00008000L
+#define BIFP0_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x00010000L
+#define BIFP0_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x00020000L
+#define BIFP0_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x003C0000L
+#define BIFP0_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L
+#define BIFP0_PCIE_LC_CNTL4__LC_TX_SWING_MASK 0x00800000L
+#define BIFP0_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L
+#define BIFP0_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L
+#define BIFP0_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xFC000000L
+//BIFP0_PCIE_LC_CNTL5
+#define BIFP0_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
+#define BIFP0_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
+#define BIFP0_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
+#define BIFP0_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
+#define BIFP0_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
+#define BIFP0_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT 0x19
+#define BIFP0_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT 0x1a
+#define BIFP0_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT 0x1b
+#define BIFP0_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT 0x1c
+#define BIFP0_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT 0x1d
+#define BIFP0_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x0000003FL
+#define BIFP0_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0x00000FC0L
+#define BIFP0_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x0003F000L
+#define BIFP0_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0x00FC0000L
+#define BIFP0_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x01000000L
+#define BIFP0_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK 0x02000000L
+#define BIFP0_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK 0x04000000L
+#define BIFP0_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK 0x08000000L
+#define BIFP0_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK 0x10000000L
+#define BIFP0_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK 0xE0000000L
+//BIFP0_PCIE_LC_FORCE_COEFF
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x00000001L
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x0000007EL
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x00001F80L
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x0007E000L
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x00080000L
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x00100000L
+//BIFP0_PCIE_LC_BEST_EQ_SETTINGS
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000FL
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003F0L
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000FC00L
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003F0000L
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3FC00000L
+//BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x00000001L
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x0000007EL
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x00001F80L
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x0007E000L
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x01F80000L
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7E000000L
+//BIFP0_PCIE_LC_CNTL6
+#define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
+#define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
+#define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
+#define BIFP0_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT 0x5
+#define BIFP0_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT 0x6
+#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT 0x8
+#define BIFP0_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT 0x9
+#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT 0xd
+#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT 0xe
+#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT 0x10
+#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT 0x12
+#define BIFP0_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT 0x13
+#define BIFP0_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT 0x14
+#define BIFP0_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT 0x15
+#define BIFP0_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT 0x16
+#define BIFP0_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT 0x17
+#define BIFP0_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT 0x18
+#define BIFP0_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT 0x1f
+#define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x00000001L
+#define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x00000004L
+#define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x00000010L
+#define BIFP0_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK 0x00000020L
+#define BIFP0_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK 0x000000C0L
+#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_EN_MASK 0x00000100L
+#define BIFP0_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK 0x00001E00L
+#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK 0x00002000L
+#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK 0x0000C000L
+#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK 0x00030000L
+#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK 0x00040000L
+#define BIFP0_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK 0x00080000L
+#define BIFP0_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK 0x00100000L
+#define BIFP0_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L
+#define BIFP0_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK 0x00400000L
+#define BIFP0_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK 0x00800000L
+#define BIFP0_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK 0x7F000000L
+#define BIFP0_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK 0x80000000L
+//BIFP0_PCIE_LC_CNTL7
+#define BIFP0_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT 0x0
+#define BIFP0_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT 0x1
+#define BIFP0_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT 0x2
+#define BIFP0_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT 0x3
+#define BIFP0_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT 0x4
+#define BIFP0_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT 0x5
+#define BIFP0_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT 0x6
+#define BIFP0_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT 0x7
+#define BIFP0_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT 0x8
+#define BIFP0_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT 0x9
+#define BIFP0_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT 0xa
+#define BIFP0_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT 0xb
+#define BIFP0_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT 0xc
+#define BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT 0xd
+#define BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT 0x15
+#define BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT 0x16
+#define BIFP0_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT 0x17
+#define BIFP0_PCIE_LC_CNTL7__LC_FOM_TIME__SHIFT 0x18
+#define BIFP0_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH__SHIFT 0x1a
+#define BIFP0_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT 0x1b
+#define BIFP0_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT 0x1c
+#define BIFP0_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT 0x1d
+#define BIFP0_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT 0x1e
+#define BIFP0_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT 0x1f
+#define BIFP0_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK 0x00000001L
+#define BIFP0_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK 0x00000002L
+#define BIFP0_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK 0x00000004L
+#define BIFP0_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK 0x00000008L
+#define BIFP0_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK 0x00000010L
+#define BIFP0_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK 0x00000020L
+#define BIFP0_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK 0x00000040L
+#define BIFP0_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK 0x00000080L
+#define BIFP0_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK 0x00000100L
+#define BIFP0_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK 0x00000200L
+#define BIFP0_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK 0x00000400L
+#define BIFP0_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK 0x00000800L
+#define BIFP0_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK 0x00001000L
+#define BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK 0x001FE000L
+#define BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK 0x00200000L
+#define BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK 0x00400000L
+#define BIFP0_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK 0x00800000L
+#define BIFP0_PCIE_LC_CNTL7__LC_FOM_TIME_MASK 0x03000000L
+#define BIFP0_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH_MASK 0x04000000L
+#define BIFP0_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK 0x08000000L
+#define BIFP0_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK 0x10000000L
+#define BIFP0_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK 0x20000000L
+#define BIFP0_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK 0x40000000L
+#define BIFP0_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN_MASK 0x80000000L
+//BIFP0_PCIE_LINK_MANAGEMENT_STATUS
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT 0x0
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x1
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT 0x2
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT 0x3
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT 0x4
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT 0x5
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT 0x6
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT 0x7
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT 0x8
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT 0x9
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT 0xa
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT 0xb
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT 0xc
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT 0xd
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK 0x00000001L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000002L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 0x00000004L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK 0x00000008L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 0x00000010L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 0x00000020L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK 0x00000040L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK 0x00000080L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK 0x00000100L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK 0x00000200L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK 0x00000400L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK 0x00000800L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK 0x00001000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK 0x00002000L
+//BIFP0_PCIE_LINK_MANAGEMENT_MASK
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT 0x0
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x1
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT 0x2
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT 0x3
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x4
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT 0x5
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT 0x6
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT 0x7
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT 0x8
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT 0x9
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT 0xa
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT 0xb
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT 0xc
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT 0xd
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK 0x00000001L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000002L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK 0x00000004L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK 0x00000008L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000010L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK 0x00000020L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK 0x00000040L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK 0x00000080L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK 0x00000100L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK 0x00000200L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK 0x00000400L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK 0x00000800L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK 0x00001000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK 0x00002000L
+//BIFP0_PCIE_LINK_MANAGEMENT_CNTL
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT 0x0
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT 0x3
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT 0x7
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT 0xb
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT 0xc
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT 0xd
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT 0xf
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT 0x11
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT 0x12
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT 0x13
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT 0x17
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT 0x1b
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK 0x00000007L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK 0x00000078L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK 0x00000780L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK 0x00000800L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK 0x00001000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK 0x00006000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK 0x00018000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK 0x00020000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK 0x00040000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK 0x00780000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK 0x07800000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK 0x38000000L
+//BIFP0_PCIEP_STRAP_LC
+#define BIFP0_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
+#define BIFP0_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
+#define BIFP0_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
+#define BIFP0_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
+#define BIFP0_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
+#define BIFP0_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
+#define BIFP0_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
+#define BIFP0_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
+#define BIFP0_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
+#define BIFP0_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
+#define BIFP0_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
+#define BIFP0_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000CL
+#define BIFP0_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000C0L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L
+//BIFP0_PCIEP_STRAP_MISC
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x00000020L
+//BIFP0_PCIE_LC_L1_PM_SUBSTATE
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT 0x0
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT 0x1
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT 0x2
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT 0x3
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT 0x4
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT 0x6
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT 0x8
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT 0x10
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT 0x14
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT 0x17
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK 0x000000C0L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK 0x00001F00L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK 0x00070000L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK 0x00700000L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK 0x03800000L
+//BIFP0_PCIE_LC_L1_PM_SUBSTATE2
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT 0x0
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT 0x8
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK 0x000000FFL
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK 0x00000700L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK 0x03FF0000L
+//BIFP0_PCIE_LC_PORT_ORDER
+#define BIFP0_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT 0x0
+#define BIFP0_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK 0x0000000FL
+//BIFP0_PCIEP_BCH_ECC_CNTL
+#define BIFP0_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
+#define BIFP0_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
+#define BIFP0_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
+#define BIFP0_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x00000001L
+#define BIFP0_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0x0000FF00L
+#define BIFP0_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xFFFF0000L
+//BIFP0_PCIEP_HPGI_PRIVATE
+#define BIFP0_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
+#define BIFP0_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
+#define BIFP0_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x00000008L
+#define BIFP0_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x00000040L
+//BIFP0_PCIEP_HPGI
+#define BIFP0_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
+#define BIFP0_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
+#define BIFP0_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
+#define BIFP0_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
+#define BIFP0_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
+#define BIFP0_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
+#define BIFP0_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
+#define BIFP0_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
+#define BIFP0_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
+#define BIFP0_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
+#define BIFP0_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
+#define BIFP0_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x00000001L
+#define BIFP0_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x00000002L
+#define BIFP0_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x00000004L
+#define BIFP0_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x00000008L
+#define BIFP0_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x00000080L
+#define BIFP0_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x00000100L
+#define BIFP0_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x00000200L
+#define BIFP0_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x00000400L
+#define BIFP0_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x00000800L
+#define BIFP0_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x00008000L
+#define BIFP0_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x00010000L
+//BIFP0_PCIEP_HCNT_DESCRIPTOR
+#define BIFP0_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT 0x0
+#define BIFP0_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT 0x1f
+#define BIFP0_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK 0x0000003FL
+#define BIFP0_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK 0x80000000L
+//BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK
+#define BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT 0x0
+#define BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT 0x10
+#define BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL
+#define BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L
+
+
+// addressBlock: nbio_pcie0_bifp1_pciedir_p
+//BIFP1_PCIEP_RESERVED
+#define BIFP1_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define BIFP1_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL
+//BIFP1_PCIEP_SCRATCH
+#define BIFP1_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
+#define BIFP1_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xFFFFFFFFL
+//BIFP1_PCIEP_PORT_CNTL
+#define BIFP1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
+#define BIFP1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
+#define BIFP1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
+#define BIFP1_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
+#define BIFP1_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
+#define BIFP1_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
+#define BIFP1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
+#define BIFP1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
+#define BIFP1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
+#define BIFP1_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT 0x18
+#define BIFP1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L
+#define BIFP1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L
+#define BIFP1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L
+#define BIFP1_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L
+#define BIFP1_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L
+#define BIFP1_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L
+#define BIFP1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x00007F00L
+#define BIFP1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x00030000L
+#define BIFP1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x001C0000L
+#define BIFP1_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK 0x03000000L
+//BIFP1_PCIE_TX_CNTL
+#define BIFP1_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define BIFP1_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define BIFP1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
+#define BIFP1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
+#define BIFP1_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
+#define BIFP1_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
+#define BIFP1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
+#define BIFP1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
+#define BIFP1_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define BIFP1_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define BIFP1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L
+#define BIFP1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L
+#define BIFP1_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L
+#define BIFP1_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L
+#define BIFP1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L
+#define BIFP1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L
+//BIFP1_PCIE_TX_REQUESTER_ID
+#define BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//BIFP1_PCIE_TX_VENDOR_SPECIFIC
+#define BIFP1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
+#define BIFP1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00FFFFFFL
+//BIFP1_PCIE_TX_REQUEST_NUM_CNTL
+#define BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
+#define BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
+#define BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
+#define BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3F000000L
+#define BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L
+#define BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L
+//BIFP1_PCIE_TX_SEQ
+#define BIFP1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
+#define BIFP1_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
+#define BIFP1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000FFFL
+#define BIFP1_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0FFF0000L
+//BIFP1_PCIE_TX_REPLAY
+#define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
+#define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
+#define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
+#define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L
+#define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L
+#define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xFFFF0000L
+//BIFP1_PCIE_TX_ACK_LATENCY_LIMIT
+#define BIFP1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
+#define BIFP1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
+#define BIFP1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000FFFL
+#define BIFP1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L
+//BIFP1_PCIE_TX_CREDITS_ADVT_P
+#define BIFP1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
+#define BIFP1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
+#define BIFP1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00000FFFL
+#define BIFP1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x00FF0000L
+//BIFP1_PCIE_TX_CREDITS_ADVT_NP
+#define BIFP1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
+#define BIFP1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
+#define BIFP1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00000FFFL
+#define BIFP1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x00FF0000L
+//BIFP1_PCIE_TX_CREDITS_ADVT_CPL
+#define BIFP1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
+#define BIFP1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
+#define BIFP1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00000FFFL
+#define BIFP1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x00FF0000L
+//BIFP1_PCIE_TX_CREDITS_INIT_P
+#define BIFP1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
+#define BIFP1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
+#define BIFP1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000FFFL
+#define BIFP1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00FF0000L
+//BIFP1_PCIE_TX_CREDITS_INIT_NP
+#define BIFP1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
+#define BIFP1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
+#define BIFP1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000FFFL
+#define BIFP1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00FF0000L
+//BIFP1_PCIE_TX_CREDITS_INIT_CPL
+#define BIFP1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
+#define BIFP1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
+#define BIFP1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000FFFL
+#define BIFP1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00FF0000L
+//BIFP1_PCIE_TX_CREDITS_STATUS
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L
+//BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L
+//BIFP1_PCIE_P_PORT_LANE_STATUS
+#define BIFP1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
+#define BIFP1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
+#define BIFP1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L
+#define BIFP1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007EL
+//BIFP1_PCIE_FC_P
+#define BIFP1_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
+#define BIFP1_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
+#define BIFP1_PCIE_FC_P__PD_CREDITS_MASK 0x000000FFL
+#define BIFP1_PCIE_FC_P__PH_CREDITS_MASK 0x0000FF00L
+//BIFP1_PCIE_FC_NP
+#define BIFP1_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
+#define BIFP1_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
+#define BIFP1_PCIE_FC_NP__NPD_CREDITS_MASK 0x000000FFL
+#define BIFP1_PCIE_FC_NP__NPH_CREDITS_MASK 0x0000FF00L
+//BIFP1_PCIE_FC_CPL
+#define BIFP1_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
+#define BIFP1_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
+#define BIFP1_PCIE_FC_CPL__CPLD_CREDITS_MASK 0x000000FFL
+#define BIFP1_PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0000FF00L
+//BIFP1_PCIE_ERR_CNTL
+#define BIFP1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define BIFP1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
+#define BIFP1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
+#define BIFP1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
+#define BIFP1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
+#define BIFP1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
+#define BIFP1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
+#define BIFP1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define BIFP1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define BIFP1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
+#define BIFP1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
+#define BIFP1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
+#define BIFP1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define BIFP1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define BIFP1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define BIFP1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L
+#define BIFP1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x00000004L
+#define BIFP1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L
+#define BIFP1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L
+#define BIFP1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L
+#define BIFP1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L
+#define BIFP1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define BIFP1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define BIFP1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L
+#define BIFP1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L
+#define BIFP1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L
+#define BIFP1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define BIFP1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+//BIFP1_PCIE_RX_CNTL
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
+#define BIFP1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
+#define BIFP1_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
+#define BIFP1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
+#define BIFP1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
+#define BIFP1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
+#define BIFP1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define BIFP1_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define BIFP1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L
+#define BIFP1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L
+#define BIFP1_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x00004000L
+#define BIFP1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L
+#define BIFP1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L
+#define BIFP1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L
+#define BIFP1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define BIFP1_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+#define BIFP1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+//BIFP1_PCIE_RX_EXPECTED_SEQNUM
+#define BIFP1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
+#define BIFP1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000FFFL
+//BIFP1_PCIE_RX_VENDOR_SPECIFIC
+#define BIFP1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
+#define BIFP1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
+#define BIFP1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00FFFFFFL
+#define BIFP1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L
+//BIFP1_PCIE_RX_CNTL3
+#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
+#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
+#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
+#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
+#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
+#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L
+#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L
+#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L
+#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L
+#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L
+//BIFP1_PCIE_RX_CREDITS_ALLOCATED_P
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000FFFL
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00FF0000L
+//BIFP1_PCIE_RX_CREDITS_ALLOCATED_NP
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000FFFL
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00FF0000L
+//BIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000FFFL
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00FF0000L
+//BIFP1_PCIEP_ERROR_INJECT_PHYSICAL
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x00000003L
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0x0000000CL
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x00000030L
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0x000000C0L
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x00000300L
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0x00000C00L
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x00003000L
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0x0000C000L
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x00030000L
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0x000C0000L
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x00300000L
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0x00C00000L
+//BIFP1_PCIEP_ERROR_INJECT_TRANSACTION
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x00000003L
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0x0000000CL
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x00000030L
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0x000000C0L
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x00000300L
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0x00000C00L
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x00003000L
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0x0000C000L
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x00030000L
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0x000C0000L
+//BIFP1_PCIEP_NAK_COUNTER
+#define BIFP1_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT 0x0
+#define BIFP1_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT 0x10
+#define BIFP1_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK 0x0000FFFFL
+#define BIFP1_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK 0xFFFF0000L
+//BIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS__SHIFT 0x0
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK__SHIFT 0x8
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK__SHIFT 0x9
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS_MASK 0x00000001L
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK_MASK 0x00000100L
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK_MASK 0x00000200L
+//BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT 0x0
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT 0xa
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT 0xf
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT 0x1a
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT 0x1f
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK 0x000003FFL
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK 0x00001C00L
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK 0x00008000L
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK 0x1C000000L
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK 0x80000000L
+//BIFP1_PCIE_LC_CNTL
+#define BIFP1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
+#define BIFP1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
+#define BIFP1_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
+#define BIFP1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
+#define BIFP1_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
+#define BIFP1_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
+#define BIFP1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
+#define BIFP1_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
+#define BIFP1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
+#define BIFP1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
+#define BIFP1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
+#define BIFP1_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
+#define BIFP1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
+#define BIFP1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
+#define BIFP1_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
+#define BIFP1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
+#define BIFP1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
+#define BIFP1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
+#define BIFP1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
+#define BIFP1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
+#define BIFP1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L
+#define BIFP1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L
+#define BIFP1_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L
+#define BIFP1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000F0L
+#define BIFP1_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000F00L
+#define BIFP1_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000F000L
+#define BIFP1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L
+#define BIFP1_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L
+#define BIFP1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000C0000L
+#define BIFP1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L
+#define BIFP1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L
+#define BIFP1_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L
+#define BIFP1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L
+#define BIFP1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L
+#define BIFP1_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L
+#define BIFP1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L
+#define BIFP1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L
+#define BIFP1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L
+#define BIFP1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L
+#define BIFP1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L
+//BIFP1_PCIE_LC_TRAINING_CNTL
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000FL
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x00004000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x00008000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00C00000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xC0000000L
+//BIFP1_PCIE_LC_LINK_WIDTH_CNTL
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT 0x1e
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT 0x1f
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x00010000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x01000000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x02000000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x04000000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x08000000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK 0x40000000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK 0x80000000L
+//BIFP1_PCIE_LC_N_FTS_CNTL
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT 0xf
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000FFL
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK 0x00008000L
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00FF0000L
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xFF000000L
+//BIFP1_PCIE_LC_SPEED_CNTL
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000004L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000018L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000020L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000040L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000080L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000100L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000200L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00000C00L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00001000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x00006000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00008000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00010000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00020000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00040000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00080000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00100000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00200000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x00400000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x00800000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x03000000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x04000000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x08000000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000L
+//BIFP1_PCIE_LC_STATE0
+#define BIFP1_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
+#define BIFP1_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
+#define BIFP1_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
+#define BIFP1_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
+#define BIFP1_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003FL
+#define BIFP1_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003F00L
+#define BIFP1_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003F0000L
+#define BIFP1_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3F000000L
+//BIFP1_PCIE_LC_STATE1
+#define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
+#define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
+#define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
+#define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
+#define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003FL
+#define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003F00L
+#define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003F0000L
+#define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3F000000L
+//BIFP1_PCIE_LC_STATE2
+#define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
+#define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
+#define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
+#define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
+#define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003FL
+#define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003F00L
+#define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003F0000L
+#define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3F000000L
+//BIFP1_PCIE_LC_STATE3
+#define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
+#define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
+#define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
+#define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
+#define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003FL
+#define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003F00L
+#define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003F0000L
+#define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3F000000L
+//BIFP1_PCIE_LC_STATE4
+#define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
+#define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
+#define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
+#define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
+#define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003FL
+#define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003F00L
+#define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003F0000L
+#define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3F000000L
+//BIFP1_PCIE_LC_STATE5
+#define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
+#define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
+#define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
+#define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
+#define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003FL
+#define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003F00L
+#define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003F0000L
+#define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3F000000L
+//BIFP1_PCIE_LINK_MANAGEMENT_CNTL2
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT 0x0
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT 0x1
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT 0x2
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT 0x3
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT 0x4
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT 0x7
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT 0xb
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT 0xf
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT 0x13
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK 0x00000001L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK 0x00000002L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK 0x00000004L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK 0x00000008L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK 0x00000070L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK 0x00000780L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK 0x00007800L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK 0x00078000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK 0x00780000L
+//BIFP1_PCIE_LC_CNTL2
+#define BIFP1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
+#define BIFP1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
+#define BIFP1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
+#define BIFP1_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
+#define BIFP1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
+#define BIFP1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
+#define BIFP1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
+#define BIFP1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
+#define BIFP1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
+#define BIFP1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
+#define BIFP1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
+#define BIFP1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
+#define BIFP1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
+#define BIFP1_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
+#define BIFP1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
+#define BIFP1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
+#define BIFP1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
+#define BIFP1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
+#define BIFP1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
+#define BIFP1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
+#define BIFP1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define BIFP1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
+#define BIFP1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
+#define BIFP1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
+#define BIFP1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003FL
+#define BIFP1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L
+#define BIFP1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L
+#define BIFP1_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L
+#define BIFP1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L
+#define BIFP1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L
+#define BIFP1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L
+#define BIFP1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L
+#define BIFP1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L
+#define BIFP1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000C000L
+#define BIFP1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L
+#define BIFP1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L
+#define BIFP1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L
+#define BIFP1_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x00080000L
+#define BIFP1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L
+#define BIFP1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L
+#define BIFP1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L
+#define BIFP1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L
+#define BIFP1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L
+#define BIFP1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L
+#define BIFP1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+#define BIFP1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L
+#define BIFP1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L
+#define BIFP1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L
+//BIFP1_PCIE_LC_BW_CHANGE_CNTL
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT 0xb
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK 0x00000800L
+//BIFP1_PCIE_LC_CDR_CNTL
+#define BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
+#define BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
+#define BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
+#define BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000FFFL
+#define BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00FFF000L
+#define BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L
+//BIFP1_PCIE_LC_LANE_CNTL
+#define BIFP1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
+#define BIFP1_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
+#define BIFP1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000FFFFL
+#define BIFP1_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xFFFF0000L
+//BIFP1_PCIE_LC_CNTL3
+#define BIFP1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
+#define BIFP1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
+#define BIFP1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
+#define BIFP1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
+#define BIFP1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
+#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
+#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
+#define BIFP1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
+#define BIFP1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
+#define BIFP1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
+#define BIFP1_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
+#define BIFP1_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
+#define BIFP1_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
+#define BIFP1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
+#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
+#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
+#define BIFP1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
+#define BIFP1_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
+#define BIFP1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
+#define BIFP1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
+#define BIFP1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
+#define BIFP1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
+#define BIFP1_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
+#define BIFP1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L
+#define BIFP1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L
+#define BIFP1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L
+#define BIFP1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L
+#define BIFP1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L
+#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000C0L
+#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L
+#define BIFP1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L
+#define BIFP1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L
+#define BIFP1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L
+#define BIFP1_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x00003000L
+#define BIFP1_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0x0000C000L
+#define BIFP1_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x00010000L
+#define BIFP1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L
+#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L
+#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L
+#define BIFP1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L
+#define BIFP1_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x00400000L
+#define BIFP1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L
+#define BIFP1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L
+#define BIFP1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3C000000L
+#define BIFP1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L
+#define BIFP1_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000L
+//BIFP1_PCIE_LC_CNTL4
+#define BIFP1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
+#define BIFP1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
+#define BIFP1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
+#define BIFP1_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
+#define BIFP1_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
+#define BIFP1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
+#define BIFP1_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
+#define BIFP1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
+#define BIFP1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
+#define BIFP1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
+#define BIFP1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
+#define BIFP1_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
+#define BIFP1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
+#define BIFP1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
+#define BIFP1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
+#define BIFP1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
+#define BIFP1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
+#define BIFP1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
+#define BIFP1_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT 0x17
+#define BIFP1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
+#define BIFP1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
+#define BIFP1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
+#define BIFP1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L
+#define BIFP1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x00000004L
+#define BIFP1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x00000008L
+#define BIFP1_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x00000010L
+#define BIFP1_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x00000020L
+#define BIFP1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L
+#define BIFP1_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L
+#define BIFP1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x00000300L
+#define BIFP1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L
+#define BIFP1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x00000800L
+#define BIFP1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x00001000L
+#define BIFP1_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L
+#define BIFP1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L
+#define BIFP1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x00008000L
+#define BIFP1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x00010000L
+#define BIFP1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x00020000L
+#define BIFP1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x003C0000L
+#define BIFP1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L
+#define BIFP1_PCIE_LC_CNTL4__LC_TX_SWING_MASK 0x00800000L
+#define BIFP1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L
+#define BIFP1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L
+#define BIFP1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xFC000000L
+//BIFP1_PCIE_LC_CNTL5
+#define BIFP1_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
+#define BIFP1_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
+#define BIFP1_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
+#define BIFP1_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
+#define BIFP1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
+#define BIFP1_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT 0x19
+#define BIFP1_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT 0x1a
+#define BIFP1_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT 0x1b
+#define BIFP1_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT 0x1c
+#define BIFP1_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT 0x1d
+#define BIFP1_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x0000003FL
+#define BIFP1_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0x00000FC0L
+#define BIFP1_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x0003F000L
+#define BIFP1_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0x00FC0000L
+#define BIFP1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x01000000L
+#define BIFP1_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK 0x02000000L
+#define BIFP1_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK 0x04000000L
+#define BIFP1_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK 0x08000000L
+#define BIFP1_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK 0x10000000L
+#define BIFP1_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK 0xE0000000L
+//BIFP1_PCIE_LC_FORCE_COEFF
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x00000001L
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x0000007EL
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x00001F80L
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x0007E000L
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x00080000L
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x00100000L
+//BIFP1_PCIE_LC_BEST_EQ_SETTINGS
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000FL
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003F0L
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000FC00L
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003F0000L
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3FC00000L
+//BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x00000001L
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x0000007EL
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x00001F80L
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x0007E000L
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x01F80000L
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7E000000L
+//BIFP1_PCIE_LC_CNTL6
+#define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
+#define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
+#define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
+#define BIFP1_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT 0x5
+#define BIFP1_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT 0x6
+#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT 0x8
+#define BIFP1_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT 0x9
+#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT 0xd
+#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT 0xe
+#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT 0x10
+#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT 0x12
+#define BIFP1_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT 0x13
+#define BIFP1_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT 0x14
+#define BIFP1_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT 0x15
+#define BIFP1_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT 0x16
+#define BIFP1_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT 0x17
+#define BIFP1_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT 0x18
+#define BIFP1_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT 0x1f
+#define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x00000001L
+#define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x00000004L
+#define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x00000010L
+#define BIFP1_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK 0x00000020L
+#define BIFP1_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK 0x000000C0L
+#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_EN_MASK 0x00000100L
+#define BIFP1_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK 0x00001E00L
+#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK 0x00002000L
+#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK 0x0000C000L
+#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK 0x00030000L
+#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK 0x00040000L
+#define BIFP1_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK 0x00080000L
+#define BIFP1_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK 0x00100000L
+#define BIFP1_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L
+#define BIFP1_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK 0x00400000L
+#define BIFP1_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK 0x00800000L
+#define BIFP1_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK 0x7F000000L
+#define BIFP1_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK 0x80000000L
+//BIFP1_PCIE_LC_CNTL7
+#define BIFP1_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT 0x0
+#define BIFP1_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT 0x1
+#define BIFP1_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT 0x2
+#define BIFP1_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT 0x3
+#define BIFP1_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT 0x4
+#define BIFP1_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT 0x5
+#define BIFP1_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT 0x6
+#define BIFP1_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT 0x7
+#define BIFP1_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT 0x8
+#define BIFP1_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT 0x9
+#define BIFP1_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT 0xa
+#define BIFP1_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT 0xb
+#define BIFP1_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT 0xc
+#define BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT 0xd
+#define BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT 0x15
+#define BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT 0x16
+#define BIFP1_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT 0x17
+#define BIFP1_PCIE_LC_CNTL7__LC_FOM_TIME__SHIFT 0x18
+#define BIFP1_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH__SHIFT 0x1a
+#define BIFP1_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT 0x1b
+#define BIFP1_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT 0x1c
+#define BIFP1_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT 0x1d
+#define BIFP1_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT 0x1e
+#define BIFP1_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT 0x1f
+#define BIFP1_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK 0x00000001L
+#define BIFP1_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK 0x00000002L
+#define BIFP1_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK 0x00000004L
+#define BIFP1_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK 0x00000008L
+#define BIFP1_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK 0x00000010L
+#define BIFP1_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK 0x00000020L
+#define BIFP1_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK 0x00000040L
+#define BIFP1_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK 0x00000080L
+#define BIFP1_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK 0x00000100L
+#define BIFP1_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK 0x00000200L
+#define BIFP1_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK 0x00000400L
+#define BIFP1_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK 0x00000800L
+#define BIFP1_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK 0x00001000L
+#define BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK 0x001FE000L
+#define BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK 0x00200000L
+#define BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK 0x00400000L
+#define BIFP1_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK 0x00800000L
+#define BIFP1_PCIE_LC_CNTL7__LC_FOM_TIME_MASK 0x03000000L
+#define BIFP1_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH_MASK 0x04000000L
+#define BIFP1_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK 0x08000000L
+#define BIFP1_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK 0x10000000L
+#define BIFP1_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK 0x20000000L
+#define BIFP1_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK 0x40000000L
+#define BIFP1_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN_MASK 0x80000000L
+//BIFP1_PCIE_LINK_MANAGEMENT_STATUS
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT 0x0
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x1
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT 0x2
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT 0x3
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT 0x4
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT 0x5
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT 0x6
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT 0x7
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT 0x8
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT 0x9
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT 0xa
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT 0xb
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT 0xc
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT 0xd
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK 0x00000001L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000002L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 0x00000004L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK 0x00000008L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 0x00000010L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 0x00000020L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK 0x00000040L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK 0x00000080L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK 0x00000100L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK 0x00000200L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK 0x00000400L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK 0x00000800L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK 0x00001000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK 0x00002000L
+//BIFP1_PCIE_LINK_MANAGEMENT_MASK
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT 0x0
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x1
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT 0x2
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT 0x3
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x4
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT 0x5
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT 0x6
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT 0x7
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT 0x8
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT 0x9
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT 0xa
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT 0xb
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT 0xc
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT 0xd
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK 0x00000001L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000002L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK 0x00000004L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK 0x00000008L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000010L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK 0x00000020L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK 0x00000040L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK 0x00000080L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK 0x00000100L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK 0x00000200L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK 0x00000400L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK 0x00000800L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK 0x00001000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK 0x00002000L
+//BIFP1_PCIE_LINK_MANAGEMENT_CNTL
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT 0x0
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT 0x3
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT 0x7
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT 0xb
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT 0xc
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT 0xd
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT 0xf
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT 0x11
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT 0x12
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT 0x13
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT 0x17
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT 0x1b
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK 0x00000007L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK 0x00000078L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK 0x00000780L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK 0x00000800L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK 0x00001000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK 0x00006000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK 0x00018000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK 0x00020000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK 0x00040000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK 0x00780000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK 0x07800000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK 0x38000000L
+//BIFP1_PCIEP_STRAP_LC
+#define BIFP1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
+#define BIFP1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
+#define BIFP1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
+#define BIFP1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
+#define BIFP1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
+#define BIFP1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
+#define BIFP1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
+#define BIFP1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
+#define BIFP1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
+#define BIFP1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
+#define BIFP1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
+#define BIFP1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000CL
+#define BIFP1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000C0L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L
+//BIFP1_PCIEP_STRAP_MISC
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x00000020L
+//BIFP1_PCIE_LC_L1_PM_SUBSTATE
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT 0x0
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT 0x1
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT 0x2
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT 0x3
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT 0x4
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT 0x6
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT 0x8
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT 0x10
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT 0x14
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT 0x17
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK 0x000000C0L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK 0x00001F00L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK 0x00070000L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK 0x00700000L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK 0x03800000L
+//BIFP1_PCIE_LC_L1_PM_SUBSTATE2
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT 0x0
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT 0x8
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK 0x000000FFL
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK 0x00000700L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK 0x03FF0000L
+//BIFP1_PCIE_LC_PORT_ORDER
+#define BIFP1_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT 0x0
+#define BIFP1_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK 0x0000000FL
+//BIFP1_PCIEP_BCH_ECC_CNTL
+#define BIFP1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
+#define BIFP1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
+#define BIFP1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
+#define BIFP1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x00000001L
+#define BIFP1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0x0000FF00L
+#define BIFP1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xFFFF0000L
+//BIFP1_PCIEP_HPGI_PRIVATE
+#define BIFP1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
+#define BIFP1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
+#define BIFP1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x00000008L
+#define BIFP1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x00000040L
+//BIFP1_PCIEP_HPGI
+#define BIFP1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
+#define BIFP1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
+#define BIFP1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
+#define BIFP1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
+#define BIFP1_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
+#define BIFP1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
+#define BIFP1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
+#define BIFP1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
+#define BIFP1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
+#define BIFP1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
+#define BIFP1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
+#define BIFP1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x00000001L
+#define BIFP1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x00000002L
+#define BIFP1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x00000004L
+#define BIFP1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x00000008L
+#define BIFP1_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x00000080L
+#define BIFP1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x00000100L
+#define BIFP1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x00000200L
+#define BIFP1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x00000400L
+#define BIFP1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x00000800L
+#define BIFP1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x00008000L
+#define BIFP1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x00010000L
+//BIFP1_PCIEP_HCNT_DESCRIPTOR
+#define BIFP1_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT 0x0
+#define BIFP1_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT 0x1f
+#define BIFP1_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK 0x0000003FL
+#define BIFP1_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK 0x80000000L
+//BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK
+#define BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT 0x0
+#define BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT 0x10
+#define BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL
+#define BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L
+
+
+// addressBlock: nbio_pcie0_bifp2_pciedir_p
+//BIFP2_PCIEP_RESERVED
+#define BIFP2_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define BIFP2_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL
+//BIFP2_PCIEP_SCRATCH
+#define BIFP2_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
+#define BIFP2_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xFFFFFFFFL
+//BIFP2_PCIEP_PORT_CNTL
+#define BIFP2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
+#define BIFP2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
+#define BIFP2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
+#define BIFP2_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
+#define BIFP2_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
+#define BIFP2_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
+#define BIFP2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
+#define BIFP2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
+#define BIFP2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
+#define BIFP2_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT 0x18
+#define BIFP2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L
+#define BIFP2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L
+#define BIFP2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L
+#define BIFP2_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L
+#define BIFP2_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L
+#define BIFP2_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L
+#define BIFP2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x00007F00L
+#define BIFP2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x00030000L
+#define BIFP2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x001C0000L
+#define BIFP2_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK 0x03000000L
+//BIFP2_PCIE_TX_CNTL
+#define BIFP2_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define BIFP2_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define BIFP2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
+#define BIFP2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
+#define BIFP2_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
+#define BIFP2_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
+#define BIFP2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
+#define BIFP2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
+#define BIFP2_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define BIFP2_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define BIFP2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L
+#define BIFP2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L
+#define BIFP2_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L
+#define BIFP2_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L
+#define BIFP2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L
+#define BIFP2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L
+//BIFP2_PCIE_TX_REQUESTER_ID
+#define BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//BIFP2_PCIE_TX_VENDOR_SPECIFIC
+#define BIFP2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
+#define BIFP2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00FFFFFFL
+//BIFP2_PCIE_TX_REQUEST_NUM_CNTL
+#define BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
+#define BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
+#define BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
+#define BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3F000000L
+#define BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L
+#define BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L
+//BIFP2_PCIE_TX_SEQ
+#define BIFP2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
+#define BIFP2_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
+#define BIFP2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000FFFL
+#define BIFP2_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0FFF0000L
+//BIFP2_PCIE_TX_REPLAY
+#define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
+#define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
+#define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
+#define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L
+#define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L
+#define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xFFFF0000L
+//BIFP2_PCIE_TX_ACK_LATENCY_LIMIT
+#define BIFP2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
+#define BIFP2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
+#define BIFP2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000FFFL
+#define BIFP2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L
+//BIFP2_PCIE_TX_CREDITS_ADVT_P
+#define BIFP2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
+#define BIFP2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
+#define BIFP2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00000FFFL
+#define BIFP2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x00FF0000L
+//BIFP2_PCIE_TX_CREDITS_ADVT_NP
+#define BIFP2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
+#define BIFP2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
+#define BIFP2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00000FFFL
+#define BIFP2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x00FF0000L
+//BIFP2_PCIE_TX_CREDITS_ADVT_CPL
+#define BIFP2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
+#define BIFP2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
+#define BIFP2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00000FFFL
+#define BIFP2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x00FF0000L
+//BIFP2_PCIE_TX_CREDITS_INIT_P
+#define BIFP2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
+#define BIFP2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
+#define BIFP2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000FFFL
+#define BIFP2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00FF0000L
+//BIFP2_PCIE_TX_CREDITS_INIT_NP
+#define BIFP2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
+#define BIFP2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
+#define BIFP2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000FFFL
+#define BIFP2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00FF0000L
+//BIFP2_PCIE_TX_CREDITS_INIT_CPL
+#define BIFP2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
+#define BIFP2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
+#define BIFP2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000FFFL
+#define BIFP2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00FF0000L
+//BIFP2_PCIE_TX_CREDITS_STATUS
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L
+//BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L
+//BIFP2_PCIE_P_PORT_LANE_STATUS
+#define BIFP2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
+#define BIFP2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
+#define BIFP2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L
+#define BIFP2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007EL
+//BIFP2_PCIE_FC_P
+#define BIFP2_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
+#define BIFP2_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
+#define BIFP2_PCIE_FC_P__PD_CREDITS_MASK 0x000000FFL
+#define BIFP2_PCIE_FC_P__PH_CREDITS_MASK 0x0000FF00L
+//BIFP2_PCIE_FC_NP
+#define BIFP2_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
+#define BIFP2_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
+#define BIFP2_PCIE_FC_NP__NPD_CREDITS_MASK 0x000000FFL
+#define BIFP2_PCIE_FC_NP__NPH_CREDITS_MASK 0x0000FF00L
+//BIFP2_PCIE_FC_CPL
+#define BIFP2_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
+#define BIFP2_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
+#define BIFP2_PCIE_FC_CPL__CPLD_CREDITS_MASK 0x000000FFL
+#define BIFP2_PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0000FF00L
+//BIFP2_PCIE_ERR_CNTL
+#define BIFP2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define BIFP2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
+#define BIFP2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
+#define BIFP2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
+#define BIFP2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
+#define BIFP2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
+#define BIFP2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
+#define BIFP2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define BIFP2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define BIFP2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
+#define BIFP2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
+#define BIFP2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
+#define BIFP2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define BIFP2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define BIFP2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define BIFP2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L
+#define BIFP2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x00000004L
+#define BIFP2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L
+#define BIFP2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L
+#define BIFP2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L
+#define BIFP2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L
+#define BIFP2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define BIFP2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define BIFP2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L
+#define BIFP2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L
+#define BIFP2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L
+#define BIFP2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define BIFP2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+//BIFP2_PCIE_RX_CNTL
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
+#define BIFP2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
+#define BIFP2_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
+#define BIFP2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
+#define BIFP2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
+#define BIFP2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
+#define BIFP2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define BIFP2_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define BIFP2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L
+#define BIFP2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L
+#define BIFP2_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x00004000L
+#define BIFP2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L
+#define BIFP2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L
+#define BIFP2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L
+#define BIFP2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define BIFP2_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+#define BIFP2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+//BIFP2_PCIE_RX_EXPECTED_SEQNUM
+#define BIFP2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
+#define BIFP2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000FFFL
+//BIFP2_PCIE_RX_VENDOR_SPECIFIC
+#define BIFP2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
+#define BIFP2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
+#define BIFP2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00FFFFFFL
+#define BIFP2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L
+//BIFP2_PCIE_RX_CNTL3
+#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
+#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
+#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
+#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
+#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
+#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L
+#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L
+#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L
+#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L
+#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L
+//BIFP2_PCIE_RX_CREDITS_ALLOCATED_P
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000FFFL
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00FF0000L
+//BIFP2_PCIE_RX_CREDITS_ALLOCATED_NP
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000FFFL
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00FF0000L
+//BIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000FFFL
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00FF0000L
+//BIFP2_PCIEP_ERROR_INJECT_PHYSICAL
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x00000003L
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0x0000000CL
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x00000030L
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0x000000C0L
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x00000300L
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0x00000C00L
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x00003000L
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0x0000C000L
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x00030000L
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0x000C0000L
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x00300000L
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0x00C00000L
+//BIFP2_PCIEP_ERROR_INJECT_TRANSACTION
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x00000003L
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0x0000000CL
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x00000030L
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0x000000C0L
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x00000300L
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0x00000C00L
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x00003000L
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0x0000C000L
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x00030000L
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0x000C0000L
+//BIFP2_PCIEP_NAK_COUNTER
+#define BIFP2_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT 0x0
+#define BIFP2_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT 0x10
+#define BIFP2_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK 0x0000FFFFL
+#define BIFP2_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK 0xFFFF0000L
+//BIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS__SHIFT 0x0
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK__SHIFT 0x8
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK__SHIFT 0x9
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS_MASK 0x00000001L
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK_MASK 0x00000100L
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK_MASK 0x00000200L
+//BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT 0x0
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT 0xa
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT 0xf
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT 0x1a
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT 0x1f
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK 0x000003FFL
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK 0x00001C00L
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK 0x00008000L
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK 0x1C000000L
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK 0x80000000L
+//BIFP2_PCIE_LC_CNTL
+#define BIFP2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
+#define BIFP2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
+#define BIFP2_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
+#define BIFP2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
+#define BIFP2_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
+#define BIFP2_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
+#define BIFP2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
+#define BIFP2_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
+#define BIFP2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
+#define BIFP2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
+#define BIFP2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
+#define BIFP2_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
+#define BIFP2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
+#define BIFP2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
+#define BIFP2_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
+#define BIFP2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
+#define BIFP2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
+#define BIFP2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
+#define BIFP2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
+#define BIFP2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
+#define BIFP2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L
+#define BIFP2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L
+#define BIFP2_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L
+#define BIFP2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000F0L
+#define BIFP2_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000F00L
+#define BIFP2_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000F000L
+#define BIFP2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L
+#define BIFP2_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L
+#define BIFP2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000C0000L
+#define BIFP2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L
+#define BIFP2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L
+#define BIFP2_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L
+#define BIFP2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L
+#define BIFP2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L
+#define BIFP2_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L
+#define BIFP2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L
+#define BIFP2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L
+#define BIFP2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L
+#define BIFP2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L
+#define BIFP2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L
+//BIFP2_PCIE_LC_TRAINING_CNTL
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000FL
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x00004000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x00008000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00C00000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xC0000000L
+//BIFP2_PCIE_LC_LINK_WIDTH_CNTL
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT 0x1e
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT 0x1f
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x00010000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x01000000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x02000000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x04000000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x08000000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK 0x40000000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK 0x80000000L
+//BIFP2_PCIE_LC_N_FTS_CNTL
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT 0xf
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000FFL
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK 0x00008000L
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00FF0000L
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xFF000000L
+//BIFP2_PCIE_LC_SPEED_CNTL
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000004L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000018L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000020L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000040L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000080L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000100L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000200L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00000C00L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00001000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x00006000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00008000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00010000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00020000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00040000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00080000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00100000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00200000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x00400000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x00800000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x03000000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x04000000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x08000000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000L
+//BIFP2_PCIE_LC_STATE0
+#define BIFP2_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
+#define BIFP2_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
+#define BIFP2_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
+#define BIFP2_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
+#define BIFP2_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003FL
+#define BIFP2_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003F00L
+#define BIFP2_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003F0000L
+#define BIFP2_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3F000000L
+//BIFP2_PCIE_LC_STATE1
+#define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
+#define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
+#define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
+#define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
+#define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003FL
+#define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003F00L
+#define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003F0000L
+#define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3F000000L
+//BIFP2_PCIE_LC_STATE2
+#define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
+#define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
+#define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
+#define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
+#define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003FL
+#define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003F00L
+#define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003F0000L
+#define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3F000000L
+//BIFP2_PCIE_LC_STATE3
+#define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
+#define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
+#define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
+#define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
+#define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003FL
+#define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003F00L
+#define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003F0000L
+#define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3F000000L
+//BIFP2_PCIE_LC_STATE4
+#define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
+#define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
+#define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
+#define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
+#define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003FL
+#define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003F00L
+#define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003F0000L
+#define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3F000000L
+//BIFP2_PCIE_LC_STATE5
+#define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
+#define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
+#define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
+#define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
+#define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003FL
+#define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003F00L
+#define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003F0000L
+#define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3F000000L
+//BIFP2_PCIE_LINK_MANAGEMENT_CNTL2
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT 0x0
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT 0x1
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT 0x2
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT 0x3
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT 0x4
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT 0x7
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT 0xb
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT 0xf
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT 0x13
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK 0x00000001L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK 0x00000002L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK 0x00000004L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK 0x00000008L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK 0x00000070L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK 0x00000780L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK 0x00007800L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK 0x00078000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK 0x00780000L
+//BIFP2_PCIE_LC_CNTL2
+#define BIFP2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
+#define BIFP2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
+#define BIFP2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
+#define BIFP2_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
+#define BIFP2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
+#define BIFP2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
+#define BIFP2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
+#define BIFP2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
+#define BIFP2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
+#define BIFP2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
+#define BIFP2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
+#define BIFP2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
+#define BIFP2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
+#define BIFP2_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
+#define BIFP2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
+#define BIFP2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
+#define BIFP2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
+#define BIFP2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
+#define BIFP2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
+#define BIFP2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
+#define BIFP2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define BIFP2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
+#define BIFP2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
+#define BIFP2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
+#define BIFP2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003FL
+#define BIFP2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L
+#define BIFP2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L
+#define BIFP2_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L
+#define BIFP2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L
+#define BIFP2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L
+#define BIFP2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L
+#define BIFP2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L
+#define BIFP2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L
+#define BIFP2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000C000L
+#define BIFP2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L
+#define BIFP2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L
+#define BIFP2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L
+#define BIFP2_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x00080000L
+#define BIFP2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L
+#define BIFP2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L
+#define BIFP2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L
+#define BIFP2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L
+#define BIFP2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L
+#define BIFP2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L
+#define BIFP2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+#define BIFP2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L
+#define BIFP2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L
+#define BIFP2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L
+//BIFP2_PCIE_LC_BW_CHANGE_CNTL
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT 0xb
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK 0x00000800L
+//BIFP2_PCIE_LC_CDR_CNTL
+#define BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
+#define BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
+#define BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
+#define BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000FFFL
+#define BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00FFF000L
+#define BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L
+//BIFP2_PCIE_LC_LANE_CNTL
+#define BIFP2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
+#define BIFP2_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
+#define BIFP2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000FFFFL
+#define BIFP2_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xFFFF0000L
+//BIFP2_PCIE_LC_CNTL3
+#define BIFP2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
+#define BIFP2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
+#define BIFP2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
+#define BIFP2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
+#define BIFP2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
+#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
+#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
+#define BIFP2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
+#define BIFP2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
+#define BIFP2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
+#define BIFP2_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
+#define BIFP2_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
+#define BIFP2_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
+#define BIFP2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
+#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
+#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
+#define BIFP2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
+#define BIFP2_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
+#define BIFP2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
+#define BIFP2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
+#define BIFP2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
+#define BIFP2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
+#define BIFP2_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
+#define BIFP2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L
+#define BIFP2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L
+#define BIFP2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L
+#define BIFP2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L
+#define BIFP2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L
+#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000C0L
+#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L
+#define BIFP2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L
+#define BIFP2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L
+#define BIFP2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L
+#define BIFP2_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x00003000L
+#define BIFP2_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0x0000C000L
+#define BIFP2_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x00010000L
+#define BIFP2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L
+#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L
+#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L
+#define BIFP2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L
+#define BIFP2_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x00400000L
+#define BIFP2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L
+#define BIFP2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L
+#define BIFP2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3C000000L
+#define BIFP2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L
+#define BIFP2_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000L
+//BIFP2_PCIE_LC_CNTL4
+#define BIFP2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
+#define BIFP2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
+#define BIFP2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
+#define BIFP2_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
+#define BIFP2_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
+#define BIFP2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
+#define BIFP2_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
+#define BIFP2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
+#define BIFP2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
+#define BIFP2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
+#define BIFP2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
+#define BIFP2_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
+#define BIFP2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
+#define BIFP2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
+#define BIFP2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
+#define BIFP2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
+#define BIFP2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
+#define BIFP2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
+#define BIFP2_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT 0x17
+#define BIFP2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
+#define BIFP2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
+#define BIFP2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
+#define BIFP2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L
+#define BIFP2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x00000004L
+#define BIFP2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x00000008L
+#define BIFP2_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x00000010L
+#define BIFP2_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x00000020L
+#define BIFP2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L
+#define BIFP2_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L
+#define BIFP2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x00000300L
+#define BIFP2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L
+#define BIFP2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x00000800L
+#define BIFP2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x00001000L
+#define BIFP2_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L
+#define BIFP2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L
+#define BIFP2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x00008000L
+#define BIFP2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x00010000L
+#define BIFP2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x00020000L
+#define BIFP2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x003C0000L
+#define BIFP2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L
+#define BIFP2_PCIE_LC_CNTL4__LC_TX_SWING_MASK 0x00800000L
+#define BIFP2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L
+#define BIFP2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L
+#define BIFP2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xFC000000L
+//BIFP2_PCIE_LC_CNTL5
+#define BIFP2_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
+#define BIFP2_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
+#define BIFP2_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
+#define BIFP2_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
+#define BIFP2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
+#define BIFP2_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT 0x19
+#define BIFP2_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT 0x1a
+#define BIFP2_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT 0x1b
+#define BIFP2_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT 0x1c
+#define BIFP2_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT 0x1d
+#define BIFP2_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x0000003FL
+#define BIFP2_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0x00000FC0L
+#define BIFP2_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x0003F000L
+#define BIFP2_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0x00FC0000L
+#define BIFP2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x01000000L
+#define BIFP2_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK 0x02000000L
+#define BIFP2_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK 0x04000000L
+#define BIFP2_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK 0x08000000L
+#define BIFP2_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK 0x10000000L
+#define BIFP2_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK 0xE0000000L
+//BIFP2_PCIE_LC_FORCE_COEFF
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x00000001L
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x0000007EL
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x00001F80L
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x0007E000L
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x00080000L
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x00100000L
+//BIFP2_PCIE_LC_BEST_EQ_SETTINGS
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000FL
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003F0L
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000FC00L
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003F0000L
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3FC00000L
+//BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x00000001L
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x0000007EL
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x00001F80L
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x0007E000L
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x01F80000L
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7E000000L
+//BIFP2_PCIE_LC_CNTL6
+#define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
+#define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
+#define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
+#define BIFP2_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT 0x5
+#define BIFP2_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT 0x6
+#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT 0x8
+#define BIFP2_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT 0x9
+#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT 0xd
+#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT 0xe
+#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT 0x10
+#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT 0x12
+#define BIFP2_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT 0x13
+#define BIFP2_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT 0x14
+#define BIFP2_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT 0x15
+#define BIFP2_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT 0x16
+#define BIFP2_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT 0x17
+#define BIFP2_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT 0x18
+#define BIFP2_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT 0x1f
+#define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x00000001L
+#define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x00000004L
+#define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x00000010L
+#define BIFP2_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK 0x00000020L
+#define BIFP2_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK 0x000000C0L
+#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_EN_MASK 0x00000100L
+#define BIFP2_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK 0x00001E00L
+#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK 0x00002000L
+#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK 0x0000C000L
+#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK 0x00030000L
+#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK 0x00040000L
+#define BIFP2_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK 0x00080000L
+#define BIFP2_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK 0x00100000L
+#define BIFP2_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L
+#define BIFP2_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK 0x00400000L
+#define BIFP2_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK 0x00800000L
+#define BIFP2_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK 0x7F000000L
+#define BIFP2_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK 0x80000000L
+//BIFP2_PCIE_LC_CNTL7
+#define BIFP2_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT 0x0
+#define BIFP2_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT 0x1
+#define BIFP2_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT 0x2
+#define BIFP2_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT 0x3
+#define BIFP2_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT 0x4
+#define BIFP2_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT 0x5
+#define BIFP2_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT 0x6
+#define BIFP2_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT 0x7
+#define BIFP2_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT 0x8
+#define BIFP2_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT 0x9
+#define BIFP2_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT 0xa
+#define BIFP2_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT 0xb
+#define BIFP2_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT 0xc
+#define BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT 0xd
+#define BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT 0x15
+#define BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT 0x16
+#define BIFP2_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT 0x17
+#define BIFP2_PCIE_LC_CNTL7__LC_FOM_TIME__SHIFT 0x18
+#define BIFP2_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH__SHIFT 0x1a
+#define BIFP2_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT 0x1b
+#define BIFP2_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT 0x1c
+#define BIFP2_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT 0x1d
+#define BIFP2_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT 0x1e
+#define BIFP2_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT 0x1f
+#define BIFP2_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK 0x00000001L
+#define BIFP2_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK 0x00000002L
+#define BIFP2_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK 0x00000004L
+#define BIFP2_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK 0x00000008L
+#define BIFP2_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK 0x00000010L
+#define BIFP2_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK 0x00000020L
+#define BIFP2_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK 0x00000040L
+#define BIFP2_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK 0x00000080L
+#define BIFP2_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK 0x00000100L
+#define BIFP2_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK 0x00000200L
+#define BIFP2_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK 0x00000400L
+#define BIFP2_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK 0x00000800L
+#define BIFP2_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK 0x00001000L
+#define BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK 0x001FE000L
+#define BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK 0x00200000L
+#define BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK 0x00400000L
+#define BIFP2_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK 0x00800000L
+#define BIFP2_PCIE_LC_CNTL7__LC_FOM_TIME_MASK 0x03000000L
+#define BIFP2_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH_MASK 0x04000000L
+#define BIFP2_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK 0x08000000L
+#define BIFP2_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK 0x10000000L
+#define BIFP2_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK 0x20000000L
+#define BIFP2_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK 0x40000000L
+#define BIFP2_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN_MASK 0x80000000L
+//BIFP2_PCIE_LINK_MANAGEMENT_STATUS
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT 0x0
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x1
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT 0x2
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT 0x3
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT 0x4
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT 0x5
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT 0x6
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT 0x7
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT 0x8
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT 0x9
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT 0xa
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT 0xb
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT 0xc
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT 0xd
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK 0x00000001L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000002L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 0x00000004L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK 0x00000008L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 0x00000010L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 0x00000020L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK 0x00000040L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK 0x00000080L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK 0x00000100L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK 0x00000200L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK 0x00000400L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK 0x00000800L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK 0x00001000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK 0x00002000L
+//BIFP2_PCIE_LINK_MANAGEMENT_MASK
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT 0x0
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x1
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT 0x2
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT 0x3
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x4
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT 0x5
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT 0x6
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT 0x7
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT 0x8
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT 0x9
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT 0xa
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT 0xb
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT 0xc
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT 0xd
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK 0x00000001L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000002L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK 0x00000004L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK 0x00000008L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000010L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK 0x00000020L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK 0x00000040L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK 0x00000080L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK 0x00000100L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK 0x00000200L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK 0x00000400L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK 0x00000800L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK 0x00001000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK 0x00002000L
+//BIFP2_PCIE_LINK_MANAGEMENT_CNTL
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT 0x0
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT 0x3
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT 0x7
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT 0xb
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT 0xc
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT 0xd
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT 0xf
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT 0x11
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT 0x12
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT 0x13
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT 0x17
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT 0x1b
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK 0x00000007L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK 0x00000078L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK 0x00000780L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK 0x00000800L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK 0x00001000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK 0x00006000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK 0x00018000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK 0x00020000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK 0x00040000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK 0x00780000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK 0x07800000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK 0x38000000L
+//BIFP2_PCIEP_STRAP_LC
+#define BIFP2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
+#define BIFP2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
+#define BIFP2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
+#define BIFP2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
+#define BIFP2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
+#define BIFP2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
+#define BIFP2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
+#define BIFP2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
+#define BIFP2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
+#define BIFP2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
+#define BIFP2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
+#define BIFP2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000CL
+#define BIFP2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000C0L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L
+//BIFP2_PCIEP_STRAP_MISC
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x00000020L
+//BIFP2_PCIE_LC_L1_PM_SUBSTATE
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT 0x0
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT 0x1
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT 0x2
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT 0x3
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT 0x4
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT 0x6
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT 0x8
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT 0x10
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT 0x14
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT 0x17
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK 0x000000C0L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK 0x00001F00L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK 0x00070000L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK 0x00700000L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK 0x03800000L
+//BIFP2_PCIE_LC_L1_PM_SUBSTATE2
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT 0x0
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT 0x8
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK 0x000000FFL
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK 0x00000700L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK 0x03FF0000L
+//BIFP2_PCIE_LC_PORT_ORDER
+#define BIFP2_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT 0x0
+#define BIFP2_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK 0x0000000FL
+//BIFP2_PCIEP_BCH_ECC_CNTL
+#define BIFP2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
+#define BIFP2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
+#define BIFP2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
+#define BIFP2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x00000001L
+#define BIFP2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0x0000FF00L
+#define BIFP2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xFFFF0000L
+//BIFP2_PCIEP_HPGI_PRIVATE
+#define BIFP2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
+#define BIFP2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
+#define BIFP2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x00000008L
+#define BIFP2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x00000040L
+//BIFP2_PCIEP_HPGI
+#define BIFP2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
+#define BIFP2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
+#define BIFP2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
+#define BIFP2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
+#define BIFP2_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
+#define BIFP2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
+#define BIFP2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
+#define BIFP2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
+#define BIFP2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
+#define BIFP2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
+#define BIFP2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
+#define BIFP2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x00000001L
+#define BIFP2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x00000002L
+#define BIFP2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x00000004L
+#define BIFP2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x00000008L
+#define BIFP2_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x00000080L
+#define BIFP2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x00000100L
+#define BIFP2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x00000200L
+#define BIFP2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x00000400L
+#define BIFP2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x00000800L
+#define BIFP2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x00008000L
+#define BIFP2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x00010000L
+//BIFP2_PCIEP_HCNT_DESCRIPTOR
+#define BIFP2_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT 0x0
+#define BIFP2_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT 0x1f
+#define BIFP2_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK 0x0000003FL
+#define BIFP2_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK 0x80000000L
+//BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK
+#define BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT 0x0
+#define BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT 0x10
+#define BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL
+#define BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L
+
+
+// addressBlock: nbio_pcie0_bifp3_pciedir_p
+//BIFP3_PCIEP_RESERVED
+#define BIFP3_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define BIFP3_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL
+//BIFP3_PCIEP_SCRATCH
+#define BIFP3_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
+#define BIFP3_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xFFFFFFFFL
+//BIFP3_PCIEP_PORT_CNTL
+#define BIFP3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
+#define BIFP3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
+#define BIFP3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
+#define BIFP3_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
+#define BIFP3_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
+#define BIFP3_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
+#define BIFP3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
+#define BIFP3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
+#define BIFP3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
+#define BIFP3_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT 0x18
+#define BIFP3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L
+#define BIFP3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L
+#define BIFP3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L
+#define BIFP3_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L
+#define BIFP3_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L
+#define BIFP3_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L
+#define BIFP3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x00007F00L
+#define BIFP3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x00030000L
+#define BIFP3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x001C0000L
+#define BIFP3_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK 0x03000000L
+//BIFP3_PCIE_TX_CNTL
+#define BIFP3_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define BIFP3_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define BIFP3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
+#define BIFP3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
+#define BIFP3_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
+#define BIFP3_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
+#define BIFP3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
+#define BIFP3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
+#define BIFP3_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define BIFP3_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define BIFP3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L
+#define BIFP3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L
+#define BIFP3_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L
+#define BIFP3_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L
+#define BIFP3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L
+#define BIFP3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L
+//BIFP3_PCIE_TX_REQUESTER_ID
+#define BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//BIFP3_PCIE_TX_VENDOR_SPECIFIC
+#define BIFP3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
+#define BIFP3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00FFFFFFL
+//BIFP3_PCIE_TX_REQUEST_NUM_CNTL
+#define BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
+#define BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
+#define BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
+#define BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3F000000L
+#define BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L
+#define BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L
+//BIFP3_PCIE_TX_SEQ
+#define BIFP3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
+#define BIFP3_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
+#define BIFP3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000FFFL
+#define BIFP3_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0FFF0000L
+//BIFP3_PCIE_TX_REPLAY
+#define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
+#define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
+#define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
+#define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L
+#define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L
+#define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xFFFF0000L
+//BIFP3_PCIE_TX_ACK_LATENCY_LIMIT
+#define BIFP3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
+#define BIFP3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
+#define BIFP3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000FFFL
+#define BIFP3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L
+//BIFP3_PCIE_TX_CREDITS_ADVT_P
+#define BIFP3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
+#define BIFP3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
+#define BIFP3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00000FFFL
+#define BIFP3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x00FF0000L
+//BIFP3_PCIE_TX_CREDITS_ADVT_NP
+#define BIFP3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
+#define BIFP3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
+#define BIFP3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00000FFFL
+#define BIFP3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x00FF0000L
+//BIFP3_PCIE_TX_CREDITS_ADVT_CPL
+#define BIFP3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
+#define BIFP3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
+#define BIFP3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00000FFFL
+#define BIFP3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x00FF0000L
+//BIFP3_PCIE_TX_CREDITS_INIT_P
+#define BIFP3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
+#define BIFP3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
+#define BIFP3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000FFFL
+#define BIFP3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00FF0000L
+//BIFP3_PCIE_TX_CREDITS_INIT_NP
+#define BIFP3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
+#define BIFP3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
+#define BIFP3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000FFFL
+#define BIFP3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00FF0000L
+//BIFP3_PCIE_TX_CREDITS_INIT_CPL
+#define BIFP3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
+#define BIFP3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
+#define BIFP3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000FFFL
+#define BIFP3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00FF0000L
+//BIFP3_PCIE_TX_CREDITS_STATUS
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L
+//BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L
+//BIFP3_PCIE_P_PORT_LANE_STATUS
+#define BIFP3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
+#define BIFP3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
+#define BIFP3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L
+#define BIFP3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007EL
+//BIFP3_PCIE_FC_P
+#define BIFP3_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
+#define BIFP3_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
+#define BIFP3_PCIE_FC_P__PD_CREDITS_MASK 0x000000FFL
+#define BIFP3_PCIE_FC_P__PH_CREDITS_MASK 0x0000FF00L
+//BIFP3_PCIE_FC_NP
+#define BIFP3_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
+#define BIFP3_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
+#define BIFP3_PCIE_FC_NP__NPD_CREDITS_MASK 0x000000FFL
+#define BIFP3_PCIE_FC_NP__NPH_CREDITS_MASK 0x0000FF00L
+//BIFP3_PCIE_FC_CPL
+#define BIFP3_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
+#define BIFP3_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
+#define BIFP3_PCIE_FC_CPL__CPLD_CREDITS_MASK 0x000000FFL
+#define BIFP3_PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0000FF00L
+//BIFP3_PCIE_ERR_CNTL
+#define BIFP3_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define BIFP3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
+#define BIFP3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
+#define BIFP3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
+#define BIFP3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
+#define BIFP3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
+#define BIFP3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
+#define BIFP3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define BIFP3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define BIFP3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
+#define BIFP3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
+#define BIFP3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
+#define BIFP3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define BIFP3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define BIFP3_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define BIFP3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L
+#define BIFP3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x00000004L
+#define BIFP3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L
+#define BIFP3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L
+#define BIFP3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L
+#define BIFP3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L
+#define BIFP3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define BIFP3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define BIFP3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L
+#define BIFP3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L
+#define BIFP3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L
+#define BIFP3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define BIFP3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+//BIFP3_PCIE_RX_CNTL
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
+#define BIFP3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
+#define BIFP3_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
+#define BIFP3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
+#define BIFP3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
+#define BIFP3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
+#define BIFP3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define BIFP3_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define BIFP3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L
+#define BIFP3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L
+#define BIFP3_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x00004000L
+#define BIFP3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L
+#define BIFP3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L
+#define BIFP3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L
+#define BIFP3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define BIFP3_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+#define BIFP3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+//BIFP3_PCIE_RX_EXPECTED_SEQNUM
+#define BIFP3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
+#define BIFP3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000FFFL
+//BIFP3_PCIE_RX_VENDOR_SPECIFIC
+#define BIFP3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
+#define BIFP3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
+#define BIFP3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00FFFFFFL
+#define BIFP3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L
+//BIFP3_PCIE_RX_CNTL3
+#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
+#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
+#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
+#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
+#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
+#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L
+#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L
+#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L
+#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L
+#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L
+//BIFP3_PCIE_RX_CREDITS_ALLOCATED_P
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000FFFL
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00FF0000L
+//BIFP3_PCIE_RX_CREDITS_ALLOCATED_NP
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000FFFL
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00FF0000L
+//BIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000FFFL
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00FF0000L
+//BIFP3_PCIEP_ERROR_INJECT_PHYSICAL
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x00000003L
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0x0000000CL
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x00000030L
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0x000000C0L
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x00000300L
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0x00000C00L
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x00003000L
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0x0000C000L
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x00030000L
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0x000C0000L
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x00300000L
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0x00C00000L
+//BIFP3_PCIEP_ERROR_INJECT_TRANSACTION
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x00000003L
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0x0000000CL
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x00000030L
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0x000000C0L
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x00000300L
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0x00000C00L
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x00003000L
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0x0000C000L
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x00030000L
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0x000C0000L
+//BIFP3_PCIEP_NAK_COUNTER
+#define BIFP3_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT 0x0
+#define BIFP3_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT 0x10
+#define BIFP3_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK 0x0000FFFFL
+#define BIFP3_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK 0xFFFF0000L
+//BIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS__SHIFT 0x0
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK__SHIFT 0x8
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK__SHIFT 0x9
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS_MASK 0x00000001L
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK_MASK 0x00000100L
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK_MASK 0x00000200L
+//BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT 0x0
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT 0xa
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT 0xf
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT 0x1a
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT 0x1f
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK 0x000003FFL
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK 0x00001C00L
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK 0x00008000L
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK 0x1C000000L
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK 0x80000000L
+//BIFP3_PCIE_LC_CNTL
+#define BIFP3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
+#define BIFP3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
+#define BIFP3_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
+#define BIFP3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
+#define BIFP3_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
+#define BIFP3_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
+#define BIFP3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
+#define BIFP3_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
+#define BIFP3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
+#define BIFP3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
+#define BIFP3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
+#define BIFP3_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
+#define BIFP3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
+#define BIFP3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
+#define BIFP3_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
+#define BIFP3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
+#define BIFP3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
+#define BIFP3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
+#define BIFP3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
+#define BIFP3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
+#define BIFP3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L
+#define BIFP3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L
+#define BIFP3_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L
+#define BIFP3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000F0L
+#define BIFP3_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000F00L
+#define BIFP3_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000F000L
+#define BIFP3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L
+#define BIFP3_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L
+#define BIFP3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000C0000L
+#define BIFP3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L
+#define BIFP3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L
+#define BIFP3_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L
+#define BIFP3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L
+#define BIFP3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L
+#define BIFP3_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L
+#define BIFP3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L
+#define BIFP3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L
+#define BIFP3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L
+#define BIFP3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L
+#define BIFP3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L
+//BIFP3_PCIE_LC_TRAINING_CNTL
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000FL
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x00004000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x00008000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00C00000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xC0000000L
+//BIFP3_PCIE_LC_LINK_WIDTH_CNTL
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT 0x1e
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT 0x1f
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x00010000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x01000000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x02000000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x04000000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x08000000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK 0x40000000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK 0x80000000L
+//BIFP3_PCIE_LC_N_FTS_CNTL
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT 0xf
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000FFL
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK 0x00008000L
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00FF0000L
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xFF000000L
+//BIFP3_PCIE_LC_SPEED_CNTL
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000004L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000018L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000020L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000040L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000080L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000100L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000200L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00000C00L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00001000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x00006000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00008000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00010000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00020000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00040000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00080000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00100000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00200000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x00400000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x00800000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x03000000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x04000000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x08000000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000L
+//BIFP3_PCIE_LC_STATE0
+#define BIFP3_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
+#define BIFP3_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
+#define BIFP3_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
+#define BIFP3_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
+#define BIFP3_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003FL
+#define BIFP3_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003F00L
+#define BIFP3_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003F0000L
+#define BIFP3_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3F000000L
+//BIFP3_PCIE_LC_STATE1
+#define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
+#define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
+#define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
+#define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
+#define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003FL
+#define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003F00L
+#define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003F0000L
+#define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3F000000L
+//BIFP3_PCIE_LC_STATE2
+#define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
+#define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
+#define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
+#define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
+#define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003FL
+#define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003F00L
+#define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003F0000L
+#define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3F000000L
+//BIFP3_PCIE_LC_STATE3
+#define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
+#define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
+#define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
+#define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
+#define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003FL
+#define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003F00L
+#define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003F0000L
+#define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3F000000L
+//BIFP3_PCIE_LC_STATE4
+#define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
+#define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
+#define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
+#define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
+#define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003FL
+#define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003F00L
+#define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003F0000L
+#define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3F000000L
+//BIFP3_PCIE_LC_STATE5
+#define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
+#define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
+#define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
+#define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
+#define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003FL
+#define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003F00L
+#define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003F0000L
+#define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3F000000L
+//BIFP3_PCIE_LINK_MANAGEMENT_CNTL2
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT 0x0
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT 0x1
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT 0x2
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT 0x3
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT 0x4
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT 0x7
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT 0xb
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT 0xf
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT 0x13
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK 0x00000001L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK 0x00000002L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK 0x00000004L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK 0x00000008L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK 0x00000070L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK 0x00000780L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK 0x00007800L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK 0x00078000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK 0x00780000L
+//BIFP3_PCIE_LC_CNTL2
+#define BIFP3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
+#define BIFP3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
+#define BIFP3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
+#define BIFP3_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
+#define BIFP3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
+#define BIFP3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
+#define BIFP3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
+#define BIFP3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
+#define BIFP3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
+#define BIFP3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
+#define BIFP3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
+#define BIFP3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
+#define BIFP3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
+#define BIFP3_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
+#define BIFP3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
+#define BIFP3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
+#define BIFP3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
+#define BIFP3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
+#define BIFP3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
+#define BIFP3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
+#define BIFP3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define BIFP3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
+#define BIFP3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
+#define BIFP3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
+#define BIFP3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003FL
+#define BIFP3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L
+#define BIFP3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L
+#define BIFP3_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L
+#define BIFP3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L
+#define BIFP3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L
+#define BIFP3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L
+#define BIFP3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L
+#define BIFP3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L
+#define BIFP3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000C000L
+#define BIFP3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L
+#define BIFP3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L
+#define BIFP3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L
+#define BIFP3_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x00080000L
+#define BIFP3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L
+#define BIFP3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L
+#define BIFP3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L
+#define BIFP3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L
+#define BIFP3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L
+#define BIFP3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L
+#define BIFP3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+#define BIFP3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L
+#define BIFP3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L
+#define BIFP3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L
+//BIFP3_PCIE_LC_BW_CHANGE_CNTL
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT 0xb
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK 0x00000800L
+//BIFP3_PCIE_LC_CDR_CNTL
+#define BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
+#define BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
+#define BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
+#define BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000FFFL
+#define BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00FFF000L
+#define BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L
+//BIFP3_PCIE_LC_LANE_CNTL
+#define BIFP3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
+#define BIFP3_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
+#define BIFP3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000FFFFL
+#define BIFP3_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xFFFF0000L
+//BIFP3_PCIE_LC_CNTL3
+#define BIFP3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
+#define BIFP3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
+#define BIFP3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
+#define BIFP3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
+#define BIFP3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
+#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
+#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
+#define BIFP3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
+#define BIFP3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
+#define BIFP3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
+#define BIFP3_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
+#define BIFP3_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
+#define BIFP3_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
+#define BIFP3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
+#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
+#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
+#define BIFP3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
+#define BIFP3_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
+#define BIFP3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
+#define BIFP3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
+#define BIFP3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
+#define BIFP3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
+#define BIFP3_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
+#define BIFP3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L
+#define BIFP3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L
+#define BIFP3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L
+#define BIFP3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L
+#define BIFP3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L
+#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000C0L
+#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L
+#define BIFP3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L
+#define BIFP3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L
+#define BIFP3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L
+#define BIFP3_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x00003000L
+#define BIFP3_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0x0000C000L
+#define BIFP3_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x00010000L
+#define BIFP3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L
+#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L
+#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L
+#define BIFP3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L
+#define BIFP3_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x00400000L
+#define BIFP3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L
+#define BIFP3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L
+#define BIFP3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3C000000L
+#define BIFP3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L
+#define BIFP3_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000L
+//BIFP3_PCIE_LC_CNTL4
+#define BIFP3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
+#define BIFP3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
+#define BIFP3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
+#define BIFP3_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
+#define BIFP3_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
+#define BIFP3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
+#define BIFP3_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
+#define BIFP3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
+#define BIFP3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
+#define BIFP3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
+#define BIFP3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
+#define BIFP3_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
+#define BIFP3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
+#define BIFP3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
+#define BIFP3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
+#define BIFP3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
+#define BIFP3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
+#define BIFP3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
+#define BIFP3_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT 0x17
+#define BIFP3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
+#define BIFP3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
+#define BIFP3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
+#define BIFP3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L
+#define BIFP3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x00000004L
+#define BIFP3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x00000008L
+#define BIFP3_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x00000010L
+#define BIFP3_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x00000020L
+#define BIFP3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L
+#define BIFP3_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L
+#define BIFP3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x00000300L
+#define BIFP3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L
+#define BIFP3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x00000800L
+#define BIFP3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x00001000L
+#define BIFP3_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L
+#define BIFP3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L
+#define BIFP3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x00008000L
+#define BIFP3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x00010000L
+#define BIFP3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x00020000L
+#define BIFP3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x003C0000L
+#define BIFP3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L
+#define BIFP3_PCIE_LC_CNTL4__LC_TX_SWING_MASK 0x00800000L
+#define BIFP3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L
+#define BIFP3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L
+#define BIFP3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xFC000000L
+//BIFP3_PCIE_LC_CNTL5
+#define BIFP3_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
+#define BIFP3_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
+#define BIFP3_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
+#define BIFP3_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
+#define BIFP3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
+#define BIFP3_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT 0x19
+#define BIFP3_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT 0x1a
+#define BIFP3_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT 0x1b
+#define BIFP3_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT 0x1c
+#define BIFP3_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT 0x1d
+#define BIFP3_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x0000003FL
+#define BIFP3_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0x00000FC0L
+#define BIFP3_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x0003F000L
+#define BIFP3_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0x00FC0000L
+#define BIFP3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x01000000L
+#define BIFP3_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK 0x02000000L
+#define BIFP3_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK 0x04000000L
+#define BIFP3_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK 0x08000000L
+#define BIFP3_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK 0x10000000L
+#define BIFP3_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK 0xE0000000L
+//BIFP3_PCIE_LC_FORCE_COEFF
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x00000001L
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x0000007EL
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x00001F80L
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x0007E000L
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x00080000L
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x00100000L
+//BIFP3_PCIE_LC_BEST_EQ_SETTINGS
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000FL
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003F0L
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000FC00L
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003F0000L
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3FC00000L
+//BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x00000001L
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x0000007EL
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x00001F80L
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x0007E000L
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x01F80000L
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7E000000L
+//BIFP3_PCIE_LC_CNTL6
+#define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
+#define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
+#define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
+#define BIFP3_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT 0x5
+#define BIFP3_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT 0x6
+#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT 0x8
+#define BIFP3_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT 0x9
+#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT 0xd
+#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT 0xe
+#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT 0x10
+#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT 0x12
+#define BIFP3_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT 0x13
+#define BIFP3_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT 0x14
+#define BIFP3_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT 0x15
+#define BIFP3_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT 0x16
+#define BIFP3_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT 0x17
+#define BIFP3_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT 0x18
+#define BIFP3_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT 0x1f
+#define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x00000001L
+#define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x00000004L
+#define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x00000010L
+#define BIFP3_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK 0x00000020L
+#define BIFP3_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK 0x000000C0L
+#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_EN_MASK 0x00000100L
+#define BIFP3_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK 0x00001E00L
+#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK 0x00002000L
+#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK 0x0000C000L
+#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK 0x00030000L
+#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK 0x00040000L
+#define BIFP3_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK 0x00080000L
+#define BIFP3_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK 0x00100000L
+#define BIFP3_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L
+#define BIFP3_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK 0x00400000L
+#define BIFP3_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK 0x00800000L
+#define BIFP3_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK 0x7F000000L
+#define BIFP3_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK 0x80000000L
+//BIFP3_PCIE_LC_CNTL7
+#define BIFP3_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT 0x0
+#define BIFP3_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT 0x1
+#define BIFP3_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT 0x2
+#define BIFP3_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT 0x3
+#define BIFP3_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT 0x4
+#define BIFP3_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT 0x5
+#define BIFP3_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT 0x6
+#define BIFP3_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT 0x7
+#define BIFP3_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT 0x8
+#define BIFP3_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT 0x9
+#define BIFP3_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT 0xa
+#define BIFP3_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT 0xb
+#define BIFP3_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT 0xc
+#define BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT 0xd
+#define BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT 0x15
+#define BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT 0x16
+#define BIFP3_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT 0x17
+#define BIFP3_PCIE_LC_CNTL7__LC_FOM_TIME__SHIFT 0x18
+#define BIFP3_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH__SHIFT 0x1a
+#define BIFP3_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT 0x1b
+#define BIFP3_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT 0x1c
+#define BIFP3_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT 0x1d
+#define BIFP3_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT 0x1e
+#define BIFP3_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT 0x1f
+#define BIFP3_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK 0x00000001L
+#define BIFP3_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK 0x00000002L
+#define BIFP3_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK 0x00000004L
+#define BIFP3_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK 0x00000008L
+#define BIFP3_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK 0x00000010L
+#define BIFP3_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK 0x00000020L
+#define BIFP3_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK 0x00000040L
+#define BIFP3_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK 0x00000080L
+#define BIFP3_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK 0x00000100L
+#define BIFP3_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK 0x00000200L
+#define BIFP3_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK 0x00000400L
+#define BIFP3_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK 0x00000800L
+#define BIFP3_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK 0x00001000L
+#define BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK 0x001FE000L
+#define BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK 0x00200000L
+#define BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK 0x00400000L
+#define BIFP3_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK 0x00800000L
+#define BIFP3_PCIE_LC_CNTL7__LC_FOM_TIME_MASK 0x03000000L
+#define BIFP3_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH_MASK 0x04000000L
+#define BIFP3_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK 0x08000000L
+#define BIFP3_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK 0x10000000L
+#define BIFP3_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK 0x20000000L
+#define BIFP3_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK 0x40000000L
+#define BIFP3_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN_MASK 0x80000000L
+//BIFP3_PCIE_LINK_MANAGEMENT_STATUS
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT 0x0
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x1
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT 0x2
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT 0x3
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT 0x4
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT 0x5
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT 0x6
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT 0x7
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT 0x8
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT 0x9
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT 0xa
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT 0xb
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT 0xc
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT 0xd
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK 0x00000001L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000002L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 0x00000004L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK 0x00000008L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 0x00000010L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 0x00000020L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK 0x00000040L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK 0x00000080L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK 0x00000100L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK 0x00000200L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK 0x00000400L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK 0x00000800L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK 0x00001000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK 0x00002000L
+//BIFP3_PCIE_LINK_MANAGEMENT_MASK
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT 0x0
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x1
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT 0x2
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT 0x3
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x4
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT 0x5
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT 0x6
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT 0x7
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT 0x8
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT 0x9
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT 0xa
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT 0xb
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT 0xc
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT 0xd
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK 0x00000001L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000002L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK 0x00000004L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK 0x00000008L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000010L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK 0x00000020L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK 0x00000040L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK 0x00000080L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK 0x00000100L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK 0x00000200L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK 0x00000400L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK 0x00000800L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK 0x00001000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK 0x00002000L
+//BIFP3_PCIE_LINK_MANAGEMENT_CNTL
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT 0x0
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT 0x3
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT 0x7
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT 0xb
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT 0xc
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT 0xd
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT 0xf
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT 0x11
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT 0x12
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT 0x13
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT 0x17
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT 0x1b
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK 0x00000007L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK 0x00000078L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK 0x00000780L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK 0x00000800L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK 0x00001000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK 0x00006000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK 0x00018000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK 0x00020000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK 0x00040000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK 0x00780000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK 0x07800000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK 0x38000000L
+//BIFP3_PCIEP_STRAP_LC
+#define BIFP3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
+#define BIFP3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
+#define BIFP3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
+#define BIFP3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
+#define BIFP3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
+#define BIFP3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
+#define BIFP3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
+#define BIFP3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
+#define BIFP3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
+#define BIFP3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
+#define BIFP3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
+#define BIFP3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000CL
+#define BIFP3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000C0L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L
+//BIFP3_PCIEP_STRAP_MISC
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x00000020L
+//BIFP3_PCIE_LC_L1_PM_SUBSTATE
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT 0x0
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT 0x1
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT 0x2
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT 0x3
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT 0x4
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT 0x6
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT 0x8
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT 0x10
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT 0x14
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT 0x17
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK 0x000000C0L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK 0x00001F00L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK 0x00070000L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK 0x00700000L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK 0x03800000L
+//BIFP3_PCIE_LC_L1_PM_SUBSTATE2
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT 0x0
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT 0x8
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK 0x000000FFL
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK 0x00000700L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK 0x03FF0000L
+//BIFP3_PCIE_LC_PORT_ORDER
+#define BIFP3_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT 0x0
+#define BIFP3_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK 0x0000000FL
+//BIFP3_PCIEP_BCH_ECC_CNTL
+#define BIFP3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
+#define BIFP3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
+#define BIFP3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
+#define BIFP3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x00000001L
+#define BIFP3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0x0000FF00L
+#define BIFP3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xFFFF0000L
+//BIFP3_PCIEP_HPGI_PRIVATE
+#define BIFP3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
+#define BIFP3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
+#define BIFP3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x00000008L
+#define BIFP3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x00000040L
+//BIFP3_PCIEP_HPGI
+#define BIFP3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
+#define BIFP3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
+#define BIFP3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
+#define BIFP3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
+#define BIFP3_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
+#define BIFP3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
+#define BIFP3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
+#define BIFP3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
+#define BIFP3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
+#define BIFP3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
+#define BIFP3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
+#define BIFP3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x00000001L
+#define BIFP3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x00000002L
+#define BIFP3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x00000004L
+#define BIFP3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x00000008L
+#define BIFP3_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x00000080L
+#define BIFP3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x00000100L
+#define BIFP3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x00000200L
+#define BIFP3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x00000400L
+#define BIFP3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x00000800L
+#define BIFP3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x00008000L
+#define BIFP3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x00010000L
+//BIFP3_PCIEP_HCNT_DESCRIPTOR
+#define BIFP3_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT 0x0
+#define BIFP3_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT 0x1f
+#define BIFP3_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK 0x0000003FL
+#define BIFP3_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK 0x80000000L
+//BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK
+#define BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT 0x0
+#define BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT 0x10
+#define BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL
+#define BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L
+
+
+// addressBlock: nbio_pcie0_bifp4_pciedir_p
+//BIFP4_PCIEP_RESERVED
+#define BIFP4_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define BIFP4_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL
+//BIFP4_PCIEP_SCRATCH
+#define BIFP4_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
+#define BIFP4_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xFFFFFFFFL
+//BIFP4_PCIEP_PORT_CNTL
+#define BIFP4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
+#define BIFP4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
+#define BIFP4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
+#define BIFP4_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
+#define BIFP4_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
+#define BIFP4_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
+#define BIFP4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
+#define BIFP4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
+#define BIFP4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
+#define BIFP4_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT 0x18
+#define BIFP4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L
+#define BIFP4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L
+#define BIFP4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L
+#define BIFP4_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L
+#define BIFP4_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L
+#define BIFP4_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L
+#define BIFP4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x00007F00L
+#define BIFP4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x00030000L
+#define BIFP4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x001C0000L
+#define BIFP4_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK 0x03000000L
+//BIFP4_PCIE_TX_CNTL
+#define BIFP4_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define BIFP4_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define BIFP4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
+#define BIFP4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
+#define BIFP4_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
+#define BIFP4_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
+#define BIFP4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
+#define BIFP4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
+#define BIFP4_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define BIFP4_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define BIFP4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L
+#define BIFP4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L
+#define BIFP4_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L
+#define BIFP4_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L
+#define BIFP4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L
+#define BIFP4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L
+//BIFP4_PCIE_TX_REQUESTER_ID
+#define BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//BIFP4_PCIE_TX_VENDOR_SPECIFIC
+#define BIFP4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
+#define BIFP4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00FFFFFFL
+//BIFP4_PCIE_TX_REQUEST_NUM_CNTL
+#define BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
+#define BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
+#define BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
+#define BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3F000000L
+#define BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L
+#define BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L
+//BIFP4_PCIE_TX_SEQ
+#define BIFP4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
+#define BIFP4_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
+#define BIFP4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000FFFL
+#define BIFP4_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0FFF0000L
+//BIFP4_PCIE_TX_REPLAY
+#define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
+#define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
+#define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
+#define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L
+#define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L
+#define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xFFFF0000L
+//BIFP4_PCIE_TX_ACK_LATENCY_LIMIT
+#define BIFP4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
+#define BIFP4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
+#define BIFP4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000FFFL
+#define BIFP4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L
+//BIFP4_PCIE_TX_CREDITS_ADVT_P
+#define BIFP4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
+#define BIFP4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
+#define BIFP4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00000FFFL
+#define BIFP4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x00FF0000L
+//BIFP4_PCIE_TX_CREDITS_ADVT_NP
+#define BIFP4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
+#define BIFP4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
+#define BIFP4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00000FFFL
+#define BIFP4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x00FF0000L
+//BIFP4_PCIE_TX_CREDITS_ADVT_CPL
+#define BIFP4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
+#define BIFP4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
+#define BIFP4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00000FFFL
+#define BIFP4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x00FF0000L
+//BIFP4_PCIE_TX_CREDITS_INIT_P
+#define BIFP4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
+#define BIFP4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
+#define BIFP4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000FFFL
+#define BIFP4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00FF0000L
+//BIFP4_PCIE_TX_CREDITS_INIT_NP
+#define BIFP4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
+#define BIFP4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
+#define BIFP4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000FFFL
+#define BIFP4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00FF0000L
+//BIFP4_PCIE_TX_CREDITS_INIT_CPL
+#define BIFP4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
+#define BIFP4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
+#define BIFP4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000FFFL
+#define BIFP4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00FF0000L
+//BIFP4_PCIE_TX_CREDITS_STATUS
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L
+//BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L
+//BIFP4_PCIE_P_PORT_LANE_STATUS
+#define BIFP4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
+#define BIFP4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
+#define BIFP4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L
+#define BIFP4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007EL
+//BIFP4_PCIE_FC_P
+#define BIFP4_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
+#define BIFP4_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
+#define BIFP4_PCIE_FC_P__PD_CREDITS_MASK 0x000000FFL
+#define BIFP4_PCIE_FC_P__PH_CREDITS_MASK 0x0000FF00L
+//BIFP4_PCIE_FC_NP
+#define BIFP4_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
+#define BIFP4_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
+#define BIFP4_PCIE_FC_NP__NPD_CREDITS_MASK 0x000000FFL
+#define BIFP4_PCIE_FC_NP__NPH_CREDITS_MASK 0x0000FF00L
+//BIFP4_PCIE_FC_CPL
+#define BIFP4_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
+#define BIFP4_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
+#define BIFP4_PCIE_FC_CPL__CPLD_CREDITS_MASK 0x000000FFL
+#define BIFP4_PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0000FF00L
+//BIFP4_PCIE_ERR_CNTL
+#define BIFP4_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define BIFP4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
+#define BIFP4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
+#define BIFP4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
+#define BIFP4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
+#define BIFP4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
+#define BIFP4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
+#define BIFP4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define BIFP4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define BIFP4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
+#define BIFP4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
+#define BIFP4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
+#define BIFP4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define BIFP4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define BIFP4_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define BIFP4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L
+#define BIFP4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x00000004L
+#define BIFP4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L
+#define BIFP4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L
+#define BIFP4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L
+#define BIFP4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L
+#define BIFP4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define BIFP4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define BIFP4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L
+#define BIFP4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L
+#define BIFP4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L
+#define BIFP4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define BIFP4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+//BIFP4_PCIE_RX_CNTL
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
+#define BIFP4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
+#define BIFP4_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
+#define BIFP4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
+#define BIFP4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
+#define BIFP4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
+#define BIFP4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define BIFP4_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define BIFP4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L
+#define BIFP4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L
+#define BIFP4_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x00004000L
+#define BIFP4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L
+#define BIFP4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L
+#define BIFP4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L
+#define BIFP4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define BIFP4_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+#define BIFP4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+//BIFP4_PCIE_RX_EXPECTED_SEQNUM
+#define BIFP4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
+#define BIFP4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000FFFL
+//BIFP4_PCIE_RX_VENDOR_SPECIFIC
+#define BIFP4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
+#define BIFP4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
+#define BIFP4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00FFFFFFL
+#define BIFP4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L
+//BIFP4_PCIE_RX_CNTL3
+#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
+#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
+#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
+#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
+#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
+#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L
+#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L
+#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L
+#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L
+#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L
+//BIFP4_PCIE_RX_CREDITS_ALLOCATED_P
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000FFFL
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00FF0000L
+//BIFP4_PCIE_RX_CREDITS_ALLOCATED_NP
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000FFFL
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00FF0000L
+//BIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000FFFL
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00FF0000L
+//BIFP4_PCIEP_ERROR_INJECT_PHYSICAL
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x00000003L
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0x0000000CL
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x00000030L
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0x000000C0L
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x00000300L
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0x00000C00L
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x00003000L
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0x0000C000L
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x00030000L
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0x000C0000L
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x00300000L
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0x00C00000L
+//BIFP4_PCIEP_ERROR_INJECT_TRANSACTION
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x00000003L
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0x0000000CL
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x00000030L
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0x000000C0L
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x00000300L
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0x00000C00L
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x00003000L
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0x0000C000L
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x00030000L
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0x000C0000L
+//BIFP4_PCIEP_NAK_COUNTER
+#define BIFP4_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT 0x0
+#define BIFP4_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT 0x10
+#define BIFP4_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK 0x0000FFFFL
+#define BIFP4_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK 0xFFFF0000L
+//BIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS__SHIFT 0x0
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK__SHIFT 0x8
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK__SHIFT 0x9
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS_MASK 0x00000001L
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK_MASK 0x00000100L
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK_MASK 0x00000200L
+//BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT 0x0
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT 0xa
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT 0xf
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT 0x1a
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT 0x1f
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK 0x000003FFL
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK 0x00001C00L
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK 0x00008000L
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK 0x1C000000L
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK 0x80000000L
+//BIFP4_PCIE_LC_CNTL
+#define BIFP4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
+#define BIFP4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
+#define BIFP4_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
+#define BIFP4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
+#define BIFP4_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
+#define BIFP4_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
+#define BIFP4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
+#define BIFP4_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
+#define BIFP4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
+#define BIFP4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
+#define BIFP4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
+#define BIFP4_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
+#define BIFP4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
+#define BIFP4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
+#define BIFP4_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
+#define BIFP4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
+#define BIFP4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
+#define BIFP4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
+#define BIFP4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
+#define BIFP4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
+#define BIFP4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L
+#define BIFP4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L
+#define BIFP4_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L
+#define BIFP4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000F0L
+#define BIFP4_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000F00L
+#define BIFP4_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000F000L
+#define BIFP4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L
+#define BIFP4_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L
+#define BIFP4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000C0000L
+#define BIFP4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L
+#define BIFP4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L
+#define BIFP4_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L
+#define BIFP4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L
+#define BIFP4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L
+#define BIFP4_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L
+#define BIFP4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L
+#define BIFP4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L
+#define BIFP4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L
+#define BIFP4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L
+#define BIFP4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L
+//BIFP4_PCIE_LC_TRAINING_CNTL
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000FL
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x00004000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x00008000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00C00000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xC0000000L
+//BIFP4_PCIE_LC_LINK_WIDTH_CNTL
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT 0x1e
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT 0x1f
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x00010000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x01000000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x02000000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x04000000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x08000000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK 0x40000000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK 0x80000000L
+//BIFP4_PCIE_LC_N_FTS_CNTL
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT 0xf
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000FFL
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK 0x00008000L
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00FF0000L
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xFF000000L
+//BIFP4_PCIE_LC_SPEED_CNTL
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000004L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000018L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000020L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000040L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000080L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000100L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000200L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00000C00L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00001000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x00006000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00008000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00010000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00020000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00040000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00080000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00100000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00200000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x00400000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x00800000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x03000000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x04000000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x08000000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000L
+//BIFP4_PCIE_LC_STATE0
+#define BIFP4_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
+#define BIFP4_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
+#define BIFP4_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
+#define BIFP4_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
+#define BIFP4_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003FL
+#define BIFP4_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003F00L
+#define BIFP4_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003F0000L
+#define BIFP4_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3F000000L
+//BIFP4_PCIE_LC_STATE1
+#define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
+#define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
+#define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
+#define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
+#define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003FL
+#define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003F00L
+#define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003F0000L
+#define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3F000000L
+//BIFP4_PCIE_LC_STATE2
+#define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
+#define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
+#define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
+#define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
+#define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003FL
+#define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003F00L
+#define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003F0000L
+#define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3F000000L
+//BIFP4_PCIE_LC_STATE3
+#define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
+#define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
+#define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
+#define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
+#define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003FL
+#define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003F00L
+#define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003F0000L
+#define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3F000000L
+//BIFP4_PCIE_LC_STATE4
+#define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
+#define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
+#define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
+#define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
+#define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003FL
+#define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003F00L
+#define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003F0000L
+#define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3F000000L
+//BIFP4_PCIE_LC_STATE5
+#define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
+#define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
+#define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
+#define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
+#define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003FL
+#define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003F00L
+#define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003F0000L
+#define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3F000000L
+//BIFP4_PCIE_LINK_MANAGEMENT_CNTL2
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT 0x0
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT 0x1
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT 0x2
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT 0x3
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT 0x4
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT 0x7
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT 0xb
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT 0xf
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT 0x13
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK 0x00000001L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK 0x00000002L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK 0x00000004L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK 0x00000008L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK 0x00000070L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK 0x00000780L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK 0x00007800L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK 0x00078000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK 0x00780000L
+//BIFP4_PCIE_LC_CNTL2
+#define BIFP4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
+#define BIFP4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
+#define BIFP4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
+#define BIFP4_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
+#define BIFP4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
+#define BIFP4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
+#define BIFP4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
+#define BIFP4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
+#define BIFP4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
+#define BIFP4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
+#define BIFP4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
+#define BIFP4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
+#define BIFP4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
+#define BIFP4_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
+#define BIFP4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
+#define BIFP4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
+#define BIFP4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
+#define BIFP4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
+#define BIFP4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
+#define BIFP4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
+#define BIFP4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define BIFP4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
+#define BIFP4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
+#define BIFP4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
+#define BIFP4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003FL
+#define BIFP4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L
+#define BIFP4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L
+#define BIFP4_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L
+#define BIFP4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L
+#define BIFP4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L
+#define BIFP4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L
+#define BIFP4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L
+#define BIFP4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L
+#define BIFP4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000C000L
+#define BIFP4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L
+#define BIFP4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L
+#define BIFP4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L
+#define BIFP4_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x00080000L
+#define BIFP4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L
+#define BIFP4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L
+#define BIFP4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L
+#define BIFP4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L
+#define BIFP4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L
+#define BIFP4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L
+#define BIFP4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+#define BIFP4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L
+#define BIFP4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L
+#define BIFP4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L
+//BIFP4_PCIE_LC_BW_CHANGE_CNTL
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT 0xb
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK 0x00000800L
+//BIFP4_PCIE_LC_CDR_CNTL
+#define BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
+#define BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
+#define BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
+#define BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000FFFL
+#define BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00FFF000L
+#define BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L
+//BIFP4_PCIE_LC_LANE_CNTL
+#define BIFP4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
+#define BIFP4_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
+#define BIFP4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000FFFFL
+#define BIFP4_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xFFFF0000L
+//BIFP4_PCIE_LC_CNTL3
+#define BIFP4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
+#define BIFP4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
+#define BIFP4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
+#define BIFP4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
+#define BIFP4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
+#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
+#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
+#define BIFP4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
+#define BIFP4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
+#define BIFP4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
+#define BIFP4_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
+#define BIFP4_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
+#define BIFP4_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
+#define BIFP4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
+#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
+#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
+#define BIFP4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
+#define BIFP4_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
+#define BIFP4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
+#define BIFP4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
+#define BIFP4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
+#define BIFP4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
+#define BIFP4_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
+#define BIFP4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L
+#define BIFP4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L
+#define BIFP4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L
+#define BIFP4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L
+#define BIFP4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L
+#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000C0L
+#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L
+#define BIFP4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L
+#define BIFP4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L
+#define BIFP4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L
+#define BIFP4_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x00003000L
+#define BIFP4_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0x0000C000L
+#define BIFP4_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x00010000L
+#define BIFP4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L
+#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L
+#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L
+#define BIFP4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L
+#define BIFP4_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x00400000L
+#define BIFP4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L
+#define BIFP4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L
+#define BIFP4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3C000000L
+#define BIFP4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L
+#define BIFP4_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000L
+//BIFP4_PCIE_LC_CNTL4
+#define BIFP4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
+#define BIFP4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
+#define BIFP4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
+#define BIFP4_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
+#define BIFP4_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
+#define BIFP4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
+#define BIFP4_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
+#define BIFP4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
+#define BIFP4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
+#define BIFP4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
+#define BIFP4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
+#define BIFP4_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
+#define BIFP4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
+#define BIFP4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
+#define BIFP4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
+#define BIFP4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
+#define BIFP4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
+#define BIFP4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
+#define BIFP4_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT 0x17
+#define BIFP4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
+#define BIFP4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
+#define BIFP4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
+#define BIFP4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L
+#define BIFP4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x00000004L
+#define BIFP4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x00000008L
+#define BIFP4_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x00000010L
+#define BIFP4_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x00000020L
+#define BIFP4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L
+#define BIFP4_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L
+#define BIFP4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x00000300L
+#define BIFP4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L
+#define BIFP4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x00000800L
+#define BIFP4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x00001000L
+#define BIFP4_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L
+#define BIFP4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L
+#define BIFP4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x00008000L
+#define BIFP4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x00010000L
+#define BIFP4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x00020000L
+#define BIFP4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x003C0000L
+#define BIFP4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L
+#define BIFP4_PCIE_LC_CNTL4__LC_TX_SWING_MASK 0x00800000L
+#define BIFP4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L
+#define BIFP4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L
+#define BIFP4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xFC000000L
+//BIFP4_PCIE_LC_CNTL5
+#define BIFP4_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
+#define BIFP4_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
+#define BIFP4_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
+#define BIFP4_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
+#define BIFP4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
+#define BIFP4_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT 0x19
+#define BIFP4_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT 0x1a
+#define BIFP4_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT 0x1b
+#define BIFP4_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT 0x1c
+#define BIFP4_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT 0x1d
+#define BIFP4_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x0000003FL
+#define BIFP4_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0x00000FC0L
+#define BIFP4_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x0003F000L
+#define BIFP4_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0x00FC0000L
+#define BIFP4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x01000000L
+#define BIFP4_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK 0x02000000L
+#define BIFP4_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK 0x04000000L
+#define BIFP4_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK 0x08000000L
+#define BIFP4_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK 0x10000000L
+#define BIFP4_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK 0xE0000000L
+//BIFP4_PCIE_LC_FORCE_COEFF
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x00000001L
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x0000007EL
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x00001F80L
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x0007E000L
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x00080000L
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x00100000L
+//BIFP4_PCIE_LC_BEST_EQ_SETTINGS
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000FL
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003F0L
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000FC00L
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003F0000L
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3FC00000L
+//BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x00000001L
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x0000007EL
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x00001F80L
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x0007E000L
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x01F80000L
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7E000000L
+//BIFP4_PCIE_LC_CNTL6
+#define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
+#define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
+#define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
+#define BIFP4_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT 0x5
+#define BIFP4_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT 0x6
+#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT 0x8
+#define BIFP4_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT 0x9
+#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT 0xd
+#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT 0xe
+#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT 0x10
+#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT 0x12
+#define BIFP4_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT 0x13
+#define BIFP4_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT 0x14
+#define BIFP4_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT 0x15
+#define BIFP4_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT 0x16
+#define BIFP4_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT 0x17
+#define BIFP4_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT 0x18
+#define BIFP4_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT 0x1f
+#define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x00000001L
+#define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x00000004L
+#define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x00000010L
+#define BIFP4_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK 0x00000020L
+#define BIFP4_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK 0x000000C0L
+#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_EN_MASK 0x00000100L
+#define BIFP4_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK 0x00001E00L
+#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK 0x00002000L
+#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK 0x0000C000L
+#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK 0x00030000L
+#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK 0x00040000L
+#define BIFP4_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK 0x00080000L
+#define BIFP4_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK 0x00100000L
+#define BIFP4_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L
+#define BIFP4_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK 0x00400000L
+#define BIFP4_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK 0x00800000L
+#define BIFP4_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK 0x7F000000L
+#define BIFP4_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK 0x80000000L
+//BIFP4_PCIE_LC_CNTL7
+#define BIFP4_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT 0x0
+#define BIFP4_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT 0x1
+#define BIFP4_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT 0x2
+#define BIFP4_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT 0x3
+#define BIFP4_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT 0x4
+#define BIFP4_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT 0x5
+#define BIFP4_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT 0x6
+#define BIFP4_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT 0x7
+#define BIFP4_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT 0x8
+#define BIFP4_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT 0x9
+#define BIFP4_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT 0xa
+#define BIFP4_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT 0xb
+#define BIFP4_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT 0xc
+#define BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT 0xd
+#define BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT 0x15
+#define BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT 0x16
+#define BIFP4_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT 0x17
+#define BIFP4_PCIE_LC_CNTL7__LC_FOM_TIME__SHIFT 0x18
+#define BIFP4_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH__SHIFT 0x1a
+#define BIFP4_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT 0x1b
+#define BIFP4_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT 0x1c
+#define BIFP4_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT 0x1d
+#define BIFP4_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT 0x1e
+#define BIFP4_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT 0x1f
+#define BIFP4_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK 0x00000001L
+#define BIFP4_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK 0x00000002L
+#define BIFP4_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK 0x00000004L
+#define BIFP4_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK 0x00000008L
+#define BIFP4_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK 0x00000010L
+#define BIFP4_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK 0x00000020L
+#define BIFP4_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK 0x00000040L
+#define BIFP4_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK 0x00000080L
+#define BIFP4_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK 0x00000100L
+#define BIFP4_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK 0x00000200L
+#define BIFP4_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK 0x00000400L
+#define BIFP4_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK 0x00000800L
+#define BIFP4_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK 0x00001000L
+#define BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK 0x001FE000L
+#define BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK 0x00200000L
+#define BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK 0x00400000L
+#define BIFP4_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK 0x00800000L
+#define BIFP4_PCIE_LC_CNTL7__LC_FOM_TIME_MASK 0x03000000L
+#define BIFP4_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH_MASK 0x04000000L
+#define BIFP4_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK 0x08000000L
+#define BIFP4_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK 0x10000000L
+#define BIFP4_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK 0x20000000L
+#define BIFP4_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK 0x40000000L
+#define BIFP4_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN_MASK 0x80000000L
+//BIFP4_PCIE_LINK_MANAGEMENT_STATUS
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT 0x0
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x1
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT 0x2
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT 0x3
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT 0x4
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT 0x5
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT 0x6
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT 0x7
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT 0x8
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT 0x9
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT 0xa
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT 0xb
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT 0xc
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT 0xd
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK 0x00000001L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000002L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 0x00000004L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK 0x00000008L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 0x00000010L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 0x00000020L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK 0x00000040L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK 0x00000080L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK 0x00000100L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK 0x00000200L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK 0x00000400L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK 0x00000800L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK 0x00001000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK 0x00002000L
+//BIFP4_PCIE_LINK_MANAGEMENT_MASK
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT 0x0
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x1
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT 0x2
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT 0x3
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x4
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT 0x5
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT 0x6
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT 0x7
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT 0x8
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT 0x9
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT 0xa
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT 0xb
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT 0xc
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT 0xd
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK 0x00000001L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000002L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK 0x00000004L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK 0x00000008L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000010L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK 0x00000020L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK 0x00000040L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK 0x00000080L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK 0x00000100L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK 0x00000200L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK 0x00000400L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK 0x00000800L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK 0x00001000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK 0x00002000L
+//BIFP4_PCIE_LINK_MANAGEMENT_CNTL
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT 0x0
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT 0x3
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT 0x7
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT 0xb
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT 0xc
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT 0xd
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT 0xf
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT 0x11
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT 0x12
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT 0x13
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT 0x17
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT 0x1b
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK 0x00000007L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK 0x00000078L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK 0x00000780L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK 0x00000800L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK 0x00001000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK 0x00006000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK 0x00018000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK 0x00020000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK 0x00040000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK 0x00780000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK 0x07800000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK 0x38000000L
+//BIFP4_PCIEP_STRAP_LC
+#define BIFP4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
+#define BIFP4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
+#define BIFP4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
+#define BIFP4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
+#define BIFP4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
+#define BIFP4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
+#define BIFP4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
+#define BIFP4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
+#define BIFP4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
+#define BIFP4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
+#define BIFP4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
+#define BIFP4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000CL
+#define BIFP4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000C0L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L
+//BIFP4_PCIEP_STRAP_MISC
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x00000020L
+//BIFP4_PCIE_LC_L1_PM_SUBSTATE
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT 0x0
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT 0x1
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT 0x2
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT 0x3
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT 0x4
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT 0x6
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT 0x8
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT 0x10
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT 0x14
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT 0x17
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK 0x000000C0L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK 0x00001F00L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK 0x00070000L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK 0x00700000L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK 0x03800000L
+//BIFP4_PCIE_LC_L1_PM_SUBSTATE2
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT 0x0
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT 0x8
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK 0x000000FFL
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK 0x00000700L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK 0x03FF0000L
+//BIFP4_PCIE_LC_PORT_ORDER
+#define BIFP4_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT 0x0
+#define BIFP4_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK 0x0000000FL
+//BIFP4_PCIEP_BCH_ECC_CNTL
+#define BIFP4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
+#define BIFP4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
+#define BIFP4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
+#define BIFP4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x00000001L
+#define BIFP4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0x0000FF00L
+#define BIFP4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xFFFF0000L
+//BIFP4_PCIEP_HPGI_PRIVATE
+#define BIFP4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
+#define BIFP4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
+#define BIFP4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x00000008L
+#define BIFP4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x00000040L
+//BIFP4_PCIEP_HPGI
+#define BIFP4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
+#define BIFP4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
+#define BIFP4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
+#define BIFP4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
+#define BIFP4_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
+#define BIFP4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
+#define BIFP4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
+#define BIFP4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
+#define BIFP4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
+#define BIFP4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
+#define BIFP4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
+#define BIFP4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x00000001L
+#define BIFP4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x00000002L
+#define BIFP4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x00000004L
+#define BIFP4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x00000008L
+#define BIFP4_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x00000080L
+#define BIFP4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x00000100L
+#define BIFP4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x00000200L
+#define BIFP4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x00000400L
+#define BIFP4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x00000800L
+#define BIFP4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x00008000L
+#define BIFP4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x00010000L
+//BIFP4_PCIEP_HCNT_DESCRIPTOR
+#define BIFP4_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT 0x0
+#define BIFP4_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT 0x1f
+#define BIFP4_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK 0x0000003FL
+#define BIFP4_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK 0x80000000L
+//BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK
+#define BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT 0x0
+#define BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT 0x10
+#define BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL
+#define BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L
+
+
+// addressBlock: nbio_pcie0_bifp5_pciedir_p
+//BIFP5_PCIEP_RESERVED
+#define BIFP5_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define BIFP5_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL
+//BIFP5_PCIEP_SCRATCH
+#define BIFP5_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
+#define BIFP5_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xFFFFFFFFL
+//BIFP5_PCIEP_PORT_CNTL
+#define BIFP5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
+#define BIFP5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
+#define BIFP5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
+#define BIFP5_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
+#define BIFP5_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
+#define BIFP5_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
+#define BIFP5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
+#define BIFP5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
+#define BIFP5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
+#define BIFP5_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT 0x18
+#define BIFP5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L
+#define BIFP5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L
+#define BIFP5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L
+#define BIFP5_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L
+#define BIFP5_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L
+#define BIFP5_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L
+#define BIFP5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x00007F00L
+#define BIFP5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x00030000L
+#define BIFP5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x001C0000L
+#define BIFP5_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK 0x03000000L
+//BIFP5_PCIE_TX_CNTL
+#define BIFP5_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define BIFP5_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define BIFP5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
+#define BIFP5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
+#define BIFP5_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
+#define BIFP5_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
+#define BIFP5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
+#define BIFP5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
+#define BIFP5_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define BIFP5_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define BIFP5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L
+#define BIFP5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L
+#define BIFP5_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L
+#define BIFP5_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L
+#define BIFP5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L
+#define BIFP5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L
+//BIFP5_PCIE_TX_REQUESTER_ID
+#define BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//BIFP5_PCIE_TX_VENDOR_SPECIFIC
+#define BIFP5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
+#define BIFP5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00FFFFFFL
+//BIFP5_PCIE_TX_REQUEST_NUM_CNTL
+#define BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
+#define BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
+#define BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
+#define BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3F000000L
+#define BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L
+#define BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L
+//BIFP5_PCIE_TX_SEQ
+#define BIFP5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
+#define BIFP5_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
+#define BIFP5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000FFFL
+#define BIFP5_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0FFF0000L
+//BIFP5_PCIE_TX_REPLAY
+#define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
+#define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
+#define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
+#define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L
+#define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L
+#define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xFFFF0000L
+//BIFP5_PCIE_TX_ACK_LATENCY_LIMIT
+#define BIFP5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
+#define BIFP5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
+#define BIFP5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000FFFL
+#define BIFP5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L
+//BIFP5_PCIE_TX_CREDITS_ADVT_P
+#define BIFP5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
+#define BIFP5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
+#define BIFP5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00000FFFL
+#define BIFP5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x00FF0000L
+//BIFP5_PCIE_TX_CREDITS_ADVT_NP
+#define BIFP5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
+#define BIFP5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
+#define BIFP5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00000FFFL
+#define BIFP5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x00FF0000L
+//BIFP5_PCIE_TX_CREDITS_ADVT_CPL
+#define BIFP5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
+#define BIFP5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
+#define BIFP5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00000FFFL
+#define BIFP5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x00FF0000L
+//BIFP5_PCIE_TX_CREDITS_INIT_P
+#define BIFP5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
+#define BIFP5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
+#define BIFP5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000FFFL
+#define BIFP5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00FF0000L
+//BIFP5_PCIE_TX_CREDITS_INIT_NP
+#define BIFP5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
+#define BIFP5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
+#define BIFP5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000FFFL
+#define BIFP5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00FF0000L
+//BIFP5_PCIE_TX_CREDITS_INIT_CPL
+#define BIFP5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
+#define BIFP5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
+#define BIFP5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000FFFL
+#define BIFP5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00FF0000L
+//BIFP5_PCIE_TX_CREDITS_STATUS
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L
+//BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L
+//BIFP5_PCIE_P_PORT_LANE_STATUS
+#define BIFP5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
+#define BIFP5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
+#define BIFP5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L
+#define BIFP5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007EL
+//BIFP5_PCIE_FC_P
+#define BIFP5_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
+#define BIFP5_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
+#define BIFP5_PCIE_FC_P__PD_CREDITS_MASK 0x000000FFL
+#define BIFP5_PCIE_FC_P__PH_CREDITS_MASK 0x0000FF00L
+//BIFP5_PCIE_FC_NP
+#define BIFP5_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
+#define BIFP5_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
+#define BIFP5_PCIE_FC_NP__NPD_CREDITS_MASK 0x000000FFL
+#define BIFP5_PCIE_FC_NP__NPH_CREDITS_MASK 0x0000FF00L
+//BIFP5_PCIE_FC_CPL
+#define BIFP5_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
+#define BIFP5_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
+#define BIFP5_PCIE_FC_CPL__CPLD_CREDITS_MASK 0x000000FFL
+#define BIFP5_PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0000FF00L
+//BIFP5_PCIE_ERR_CNTL
+#define BIFP5_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define BIFP5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
+#define BIFP5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
+#define BIFP5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
+#define BIFP5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
+#define BIFP5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
+#define BIFP5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
+#define BIFP5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define BIFP5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define BIFP5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
+#define BIFP5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
+#define BIFP5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
+#define BIFP5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define BIFP5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define BIFP5_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define BIFP5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L
+#define BIFP5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x00000004L
+#define BIFP5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L
+#define BIFP5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L
+#define BIFP5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L
+#define BIFP5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L
+#define BIFP5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define BIFP5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define BIFP5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L
+#define BIFP5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L
+#define BIFP5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L
+#define BIFP5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define BIFP5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+//BIFP5_PCIE_RX_CNTL
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
+#define BIFP5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
+#define BIFP5_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
+#define BIFP5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
+#define BIFP5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
+#define BIFP5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
+#define BIFP5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define BIFP5_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define BIFP5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L
+#define BIFP5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L
+#define BIFP5_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x00004000L
+#define BIFP5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L
+#define BIFP5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L
+#define BIFP5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L
+#define BIFP5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define BIFP5_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+#define BIFP5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+//BIFP5_PCIE_RX_EXPECTED_SEQNUM
+#define BIFP5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
+#define BIFP5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000FFFL
+//BIFP5_PCIE_RX_VENDOR_SPECIFIC
+#define BIFP5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
+#define BIFP5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
+#define BIFP5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00FFFFFFL
+#define BIFP5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L
+//BIFP5_PCIE_RX_CNTL3
+#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
+#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
+#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
+#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
+#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
+#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L
+#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L
+#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L
+#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L
+#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L
+//BIFP5_PCIE_RX_CREDITS_ALLOCATED_P
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000FFFL
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00FF0000L
+//BIFP5_PCIE_RX_CREDITS_ALLOCATED_NP
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000FFFL
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00FF0000L
+//BIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000FFFL
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00FF0000L
+//BIFP5_PCIEP_ERROR_INJECT_PHYSICAL
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x00000003L
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0x0000000CL
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x00000030L
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0x000000C0L
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x00000300L
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0x00000C00L
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x00003000L
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0x0000C000L
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x00030000L
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0x000C0000L
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x00300000L
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0x00C00000L
+//BIFP5_PCIEP_ERROR_INJECT_TRANSACTION
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x00000003L
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0x0000000CL
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x00000030L
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0x000000C0L
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x00000300L
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0x00000C00L
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x00003000L
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0x0000C000L
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x00030000L
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0x000C0000L
+//BIFP5_PCIEP_NAK_COUNTER
+#define BIFP5_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT 0x0
+#define BIFP5_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT 0x10
+#define BIFP5_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK 0x0000FFFFL
+#define BIFP5_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK 0xFFFF0000L
+//BIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS__SHIFT 0x0
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK__SHIFT 0x8
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK__SHIFT 0x9
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS_MASK 0x00000001L
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK_MASK 0x00000100L
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK_MASK 0x00000200L
+//BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT 0x0
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT 0xa
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT 0xf
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT 0x1a
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT 0x1f
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK 0x000003FFL
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK 0x00001C00L
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK 0x00008000L
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK 0x1C000000L
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK 0x80000000L
+//BIFP5_PCIE_LC_CNTL
+#define BIFP5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
+#define BIFP5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
+#define BIFP5_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
+#define BIFP5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
+#define BIFP5_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
+#define BIFP5_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
+#define BIFP5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
+#define BIFP5_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
+#define BIFP5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
+#define BIFP5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
+#define BIFP5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
+#define BIFP5_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
+#define BIFP5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
+#define BIFP5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
+#define BIFP5_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
+#define BIFP5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
+#define BIFP5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
+#define BIFP5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
+#define BIFP5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
+#define BIFP5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
+#define BIFP5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L
+#define BIFP5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L
+#define BIFP5_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L
+#define BIFP5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000F0L
+#define BIFP5_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000F00L
+#define BIFP5_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000F000L
+#define BIFP5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L
+#define BIFP5_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L
+#define BIFP5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000C0000L
+#define BIFP5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L
+#define BIFP5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L
+#define BIFP5_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L
+#define BIFP5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L
+#define BIFP5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L
+#define BIFP5_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L
+#define BIFP5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L
+#define BIFP5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L
+#define BIFP5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L
+#define BIFP5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L
+#define BIFP5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L
+//BIFP5_PCIE_LC_TRAINING_CNTL
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000FL
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x00004000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x00008000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00C00000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xC0000000L
+//BIFP5_PCIE_LC_LINK_WIDTH_CNTL
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT 0x1e
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT 0x1f
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x00010000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x01000000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x02000000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x04000000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x08000000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK 0x40000000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK 0x80000000L
+//BIFP5_PCIE_LC_N_FTS_CNTL
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT 0xf
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000FFL
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK 0x00008000L
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00FF0000L
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xFF000000L
+//BIFP5_PCIE_LC_SPEED_CNTL
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000004L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000018L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000020L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000040L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000080L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000100L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000200L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00000C00L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00001000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x00006000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00008000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00010000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00020000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00040000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00080000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00100000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00200000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x00400000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x00800000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x03000000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x04000000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x08000000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000L
+//BIFP5_PCIE_LC_STATE0
+#define BIFP5_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
+#define BIFP5_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
+#define BIFP5_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
+#define BIFP5_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
+#define BIFP5_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003FL
+#define BIFP5_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003F00L
+#define BIFP5_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003F0000L
+#define BIFP5_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3F000000L
+//BIFP5_PCIE_LC_STATE1
+#define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
+#define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
+#define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
+#define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
+#define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003FL
+#define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003F00L
+#define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003F0000L
+#define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3F000000L
+//BIFP5_PCIE_LC_STATE2
+#define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
+#define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
+#define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
+#define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
+#define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003FL
+#define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003F00L
+#define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003F0000L
+#define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3F000000L
+//BIFP5_PCIE_LC_STATE3
+#define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
+#define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
+#define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
+#define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
+#define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003FL
+#define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003F00L
+#define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003F0000L
+#define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3F000000L
+//BIFP5_PCIE_LC_STATE4
+#define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
+#define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
+#define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
+#define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
+#define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003FL
+#define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003F00L
+#define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003F0000L
+#define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3F000000L
+//BIFP5_PCIE_LC_STATE5
+#define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
+#define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
+#define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
+#define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
+#define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003FL
+#define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003F00L
+#define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003F0000L
+#define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3F000000L
+//BIFP5_PCIE_LINK_MANAGEMENT_CNTL2
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT 0x0
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT 0x1
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT 0x2
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT 0x3
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT 0x4
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT 0x7
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT 0xb
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT 0xf
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT 0x13
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK 0x00000001L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK 0x00000002L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK 0x00000004L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK 0x00000008L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK 0x00000070L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK 0x00000780L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK 0x00007800L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK 0x00078000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK 0x00780000L
+//BIFP5_PCIE_LC_CNTL2
+#define BIFP5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
+#define BIFP5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
+#define BIFP5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
+#define BIFP5_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
+#define BIFP5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
+#define BIFP5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
+#define BIFP5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
+#define BIFP5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
+#define BIFP5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
+#define BIFP5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
+#define BIFP5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
+#define BIFP5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
+#define BIFP5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
+#define BIFP5_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
+#define BIFP5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
+#define BIFP5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
+#define BIFP5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
+#define BIFP5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
+#define BIFP5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
+#define BIFP5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
+#define BIFP5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define BIFP5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
+#define BIFP5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
+#define BIFP5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
+#define BIFP5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003FL
+#define BIFP5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L
+#define BIFP5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L
+#define BIFP5_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L
+#define BIFP5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L
+#define BIFP5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L
+#define BIFP5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L
+#define BIFP5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L
+#define BIFP5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L
+#define BIFP5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000C000L
+#define BIFP5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L
+#define BIFP5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L
+#define BIFP5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L
+#define BIFP5_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x00080000L
+#define BIFP5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L
+#define BIFP5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L
+#define BIFP5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L
+#define BIFP5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L
+#define BIFP5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L
+#define BIFP5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L
+#define BIFP5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+#define BIFP5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L
+#define BIFP5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L
+#define BIFP5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L
+//BIFP5_PCIE_LC_BW_CHANGE_CNTL
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT 0xb
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK 0x00000800L
+//BIFP5_PCIE_LC_CDR_CNTL
+#define BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
+#define BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
+#define BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
+#define BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000FFFL
+#define BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00FFF000L
+#define BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L
+//BIFP5_PCIE_LC_LANE_CNTL
+#define BIFP5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
+#define BIFP5_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
+#define BIFP5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000FFFFL
+#define BIFP5_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xFFFF0000L
+//BIFP5_PCIE_LC_CNTL3
+#define BIFP5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
+#define BIFP5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
+#define BIFP5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
+#define BIFP5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
+#define BIFP5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
+#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
+#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
+#define BIFP5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
+#define BIFP5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
+#define BIFP5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
+#define BIFP5_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
+#define BIFP5_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
+#define BIFP5_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
+#define BIFP5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
+#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
+#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
+#define BIFP5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
+#define BIFP5_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
+#define BIFP5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
+#define BIFP5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
+#define BIFP5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
+#define BIFP5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
+#define BIFP5_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
+#define BIFP5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L
+#define BIFP5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L
+#define BIFP5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L
+#define BIFP5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L
+#define BIFP5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L
+#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000C0L
+#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L
+#define BIFP5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L
+#define BIFP5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L
+#define BIFP5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L
+#define BIFP5_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x00003000L
+#define BIFP5_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0x0000C000L
+#define BIFP5_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x00010000L
+#define BIFP5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L
+#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L
+#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L
+#define BIFP5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L
+#define BIFP5_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x00400000L
+#define BIFP5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L
+#define BIFP5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L
+#define BIFP5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3C000000L
+#define BIFP5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L
+#define BIFP5_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000L
+//BIFP5_PCIE_LC_CNTL4
+#define BIFP5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
+#define BIFP5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
+#define BIFP5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
+#define BIFP5_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
+#define BIFP5_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
+#define BIFP5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
+#define BIFP5_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
+#define BIFP5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
+#define BIFP5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
+#define BIFP5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
+#define BIFP5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
+#define BIFP5_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
+#define BIFP5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
+#define BIFP5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
+#define BIFP5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
+#define BIFP5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
+#define BIFP5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
+#define BIFP5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
+#define BIFP5_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT 0x17
+#define BIFP5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
+#define BIFP5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
+#define BIFP5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
+#define BIFP5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L
+#define BIFP5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x00000004L
+#define BIFP5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x00000008L
+#define BIFP5_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x00000010L
+#define BIFP5_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x00000020L
+#define BIFP5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L
+#define BIFP5_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L
+#define BIFP5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x00000300L
+#define BIFP5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L
+#define BIFP5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x00000800L
+#define BIFP5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x00001000L
+#define BIFP5_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L
+#define BIFP5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L
+#define BIFP5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x00008000L
+#define BIFP5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x00010000L
+#define BIFP5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x00020000L
+#define BIFP5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x003C0000L
+#define BIFP5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L
+#define BIFP5_PCIE_LC_CNTL4__LC_TX_SWING_MASK 0x00800000L
+#define BIFP5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L
+#define BIFP5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L
+#define BIFP5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xFC000000L
+//BIFP5_PCIE_LC_CNTL5
+#define BIFP5_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
+#define BIFP5_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
+#define BIFP5_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
+#define BIFP5_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
+#define BIFP5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
+#define BIFP5_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT 0x19
+#define BIFP5_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT 0x1a
+#define BIFP5_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT 0x1b
+#define BIFP5_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT 0x1c
+#define BIFP5_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT 0x1d
+#define BIFP5_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x0000003FL
+#define BIFP5_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0x00000FC0L
+#define BIFP5_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x0003F000L
+#define BIFP5_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0x00FC0000L
+#define BIFP5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x01000000L
+#define BIFP5_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK 0x02000000L
+#define BIFP5_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK 0x04000000L
+#define BIFP5_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK 0x08000000L
+#define BIFP5_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK 0x10000000L
+#define BIFP5_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK 0xE0000000L
+//BIFP5_PCIE_LC_FORCE_COEFF
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x00000001L
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x0000007EL
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x00001F80L
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x0007E000L
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x00080000L
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x00100000L
+//BIFP5_PCIE_LC_BEST_EQ_SETTINGS
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000FL
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003F0L
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000FC00L
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003F0000L
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3FC00000L
+//BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x00000001L
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x0000007EL
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x00001F80L
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x0007E000L
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x01F80000L
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7E000000L
+//BIFP5_PCIE_LC_CNTL6
+#define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
+#define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
+#define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
+#define BIFP5_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT 0x5
+#define BIFP5_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT 0x6
+#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT 0x8
+#define BIFP5_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT 0x9
+#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT 0xd
+#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT 0xe
+#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT 0x10
+#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT 0x12
+#define BIFP5_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT 0x13
+#define BIFP5_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT 0x14
+#define BIFP5_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT 0x15
+#define BIFP5_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT 0x16
+#define BIFP5_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT 0x17
+#define BIFP5_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT 0x18
+#define BIFP5_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT 0x1f
+#define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x00000001L
+#define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x00000004L
+#define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x00000010L
+#define BIFP5_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK 0x00000020L
+#define BIFP5_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK 0x000000C0L
+#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_EN_MASK 0x00000100L
+#define BIFP5_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK 0x00001E00L
+#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK 0x00002000L
+#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK 0x0000C000L
+#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK 0x00030000L
+#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK 0x00040000L
+#define BIFP5_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK 0x00080000L
+#define BIFP5_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK 0x00100000L
+#define BIFP5_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L
+#define BIFP5_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK 0x00400000L
+#define BIFP5_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK 0x00800000L
+#define BIFP5_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK 0x7F000000L
+#define BIFP5_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK 0x80000000L
+//BIFP5_PCIE_LC_CNTL7
+#define BIFP5_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT 0x0
+#define BIFP5_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT 0x1
+#define BIFP5_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT 0x2
+#define BIFP5_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT 0x3
+#define BIFP5_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT 0x4
+#define BIFP5_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT 0x5
+#define BIFP5_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT 0x6
+#define BIFP5_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT 0x7
+#define BIFP5_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT 0x8
+#define BIFP5_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT 0x9
+#define BIFP5_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT 0xa
+#define BIFP5_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT 0xb
+#define BIFP5_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT 0xc
+#define BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT 0xd
+#define BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT 0x15
+#define BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT 0x16
+#define BIFP5_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT 0x17
+#define BIFP5_PCIE_LC_CNTL7__LC_FOM_TIME__SHIFT 0x18
+#define BIFP5_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH__SHIFT 0x1a
+#define BIFP5_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT 0x1b
+#define BIFP5_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT 0x1c
+#define BIFP5_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT 0x1d
+#define BIFP5_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT 0x1e
+#define BIFP5_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT 0x1f
+#define BIFP5_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK 0x00000001L
+#define BIFP5_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK 0x00000002L
+#define BIFP5_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK 0x00000004L
+#define BIFP5_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK 0x00000008L
+#define BIFP5_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK 0x00000010L
+#define BIFP5_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK 0x00000020L
+#define BIFP5_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK 0x00000040L
+#define BIFP5_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK 0x00000080L
+#define BIFP5_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK 0x00000100L
+#define BIFP5_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK 0x00000200L
+#define BIFP5_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK 0x00000400L
+#define BIFP5_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK 0x00000800L
+#define BIFP5_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK 0x00001000L
+#define BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK 0x001FE000L
+#define BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK 0x00200000L
+#define BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK 0x00400000L
+#define BIFP5_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK 0x00800000L
+#define BIFP5_PCIE_LC_CNTL7__LC_FOM_TIME_MASK 0x03000000L
+#define BIFP5_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH_MASK 0x04000000L
+#define BIFP5_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK 0x08000000L
+#define BIFP5_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK 0x10000000L
+#define BIFP5_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK 0x20000000L
+#define BIFP5_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK 0x40000000L
+#define BIFP5_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN_MASK 0x80000000L
+//BIFP5_PCIE_LINK_MANAGEMENT_STATUS
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT 0x0
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x1
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT 0x2
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT 0x3
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT 0x4
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT 0x5
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT 0x6
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT 0x7
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT 0x8
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT 0x9
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT 0xa
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT 0xb
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT 0xc
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT 0xd
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK 0x00000001L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000002L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 0x00000004L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK 0x00000008L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 0x00000010L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 0x00000020L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK 0x00000040L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK 0x00000080L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK 0x00000100L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK 0x00000200L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK 0x00000400L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK 0x00000800L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK 0x00001000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK 0x00002000L
+//BIFP5_PCIE_LINK_MANAGEMENT_MASK
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT 0x0
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x1
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT 0x2
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT 0x3
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x4
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT 0x5
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT 0x6
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT 0x7
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT 0x8
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT 0x9
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT 0xa
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT 0xb
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT 0xc
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT 0xd
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK 0x00000001L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000002L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK 0x00000004L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK 0x00000008L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000010L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK 0x00000020L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK 0x00000040L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK 0x00000080L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK 0x00000100L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK 0x00000200L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK 0x00000400L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK 0x00000800L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK 0x00001000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK 0x00002000L
+//BIFP5_PCIE_LINK_MANAGEMENT_CNTL
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT 0x0
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT 0x3
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT 0x7
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT 0xb
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT 0xc
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT 0xd
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT 0xf
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT 0x11
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT 0x12
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT 0x13
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT 0x17
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT 0x1b
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK 0x00000007L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK 0x00000078L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK 0x00000780L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK 0x00000800L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK 0x00001000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK 0x00006000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK 0x00018000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK 0x00020000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK 0x00040000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK 0x00780000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK 0x07800000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK 0x38000000L
+//BIFP5_PCIEP_STRAP_LC
+#define BIFP5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
+#define BIFP5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
+#define BIFP5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
+#define BIFP5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
+#define BIFP5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
+#define BIFP5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
+#define BIFP5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
+#define BIFP5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
+#define BIFP5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
+#define BIFP5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
+#define BIFP5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
+#define BIFP5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000CL
+#define BIFP5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000C0L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L
+//BIFP5_PCIEP_STRAP_MISC
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x00000020L
+//BIFP5_PCIE_LC_L1_PM_SUBSTATE
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT 0x0
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT 0x1
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT 0x2
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT 0x3
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT 0x4
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT 0x6
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT 0x8
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT 0x10
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT 0x14
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT 0x17
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK 0x000000C0L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK 0x00001F00L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK 0x00070000L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK 0x00700000L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK 0x03800000L
+//BIFP5_PCIE_LC_L1_PM_SUBSTATE2
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT 0x0
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT 0x8
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK 0x000000FFL
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK 0x00000700L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK 0x03FF0000L
+//BIFP5_PCIE_LC_PORT_ORDER
+#define BIFP5_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT 0x0
+#define BIFP5_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK 0x0000000FL
+//BIFP5_PCIEP_BCH_ECC_CNTL
+#define BIFP5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
+#define BIFP5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
+#define BIFP5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
+#define BIFP5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x00000001L
+#define BIFP5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0x0000FF00L
+#define BIFP5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xFFFF0000L
+//BIFP5_PCIEP_HPGI_PRIVATE
+#define BIFP5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
+#define BIFP5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
+#define BIFP5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x00000008L
+#define BIFP5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x00000040L
+//BIFP5_PCIEP_HPGI
+#define BIFP5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
+#define BIFP5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
+#define BIFP5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
+#define BIFP5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
+#define BIFP5_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
+#define BIFP5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
+#define BIFP5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
+#define BIFP5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
+#define BIFP5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
+#define BIFP5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
+#define BIFP5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
+#define BIFP5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x00000001L
+#define BIFP5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x00000002L
+#define BIFP5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x00000004L
+#define BIFP5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x00000008L
+#define BIFP5_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x00000080L
+#define BIFP5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x00000100L
+#define BIFP5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x00000200L
+#define BIFP5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x00000400L
+#define BIFP5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x00000800L
+#define BIFP5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x00008000L
+#define BIFP5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x00010000L
+//BIFP5_PCIEP_HCNT_DESCRIPTOR
+#define BIFP5_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT 0x0
+#define BIFP5_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT 0x1f
+#define BIFP5_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK 0x0000003FL
+#define BIFP5_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK 0x80000000L
+//BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK
+#define BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT 0x0
+#define BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT 0x10
+#define BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL
+#define BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L
+
+
+// addressBlock: nbio_pcie0_bifp6_pciedir_p
+//BIFP6_PCIEP_RESERVED
+#define BIFP6_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define BIFP6_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL
+//BIFP6_PCIEP_SCRATCH
+#define BIFP6_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
+#define BIFP6_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xFFFFFFFFL
+//BIFP6_PCIEP_PORT_CNTL
+#define BIFP6_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
+#define BIFP6_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
+#define BIFP6_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
+#define BIFP6_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
+#define BIFP6_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
+#define BIFP6_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
+#define BIFP6_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
+#define BIFP6_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
+#define BIFP6_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
+#define BIFP6_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT 0x18
+#define BIFP6_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L
+#define BIFP6_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L
+#define BIFP6_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L
+#define BIFP6_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L
+#define BIFP6_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L
+#define BIFP6_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L
+#define BIFP6_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x00007F00L
+#define BIFP6_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x00030000L
+#define BIFP6_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x001C0000L
+#define BIFP6_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK 0x03000000L
+//BIFP6_PCIE_TX_CNTL
+#define BIFP6_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define BIFP6_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define BIFP6_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
+#define BIFP6_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
+#define BIFP6_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
+#define BIFP6_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
+#define BIFP6_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
+#define BIFP6_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
+#define BIFP6_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define BIFP6_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define BIFP6_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L
+#define BIFP6_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L
+#define BIFP6_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L
+#define BIFP6_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L
+#define BIFP6_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L
+#define BIFP6_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L
+//BIFP6_PCIE_TX_REQUESTER_ID
+#define BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//BIFP6_PCIE_TX_VENDOR_SPECIFIC
+#define BIFP6_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
+#define BIFP6_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00FFFFFFL
+//BIFP6_PCIE_TX_REQUEST_NUM_CNTL
+#define BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
+#define BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
+#define BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
+#define BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3F000000L
+#define BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L
+#define BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L
+//BIFP6_PCIE_TX_SEQ
+#define BIFP6_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
+#define BIFP6_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
+#define BIFP6_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000FFFL
+#define BIFP6_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0FFF0000L
+//BIFP6_PCIE_TX_REPLAY
+#define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
+#define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
+#define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
+#define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L
+#define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L
+#define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xFFFF0000L
+//BIFP6_PCIE_TX_ACK_LATENCY_LIMIT
+#define BIFP6_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
+#define BIFP6_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
+#define BIFP6_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000FFFL
+#define BIFP6_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L
+//BIFP6_PCIE_TX_CREDITS_ADVT_P
+#define BIFP6_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
+#define BIFP6_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
+#define BIFP6_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00000FFFL
+#define BIFP6_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x00FF0000L
+//BIFP6_PCIE_TX_CREDITS_ADVT_NP
+#define BIFP6_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
+#define BIFP6_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
+#define BIFP6_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00000FFFL
+#define BIFP6_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x00FF0000L
+//BIFP6_PCIE_TX_CREDITS_ADVT_CPL
+#define BIFP6_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
+#define BIFP6_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
+#define BIFP6_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00000FFFL
+#define BIFP6_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x00FF0000L
+//BIFP6_PCIE_TX_CREDITS_INIT_P
+#define BIFP6_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
+#define BIFP6_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
+#define BIFP6_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000FFFL
+#define BIFP6_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00FF0000L
+//BIFP6_PCIE_TX_CREDITS_INIT_NP
+#define BIFP6_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
+#define BIFP6_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
+#define BIFP6_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000FFFL
+#define BIFP6_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00FF0000L
+//BIFP6_PCIE_TX_CREDITS_INIT_CPL
+#define BIFP6_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
+#define BIFP6_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
+#define BIFP6_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000FFFL
+#define BIFP6_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00FF0000L
+//BIFP6_PCIE_TX_CREDITS_STATUS
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L
+//BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L
+//BIFP6_PCIE_P_PORT_LANE_STATUS
+#define BIFP6_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
+#define BIFP6_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
+#define BIFP6_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L
+#define BIFP6_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007EL
+//BIFP6_PCIE_FC_P
+#define BIFP6_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
+#define BIFP6_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
+#define BIFP6_PCIE_FC_P__PD_CREDITS_MASK 0x000000FFL
+#define BIFP6_PCIE_FC_P__PH_CREDITS_MASK 0x0000FF00L
+//BIFP6_PCIE_FC_NP
+#define BIFP6_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
+#define BIFP6_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
+#define BIFP6_PCIE_FC_NP__NPD_CREDITS_MASK 0x000000FFL
+#define BIFP6_PCIE_FC_NP__NPH_CREDITS_MASK 0x0000FF00L
+//BIFP6_PCIE_FC_CPL
+#define BIFP6_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
+#define BIFP6_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
+#define BIFP6_PCIE_FC_CPL__CPLD_CREDITS_MASK 0x000000FFL
+#define BIFP6_PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0000FF00L
+//BIFP6_PCIE_ERR_CNTL
+#define BIFP6_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define BIFP6_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
+#define BIFP6_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
+#define BIFP6_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
+#define BIFP6_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
+#define BIFP6_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
+#define BIFP6_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
+#define BIFP6_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define BIFP6_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define BIFP6_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
+#define BIFP6_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
+#define BIFP6_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
+#define BIFP6_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define BIFP6_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define BIFP6_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define BIFP6_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L
+#define BIFP6_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x00000004L
+#define BIFP6_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L
+#define BIFP6_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L
+#define BIFP6_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L
+#define BIFP6_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L
+#define BIFP6_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define BIFP6_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define BIFP6_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L
+#define BIFP6_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L
+#define BIFP6_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L
+#define BIFP6_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define BIFP6_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+//BIFP6_PCIE_RX_CNTL
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
+#define BIFP6_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
+#define BIFP6_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
+#define BIFP6_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
+#define BIFP6_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
+#define BIFP6_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
+#define BIFP6_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define BIFP6_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define BIFP6_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L
+#define BIFP6_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L
+#define BIFP6_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x00004000L
+#define BIFP6_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L
+#define BIFP6_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L
+#define BIFP6_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L
+#define BIFP6_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define BIFP6_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+#define BIFP6_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+//BIFP6_PCIE_RX_EXPECTED_SEQNUM
+#define BIFP6_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
+#define BIFP6_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000FFFL
+//BIFP6_PCIE_RX_VENDOR_SPECIFIC
+#define BIFP6_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
+#define BIFP6_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
+#define BIFP6_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00FFFFFFL
+#define BIFP6_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L
+//BIFP6_PCIE_RX_CNTL3
+#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
+#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
+#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
+#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
+#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
+#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L
+#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L
+#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L
+#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L
+#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L
+//BIFP6_PCIE_RX_CREDITS_ALLOCATED_P
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000FFFL
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00FF0000L
+//BIFP6_PCIE_RX_CREDITS_ALLOCATED_NP
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000FFFL
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00FF0000L
+//BIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000FFFL
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00FF0000L
+//BIFP6_PCIEP_ERROR_INJECT_PHYSICAL
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x00000003L
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0x0000000CL
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x00000030L
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0x000000C0L
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x00000300L
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0x00000C00L
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x00003000L
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0x0000C000L
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x00030000L
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0x000C0000L
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x00300000L
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0x00C00000L
+//BIFP6_PCIEP_ERROR_INJECT_TRANSACTION
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x00000003L
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0x0000000CL
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x00000030L
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0x000000C0L
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x00000300L
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0x00000C00L
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x00003000L
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0x0000C000L
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x00030000L
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0x000C0000L
+//BIFP6_PCIEP_NAK_COUNTER
+#define BIFP6_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT 0x0
+#define BIFP6_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT 0x10
+#define BIFP6_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK 0x0000FFFFL
+#define BIFP6_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK 0xFFFF0000L
+//BIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS__SHIFT 0x0
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK__SHIFT 0x8
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK__SHIFT 0x9
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_STATUS_MASK 0x00000001L
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__RX_LTR_RSMU_INTR_MASK_MASK 0x00000100L
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS__DPC_RSMU_INTR_MASK_MASK 0x00000200L
+//BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT 0x0
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT 0xa
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT 0xf
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT 0x1a
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT 0x1f
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK 0x000003FFL
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK 0x00001C00L
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK 0x00008000L
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK 0x1C000000L
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK 0x80000000L
+//BIFP6_PCIE_LC_CNTL
+#define BIFP6_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
+#define BIFP6_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
+#define BIFP6_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
+#define BIFP6_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
+#define BIFP6_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
+#define BIFP6_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
+#define BIFP6_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
+#define BIFP6_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
+#define BIFP6_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
+#define BIFP6_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
+#define BIFP6_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
+#define BIFP6_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
+#define BIFP6_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
+#define BIFP6_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
+#define BIFP6_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
+#define BIFP6_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
+#define BIFP6_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
+#define BIFP6_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
+#define BIFP6_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
+#define BIFP6_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
+#define BIFP6_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L
+#define BIFP6_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L
+#define BIFP6_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L
+#define BIFP6_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000F0L
+#define BIFP6_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000F00L
+#define BIFP6_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000F000L
+#define BIFP6_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L
+#define BIFP6_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L
+#define BIFP6_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000C0000L
+#define BIFP6_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L
+#define BIFP6_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L
+#define BIFP6_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L
+#define BIFP6_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L
+#define BIFP6_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L
+#define BIFP6_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L
+#define BIFP6_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L
+#define BIFP6_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L
+#define BIFP6_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L
+#define BIFP6_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L
+#define BIFP6_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L
+//BIFP6_PCIE_LC_TRAINING_CNTL
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000FL
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x00004000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x00008000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00C00000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xC0000000L
+//BIFP6_PCIE_LC_LINK_WIDTH_CNTL
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT 0x1e
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT 0x1f
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x00010000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x01000000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x02000000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x04000000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x08000000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK 0x40000000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK 0x80000000L
+//BIFP6_PCIE_LC_N_FTS_CNTL
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT 0xf
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000FFL
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK 0x00008000L
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00FF0000L
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xFF000000L
+//BIFP6_PCIE_LC_SPEED_CNTL
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000004L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000018L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000020L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000040L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000080L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000100L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000200L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00000C00L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00001000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x00006000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00008000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00010000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00020000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00040000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00080000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00100000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00200000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x00400000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x00800000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x03000000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x04000000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x08000000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000L
+//BIFP6_PCIE_LC_STATE0
+#define BIFP6_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
+#define BIFP6_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
+#define BIFP6_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
+#define BIFP6_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
+#define BIFP6_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003FL
+#define BIFP6_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003F00L
+#define BIFP6_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003F0000L
+#define BIFP6_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3F000000L
+//BIFP6_PCIE_LC_STATE1
+#define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
+#define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
+#define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
+#define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
+#define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003FL
+#define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003F00L
+#define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003F0000L
+#define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3F000000L
+//BIFP6_PCIE_LC_STATE2
+#define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
+#define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
+#define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
+#define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
+#define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003FL
+#define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003F00L
+#define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003F0000L
+#define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3F000000L
+//BIFP6_PCIE_LC_STATE3
+#define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
+#define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
+#define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
+#define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
+#define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003FL
+#define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003F00L
+#define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003F0000L
+#define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3F000000L
+//BIFP6_PCIE_LC_STATE4
+#define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
+#define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
+#define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
+#define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
+#define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003FL
+#define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003F00L
+#define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003F0000L
+#define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3F000000L
+//BIFP6_PCIE_LC_STATE5
+#define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
+#define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
+#define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
+#define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
+#define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003FL
+#define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003F00L
+#define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003F0000L
+#define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3F000000L
+//BIFP6_PCIE_LINK_MANAGEMENT_CNTL2
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT 0x0
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT 0x1
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT 0x2
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT 0x3
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT 0x4
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT 0x7
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT 0xb
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT 0xf
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT 0x13
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK 0x00000001L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK 0x00000002L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK 0x00000004L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK 0x00000008L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK 0x00000070L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK 0x00000780L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK 0x00007800L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK 0x00078000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK 0x00780000L
+//BIFP6_PCIE_LC_CNTL2
+#define BIFP6_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
+#define BIFP6_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
+#define BIFP6_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
+#define BIFP6_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
+#define BIFP6_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
+#define BIFP6_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
+#define BIFP6_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
+#define BIFP6_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
+#define BIFP6_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
+#define BIFP6_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
+#define BIFP6_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
+#define BIFP6_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
+#define BIFP6_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
+#define BIFP6_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
+#define BIFP6_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
+#define BIFP6_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
+#define BIFP6_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
+#define BIFP6_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
+#define BIFP6_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
+#define BIFP6_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
+#define BIFP6_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define BIFP6_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
+#define BIFP6_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
+#define BIFP6_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
+#define BIFP6_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003FL
+#define BIFP6_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L
+#define BIFP6_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L
+#define BIFP6_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L
+#define BIFP6_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L
+#define BIFP6_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L
+#define BIFP6_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L
+#define BIFP6_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L
+#define BIFP6_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L
+#define BIFP6_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000C000L
+#define BIFP6_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L
+#define BIFP6_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L
+#define BIFP6_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L
+#define BIFP6_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x00080000L
+#define BIFP6_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L
+#define BIFP6_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L
+#define BIFP6_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L
+#define BIFP6_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L
+#define BIFP6_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L
+#define BIFP6_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L
+#define BIFP6_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+#define BIFP6_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L
+#define BIFP6_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L
+#define BIFP6_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L
+//BIFP6_PCIE_LC_BW_CHANGE_CNTL
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT 0xb
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK 0x00000800L
+//BIFP6_PCIE_LC_CDR_CNTL
+#define BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
+#define BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
+#define BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
+#define BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000FFFL
+#define BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00FFF000L
+#define BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L
+//BIFP6_PCIE_LC_LANE_CNTL
+#define BIFP6_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
+#define BIFP6_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
+#define BIFP6_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000FFFFL
+#define BIFP6_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xFFFF0000L
+//BIFP6_PCIE_LC_CNTL3
+#define BIFP6_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
+#define BIFP6_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
+#define BIFP6_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
+#define BIFP6_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
+#define BIFP6_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
+#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
+#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
+#define BIFP6_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
+#define BIFP6_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
+#define BIFP6_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
+#define BIFP6_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
+#define BIFP6_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
+#define BIFP6_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
+#define BIFP6_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
+#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
+#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
+#define BIFP6_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
+#define BIFP6_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
+#define BIFP6_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
+#define BIFP6_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
+#define BIFP6_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
+#define BIFP6_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
+#define BIFP6_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
+#define BIFP6_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L
+#define BIFP6_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L
+#define BIFP6_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L
+#define BIFP6_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L
+#define BIFP6_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L
+#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000C0L
+#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L
+#define BIFP6_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L
+#define BIFP6_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L
+#define BIFP6_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L
+#define BIFP6_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x00003000L
+#define BIFP6_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0x0000C000L
+#define BIFP6_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x00010000L
+#define BIFP6_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L
+#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L
+#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L
+#define BIFP6_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L
+#define BIFP6_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x00400000L
+#define BIFP6_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L
+#define BIFP6_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L
+#define BIFP6_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3C000000L
+#define BIFP6_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L
+#define BIFP6_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000L
+//BIFP6_PCIE_LC_CNTL4
+#define BIFP6_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
+#define BIFP6_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
+#define BIFP6_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
+#define BIFP6_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
+#define BIFP6_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
+#define BIFP6_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
+#define BIFP6_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
+#define BIFP6_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
+#define BIFP6_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
+#define BIFP6_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
+#define BIFP6_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
+#define BIFP6_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
+#define BIFP6_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
+#define BIFP6_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
+#define BIFP6_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
+#define BIFP6_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
+#define BIFP6_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
+#define BIFP6_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
+#define BIFP6_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT 0x17
+#define BIFP6_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
+#define BIFP6_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
+#define BIFP6_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
+#define BIFP6_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L
+#define BIFP6_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x00000004L
+#define BIFP6_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x00000008L
+#define BIFP6_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x00000010L
+#define BIFP6_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x00000020L
+#define BIFP6_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L
+#define BIFP6_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L
+#define BIFP6_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x00000300L
+#define BIFP6_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L
+#define BIFP6_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x00000800L
+#define BIFP6_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x00001000L
+#define BIFP6_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L
+#define BIFP6_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L
+#define BIFP6_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x00008000L
+#define BIFP6_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x00010000L
+#define BIFP6_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x00020000L
+#define BIFP6_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x003C0000L
+#define BIFP6_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L
+#define BIFP6_PCIE_LC_CNTL4__LC_TX_SWING_MASK 0x00800000L
+#define BIFP6_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L
+#define BIFP6_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L
+#define BIFP6_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xFC000000L
+//BIFP6_PCIE_LC_CNTL5
+#define BIFP6_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
+#define BIFP6_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
+#define BIFP6_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
+#define BIFP6_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
+#define BIFP6_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
+#define BIFP6_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT 0x19
+#define BIFP6_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT 0x1a
+#define BIFP6_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT 0x1b
+#define BIFP6_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT 0x1c
+#define BIFP6_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT 0x1d
+#define BIFP6_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x0000003FL
+#define BIFP6_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0x00000FC0L
+#define BIFP6_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x0003F000L
+#define BIFP6_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0x00FC0000L
+#define BIFP6_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x01000000L
+#define BIFP6_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK 0x02000000L
+#define BIFP6_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK 0x04000000L
+#define BIFP6_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK 0x08000000L
+#define BIFP6_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK 0x10000000L
+#define BIFP6_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK 0xE0000000L
+//BIFP6_PCIE_LC_FORCE_COEFF
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x00000001L
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x0000007EL
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x00001F80L
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x0007E000L
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x00080000L
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x00100000L
+//BIFP6_PCIE_LC_BEST_EQ_SETTINGS
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000FL
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003F0L
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000FC00L
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003F0000L
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3FC00000L
+//BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x00000001L
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x0000007EL
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x00001F80L
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x0007E000L
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x01F80000L
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7E000000L
+//BIFP6_PCIE_LC_CNTL6
+#define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
+#define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
+#define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
+#define BIFP6_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT 0x5
+#define BIFP6_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT 0x6
+#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT 0x8
+#define BIFP6_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT 0x9
+#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT 0xd
+#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT 0xe
+#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT 0x10
+#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT 0x12
+#define BIFP6_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT 0x13
+#define BIFP6_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT 0x14
+#define BIFP6_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT 0x15
+#define BIFP6_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT 0x16
+#define BIFP6_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT 0x17
+#define BIFP6_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT 0x18
+#define BIFP6_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT 0x1f
+#define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x00000001L
+#define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x00000004L
+#define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x00000010L
+#define BIFP6_PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK 0x00000020L
+#define BIFP6_PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK 0x000000C0L
+#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_EN_MASK 0x00000100L
+#define BIFP6_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK 0x00001E00L
+#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK 0x00002000L
+#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK 0x0000C000L
+#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK 0x00030000L
+#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK 0x00040000L
+#define BIFP6_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK 0x00080000L
+#define BIFP6_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK 0x00100000L
+#define BIFP6_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L
+#define BIFP6_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK 0x00400000L
+#define BIFP6_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK 0x00800000L
+#define BIFP6_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK 0x7F000000L
+#define BIFP6_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK 0x80000000L
+//BIFP6_PCIE_LC_CNTL7
+#define BIFP6_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT 0x0
+#define BIFP6_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT 0x1
+#define BIFP6_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT 0x2
+#define BIFP6_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT 0x3
+#define BIFP6_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT 0x4
+#define BIFP6_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT 0x5
+#define BIFP6_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT 0x6
+#define BIFP6_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT 0x7
+#define BIFP6_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT 0x8
+#define BIFP6_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT 0x9
+#define BIFP6_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT 0xa
+#define BIFP6_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT 0xb
+#define BIFP6_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT 0xc
+#define BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT 0xd
+#define BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT 0x15
+#define BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT 0x16
+#define BIFP6_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT 0x17
+#define BIFP6_PCIE_LC_CNTL7__LC_FOM_TIME__SHIFT 0x18
+#define BIFP6_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH__SHIFT 0x1a
+#define BIFP6_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT 0x1b
+#define BIFP6_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT 0x1c
+#define BIFP6_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT 0x1d
+#define BIFP6_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT 0x1e
+#define BIFP6_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT 0x1f
+#define BIFP6_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK 0x00000001L
+#define BIFP6_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK 0x00000002L
+#define BIFP6_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK 0x00000004L
+#define BIFP6_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK 0x00000008L
+#define BIFP6_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK 0x00000010L
+#define BIFP6_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK 0x00000020L
+#define BIFP6_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK 0x00000040L
+#define BIFP6_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK 0x00000080L
+#define BIFP6_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK 0x00000100L
+#define BIFP6_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK 0x00000200L
+#define BIFP6_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK 0x00000400L
+#define BIFP6_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK 0x00000800L
+#define BIFP6_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK 0x00001000L
+#define BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK 0x001FE000L
+#define BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK 0x00200000L
+#define BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK 0x00400000L
+#define BIFP6_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK 0x00800000L
+#define BIFP6_PCIE_LC_CNTL7__LC_FOM_TIME_MASK 0x03000000L
+#define BIFP6_PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH_MASK 0x04000000L
+#define BIFP6_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK 0x08000000L
+#define BIFP6_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK 0x10000000L
+#define BIFP6_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK 0x20000000L
+#define BIFP6_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK 0x40000000L
+#define BIFP6_PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN_MASK 0x80000000L
+//BIFP6_PCIE_LINK_MANAGEMENT_STATUS
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT 0x0
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x1
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT 0x2
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT 0x3
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT 0x4
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT 0x5
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT 0x6
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT 0x7
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT 0x8
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT 0x9
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT 0xa
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT 0xb
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT 0xc
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT 0xd
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK 0x00000001L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000002L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 0x00000004L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK 0x00000008L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 0x00000010L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 0x00000020L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK 0x00000040L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK 0x00000080L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK 0x00000100L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK 0x00000200L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK 0x00000400L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK 0x00000800L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK 0x00001000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK 0x00002000L
+//BIFP6_PCIE_LINK_MANAGEMENT_MASK
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT 0x0
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x1
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT 0x2
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT 0x3
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x4
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT 0x5
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT 0x6
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT 0x7
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT 0x8
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT 0x9
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT 0xa
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT 0xb
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT 0xc
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT 0xd
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK 0x00000001L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000002L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK 0x00000004L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK 0x00000008L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000010L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK 0x00000020L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK 0x00000040L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK 0x00000080L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK 0x00000100L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK 0x00000200L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK 0x00000400L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK 0x00000800L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK 0x00001000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK 0x00002000L
+//BIFP6_PCIE_LINK_MANAGEMENT_CNTL
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT 0x0
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT 0x3
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT 0x7
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT 0xb
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT 0xc
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT 0xd
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT 0xf
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT 0x11
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT 0x12
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT 0x13
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT 0x17
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT 0x1b
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK 0x00000007L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK 0x00000078L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK 0x00000780L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK 0x00000800L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK 0x00001000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK 0x00006000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK 0x00018000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK 0x00020000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK 0x00040000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK 0x00780000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK 0x07800000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK 0x38000000L
+//BIFP6_PCIEP_STRAP_LC
+#define BIFP6_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
+#define BIFP6_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
+#define BIFP6_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
+#define BIFP6_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
+#define BIFP6_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
+#define BIFP6_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
+#define BIFP6_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
+#define BIFP6_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
+#define BIFP6_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
+#define BIFP6_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
+#define BIFP6_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
+#define BIFP6_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000CL
+#define BIFP6_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000C0L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L
+//BIFP6_PCIEP_STRAP_MISC
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x00000020L
+//BIFP6_PCIE_LC_L1_PM_SUBSTATE
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT 0x0
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT 0x1
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT 0x2
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT 0x3
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT 0x4
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT 0x6
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT 0x8
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT 0x10
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT 0x14
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT 0x17
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK 0x000000C0L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK 0x00001F00L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK 0x00070000L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK 0x00700000L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK 0x03800000L
+//BIFP6_PCIE_LC_L1_PM_SUBSTATE2
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT 0x0
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT 0x8
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK 0x000000FFL
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK 0x00000700L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK 0x03FF0000L
+//BIFP6_PCIE_LC_PORT_ORDER
+#define BIFP6_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT 0x0
+#define BIFP6_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK 0x0000000FL
+//BIFP6_PCIEP_BCH_ECC_CNTL
+#define BIFP6_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
+#define BIFP6_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
+#define BIFP6_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
+#define BIFP6_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x00000001L
+#define BIFP6_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0x0000FF00L
+#define BIFP6_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xFFFF0000L
+//BIFP6_PCIEP_HPGI_PRIVATE
+#define BIFP6_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
+#define BIFP6_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
+#define BIFP6_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x00000008L
+#define BIFP6_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x00000040L
+//BIFP6_PCIEP_HPGI
+#define BIFP6_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
+#define BIFP6_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
+#define BIFP6_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
+#define BIFP6_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
+#define BIFP6_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
+#define BIFP6_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
+#define BIFP6_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
+#define BIFP6_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
+#define BIFP6_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
+#define BIFP6_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
+#define BIFP6_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
+#define BIFP6_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x00000001L
+#define BIFP6_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x00000002L
+#define BIFP6_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x00000004L
+#define BIFP6_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x00000008L
+#define BIFP6_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x00000080L
+#define BIFP6_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x00000100L
+#define BIFP6_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x00000200L
+#define BIFP6_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x00000400L
+#define BIFP6_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x00000800L
+#define BIFP6_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x00008000L
+#define BIFP6_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x00010000L
+//BIFP6_PCIEP_HCNT_DESCRIPTOR
+#define BIFP6_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT 0x0
+#define BIFP6_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT 0x1f
+#define BIFP6_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK 0x0000003FL
+#define BIFP6_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK 0x80000000L
+//BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK
+#define BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT 0x0
+#define BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT 0x10
+#define BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL
+#define BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L
+
+
+// addressBlock: nbio_pcie0_pciedir
+//PCIE_RESERVED
+#define PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
+#define PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL
+//PCIE_SCRATCH
+#define PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//PCIE_RX_NUM_NAK
+#define PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0
+#define PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xFFFFFFFFL
+//PCIE_RX_NUM_NAK_GENERATED
+#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0
+#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xFFFFFFFFL
+//PCIE_CNTL
+#define PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
+#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1
+#define PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
+#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
+#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9
+#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa
+#define PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf
+#define PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10
+#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11
+#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12
+#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13
+#define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS__SHIFT 0x14
+#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15
+#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16
+#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17
+#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f
+#define PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L
+#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0x0000000EL
+#define PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L
+#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L
+#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x00000200L
+#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x00001C00L
+#define PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x00008000L
+#define PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x00010000L
+#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x00020000L
+#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x00040000L
+#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x00080000L
+#define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS_MASK 0x00100000L
+#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x00200000L
+#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x00400000L
+#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x00800000L
+#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000L
+//PCIE_CONFIG_CNTL
+#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0
+#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x8
+#define PCIE_CONFIG_CNTL__CI_SWUS_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x9
+#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10
+#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11
+#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14
+#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15
+#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x18
+#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
+#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1b
+#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV__SHIFT 0x1c
+#define PCIE_CONFIG_CNTL__CI_SWUS_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x1e
+#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0x0000000FL
+#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_PAYLOAD_SIZE_MODE_MASK 0x00000100L
+#define PCIE_CONFIG_CNTL__CI_SWUS_PRIV_MAX_PAYLOAD_SIZE_MASK 0x00000600L
+#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x00010000L
+#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0x000E0000L
+#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x00100000L
+#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0x00E00000L
+#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x01000000L
+#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L
+#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE_MASK 0x08000000L
+#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV_MASK 0x30000000L
+#define PCIE_CONFIG_CNTL__CI_SWUS_EXTENDED_TAG_EN_OVERRIDE_MASK 0xC0000000L
+//PCIE_TX_TRACKING_ADDR_LO
+#define PCIE_TX_TRACKING_ADDR_LO__TX_TRACKING_ADDR_LO__SHIFT 0x2
+#define PCIE_TX_TRACKING_ADDR_LO__TX_TRACKING_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIE_TX_TRACKING_ADDR_HI
+#define PCIE_TX_TRACKING_ADDR_HI__TX_TRACKING_ADDR_HI__SHIFT 0x0
+#define PCIE_TX_TRACKING_ADDR_HI__TX_TRACKING_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIE_TX_TRACKING_CTRL_STATUS
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_ENABLE__SHIFT 0x0
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_PORT__SHIFT 0x1
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_UNIT_ID__SHIFT 0x8
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_STATUS_VALID__SHIFT 0xf
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_ENABLE_MASK 0x00000001L
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_PORT_MASK 0x0000000EL
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_UNIT_ID_MASK 0x00007F00L
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_STATUS_VALID_MASK 0x00008000L
+//PCIE_BW_BY_UNITID
+#define PCIE_BW_BY_UNITID__CI_MST_PERF_UNITID_EN__SHIFT 0x0
+#define PCIE_BW_BY_UNITID__CI_MST_PERF_UNITID__SHIFT 0x8
+#define PCIE_BW_BY_UNITID__CI_MST_PERF_UNITID_EN_MASK 0x00000001L
+#define PCIE_BW_BY_UNITID__CI_MST_PERF_UNITID_MASK 0x00007F00L
+//PCIE_CNTL2
+#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x0
+#define PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x1
+#define PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x6
+#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT 0xb
+#define PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING__SHIFT 0xc
+#define PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE__SHIFT 0xd
+#define PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS__SHIFT 0xe
+#define PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10
+#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11
+#define PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x12
+#define PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x13
+#define PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14
+#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15
+#define PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x16
+#define PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x17
+#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18
+#define PCIE_CNTL2__SLV_MEM_DS_EN__SHIFT 0x1d
+#define PCIE_CNTL2__MST_MEM_DS_EN__SHIFT 0x1e
+#define PCIE_CNTL2__REPLAY_MEM_DS_EN__SHIFT 0x1f
+#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x00000001L
+#define PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x0000003EL
+#define PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x000007C0L
+#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK 0x00000800L
+#define PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING_MASK 0x00001000L
+#define PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE_MASK 0x00002000L
+#define PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS_MASK 0x00004000L
+#define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x00010000L
+#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x00020000L
+#define PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x00040000L
+#define PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x00080000L
+#define PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x00100000L
+#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x00200000L
+#define PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x00400000L
+#define PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x00800000L
+#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1F000000L
+#define PCIE_CNTL2__SLV_MEM_DS_EN_MASK 0x20000000L
+#define PCIE_CNTL2__MST_MEM_DS_EN_MASK 0x40000000L
+#define PCIE_CNTL2__REPLAY_MEM_DS_EN_MASK 0x80000000L
+//PCIE_RX_CNTL2
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x4
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9
+#define PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN__SHIFT 0xc
+#define PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN__SHIFT 0xd
+#define PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN__SHIFT 0xe
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10
+#define PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x00000002L
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x00000004L
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x00000008L
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x00000010L
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x00000020L
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x00000100L
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0x00000E00L
+#define PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN_MASK 0x00001000L
+#define PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN_MASK 0x00002000L
+#define PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN_MASK 0x00004000L
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x03FF0000L
+#define PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L
+//PCIE_TX_F0_ATTR_CNTL
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x00000003L
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0x0000000CL
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x00000030L
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0x000000C0L
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x00000300L
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0x00000C00L
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x00003000L
+//PCIE_TX_SWUS_ATTR_CNTL
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_P__SHIFT 0x0
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_NP__SHIFT 0x2
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_CPL__SHIFT 0x4
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_P__SHIFT 0x6
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_NP__SHIFT 0x8
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_P__SHIFT 0xa
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_NP__SHIFT 0xc
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_P_MASK 0x00000003L
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_NP_MASK 0x0000000CL
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_CPL_MASK 0x00000030L
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_P_MASK 0x000000C0L
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_NP_MASK 0x00000300L
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_P_MASK 0x00000C00L
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_NP_MASK 0x00003000L
+//PCIE_CI_CNTL
+#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2
+#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x3
+#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x4
+#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6
+#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8
+#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x9
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc
+#define PCIE_CI_CNTL__CI_SLV_SDP_ERR_DATA_ON_POISONED_DIS__SHIFT 0x10
+#define PCIE_CI_CNTL__TX_PRIV_TLP_PREFIX_BLOCKING_DIS__SHIFT 0x11
+#define PCIE_CI_CNTL__TX_PRIV_POISONED_TLP_EGRESS_BLOCKING_DIS__SHIFT 0x12
+#define PCIE_CI_CNTL__TX_PRIV_ATOMICOP_EGRESS_BLOCKING_DIS__SHIFT 0x13
+#define PCIE_CI_CNTL__PRIV_AUTO_SLOT_PWR_LIMIT_DIS__SHIFT 0x14
+#define PCIE_CI_CNTL__TX_DISABLE_SLOT_PWR_LIMIT_MSG__SHIFT 0x15
+#define PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_UR_EN__SHIFT 0x16
+#define PCIE_CI_CNTL__RX_RCB_RC_DPC_EXCEPTION_EN__SHIFT 0x17
+#define PCIE_CI_CNTL__RX_RCB_RC_DPC_CPL_CTL_EN__SHIFT 0x18
+#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x00000004L
+#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x00000008L
+#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x00000010L
+#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0x000000C0L
+#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x00000100L
+#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x00000200L
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x00000400L
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x00000800L
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x00001000L
+#define PCIE_CI_CNTL__CI_SLV_SDP_ERR_DATA_ON_POISONED_DIS_MASK 0x00010000L
+#define PCIE_CI_CNTL__TX_PRIV_TLP_PREFIX_BLOCKING_DIS_MASK 0x00020000L
+#define PCIE_CI_CNTL__TX_PRIV_POISONED_TLP_EGRESS_BLOCKING_DIS_MASK 0x00040000L
+#define PCIE_CI_CNTL__TX_PRIV_ATOMICOP_EGRESS_BLOCKING_DIS_MASK 0x00080000L
+#define PCIE_CI_CNTL__PRIV_AUTO_SLOT_PWR_LIMIT_DIS_MASK 0x00100000L
+#define PCIE_CI_CNTL__TX_DISABLE_SLOT_PWR_LIMIT_MSG_MASK 0x00200000L
+#define PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_UR_EN_MASK 0x00400000L
+#define PCIE_CI_CNTL__RX_RCB_RC_DPC_EXCEPTION_EN_MASK 0x00800000L
+#define PCIE_CI_CNTL__RX_RCB_RC_DPC_CPL_CTL_EN_MASK 0x01000000L
+//PCIE_BUS_CNTL
+#define PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6
+#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc
+#define PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x00000040L
+#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x00001000L
+//PCIE_LC_STATE6
+#define PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0
+#define PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8
+#define PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10
+#define PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18
+#define PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x0000003FL
+#define PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x00003F00L
+#define PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x003F0000L
+#define PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3F000000L
+//PCIE_LC_STATE7
+#define PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0
+#define PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8
+#define PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10
+#define PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18
+#define PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x0000003FL
+#define PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x00003F00L
+#define PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x003F0000L
+#define PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3F000000L
+//PCIE_LC_STATE8
+#define PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0
+#define PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8
+#define PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10
+#define PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18
+#define PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x0000003FL
+#define PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x00003F00L
+#define PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x003F0000L
+#define PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3F000000L
+//PCIE_LC_STATE9
+#define PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0
+#define PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8
+#define PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10
+#define PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18
+#define PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x0000003FL
+#define PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x00003F00L
+#define PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x003F0000L
+#define PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3F000000L
+//PCIE_LC_STATE10
+#define PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0
+#define PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8
+#define PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10
+#define PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18
+#define PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x0000003FL
+#define PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x00003F00L
+#define PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x003F0000L
+#define PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3F000000L
+//PCIE_LC_STATE11
+#define PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0
+#define PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8
+#define PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10
+#define PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18
+#define PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x0000003FL
+#define PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x00003F00L
+#define PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x003F0000L
+#define PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3F000000L
+//PCIE_LC_STATUS1
+#define PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0
+#define PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1
+#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2
+#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5
+#define PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x00000001L
+#define PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x00000002L
+#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x0000001CL
+#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0x000000E0L
+//PCIE_LC_STATUS2
+#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0
+#define PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10
+#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0x0000FFFFL
+#define PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xFFFF0000L
+//PCIE_WPR_CNTL
+#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0
+#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1
+#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2
+#define PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3
+#define PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4
+#define PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5
+#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6
+#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x00000001L
+#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x00000002L
+#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x00000004L
+#define PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x00000008L
+#define PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x00000010L
+#define PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x00000020L
+#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x00000040L
+//PCIE_RX_LAST_TLP0
+#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0
+#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xFFFFFFFFL
+//PCIE_RX_LAST_TLP1
+#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0
+#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xFFFFFFFFL
+//PCIE_RX_LAST_TLP2
+#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0
+#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xFFFFFFFFL
+//PCIE_RX_LAST_TLP3
+#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0
+#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xFFFFFFFFL
+//PCIE_TX_LAST_TLP0
+#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0
+#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xFFFFFFFFL
+//PCIE_TX_LAST_TLP1
+#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0
+#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xFFFFFFFFL
+//PCIE_TX_LAST_TLP2
+#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0
+#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xFFFFFFFFL
+//PCIE_TX_LAST_TLP3
+#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0
+#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xFFFFFFFFL
+//PCIE_I2C_REG_ADDR_EXPAND
+#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0
+#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x0001FFFFL
+//PCIE_I2C_REG_DATA
+#define PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0
+#define PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xFFFFFFFFL
+//PCIE_CFG_CNTL
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+//PCIE_LC_PM_CNTL
+#define PCIE_LC_PM_CNTL__LC_PORT_0_CLKREQB_MAP__SHIFT 0x0
+#define PCIE_LC_PM_CNTL__LC_PORT_1_CLKREQB_MAP__SHIFT 0x4
+#define PCIE_LC_PM_CNTL__LC_PORT_2_CLKREQB_MAP__SHIFT 0x8
+#define PCIE_LC_PM_CNTL__LC_PORT_3_CLKREQB_MAP__SHIFT 0xc
+#define PCIE_LC_PM_CNTL__LC_PORT_4_CLKREQB_MAP__SHIFT 0x10
+#define PCIE_LC_PM_CNTL__LC_PORT_5_CLKREQB_MAP__SHIFT 0x14
+#define PCIE_LC_PM_CNTL__LC_PORT_6_CLKREQB_MAP__SHIFT 0x18
+#define PCIE_LC_PM_CNTL__LC_PORT_7_CLKREQB_MAP__SHIFT 0x1c
+#define PCIE_LC_PM_CNTL__LC_PORT_0_CLKREQB_MAP_MASK 0x0000000FL
+#define PCIE_LC_PM_CNTL__LC_PORT_1_CLKREQB_MAP_MASK 0x000000F0L
+#define PCIE_LC_PM_CNTL__LC_PORT_2_CLKREQB_MAP_MASK 0x00000F00L
+#define PCIE_LC_PM_CNTL__LC_PORT_3_CLKREQB_MAP_MASK 0x0000F000L
+#define PCIE_LC_PM_CNTL__LC_PORT_4_CLKREQB_MAP_MASK 0x000F0000L
+#define PCIE_LC_PM_CNTL__LC_PORT_5_CLKREQB_MAP_MASK 0x00F00000L
+#define PCIE_LC_PM_CNTL__LC_PORT_6_CLKREQB_MAP_MASK 0x0F000000L
+#define PCIE_LC_PM_CNTL__LC_PORT_7_CLKREQB_MAP_MASK 0xF0000000L
+//PCIE_LC_PORT_ORDER_CNTL
+#define PCIE_LC_PORT_ORDER_CNTL__LC_PORT_ORDER_EN__SHIFT 0x0
+#define PCIE_LC_PORT_ORDER_CNTL__LC_PORT_ORDER_EN_MASK 0x00000001L
+//PCIE_P_CNTL
+#define PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0
+#define PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1
+#define PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4
+#define PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5
+#define PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6
+#define PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7
+#define PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8
+#define PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc
+#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd
+#define PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe
+#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT 0x10
+#define PCIE_P_CNTL__ASSERT_DVALID_ON_EI_TRANS__SHIFT 0x11
+#define PCIE_P_CNTL__P_PWRDN_EN_MASK 0x00000001L
+#define PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x00000002L
+#define PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x00000010L
+#define PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x00000020L
+#define PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x00000040L
+#define PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x00000080L
+#define PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x00000100L
+#define PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x00001000L
+#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x00002000L
+#define PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0x0000C000L
+#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK 0x00010000L
+#define PCIE_P_CNTL__ASSERT_DVALID_ON_EI_TRANS_MASK 0x00020000L
+//PCIE_P_BUF_STATUS
+#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0
+#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10
+#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0x0000FFFFL
+#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xFFFF0000L
+//PCIE_P_DECODER_STATUS
+#define PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0
+#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0x0000FFFFL
+//PCIE_P_MISC_STATUS
+#define PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0
+#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10
+#define PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0x000000FFL
+#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xFFFF0000L
+//PCIE_P_RCV_L0S_FTS_DET
+#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0
+#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8
+#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0x000000FFL
+#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0x0000FF00L
+//PCIE_RX_AD
+#define PCIE_RX_AD__RX_SWUS_DROP_PME_TO__SHIFT 0x0
+#define PCIE_RX_AD__RX_SWUS_DROP_UNLOCK__SHIFT 0x1
+#define PCIE_RX_AD__RX_SWUS_UR_VDM0__SHIFT 0x2
+#define PCIE_RX_AD__RX_SWUS_DROP_VDM0__SHIFT 0x3
+#define PCIE_RX_AD__RX_SWUS_DROP_VDM1__SHIFT 0x4
+#define PCIE_RX_AD__RX_SWUS_UR_MSG_PREFIX_DIS__SHIFT 0x5
+#define PCIE_RX_AD__RX_RC_DROP_VDM0__SHIFT 0x8
+#define PCIE_RX_AD__RX_RC_UR_VDM0__SHIFT 0x9
+#define PCIE_RX_AD__RX_RC_DROP_VDM1__SHIFT 0xa
+#define PCIE_RX_AD__RX_RC_UR_SSPL_MSG__SHIFT 0xb
+#define PCIE_RX_AD__RX_RC_UR_BFRC_MSG__SHIFT 0xc
+#define PCIE_RX_AD__RX_RC_DROP_PME_TO_ACK__SHIFT 0xd
+#define PCIE_RX_AD__RX_RC_UR_ECRC_DIS__SHIFT 0xe
+#define PCIE_RX_AD__RX_RC_DROP_CPL_ECRC_FAILURE__SHIFT 0xf
+#define PCIE_RX_AD__RX_SWUS_DROP_PME_TO_MASK 0x00000001L
+#define PCIE_RX_AD__RX_SWUS_DROP_UNLOCK_MASK 0x00000002L
+#define PCIE_RX_AD__RX_SWUS_UR_VDM0_MASK 0x00000004L
+#define PCIE_RX_AD__RX_SWUS_DROP_VDM0_MASK 0x00000008L
+#define PCIE_RX_AD__RX_SWUS_DROP_VDM1_MASK 0x00000010L
+#define PCIE_RX_AD__RX_SWUS_UR_MSG_PREFIX_DIS_MASK 0x00000020L
+#define PCIE_RX_AD__RX_RC_DROP_VDM0_MASK 0x00000100L
+#define PCIE_RX_AD__RX_RC_UR_VDM0_MASK 0x00000200L
+#define PCIE_RX_AD__RX_RC_DROP_VDM1_MASK 0x00000400L
+#define PCIE_RX_AD__RX_RC_UR_SSPL_MSG_MASK 0x00000800L
+#define PCIE_RX_AD__RX_RC_UR_BFRC_MSG_MASK 0x00001000L
+#define PCIE_RX_AD__RX_RC_DROP_PME_TO_ACK_MASK 0x00002000L
+#define PCIE_RX_AD__RX_RC_UR_ECRC_DIS_MASK 0x00004000L
+#define PCIE_RX_AD__RX_RC_DROP_CPL_ECRC_FAILURE_MASK 0x00008000L
+//PCIE_SDP_CTRL
+#define PCIE_SDP_CTRL__SDP_UNIT_ID__SHIFT 0x0
+#define PCIE_SDP_CTRL__CI_SLV_REQR_FULL_DISCONNECT_EN__SHIFT 0x4
+#define PCIE_SDP_CTRL__CI_SLV_REQR_PART_DISCONNECT_EN__SHIFT 0x5
+#define PCIE_SDP_CTRL__CI_MSTSDP_CLKGATE_ONESIDED_ENABLE__SHIFT 0x6
+#define PCIE_SDP_CTRL__TX_RC_TPH_PRIV_DIS__SHIFT 0x7
+#define PCIE_SDP_CTRL__TX_SWUS_TPH_PRIV_DIS__SHIFT 0x8
+#define PCIE_SDP_CTRL__CI_SLAVE_TAG_STEALING_DIS__SHIFT 0x9
+#define PCIE_SDP_CTRL__SLAVE_PREFIX_PRELOAD_DIS__SHIFT 0xa
+#define PCIE_SDP_CTRL__CI_DISABLE_LTR_DROPPING__SHIFT 0xb
+#define PCIE_SDP_CTRL__RX_SWUS_SIDEBAND_CPLHDR_DIS__SHIFT 0xc
+#define PCIE_SDP_CTRL__CI_MST_MEMR_RD_NONCONT_BE_EN__SHIFT 0xd
+#define PCIE_SDP_CTRL__CI_MSTSDP_DISCONNECT_RSP_ON_PARTIAL__SHIFT 0xe
+#define PCIE_SDP_CTRL__CI_SWUS_RCVD_ERR_HANDLING_DIS__SHIFT 0xf
+#define PCIE_SDP_CTRL__SDP_UNIT_ID_MASK 0x0000000FL
+#define PCIE_SDP_CTRL__CI_SLV_REQR_FULL_DISCONNECT_EN_MASK 0x00000010L
+#define PCIE_SDP_CTRL__CI_SLV_REQR_PART_DISCONNECT_EN_MASK 0x00000020L
+#define PCIE_SDP_CTRL__CI_MSTSDP_CLKGATE_ONESIDED_ENABLE_MASK 0x00000040L
+#define PCIE_SDP_CTRL__TX_RC_TPH_PRIV_DIS_MASK 0x00000080L
+#define PCIE_SDP_CTRL__TX_SWUS_TPH_PRIV_DIS_MASK 0x00000100L
+#define PCIE_SDP_CTRL__CI_SLAVE_TAG_STEALING_DIS_MASK 0x00000200L
+#define PCIE_SDP_CTRL__SLAVE_PREFIX_PRELOAD_DIS_MASK 0x00000400L
+#define PCIE_SDP_CTRL__CI_DISABLE_LTR_DROPPING_MASK 0x00000800L
+#define PCIE_SDP_CTRL__RX_SWUS_SIDEBAND_CPLHDR_DIS_MASK 0x00001000L
+#define PCIE_SDP_CTRL__CI_MST_MEMR_RD_NONCONT_BE_EN_MASK 0x00002000L
+#define PCIE_SDP_CTRL__CI_MSTSDP_DISCONNECT_RSP_ON_PARTIAL_MASK 0x00004000L
+#define PCIE_SDP_CTRL__CI_SWUS_RCVD_ERR_HANDLING_DIS_MASK 0x00008000L
+//NBIO_CLKREQb_MAP_CNTL
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_0_MAP__SHIFT 0x0
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_1_MAP__SHIFT 0x4
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_2_MAP__SHIFT 0x8
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_3_MAP__SHIFT 0xc
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_4_MAP__SHIFT 0x10
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_CNTL_MASK__SHIFT 0x1c
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_0_MAP_MASK 0x0000000FL
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_1_MAP_MASK 0x000000F0L
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_2_MAP_MASK 0x00000F00L
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_3_MAP_MASK 0x0000F000L
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_4_MAP_MASK 0x000F0000L
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_CNTL_MASK_MASK 0x10000000L
+//PCIE_SDP_SWUS_SLV_ATTR_CTRL
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMWR__SHIFT 0x0
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMRD__SHIFT 0x2
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_ATOMIC__SHIFT 0x4
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMWR__SHIFT 0x6
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMRD__SHIFT 0x8
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_ATOMIC__SHIFT 0xa
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMWR__SHIFT 0xc
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMRD__SHIFT 0xe
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_ATOMIC__SHIFT 0x10
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMWR_MASK 0x00000003L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMRD_MASK 0x0000000CL
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_ATOMIC_MASK 0x00000030L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMWR_MASK 0x000000C0L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMRD_MASK 0x00000300L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_ATOMIC_MASK 0x00000C00L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMWR_MASK 0x00003000L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMRD_MASK 0x0000C000L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_ATOMIC_MASK 0x00030000L
+//PCIE_SDP_RC_SLV_ATTR_CTRL
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_MEMWR__SHIFT 0x0
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_MEMRD__SHIFT 0x2
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_ATOMIC__SHIFT 0x4
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_MEMWR__SHIFT 0x6
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_MEMRD__SHIFT 0x8
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_ATOMIC__SHIFT 0xa
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_MEMWR__SHIFT 0xc
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_MEMRD__SHIFT 0xe
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_ATOMIC__SHIFT 0x10
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_MEMWR_MASK 0x00000003L
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_MEMRD_MASK 0x0000000CL
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_ATOMIC_MASK 0x00000030L
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_MEMWR_MASK 0x000000C0L
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_MEMRD_MASK 0x00000300L
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_ATOMIC_MASK 0x00000C00L
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_MEMWR_MASK 0x00003000L
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_MEMRD_MASK 0x0000C000L
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_ATOMIC_MASK 0x00030000L
+//PCIE_PERF_COUNT_CNTL
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x00000001L
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x00000002L
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x00000004L
+//PCIE_PERF_CNTL_TXCLK
+#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0x000000FFL
+#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0x0000FF00L
+#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0x00FF0000L
+#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xFF000000L
+//PCIE_PERF_COUNT0_TXCLK
+#define PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xFFFFFFFFL
+//PCIE_PERF_COUNT1_TXCLK
+#define PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xFFFFFFFFL
+//PCIE_PERF_CNTL_MST_R_CLK
+#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0x000000FFL
+#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0x0000FF00L
+#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0x00FF0000L
+#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xFF000000L
+//PCIE_PERF_COUNT0_MST_R_CLK
+#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xFFFFFFFFL
+//PCIE_PERF_COUNT1_MST_R_CLK
+#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xFFFFFFFFL
+//PCIE_PERF_CNTL_MST_C_CLK
+#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0x000000FFL
+#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0x0000FF00L
+#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0x00FF0000L
+#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xFF000000L
+//PCIE_PERF_COUNT0_MST_C_CLK
+#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xFFFFFFFFL
+//PCIE_PERF_COUNT1_MST_C_CLK
+#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xFFFFFFFFL
+//PCIE_PERF_CNTL_SLV_R_CLK
+#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0x000000FFL
+#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0x0000FF00L
+#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0x00FF0000L
+#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xFF000000L
+//PCIE_PERF_COUNT0_SLV_R_CLK
+#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xFFFFFFFFL
+//PCIE_PERF_COUNT1_SLV_R_CLK
+#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xFFFFFFFFL
+//PCIE_PERF_CNTL_SLV_S_C_CLK
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0x000000FFL
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0x0000FF00L
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0x00FF0000L
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xFF000000L
+//PCIE_PERF_COUNT0_SLV_S_C_CLK
+#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xFFFFFFFFL
+//PCIE_PERF_COUNT1_SLV_S_C_CLK
+#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xFFFFFFFFL
+//PCIE_PERF_CNTL_SLV_NS_C_CLK
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0x000000FFL
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0x0000FF00L
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0x00FF0000L
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xFF000000L
+//PCIE_PERF_COUNT0_SLV_NS_C_CLK
+#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xFFFFFFFFL
+//PCIE_PERF_COUNT1_SLV_NS_C_CLK
+#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xFFFFFFFFL
+//PCIE_PERF_CNTL_EVENT0_PORT_SEL
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x0
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x4
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x8
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0xc
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x18
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0x0000000FL
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0x000000F0L
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0x00000F00L
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0x0000F000L
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0x000F0000L
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0x00F00000L
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0x0F000000L
+//PCIE_PERF_CNTL_EVENT1_PORT_SEL
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x0
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x4
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x8
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0xc
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x18
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0x0000000FL
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0x000000F0L
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0x00000F00L
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0x0000F000L
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0x000F0000L
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0x00F00000L
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0x0F000000L
+//PCIE_PERF_CNTL_TXCLK2
+#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0x000000FFL
+#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0x0000FF00L
+#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0x00FF0000L
+#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xFF000000L
+//PCIE_PERF_COUNT0_TXCLK2
+#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xFFFFFFFFL
+//PCIE_PERF_COUNT1_TXCLK2
+#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xFFFFFFFFL
+//PCIE_PRBS_CLR
+#define PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0
+#define PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT 0x18
+#define PCIE_PRBS_CLR__PRBS_CLR_MASK 0x0000FFFFL
+#define PCIE_PRBS_CLR__PRBS_POLARITY_EN_MASK 0x01000000L
+//PCIE_PRBS_STATUS1
+#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0
+#define PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10
+#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0x0000FFFFL
+#define PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xFFFF0000L
+//PCIE_PRBS_STATUS2
+#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0
+#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0x0000FFFFL
+//PCIE_PRBS_FREERUN
+#define PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0
+#define PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0x0000FFFFL
+//PCIE_PRBS_MISC
+#define PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0
+#define PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1
+#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x4
+#define PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x5
+#define PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x6
+#define PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x8
+#define PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe
+#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10
+#define PCIE_PRBS_MISC__PRBS_EN_MASK 0x00000001L
+#define PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0x0000000EL
+#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x00000010L
+#define PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x00000020L
+#define PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0x000000C0L
+#define PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0x00001F00L
+#define PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0x0000C000L
+#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xFFFF0000L
+//PCIE_PRBS_USER_PATTERN
+#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0
+#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3FFFFFFFL
+//PCIE_PRBS_LO_BITCNT
+#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0
+#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xFFFFFFFFL
+//PCIE_PRBS_HI_BITCNT
+#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0
+#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0x000000FFL
+//PCIE_PRBS_ERRCNT_0
+#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_1
+#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_2
+#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_3
+#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_4
+#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_5
+#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_6
+#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_7
+#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_8
+#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_9
+#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_10
+#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_11
+#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_12
+#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_13
+#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_14
+#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_15
+#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xFFFFFFFFL
+//SWRST_COMMAND_STATUS
+#define SWRST_COMMAND_STATUS__RECONFIGURE__SHIFT 0x0
+#define SWRST_COMMAND_STATUS__ATOMIC_RESET__SHIFT 0x1
+#define SWRST_COMMAND_STATUS__RESET_COMPLETE__SHIFT 0x10
+#define SWRST_COMMAND_STATUS__WAIT_STATE__SHIFT 0x11
+#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET__SHIFT 0x18
+#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_CFG_ONLY__SHIFT 0x19
+#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_PHY_CALIB__SHIFT 0x1a
+#define SWRST_COMMAND_STATUS__SWDS_LINK_RESET__SHIFT 0x1b
+#define SWRST_COMMAND_STATUS__SWDS_LINK_RESET_CFG_ONLY__SHIFT 0x1c
+#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_HOT_RESET__SHIFT 0x1d
+#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DISABLE__SHIFT 0x1e
+#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DOWN__SHIFT 0x1f
+#define SWRST_COMMAND_STATUS__RECONFIGURE_MASK 0x00000001L
+#define SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK 0x00000002L
+#define SWRST_COMMAND_STATUS__RESET_COMPLETE_MASK 0x00010000L
+#define SWRST_COMMAND_STATUS__WAIT_STATE_MASK 0x00020000L
+#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_MASK 0x01000000L
+#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_CFG_ONLY_MASK 0x02000000L
+#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_PHY_CALIB_MASK 0x04000000L
+#define SWRST_COMMAND_STATUS__SWDS_LINK_RESET_MASK 0x08000000L
+#define SWRST_COMMAND_STATUS__SWDS_LINK_RESET_CFG_ONLY_MASK 0x10000000L
+#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_HOT_RESET_MASK 0x20000000L
+#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DISABLE_MASK 0x40000000L
+#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DOWN_MASK 0x80000000L
+//SWRST_GENERAL_CONTROL
+#define SWRST_GENERAL_CONTROL__RECONFIGURE_EN__SHIFT 0x0
+#define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN__SHIFT 0x1
+#define SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT 0x2
+#define SWRST_GENERAL_CONTROL__WAIT_LINKUP__SHIFT 0x8
+#define SWRST_GENERAL_CONTROL__FORCE_REGIDLE__SHIFT 0x9
+#define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE__SHIFT 0xa
+#define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE__SHIFT 0xc
+#define SWRST_GENERAL_CONTROL__BYPASS_PCS_HOLD__SHIFT 0x11
+#define SWRST_GENERAL_CONTROL__MP1_PCIE_CROSSFIRE_LOCKDOWN_EN__SHIFT 0x18
+#define SWRST_GENERAL_CONTROL__IGNORE_SDP_RESET__SHIFT 0x19
+#define SWRST_GENERAL_CONTROL__RECONFIGURE_EN_MASK 0x00000001L
+#define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK 0x00000002L
+#define SWRST_GENERAL_CONTROL__RESET_PERIOD_MASK 0x0000001CL
+#define SWRST_GENERAL_CONTROL__WAIT_LINKUP_MASK 0x00000100L
+#define SWRST_GENERAL_CONTROL__FORCE_REGIDLE_MASK 0x00000200L
+#define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE_MASK 0x00000400L
+#define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE_MASK 0x00001000L
+#define SWRST_GENERAL_CONTROL__BYPASS_PCS_HOLD_MASK 0x00020000L
+#define SWRST_GENERAL_CONTROL__MP1_PCIE_CROSSFIRE_LOCKDOWN_EN_MASK 0x01000000L
+#define SWRST_GENERAL_CONTROL__IGNORE_SDP_RESET_MASK 0x02000000L
+//SWRST_COMMAND_0
+#define SWRST_COMMAND_0__PORT0_COR_RESET__SHIFT 0x0
+#define SWRST_COMMAND_0__PORT0_CFG_RESET__SHIFT 0x8
+#define SWRST_COMMAND_0__PORT1_CFG_RESET__SHIFT 0x9
+#define SWRST_COMMAND_0__PORT2_CFG_RESET__SHIFT 0xa
+#define SWRST_COMMAND_0__PORT3_CFG_RESET__SHIFT 0xb
+#define SWRST_COMMAND_0__PORT4_CFG_RESET__SHIFT 0xc
+#define SWRST_COMMAND_0__PORT5_CFG_RESET__SHIFT 0xd
+#define SWRST_COMMAND_0__PORT6_CFG_RESET__SHIFT 0xe
+#define SWRST_COMMAND_0__PORT7_CFG_RESET__SHIFT 0xf
+#define SWRST_COMMAND_0__BIF0_GLOBAL_RESET__SHIFT 0x18
+#define SWRST_COMMAND_0__BIF0_CALIB_RESET__SHIFT 0x19
+#define SWRST_COMMAND_0__BIF0_CORE_RESET__SHIFT 0x1a
+#define SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT 0x1b
+#define SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT 0x1c
+#define SWRST_COMMAND_0__BIF0_STICKY_RESET__SHIFT 0x1d
+#define SWRST_COMMAND_0__BIF0_CONFIG_RESET__SHIFT 0x1e
+#define SWRST_COMMAND_0__PORT0_COR_RESET_MASK 0x00000001L
+#define SWRST_COMMAND_0__PORT0_CFG_RESET_MASK 0x00000100L
+#define SWRST_COMMAND_0__PORT1_CFG_RESET_MASK 0x00000200L
+#define SWRST_COMMAND_0__PORT2_CFG_RESET_MASK 0x00000400L
+#define SWRST_COMMAND_0__PORT3_CFG_RESET_MASK 0x00000800L
+#define SWRST_COMMAND_0__PORT4_CFG_RESET_MASK 0x00001000L
+#define SWRST_COMMAND_0__PORT5_CFG_RESET_MASK 0x00002000L
+#define SWRST_COMMAND_0__PORT6_CFG_RESET_MASK 0x00004000L
+#define SWRST_COMMAND_0__PORT7_CFG_RESET_MASK 0x00008000L
+#define SWRST_COMMAND_0__BIF0_GLOBAL_RESET_MASK 0x01000000L
+#define SWRST_COMMAND_0__BIF0_CALIB_RESET_MASK 0x02000000L
+#define SWRST_COMMAND_0__BIF0_CORE_RESET_MASK 0x04000000L
+#define SWRST_COMMAND_0__BIF0_REGISTER_RESET_MASK 0x08000000L
+#define SWRST_COMMAND_0__BIF0_PHY_RESET_MASK 0x10000000L
+#define SWRST_COMMAND_0__BIF0_STICKY_RESET_MASK 0x20000000L
+#define SWRST_COMMAND_0__BIF0_CONFIG_RESET_MASK 0x40000000L
+//SWRST_COMMAND_1
+#define SWRST_COMMAND_1__RESETPCS0__SHIFT 0x0
+#define SWRST_COMMAND_1__RESETPCS1__SHIFT 0x1
+#define SWRST_COMMAND_1__RESETPCS2__SHIFT 0x2
+#define SWRST_COMMAND_1__RESETPCS3__SHIFT 0x3
+#define SWRST_COMMAND_1__RESETPCS4__SHIFT 0x4
+#define SWRST_COMMAND_1__RESETPCS5__SHIFT 0x5
+#define SWRST_COMMAND_1__RESETPCS6__SHIFT 0x6
+#define SWRST_COMMAND_1__RESETPCS7__SHIFT 0x7
+#define SWRST_COMMAND_1__RESETPCS8__SHIFT 0x8
+#define SWRST_COMMAND_1__RESETPCS9__SHIFT 0x9
+#define SWRST_COMMAND_1__RESETPCS10__SHIFT 0xa
+#define SWRST_COMMAND_1__RESETPCS11__SHIFT 0xb
+#define SWRST_COMMAND_1__RESETPCS12__SHIFT 0xc
+#define SWRST_COMMAND_1__RESETPCS13__SHIFT 0xd
+#define SWRST_COMMAND_1__RESETPCS14__SHIFT 0xe
+#define SWRST_COMMAND_1__RESETPCS15__SHIFT 0xf
+#define SWRST_COMMAND_1__SWITCHCLK__SHIFT 0x15
+#define SWRST_COMMAND_1__RESETAXIMST__SHIFT 0x16
+#define SWRST_COMMAND_1__RESETAXISLV__SHIFT 0x17
+#define SWRST_COMMAND_1__RESETAXIINT__SHIFT 0x18
+#define SWRST_COMMAND_1__RESETPCFG__SHIFT 0x19
+#define SWRST_COMMAND_1__RESETLNCT__SHIFT 0x1a
+#define SWRST_COMMAND_1__RESETMNTR__SHIFT 0x1b
+#define SWRST_COMMAND_1__RESETHLTR__SHIFT 0x1c
+#define SWRST_COMMAND_1__RESETCPM__SHIFT 0x1d
+#define SWRST_COMMAND_1__RESETPHY0__SHIFT 0x1e
+#define SWRST_COMMAND_1__TOGGLESTRAP__SHIFT 0x1f
+#define SWRST_COMMAND_1__RESETPCS0_MASK 0x00000001L
+#define SWRST_COMMAND_1__RESETPCS1_MASK 0x00000002L
+#define SWRST_COMMAND_1__RESETPCS2_MASK 0x00000004L
+#define SWRST_COMMAND_1__RESETPCS3_MASK 0x00000008L
+#define SWRST_COMMAND_1__RESETPCS4_MASK 0x00000010L
+#define SWRST_COMMAND_1__RESETPCS5_MASK 0x00000020L
+#define SWRST_COMMAND_1__RESETPCS6_MASK 0x00000040L
+#define SWRST_COMMAND_1__RESETPCS7_MASK 0x00000080L
+#define SWRST_COMMAND_1__RESETPCS8_MASK 0x00000100L
+#define SWRST_COMMAND_1__RESETPCS9_MASK 0x00000200L
+#define SWRST_COMMAND_1__RESETPCS10_MASK 0x00000400L
+#define SWRST_COMMAND_1__RESETPCS11_MASK 0x00000800L
+#define SWRST_COMMAND_1__RESETPCS12_MASK 0x00001000L
+#define SWRST_COMMAND_1__RESETPCS13_MASK 0x00002000L
+#define SWRST_COMMAND_1__RESETPCS14_MASK 0x00004000L
+#define SWRST_COMMAND_1__RESETPCS15_MASK 0x00008000L
+#define SWRST_COMMAND_1__SWITCHCLK_MASK 0x00200000L
+#define SWRST_COMMAND_1__RESETAXIMST_MASK 0x00400000L
+#define SWRST_COMMAND_1__RESETAXISLV_MASK 0x00800000L
+#define SWRST_COMMAND_1__RESETAXIINT_MASK 0x01000000L
+#define SWRST_COMMAND_1__RESETPCFG_MASK 0x02000000L
+#define SWRST_COMMAND_1__RESETLNCT_MASK 0x04000000L
+#define SWRST_COMMAND_1__RESETMNTR_MASK 0x08000000L
+#define SWRST_COMMAND_1__RESETHLTR_MASK 0x10000000L
+#define SWRST_COMMAND_1__RESETCPM_MASK 0x20000000L
+#define SWRST_COMMAND_1__RESETPHY0_MASK 0x40000000L
+#define SWRST_COMMAND_1__TOGGLESTRAP_MASK 0x80000000L
+//SWRST_CONTROL_0
+#define SWRST_CONTROL_0__PORT0_COR_RCEN__SHIFT 0x0
+#define SWRST_CONTROL_0__PORT0_CFG_RCEN__SHIFT 0x8
+#define SWRST_CONTROL_0__PORT1_CFG_RCEN__SHIFT 0x9
+#define SWRST_CONTROL_0__PORT2_CFG_RCEN__SHIFT 0xa
+#define SWRST_CONTROL_0__PORT3_CFG_RCEN__SHIFT 0xb
+#define SWRST_CONTROL_0__PORT4_CFG_RCEN__SHIFT 0xc
+#define SWRST_CONTROL_0__PORT5_CFG_RCEN__SHIFT 0xd
+#define SWRST_CONTROL_0__PORT6_CFG_RCEN__SHIFT 0xe
+#define SWRST_CONTROL_0__PORT7_CFG_RCEN__SHIFT 0xf
+#define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN__SHIFT 0x18
+#define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN__SHIFT 0x19
+#define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN__SHIFT 0x1a
+#define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN__SHIFT 0x1b
+#define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN__SHIFT 0x1c
+#define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN__SHIFT 0x1d
+#define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN__SHIFT 0x1e
+#define SWRST_CONTROL_0__PORT0_COR_RCEN_MASK 0x00000001L
+#define SWRST_CONTROL_0__PORT0_CFG_RCEN_MASK 0x00000100L
+#define SWRST_CONTROL_0__PORT1_CFG_RCEN_MASK 0x00000200L
+#define SWRST_CONTROL_0__PORT2_CFG_RCEN_MASK 0x00000400L
+#define SWRST_CONTROL_0__PORT3_CFG_RCEN_MASK 0x00000800L
+#define SWRST_CONTROL_0__PORT4_CFG_RCEN_MASK 0x00001000L
+#define SWRST_CONTROL_0__PORT5_CFG_RCEN_MASK 0x00002000L
+#define SWRST_CONTROL_0__PORT6_CFG_RCEN_MASK 0x00004000L
+#define SWRST_CONTROL_0__PORT7_CFG_RCEN_MASK 0x00008000L
+#define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN_MASK 0x01000000L
+#define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN_MASK 0x02000000L
+#define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN_MASK 0x04000000L
+#define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN_MASK 0x08000000L
+#define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN_MASK 0x10000000L
+#define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN_MASK 0x20000000L
+#define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN_MASK 0x40000000L
+//SWRST_CONTROL_1
+#define SWRST_CONTROL_1__PCSRESET0_RCEN__SHIFT 0x0
+#define SWRST_CONTROL_1__PCSRESET1_RCEN__SHIFT 0x1
+#define SWRST_CONTROL_1__PCSRESET2_RCEN__SHIFT 0x2
+#define SWRST_CONTROL_1__PCSRESET3_RCEN__SHIFT 0x3
+#define SWRST_CONTROL_1__PCSRESET4_RCEN__SHIFT 0x4
+#define SWRST_CONTROL_1__PCSRESET5_RCEN__SHIFT 0x5
+#define SWRST_CONTROL_1__PCSRESET6_RCEN__SHIFT 0x6
+#define SWRST_CONTROL_1__PCSRESET7_RCEN__SHIFT 0x7
+#define SWRST_CONTROL_1__PCSRESET8_RCEN__SHIFT 0x8
+#define SWRST_CONTROL_1__PCSRESET9_RCEN__SHIFT 0x9
+#define SWRST_CONTROL_1__PCSRESET10_RCEN__SHIFT 0xa
+#define SWRST_CONTROL_1__PCSRESET11_RCEN__SHIFT 0xb
+#define SWRST_CONTROL_1__PCSRESET12_RCEN__SHIFT 0xc
+#define SWRST_CONTROL_1__PCSRESET13_RCEN__SHIFT 0xd
+#define SWRST_CONTROL_1__PCSRESET14_RCEN__SHIFT 0xe
+#define SWRST_CONTROL_1__PCSRESET15_RCEN__SHIFT 0xf
+#define SWRST_CONTROL_1__SWITCHCLK_RCEN__SHIFT 0x15
+#define SWRST_CONTROL_1__RESETAXIMST_RCEN__SHIFT 0x16
+#define SWRST_CONTROL_1__RESETAXISLV_RCEN__SHIFT 0x17
+#define SWRST_CONTROL_1__RESETAXIINT_RCEN__SHIFT 0x18
+#define SWRST_CONTROL_1__RESETPCFG_RCEN__SHIFT 0x19
+#define SWRST_CONTROL_1__RESETLNCT_RCEN__SHIFT 0x1a
+#define SWRST_CONTROL_1__RESETMNTR_RCEN__SHIFT 0x1b
+#define SWRST_CONTROL_1__RESETHLTR_RCEN__SHIFT 0x1c
+#define SWRST_CONTROL_1__RESETCPM_RCEN__SHIFT 0x1d
+#define SWRST_CONTROL_1__RESETPHY0_RCEN__SHIFT 0x1e
+#define SWRST_CONTROL_1__STRAPVLD_RCEN__SHIFT 0x1f
+#define SWRST_CONTROL_1__PCSRESET0_RCEN_MASK 0x00000001L
+#define SWRST_CONTROL_1__PCSRESET1_RCEN_MASK 0x00000002L
+#define SWRST_CONTROL_1__PCSRESET2_RCEN_MASK 0x00000004L
+#define SWRST_CONTROL_1__PCSRESET3_RCEN_MASK 0x00000008L
+#define SWRST_CONTROL_1__PCSRESET4_RCEN_MASK 0x00000010L
+#define SWRST_CONTROL_1__PCSRESET5_RCEN_MASK 0x00000020L
+#define SWRST_CONTROL_1__PCSRESET6_RCEN_MASK 0x00000040L
+#define SWRST_CONTROL_1__PCSRESET7_RCEN_MASK 0x00000080L
+#define SWRST_CONTROL_1__PCSRESET8_RCEN_MASK 0x00000100L
+#define SWRST_CONTROL_1__PCSRESET9_RCEN_MASK 0x00000200L
+#define SWRST_CONTROL_1__PCSRESET10_RCEN_MASK 0x00000400L
+#define SWRST_CONTROL_1__PCSRESET11_RCEN_MASK 0x00000800L
+#define SWRST_CONTROL_1__PCSRESET12_RCEN_MASK 0x00001000L
+#define SWRST_CONTROL_1__PCSRESET13_RCEN_MASK 0x00002000L
+#define SWRST_CONTROL_1__PCSRESET14_RCEN_MASK 0x00004000L
+#define SWRST_CONTROL_1__PCSRESET15_RCEN_MASK 0x00008000L
+#define SWRST_CONTROL_1__SWITCHCLK_RCEN_MASK 0x00200000L
+#define SWRST_CONTROL_1__RESETAXIMST_RCEN_MASK 0x00400000L
+#define SWRST_CONTROL_1__RESETAXISLV_RCEN_MASK 0x00800000L
+#define SWRST_CONTROL_1__RESETAXIINT_RCEN_MASK 0x01000000L
+#define SWRST_CONTROL_1__RESETPCFG_RCEN_MASK 0x02000000L
+#define SWRST_CONTROL_1__RESETLNCT_RCEN_MASK 0x04000000L
+#define SWRST_CONTROL_1__RESETMNTR_RCEN_MASK 0x08000000L
+#define SWRST_CONTROL_1__RESETHLTR_RCEN_MASK 0x10000000L
+#define SWRST_CONTROL_1__RESETCPM_RCEN_MASK 0x20000000L
+#define SWRST_CONTROL_1__RESETPHY0_RCEN_MASK 0x40000000L
+#define SWRST_CONTROL_1__STRAPVLD_RCEN_MASK 0x80000000L
+//SWRST_CONTROL_2
+#define SWRST_CONTROL_2__PORT0_COR_ATEN__SHIFT 0x0
+#define SWRST_CONTROL_2__PORT0_CFG_ATEN__SHIFT 0x8
+#define SWRST_CONTROL_2__PORT1_CFG_ATEN__SHIFT 0x9
+#define SWRST_CONTROL_2__PORT2_CFG_ATEN__SHIFT 0xa
+#define SWRST_CONTROL_2__PORT3_CFG_ATEN__SHIFT 0xb
+#define SWRST_CONTROL_2__PORT4_CFG_ATEN__SHIFT 0xc
+#define SWRST_CONTROL_2__PORT5_CFG_ATEN__SHIFT 0xd
+#define SWRST_CONTROL_2__PORT6_CFG_ATEN__SHIFT 0xe
+#define SWRST_CONTROL_2__PORT7_CFG_ATEN__SHIFT 0xf
+#define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN__SHIFT 0x18
+#define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN__SHIFT 0x19
+#define SWRST_CONTROL_2__BIF0_CORE_RESETATEN__SHIFT 0x1a
+#define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN__SHIFT 0x1b
+#define SWRST_CONTROL_2__BIF0_PHY_RESETATEN__SHIFT 0x1c
+#define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN__SHIFT 0x1d
+#define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN__SHIFT 0x1e
+#define SWRST_CONTROL_2__PORT0_COR_ATEN_MASK 0x00000001L
+#define SWRST_CONTROL_2__PORT0_CFG_ATEN_MASK 0x00000100L
+#define SWRST_CONTROL_2__PORT1_CFG_ATEN_MASK 0x00000200L
+#define SWRST_CONTROL_2__PORT2_CFG_ATEN_MASK 0x00000400L
+#define SWRST_CONTROL_2__PORT3_CFG_ATEN_MASK 0x00000800L
+#define SWRST_CONTROL_2__PORT4_CFG_ATEN_MASK 0x00001000L
+#define SWRST_CONTROL_2__PORT5_CFG_ATEN_MASK 0x00002000L
+#define SWRST_CONTROL_2__PORT6_CFG_ATEN_MASK 0x00004000L
+#define SWRST_CONTROL_2__PORT7_CFG_ATEN_MASK 0x00008000L
+#define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN_MASK 0x01000000L
+#define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN_MASK 0x02000000L
+#define SWRST_CONTROL_2__BIF0_CORE_RESETATEN_MASK 0x04000000L
+#define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN_MASK 0x08000000L
+#define SWRST_CONTROL_2__BIF0_PHY_RESETATEN_MASK 0x10000000L
+#define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN_MASK 0x20000000L
+#define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN_MASK 0x40000000L
+//SWRST_CONTROL_3
+#define SWRST_CONTROL_3__PCSRESET0_ATEN__SHIFT 0x0
+#define SWRST_CONTROL_3__PCSRESET1_ATEN__SHIFT 0x1
+#define SWRST_CONTROL_3__PCSRESET2_ATEN__SHIFT 0x2
+#define SWRST_CONTROL_3__PCSRESET3_ATEN__SHIFT 0x3
+#define SWRST_CONTROL_3__PCSRESET4_ATEN__SHIFT 0x4
+#define SWRST_CONTROL_3__PCSRESET5_ATEN__SHIFT 0x5
+#define SWRST_CONTROL_3__PCSRESET6_ATEN__SHIFT 0x6
+#define SWRST_CONTROL_3__PCSRESET7_ATEN__SHIFT 0x7
+#define SWRST_CONTROL_3__PCSRESET8_ATEN__SHIFT 0x8
+#define SWRST_CONTROL_3__PCSRESET9_ATEN__SHIFT 0x9
+#define SWRST_CONTROL_3__PCSRESET10_ATEN__SHIFT 0xa
+#define SWRST_CONTROL_3__PCSRESET11_ATEN__SHIFT 0xb
+#define SWRST_CONTROL_3__PCSRESET12_ATEN__SHIFT 0xc
+#define SWRST_CONTROL_3__PCSRESET13_ATEN__SHIFT 0xd
+#define SWRST_CONTROL_3__PCSRESET14_ATEN__SHIFT 0xe
+#define SWRST_CONTROL_3__PCSRESET15_ATEN__SHIFT 0xf
+#define SWRST_CONTROL_3__SWITCHCLK_ATEN__SHIFT 0x15
+#define SWRST_CONTROL_3__RESETAXIMST_ATEN__SHIFT 0x16
+#define SWRST_CONTROL_3__RESETAXISLV_ATEN__SHIFT 0x17
+#define SWRST_CONTROL_3__RESETAXIINT_ATEN__SHIFT 0x18
+#define SWRST_CONTROL_3__RESETPCFG_ATEN__SHIFT 0x19
+#define SWRST_CONTROL_3__RESETLNCT_ATEN__SHIFT 0x1a
+#define SWRST_CONTROL_3__RESETMNTR_ATEN__SHIFT 0x1b
+#define SWRST_CONTROL_3__RESETHLTR_ATEN__SHIFT 0x1c
+#define SWRST_CONTROL_3__RESETCPM_ATEN__SHIFT 0x1d
+#define SWRST_CONTROL_3__RESETPHY0_ATEN__SHIFT 0x1e
+#define SWRST_CONTROL_3__STRAPVLD_ATEN__SHIFT 0x1f
+#define SWRST_CONTROL_3__PCSRESET0_ATEN_MASK 0x00000001L
+#define SWRST_CONTROL_3__PCSRESET1_ATEN_MASK 0x00000002L
+#define SWRST_CONTROL_3__PCSRESET2_ATEN_MASK 0x00000004L
+#define SWRST_CONTROL_3__PCSRESET3_ATEN_MASK 0x00000008L
+#define SWRST_CONTROL_3__PCSRESET4_ATEN_MASK 0x00000010L
+#define SWRST_CONTROL_3__PCSRESET5_ATEN_MASK 0x00000020L
+#define SWRST_CONTROL_3__PCSRESET6_ATEN_MASK 0x00000040L
+#define SWRST_CONTROL_3__PCSRESET7_ATEN_MASK 0x00000080L
+#define SWRST_CONTROL_3__PCSRESET8_ATEN_MASK 0x00000100L
+#define SWRST_CONTROL_3__PCSRESET9_ATEN_MASK 0x00000200L
+#define SWRST_CONTROL_3__PCSRESET10_ATEN_MASK 0x00000400L
+#define SWRST_CONTROL_3__PCSRESET11_ATEN_MASK 0x00000800L
+#define SWRST_CONTROL_3__PCSRESET12_ATEN_MASK 0x00001000L
+#define SWRST_CONTROL_3__PCSRESET13_ATEN_MASK 0x00002000L
+#define SWRST_CONTROL_3__PCSRESET14_ATEN_MASK 0x00004000L
+#define SWRST_CONTROL_3__PCSRESET15_ATEN_MASK 0x00008000L
+#define SWRST_CONTROL_3__SWITCHCLK_ATEN_MASK 0x00200000L
+#define SWRST_CONTROL_3__RESETAXIMST_ATEN_MASK 0x00400000L
+#define SWRST_CONTROL_3__RESETAXISLV_ATEN_MASK 0x00800000L
+#define SWRST_CONTROL_3__RESETAXIINT_ATEN_MASK 0x01000000L
+#define SWRST_CONTROL_3__RESETPCFG_ATEN_MASK 0x02000000L
+#define SWRST_CONTROL_3__RESETLNCT_ATEN_MASK 0x04000000L
+#define SWRST_CONTROL_3__RESETMNTR_ATEN_MASK 0x08000000L
+#define SWRST_CONTROL_3__RESETHLTR_ATEN_MASK 0x10000000L
+#define SWRST_CONTROL_3__RESETCPM_ATEN_MASK 0x20000000L
+#define SWRST_CONTROL_3__RESETPHY0_ATEN_MASK 0x40000000L
+#define SWRST_CONTROL_3__STRAPVLD_ATEN_MASK 0x80000000L
+//SWRST_CONTROL_4
+#define SWRST_CONTROL_4__PORT0_COR_WREN__SHIFT 0x0
+#define SWRST_CONTROL_4__PORT0_CFG_WREN__SHIFT 0x8
+#define SWRST_CONTROL_4__PORT1_CFG_WREN__SHIFT 0x9
+#define SWRST_CONTROL_4__PORT2_CFG_WREN__SHIFT 0xa
+#define SWRST_CONTROL_4__PORT3_CFG_WREN__SHIFT 0xb
+#define SWRST_CONTROL_4__PORT4_CFG_WREN__SHIFT 0xc
+#define SWRST_CONTROL_4__PORT5_CFG_WREN__SHIFT 0xd
+#define SWRST_CONTROL_4__PORT6_CFG_WREN__SHIFT 0xe
+#define SWRST_CONTROL_4__PORT7_CFG_WREN__SHIFT 0xf
+#define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN__SHIFT 0x18
+#define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN__SHIFT 0x19
+#define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN__SHIFT 0x1a
+#define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN__SHIFT 0x1b
+#define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN__SHIFT 0x1c
+#define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN__SHIFT 0x1d
+#define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN__SHIFT 0x1e
+#define SWRST_CONTROL_4__PORT0_COR_WREN_MASK 0x00000001L
+#define SWRST_CONTROL_4__PORT0_CFG_WREN_MASK 0x00000100L
+#define SWRST_CONTROL_4__PORT1_CFG_WREN_MASK 0x00000200L
+#define SWRST_CONTROL_4__PORT2_CFG_WREN_MASK 0x00000400L
+#define SWRST_CONTROL_4__PORT3_CFG_WREN_MASK 0x00000800L
+#define SWRST_CONTROL_4__PORT4_CFG_WREN_MASK 0x00001000L
+#define SWRST_CONTROL_4__PORT5_CFG_WREN_MASK 0x00002000L
+#define SWRST_CONTROL_4__PORT6_CFG_WREN_MASK 0x00004000L
+#define SWRST_CONTROL_4__PORT7_CFG_WREN_MASK 0x00008000L
+#define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN_MASK 0x01000000L
+#define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN_MASK 0x02000000L
+#define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN_MASK 0x04000000L
+#define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN_MASK 0x08000000L
+#define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN_MASK 0x10000000L
+#define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN_MASK 0x20000000L
+#define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN_MASK 0x40000000L
+//SWRST_CONTROL_5
+#define SWRST_CONTROL_5__PCSRESET0_WREN__SHIFT 0x0
+#define SWRST_CONTROL_5__PCSRESET1_WREN__SHIFT 0x1
+#define SWRST_CONTROL_5__PCSRESET2_WREN__SHIFT 0x2
+#define SWRST_CONTROL_5__PCSRESET3_WREN__SHIFT 0x3
+#define SWRST_CONTROL_5__PCSRESET4_WREN__SHIFT 0x4
+#define SWRST_CONTROL_5__PCSRESET5_WREN__SHIFT 0x5
+#define SWRST_CONTROL_5__PCSRESET6_WREN__SHIFT 0x6
+#define SWRST_CONTROL_5__PCSRESET7_WREN__SHIFT 0x7
+#define SWRST_CONTROL_5__PCSRESET8_WREN__SHIFT 0x8
+#define SWRST_CONTROL_5__PCSRESET9_WREN__SHIFT 0x9
+#define SWRST_CONTROL_5__PCSRESET10_WREN__SHIFT 0xa
+#define SWRST_CONTROL_5__PCSRESET11_WREN__SHIFT 0xb
+#define SWRST_CONTROL_5__PCSRESET12_WREN__SHIFT 0xc
+#define SWRST_CONTROL_5__PCSRESET13_WREN__SHIFT 0xd
+#define SWRST_CONTROL_5__PCSRESET14_WREN__SHIFT 0xe
+#define SWRST_CONTROL_5__PCSRESET15_WREN__SHIFT 0xf
+#define SWRST_CONTROL_5__WRSWITCHCLK_EN__SHIFT 0x15
+#define SWRST_CONTROL_5__WRRESETAXIMST_EN__SHIFT 0x16
+#define SWRST_CONTROL_5__WRRESETAXISLV_EN__SHIFT 0x17
+#define SWRST_CONTROL_5__WRRESETAXIINT_EN__SHIFT 0x18
+#define SWRST_CONTROL_5__WRRESETPCFG_EN__SHIFT 0x19
+#define SWRST_CONTROL_5__WRRESETLNCT_EN__SHIFT 0x1a
+#define SWRST_CONTROL_5__WRRESETMNTR_EN__SHIFT 0x1b
+#define SWRST_CONTROL_5__WRRESETHLTR_EN__SHIFT 0x1c
+#define SWRST_CONTROL_5__WRRESETCPM_EN__SHIFT 0x1d
+#define SWRST_CONTROL_5__WRRESETPHY0_EN__SHIFT 0x1e
+#define SWRST_CONTROL_5__WRSTRAPVLD_EN__SHIFT 0x1f
+#define SWRST_CONTROL_5__PCSRESET0_WREN_MASK 0x00000001L
+#define SWRST_CONTROL_5__PCSRESET1_WREN_MASK 0x00000002L
+#define SWRST_CONTROL_5__PCSRESET2_WREN_MASK 0x00000004L
+#define SWRST_CONTROL_5__PCSRESET3_WREN_MASK 0x00000008L
+#define SWRST_CONTROL_5__PCSRESET4_WREN_MASK 0x00000010L
+#define SWRST_CONTROL_5__PCSRESET5_WREN_MASK 0x00000020L
+#define SWRST_CONTROL_5__PCSRESET6_WREN_MASK 0x00000040L
+#define SWRST_CONTROL_5__PCSRESET7_WREN_MASK 0x00000080L
+#define SWRST_CONTROL_5__PCSRESET8_WREN_MASK 0x00000100L
+#define SWRST_CONTROL_5__PCSRESET9_WREN_MASK 0x00000200L
+#define SWRST_CONTROL_5__PCSRESET10_WREN_MASK 0x00000400L
+#define SWRST_CONTROL_5__PCSRESET11_WREN_MASK 0x00000800L
+#define SWRST_CONTROL_5__PCSRESET12_WREN_MASK 0x00001000L
+#define SWRST_CONTROL_5__PCSRESET13_WREN_MASK 0x00002000L
+#define SWRST_CONTROL_5__PCSRESET14_WREN_MASK 0x00004000L
+#define SWRST_CONTROL_5__PCSRESET15_WREN_MASK 0x00008000L
+#define SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK 0x00200000L
+#define SWRST_CONTROL_5__WRRESETAXIMST_EN_MASK 0x00400000L
+#define SWRST_CONTROL_5__WRRESETAXISLV_EN_MASK 0x00800000L
+#define SWRST_CONTROL_5__WRRESETAXIINT_EN_MASK 0x01000000L
+#define SWRST_CONTROL_5__WRRESETPCFG_EN_MASK 0x02000000L
+#define SWRST_CONTROL_5__WRRESETLNCT_EN_MASK 0x04000000L
+#define SWRST_CONTROL_5__WRRESETMNTR_EN_MASK 0x08000000L
+#define SWRST_CONTROL_5__WRRESETHLTR_EN_MASK 0x10000000L
+#define SWRST_CONTROL_5__WRRESETCPM_EN_MASK 0x20000000L
+#define SWRST_CONTROL_5__WRRESETPHY0_EN_MASK 0x40000000L
+#define SWRST_CONTROL_5__WRSTRAPVLD_EN_MASK 0x80000000L
+//SWRST_CONTROL_6
+#define SWRST_CONTROL_6__HOLD_TRAINING_A__SHIFT 0x0
+#define SWRST_CONTROL_6__HOLD_TRAINING_B__SHIFT 0x1
+#define SWRST_CONTROL_6__HOLD_TRAINING_C__SHIFT 0x2
+#define SWRST_CONTROL_6__HOLD_TRAINING_D__SHIFT 0x3
+#define SWRST_CONTROL_6__HOLD_TRAINING_E__SHIFT 0x4
+#define SWRST_CONTROL_6__HOLD_TRAINING_F__SHIFT 0x5
+#define SWRST_CONTROL_6__HOLD_TRAINING_G__SHIFT 0x6
+#define SWRST_CONTROL_6__HOLD_TRAINING_H__SHIFT 0x7
+#define SWRST_CONTROL_6__HOLD_TRAINING_I__SHIFT 0x8
+#define SWRST_CONTROL_6__HOLD_TRAINING_J__SHIFT 0x9
+#define SWRST_CONTROL_6__HOLD_TRAINING_K__SHIFT 0xa
+#define SWRST_CONTROL_6__HOLD_TRAINING_A_MASK 0x00000001L
+#define SWRST_CONTROL_6__HOLD_TRAINING_B_MASK 0x00000002L
+#define SWRST_CONTROL_6__HOLD_TRAINING_C_MASK 0x00000004L
+#define SWRST_CONTROL_6__HOLD_TRAINING_D_MASK 0x00000008L
+#define SWRST_CONTROL_6__HOLD_TRAINING_E_MASK 0x00000010L
+#define SWRST_CONTROL_6__HOLD_TRAINING_F_MASK 0x00000020L
+#define SWRST_CONTROL_6__HOLD_TRAINING_G_MASK 0x00000040L
+#define SWRST_CONTROL_6__HOLD_TRAINING_H_MASK 0x00000080L
+#define SWRST_CONTROL_6__HOLD_TRAINING_I_MASK 0x00000100L
+#define SWRST_CONTROL_6__HOLD_TRAINING_J_MASK 0x00000200L
+#define SWRST_CONTROL_6__HOLD_TRAINING_K_MASK 0x00000400L
+//SWRST_EP_COMMAND_0
+#define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY__SHIFT 0x0
+#define SWRST_EP_COMMAND_0__EP_HOT_RESET__SHIFT 0x8
+#define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET__SHIFT 0x9
+#define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET__SHIFT 0xa
+#define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY_MASK 0x00000001L
+#define SWRST_EP_COMMAND_0__EP_HOT_RESET_MASK 0x00000100L
+#define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET_MASK 0x00000200L
+#define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET_MASK 0x00000400L
+//SWRST_EP_CONTROL_0
+#define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN__SHIFT 0x0
+#define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN__SHIFT 0x8
+#define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN__SHIFT 0x9
+#define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN__SHIFT 0xa
+#define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN_MASK 0x00000001L
+#define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN_MASK 0x00000100L
+#define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN_MASK 0x00000200L
+#define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN_MASK 0x00000400L
+//CPM_CONTROL
+#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT 0x0
+#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE__SHIFT 0x1
+#define CPM_CONTROL__TXCLK_PERM_GATE_ENABLE__SHIFT 0x2
+#define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE__SHIFT 0x5
+#define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE__SHIFT 0x6
+#define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE__SHIFT 0x7
+#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE__SHIFT 0x8
+#define CPM_CONTROL__LCLK_DYN_GATE_LATENCY__SHIFT 0x9
+#define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY__SHIFT 0xb
+#define CPM_CONTROL__TXCLK_PERM_GATE_LATENCY__SHIFT 0xc
+#define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY__SHIFT 0xe
+#define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY__SHIFT 0xf
+#define CPM_CONTROL__LCLK_GATE_TXCLK_FREE__SHIFT 0x10
+#define CPM_CONTROL__RCVR_DET_CLK_ENABLE__SHIFT 0x11
+#define CPM_CONTROL__FAST_TXCLK_LATENCY__SHIFT 0x12
+#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE__SHIFT 0x16
+#define CPM_CONTROL__REFCLK_XSTCLK_LATENCY__SHIFT 0x17
+#define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE__SHIFT 0x18
+#define CPM_CONTROL__LCLK_GATE_ALLOW_IN_L1__SHIFT 0x19
+#define CPM_CONTROL__SPARE_REGS__SHIFT 0x1a
+#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x00000001L
+#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x00000002L
+#define CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK 0x00000004L
+#define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK 0x00000020L
+#define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK 0x00000040L
+#define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK 0x00000080L
+#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x00000100L
+#define CPM_CONTROL__LCLK_DYN_GATE_LATENCY_MASK 0x00000600L
+#define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY_MASK 0x00000800L
+#define CPM_CONTROL__TXCLK_PERM_GATE_LATENCY_MASK 0x00003000L
+#define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY_MASK 0x00004000L
+#define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY_MASK 0x00008000L
+#define CPM_CONTROL__LCLK_GATE_TXCLK_FREE_MASK 0x00010000L
+#define CPM_CONTROL__RCVR_DET_CLK_ENABLE_MASK 0x00020000L
+#define CPM_CONTROL__FAST_TXCLK_LATENCY_MASK 0x001C0000L
+#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK 0x00400000L
+#define CPM_CONTROL__REFCLK_XSTCLK_LATENCY_MASK 0x00800000L
+#define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE_MASK 0x01000000L
+#define CPM_CONTROL__LCLK_GATE_ALLOW_IN_L1_MASK 0x02000000L
+#define CPM_CONTROL__SPARE_REGS_MASK 0xFC000000L
+//SMN_APERTURE_ID_A
+#define SMN_APERTURE_ID_A__SMU_APERTURE_ID__SHIFT 0x0
+#define SMN_APERTURE_ID_A__PCS_APERTURE_ID__SHIFT 0xc
+#define SMN_APERTURE_ID_A__SMU_APERTURE_ID_MASK 0x00000FFFL
+#define SMN_APERTURE_ID_A__PCS_APERTURE_ID_MASK 0x00FFF000L
+//SMN_APERTURE_ID_B
+#define SMN_APERTURE_ID_B__IOHUB_APERTURE_ID__SHIFT 0x0
+#define SMN_APERTURE_ID_B__NBIF_APERTURE_ID__SHIFT 0xc
+#define SMN_APERTURE_ID_B__IOHUB_APERTURE_ID_MASK 0x00000FFFL
+#define SMN_APERTURE_ID_B__NBIF_APERTURE_ID_MASK 0x00FFF000L
+//RSMU_MASTER_CONTROL
+#define RSMU_MASTER_CONTROL__RSMU_MASTER_MESSAGE_SEND_ENABLE__SHIFT 0x0
+#define RSMU_MASTER_CONTROL__RSMU_MASTER_MESSAGE_SEND_ENABLE_MASK 0x00000001L
+//RSMU_SLAVE_CONTROL
+#define RSMU_SLAVE_CONTROL__RSMU_SLAVE_INVALID_READ_RETURN_ZERO__SHIFT 0x0
+#define RSMU_SLAVE_CONTROL__RSMU_SLAVE_IGNORE_INVALID_CONFIG_WRITE__SHIFT 0x2
+#define RSMU_SLAVE_CONTROL__RSMU_SLAVE_INVALID_READ_RETURN_ZERO_MASK 0x00000001L
+#define RSMU_SLAVE_CONTROL__RSMU_SLAVE_IGNORE_INVALID_CONFIG_WRITE_MASK 0x00000004L
+//RSMU_POWER_GATING_CONTROL
+#define RSMU_POWER_GATING_CONTROL__PWR_GATE_MAC_ONLY__SHIFT 0x0
+#define RSMU_POWER_GATING_CONTROL__PWR_GATE_PHY_ONLY__SHIFT 0x1
+#define RSMU_POWER_GATING_CONTROL__PWR_GATE_MAC_ONLY_MASK 0x00000001L
+#define RSMU_POWER_GATING_CONTROL__PWR_GATE_PHY_ONLY_MASK 0x00000002L
+//RSMU_BIOS_TIMER_CMD
+#define RSMU_BIOS_TIMER_CMD__CFG_TMR_MICROSECONDS__SHIFT 0x0
+#define RSMU_BIOS_TIMER_CMD__CFG_TMR_MICROSECONDS_MASK 0xFFFFFFFFL
+//RSMU_BIOS_TIMER_CNTL
+#define RSMU_BIOS_TIMER_CNTL__CFG_TMR_CLOCKRATE__SHIFT 0x0
+#define RSMU_BIOS_TIMER_CNTL__CFG_TMR_CLOCKRATE_MASK 0x000000FFL
+//LNCNT_CONTROL
+#define LNCNT_CONTROL__CFG_LNC_WINDOW_EN__SHIFT 0x0
+#define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN__SHIFT 0x1
+#define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN__SHIFT 0x2
+#define LNCNT_CONTROL__CFG_LNC_OVRD_EN__SHIFT 0x3
+#define LNCNT_CONTROL__CFG_LNC_OVRD_VAL__SHIFT 0x4
+#define LNCNT_CONTROL__CFG_LNC_WINDOW_EN_MASK 0x00000001L
+#define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN_MASK 0x00000002L
+#define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN_MASK 0x00000004L
+#define LNCNT_CONTROL__CFG_LNC_OVRD_EN_MASK 0x00000008L
+#define LNCNT_CONTROL__CFG_LNC_OVRD_VAL_MASK 0x00000010L
+//CFG_LNC_WINDOW_REGISTER
+#define CFG_LNC_WINDOW_REGISTER__CFG_LNC_WINDOW__SHIFT 0x0
+#define CFG_LNC_WINDOW_REGISTER__CFG_LNC_WINDOW_MASK 0x00FFFFFFL
+//LNCNT_QUAN_THRD
+#define LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD__SHIFT 0x0
+#define LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD__SHIFT 0x4
+#define LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD_MASK 0x00000007L
+#define LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD_MASK 0x00000070L
+//LNCNT_WEIGHT
+#define LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT__SHIFT 0x0
+#define LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT__SHIFT 0x10
+#define LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT_MASK 0x0000FFFFL
+#define LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT_MASK 0xFFFF0000L
+//LNC_TOTAL_WACC_REGISTER
+#define LNC_TOTAL_WACC_REGISTER__LNC_TOTAL_WACC__SHIFT 0x0
+#define LNC_TOTAL_WACC_REGISTER__LNC_TOTAL_WACC_MASK 0xFFFFFFFFL
+//LNC_BW_WACC_REGISTER
+#define LNC_BW_WACC_REGISTER__LNC_BW_WACC__SHIFT 0x0
+#define LNC_BW_WACC_REGISTER__LNC_BW_WACC_MASK 0xFFFFFFFFL
+//LNC_CMN_WACC_REGISTER
+#define LNC_CMN_WACC_REGISTER__LNC_CMN_WACC__SHIFT 0x0
+#define LNC_CMN_WACC_REGISTER__LNC_CMN_WACC_MASK 0xFFFFFFFFL
+//SMU_HP_STATUS_UPDATE
+#define SMU_HP_STATUS_UPDATE__SMU_HP_STATUS__SHIFT 0x0
+#define SMU_HP_STATUS_UPDATE__SMU_HP_STATUS_MASK 0xFFFFFFFFL
+//HP_SMU_COMMAND_UPDATE
+#define HP_SMU_COMMAND_UPDATE__HP_SMU_COMMAND__SHIFT 0x0
+#define HP_SMU_COMMAND_UPDATE__HP_SMU_COMMAND_MASK 0xFFFFFFFFL
+//SMU_HP_END_OF_INTERRUPT
+#define SMU_HP_END_OF_INTERRUPT__SMU_HP_EOI__SHIFT 0x0
+#define SMU_HP_END_OF_INTERRUPT__SMU_HP_EOI_MASK 0x00000001L
+//SMU_INT_PIN_SHARING_PORT_INDICATOR
+#define SMU_INT_PIN_SHARING_PORT_INDICATOR__LINK_MANAGEMENT_INT_STATUS__SHIFT 0x0
+#define SMU_INT_PIN_SHARING_PORT_INDICATOR__LTR_INT_STATUS__SHIFT 0x8
+#define SMU_INT_PIN_SHARING_PORT_INDICATOR__DPC_INT_STATUS__SHIFT 0x10
+#define SMU_INT_PIN_SHARING_PORT_INDICATOR__LINK_MANAGEMENT_INT_STATUS_MASK 0x000000FFL
+#define SMU_INT_PIN_SHARING_PORT_INDICATOR__LTR_INT_STATUS_MASK 0x0000FF00L
+#define SMU_INT_PIN_SHARING_PORT_INDICATOR__DPC_INT_STATUS_MASK 0x00FF0000L
+//PCIE_PGMST_CNTL
+#define PCIE_PGMST_CNTL__CFG_PG_HYSTERESIS__SHIFT 0x0
+#define PCIE_PGMST_CNTL__CFG_PG_EN__SHIFT 0x8
+#define PCIE_PGMST_CNTL__CFG_IDLENESS_COUNT_EN__SHIFT 0xa
+#define PCIE_PGMST_CNTL__CFG_FW_PG_EXIT_CNTL__SHIFT 0xe
+#define PCIE_PGMST_CNTL__CFG_PG_HYSTERESIS_MASK 0x000000FFL
+#define PCIE_PGMST_CNTL__CFG_PG_EN_MASK 0x00000100L
+#define PCIE_PGMST_CNTL__CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L
+#define PCIE_PGMST_CNTL__CFG_FW_PG_EXIT_CNTL_MASK 0x0000C000L
+//PCIE_PGSLV_CNTL
+#define PCIE_PGSLV_CNTL__CFG_IDLE_HYSTERESIS__SHIFT 0x0
+#define PCIE_PGSLV_CNTL__CFG_IDLE_HYSTERESIS_MASK 0x0000001FL
+//SMU_PCIE_FENCED1_REG
+#define SMU_PCIE_FENCED1_REG__MP0_PCIE_CROSSFIRE_LOCKDOWN_EN__SHIFT 0x0
+#define SMU_PCIE_FENCED1_REG__MP0_PCIE_CROSSFIRE_LOCKDOWN_EN_MASK 0x00000001L
+//SMU_PCIE_FENCED2_REG
+
+
+// addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec
+//NB_NBCFG1_NB_VENDOR_ID
+#define NB_NBCFG1_NB_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define NB_NBCFG1_NB_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//NB_NBCFG1_NB_DEVICE_ID
+#define NB_NBCFG1_NB_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define NB_NBCFG1_NB_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//NB_NBCFG1_NB_COMMAND
+#define NB_NBCFG1_NB_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define NB_NBCFG1_NB_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define NB_NBCFG1_NB_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define NB_NBCFG1_NB_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define NB_NBCFG1_NB_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define NB_NBCFG1_NB_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+//NB_NBCFG1_NB_STATUS
+#define NB_NBCFG1_NB_STATUS__CAP_LIST__SHIFT 0x4
+#define NB_NBCFG1_NB_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define NB_NBCFG1_NB_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define NB_NBCFG1_NB_STATUS__CAP_LIST_MASK 0x0010L
+#define NB_NBCFG1_NB_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define NB_NBCFG1_NB_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+//NB_NBCFG1_NB_REVISION_ID
+#define NB_NBCFG1_NB_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define NB_NBCFG1_NB_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define NB_NBCFG1_NB_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define NB_NBCFG1_NB_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//NB_NBCFG1_NB_REGPROG_INF
+#define NB_NBCFG1_NB_REGPROG_INF__REG_LEVEL_PROG_INF__SHIFT 0x0
+#define NB_NBCFG1_NB_REGPROG_INF__REG_LEVEL_PROG_INF_MASK 0xFFL
+//NB_NBCFG1_NB_SUB_CLASS
+#define NB_NBCFG1_NB_SUB_CLASS__SUB_CLASS_INF__SHIFT 0x0
+#define NB_NBCFG1_NB_SUB_CLASS__SUB_CLASS_INF_MASK 0xFFL
+//NB_NBCFG1_NB_BASE_CODE
+#define NB_NBCFG1_NB_BASE_CODE__BASE_CLASS_CODE__SHIFT 0x0
+#define NB_NBCFG1_NB_BASE_CODE__BASE_CLASS_CODE_MASK 0xFFL
+//NB_NBCFG1_NB_CACHE_LINE
+#define NB_NBCFG1_NB_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define NB_NBCFG1_NB_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//NB_NBCFG1_NB_LATENCY
+#define NB_NBCFG1_NB_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define NB_NBCFG1_NB_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//NB_NBCFG1_NB_HEADER
+#define NB_NBCFG1_NB_HEADER__HEADER_TYPE__SHIFT 0x0
+#define NB_NBCFG1_NB_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define NB_NBCFG1_NB_HEADER__HEADER_TYPE_MASK 0x7FL
+#define NB_NBCFG1_NB_HEADER__DEVICE_TYPE_MASK 0x80L
+//NB_NBCFG1_NB_ADAPTER_ID
+#define NB_NBCFG1_NB_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define NB_NBCFG1_NB_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define NB_NBCFG1_NB_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define NB_NBCFG1_NB_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//NB_NBCFG1_NB_CAPABILITIES_PTR
+#define NB_NBCFG1_NB_CAPABILITIES_PTR__CAP_PTR__SHIFT 0x0
+#define NB_NBCFG1_NB_CAPABILITIES_PTR__CAP_PTR_MASK 0x000000FFL
+//NB_NBCFG1_NB_HEADER_W
+#define NB_NBCFG1_NB_HEADER_W__DEVICE_TYPE__SHIFT 0x7
+#define NB_NBCFG1_NB_HEADER_W__DEVICE_TYPE_MASK 0x00000080L
+//NB_NBCFG1_NB_PCI_CTRL
+#define NB_NBCFG1_NB_PCI_CTRL__PMEDis__SHIFT 0x4
+#define NB_NBCFG1_NB_PCI_CTRL__SErrDis__SHIFT 0x5
+#define NB_NBCFG1_NB_PCI_CTRL__MMIOEnable__SHIFT 0x17
+#define NB_NBCFG1_NB_PCI_CTRL__HPDis__SHIFT 0x1a
+#define NB_NBCFG1_NB_PCI_CTRL__PMEDis_MASK 0x00000010L
+#define NB_NBCFG1_NB_PCI_CTRL__SErrDis_MASK 0x00000020L
+#define NB_NBCFG1_NB_PCI_CTRL__MMIOEnable_MASK 0x00800000L
+#define NB_NBCFG1_NB_PCI_CTRL__HPDis_MASK 0x04000000L
+//NB_NBCFG1_NB_ADAPTER_ID_W
+#define NB_NBCFG1_NB_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define NB_NBCFG1_NB_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define NB_NBCFG1_NB_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define NB_NBCFG1_NB_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//NB_NBCFG1_NB_SMN_INDEX_EXTENSION_0
+#define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_0__NB_SMN_INDEX_EXTENSION_0__SHIFT 0x0
+#define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_0__NB_SMN_INDEX_EXTENSION_0_MASK 0x0000000FL
+//NB_NBCFG1_NB_SMN_INDEX_0
+#define NB_NBCFG1_NB_SMN_INDEX_0__NB_SMN_INDEX_0__SHIFT 0x0
+#define NB_NBCFG1_NB_SMN_INDEX_0__NB_SMN_INDEX_0_MASK 0xFFFFFFFFL
+//NB_NBCFG1_NB_SMN_DATA_0
+#define NB_NBCFG1_NB_SMN_DATA_0__NB_SMN_DATA_0__SHIFT 0x0
+#define NB_NBCFG1_NB_SMN_DATA_0__NB_SMN_DATA_0_MASK 0xFFFFFFFFL
+//NB_NBCFG1_NBCFG_SCRATCH_0
+#define NB_NBCFG1_NBCFG_SCRATCH_0__NBCFG_SCRATCH_0__SHIFT 0x0
+#define NB_NBCFG1_NBCFG_SCRATCH_0__NBCFG_SCRATCH_0_MASK 0xFFFFFFFFL
+//NB_NBCFG1_NBCFG_SCRATCH_1
+#define NB_NBCFG1_NBCFG_SCRATCH_1__NBCFG_SCRATCH_1__SHIFT 0x0
+#define NB_NBCFG1_NBCFG_SCRATCH_1__NBCFG_SCRATCH_1_MASK 0xFFFFFFFFL
+//NB_NBCFG1_NBCFG_SCRATCH_2
+#define NB_NBCFG1_NBCFG_SCRATCH_2__NBCFG_SCRATCH_2__SHIFT 0x0
+#define NB_NBCFG1_NBCFG_SCRATCH_2__NBCFG_SCRATCH_2_MASK 0xFFFFFFFFL
+//NB_NBCFG1_NBCFG_SCRATCH_3
+#define NB_NBCFG1_NBCFG_SCRATCH_3__NBCFG_SCRATCH_3__SHIFT 0x0
+#define NB_NBCFG1_NBCFG_SCRATCH_3__NBCFG_SCRATCH_3_MASK 0xFFFFFFFFL
+//NB_NBCFG1_NBCFG_SCRATCH_4
+#define NB_NBCFG1_NBCFG_SCRATCH_4__NBCFG_SCRATCH_4__SHIFT 0x0
+#define NB_NBCFG1_NBCFG_SCRATCH_4__NBCFG_SCRATCH_4_MASK 0xFFFFFFFFL
+//NB_NBCFG1_NB_PCI_ARB
+#define NB_NBCFG1_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3
+#define NB_NBCFG1_NB_PCI_ARB__PMEMode__SHIFT 0x8
+#define NB_NBCFG1_NB_PCI_ARB__PMETurnOff__SHIFT 0x9
+#define NB_NBCFG1_NB_PCI_ARB__PMETOAckStatus__SHIFT 0xa
+#define NB_NBCFG1_NB_PCI_ARB__PMETarget__SHIFT 0x10
+#define NB_NBCFG1_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L
+#define NB_NBCFG1_NB_PCI_ARB__PMEMode_MASK 0x00000100L
+#define NB_NBCFG1_NB_PCI_ARB__PMETurnOff_MASK 0x00000200L
+#define NB_NBCFG1_NB_PCI_ARB__PMETOAckStatus_MASK 0x00000400L
+#define NB_NBCFG1_NB_PCI_ARB__PMETarget_MASK 0x00FF0000L
+//NB_NBCFG1_NB_DRAM_SLOT1_BASE
+#define NB_NBCFG1_NB_DRAM_SLOT1_BASE__DRAM_BASE__SHIFT 0x17
+#define NB_NBCFG1_NB_DRAM_SLOT1_BASE__DRAM_BASE_MASK 0xFF800000L
+//NB_NBCFG1_NB_TOP_OF_DRAM_SLOT1
+#define NB_NBCFG1_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_BIT_32__SHIFT 0x0
+#define NB_NBCFG1_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17
+#define NB_NBCFG1_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_BIT_32_MASK 0x00000001L
+#define NB_NBCFG1_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L
+//NB_NBCFG1_NB_SMN_INDEX_EXTENSION_1
+#define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_1__NB_SMN_INDEX_EXTENSION_1__SHIFT 0x0
+#define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_1__NB_SMN_INDEX_EXTENSION_1_MASK 0x0000000FL
+//NB_NBCFG1_NB_SMN_INDEX_1
+#define NB_NBCFG1_NB_SMN_INDEX_1__NB_SMN_INDEX_1__SHIFT 0x0
+#define NB_NBCFG1_NB_SMN_INDEX_1__NB_SMN_INDEX_1_MASK 0xFFFFFFFFL
+//NB_NBCFG1_NB_SMN_DATA_1
+#define NB_NBCFG1_NB_SMN_DATA_1__NB_SMN_DATA_1__SHIFT 0x0
+#define NB_NBCFG1_NB_SMN_DATA_1__NB_SMN_DATA_1_MASK 0xFFFFFFFFL
+//NB_NBCFG1_NB_INDEX_DATA_MUTEX0
+#define NB_NBCFG1_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0__SHIFT 0x0
+#define NB_NBCFG1_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_UNLOCK__SHIFT 0x1f
+#define NB_NBCFG1_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_MASK 0x7FFFFFFFL
+#define NB_NBCFG1_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_UNLOCK_MASK 0x80000000L
+//NB_NBCFG1_NB_INDEX_DATA_MUTEX1
+#define NB_NBCFG1_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1__SHIFT 0x0
+#define NB_NBCFG1_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_UNLOCK__SHIFT 0x1f
+#define NB_NBCFG1_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_MASK 0x7FFFFFFFL
+#define NB_NBCFG1_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_UNLOCK_MASK 0x80000000L
+//NB_NBCFG1_NB_SMN_INDEX_EXTENSION_2
+#define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_2__NB_SMN_INDEX_EXTENSION_2__SHIFT 0x0
+#define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_2__NB_SMN_INDEX_EXTENSION_2_MASK 0x0000000FL
+//NB_NBCFG1_NB_SMN_INDEX_2
+#define NB_NBCFG1_NB_SMN_INDEX_2__NB_SMN_INDEX_2__SHIFT 0x0
+#define NB_NBCFG1_NB_SMN_INDEX_2__NB_SMN_INDEX_2_MASK 0xFFFFFFFFL
+//NB_NBCFG1_NB_SMN_DATA_2
+#define NB_NBCFG1_NB_SMN_DATA_2__NB_SMN_DATA_2__SHIFT 0x0
+#define NB_NBCFG1_NB_SMN_DATA_2__NB_SMN_DATA_2_MASK 0xFFFFFFFFL
+//NB_NBCFG1_NB_SMN_INDEX_EXTENSION_3
+#define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_3__NB_SMN_INDEX_EXTENSION_3__SHIFT 0x0
+#define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_3__NB_SMN_INDEX_EXTENSION_3_MASK 0x0000000FL
+//NB_NBCFG1_NB_SMN_INDEX_3
+#define NB_NBCFG1_NB_SMN_INDEX_3__NB_SMN_INDEX_3__SHIFT 0x0
+#define NB_NBCFG1_NB_SMN_INDEX_3__NB_SMN_INDEX_3_MASK 0xFFFFFFFFL
+//NB_NBCFG1_NB_SMN_DATA_3
+#define NB_NBCFG1_NB_SMN_DATA_3__NB_SMN_DATA_3__SHIFT 0x0
+#define NB_NBCFG1_NB_SMN_DATA_3__NB_SMN_DATA_3_MASK 0xFFFFFFFFL
+//NB_NBCFG1_NB_SMN_INDEX_EXTENSION_4
+#define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_4__NB_SMN_INDEX_EXTENSION_4__SHIFT 0x0
+#define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_4__NB_SMN_INDEX_EXTENSION_4_MASK 0x0000000FL
+//NB_NBCFG1_NB_SMN_INDEX_4
+#define NB_NBCFG1_NB_SMN_INDEX_4__NB_SMN_INDEX_4__SHIFT 0x0
+#define NB_NBCFG1_NB_SMN_INDEX_4__NB_SMN_INDEX_4_MASK 0xFFFFFFFFL
+//NB_NBCFG1_NB_SMN_DATA_4
+#define NB_NBCFG1_NB_SMN_DATA_4__NB_SMN_DATA_4__SHIFT 0x0
+#define NB_NBCFG1_NB_SMN_DATA_4__NB_SMN_DATA_4_MASK 0xFFFFFFFFL
+//NB_NBCFG1_NB_SMN_INDEX_EXTENSION_5
+#define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_5__NB_SMN_INDEX_EXTENSION_5__SHIFT 0x0
+#define NB_NBCFG1_NB_SMN_INDEX_EXTENSION_5__NB_SMN_INDEX_EXTENSION_5_MASK 0x0000000FL
+//NB_NBCFG1_NB_SMN_INDEX_5
+#define NB_NBCFG1_NB_SMN_INDEX_5__NB_SMN_INDEX_5__SHIFT 0x0
+#define NB_NBCFG1_NB_SMN_INDEX_5__NB_SMN_INDEX_5_MASK 0xFFFFFFFFL
+//NB_NBCFG1_NB_SMN_DATA_5
+#define NB_NBCFG1_NB_SMN_DATA_5__NB_SMN_DATA_5__SHIFT 0x0
+#define NB_NBCFG1_NB_SMN_DATA_5__NB_SMN_DATA_5_MASK 0xFFFFFFFFL
+//NB_NBCFG1_NB_PERF_CNT_CTRL
+#define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_CNT_EN__SHIFT 0x0
+#define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_SHADOW_WR__SHIFT 0x1
+#define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET__SHIFT 0x2
+#define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY__SHIFT 0x8
+#define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY_EN__SHIFT 0xf
+#define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY__SHIFT 0x10
+#define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY_EN__SHIFT 0x17
+#define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_CNT_EN_MASK 0x00000001L
+#define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_SHADOW_WR_MASK 0x00000002L
+#define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_MASK 0x00000004L
+#define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY_MASK 0x00000F00L
+#define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY_EN_MASK 0x00008000L
+#define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY_MASK 0x000F0000L
+#define NB_NBCFG1_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY_EN_MASK 0x00800000L
+//NB_NBCFG1_NB_SMN_INDEX_6
+#define NB_NBCFG1_NB_SMN_INDEX_6__NB_SMN_INDEX_6__SHIFT 0x0
+#define NB_NBCFG1_NB_SMN_INDEX_6__NB_SMN_INDEX_6_MASK 0xFFFFFFFFL
+//NB_NBCFG1_NB_SMN_DATA_6
+#define NB_NBCFG1_NB_SMN_DATA_6__NB_SMN_DATA_6__SHIFT 0x0
+#define NB_NBCFG1_NB_SMN_DATA_6__NB_SMN_DATA_6_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_iohub_nb_iommushadow_iommushadow_cfgdecp
+//SHADOW_IOMMU_MMIO_CNTRL_0
+#define SHADOW_IOMMU_MMIO_CNTRL_0__IOMMU_EN__SHIFT 0x0
+#define SHADOW_IOMMU_MMIO_CNTRL_0__IOMMU_EN_MASK 0x00000001L
+//SHADOW_IOMMU_CAP_BASE_LO
+#define SHADOW_IOMMU_CAP_BASE_LO__IOMMU_ENABLE__SHIFT 0x0
+#define SHADOW_IOMMU_CAP_BASE_LO__IOMMU_BASE_ADDR_LO__SHIFT 0x13
+#define SHADOW_IOMMU_CAP_BASE_LO__IOMMU_ENABLE_MASK 0x00000001L
+#define SHADOW_IOMMU_CAP_BASE_LO__IOMMU_BASE_ADDR_LO_MASK 0xFFF80000L
+//SHADOW_IOMMU_CAP_BASE_HI
+#define SHADOW_IOMMU_CAP_BASE_HI__IOMMU_BASE_ADDR_HI__SHIFT 0x0
+#define SHADOW_IOMMU_CAP_BASE_HI__IOMMU_BASE_ADDR_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_iohub_nb_PCIE0shadow0_pcieshadow_cfgdecp
+//NB_PCIE0SHADOW0_COMMAND
+#define NB_PCIE0SHADOW0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define NB_PCIE0SHADOW0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define NB_PCIE0SHADOW0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define NB_PCIE0SHADOW0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define NB_PCIE0SHADOW0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define NB_PCIE0SHADOW0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+//NB_PCIE0SHADOW0_SUB_BUS_NUMBER_LATENCY
+#define NB_PCIE0SHADOW0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define NB_PCIE0SHADOW0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define NB_PCIE0SHADOW0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define NB_PCIE0SHADOW0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+//NB_PCIE0SHADOW0_IO_BASE_LIMIT
+#define NB_PCIE0SHADOW0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define NB_PCIE0SHADOW0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define NB_PCIE0SHADOW0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define NB_PCIE0SHADOW0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//NB_PCIE0SHADOW0_MEM_BASE_LIMIT
+#define NB_PCIE0SHADOW0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define NB_PCIE0SHADOW0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define NB_PCIE0SHADOW0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define NB_PCIE0SHADOW0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//NB_PCIE0SHADOW0_PREF_BASE_LIMIT
+#define NB_PCIE0SHADOW0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define NB_PCIE0SHADOW0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define NB_PCIE0SHADOW0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define NB_PCIE0SHADOW0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//NB_PCIE0SHADOW0_PREF_BASE_UPPER
+#define NB_PCIE0SHADOW0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define NB_PCIE0SHADOW0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//NB_PCIE0SHADOW0_PREF_LIMIT_UPPER
+#define NB_PCIE0SHADOW0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define NB_PCIE0SHADOW0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//NB_PCIE0SHADOW0_IO_BASE_LIMIT_HI
+#define NB_PCIE0SHADOW0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define NB_PCIE0SHADOW0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define NB_PCIE0SHADOW0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define NB_PCIE0SHADOW0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//NB_PCIE0SHADOW0_IRQ_BRIDGE_CNTL
+#define NB_PCIE0SHADOW0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define NB_PCIE0SHADOW0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define NB_PCIE0SHADOW0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define NB_PCIE0SHADOW0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define NB_PCIE0SHADOW0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define NB_PCIE0SHADOW0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+//NB_PCIE0SHADOW0_EXT_BRIDGE_CNTL
+#define NB_PCIE0SHADOW0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define NB_PCIE0SHADOW0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//NB_PCIE0SHADOW0_PMI_STATUS_CNTL
+#define NB_PCIE0SHADOW0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define NB_PCIE0SHADOW0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L
+//NB_PCIE0SHADOW0_SLOT_CAP
+#define NB_PCIE0SHADOW0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define NB_PCIE0SHADOW0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define NB_PCIE0SHADOW0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define NB_PCIE0SHADOW0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+//NB_PCIE0SHADOW0_ROOT_CNTL
+#define NB_PCIE0SHADOW0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define NB_PCIE0SHADOW0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//NB_PCIE0SHADOW0_DEVICE_CNTL2
+#define NB_PCIE0SHADOW0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define NB_PCIE0SHADOW0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+
+
+// addressBlock: nbio_iohub_nb_PCIE0shadow1_pcieshadow_cfgdecp
+//NB_PCIE0SHADOW1_COMMAND
+#define NB_PCIE0SHADOW1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define NB_PCIE0SHADOW1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define NB_PCIE0SHADOW1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define NB_PCIE0SHADOW1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define NB_PCIE0SHADOW1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define NB_PCIE0SHADOW1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+//NB_PCIE0SHADOW1_SUB_BUS_NUMBER_LATENCY
+#define NB_PCIE0SHADOW1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define NB_PCIE0SHADOW1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define NB_PCIE0SHADOW1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define NB_PCIE0SHADOW1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+//NB_PCIE0SHADOW1_IO_BASE_LIMIT
+#define NB_PCIE0SHADOW1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define NB_PCIE0SHADOW1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define NB_PCIE0SHADOW1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define NB_PCIE0SHADOW1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//NB_PCIE0SHADOW1_MEM_BASE_LIMIT
+#define NB_PCIE0SHADOW1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define NB_PCIE0SHADOW1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define NB_PCIE0SHADOW1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define NB_PCIE0SHADOW1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//NB_PCIE0SHADOW1_PREF_BASE_LIMIT
+#define NB_PCIE0SHADOW1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define NB_PCIE0SHADOW1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define NB_PCIE0SHADOW1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define NB_PCIE0SHADOW1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//NB_PCIE0SHADOW1_PREF_BASE_UPPER
+#define NB_PCIE0SHADOW1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define NB_PCIE0SHADOW1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//NB_PCIE0SHADOW1_PREF_LIMIT_UPPER
+#define NB_PCIE0SHADOW1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define NB_PCIE0SHADOW1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//NB_PCIE0SHADOW1_IO_BASE_LIMIT_HI
+#define NB_PCIE0SHADOW1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define NB_PCIE0SHADOW1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define NB_PCIE0SHADOW1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define NB_PCIE0SHADOW1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//NB_PCIE0SHADOW1_IRQ_BRIDGE_CNTL
+#define NB_PCIE0SHADOW1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define NB_PCIE0SHADOW1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define NB_PCIE0SHADOW1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define NB_PCIE0SHADOW1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define NB_PCIE0SHADOW1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define NB_PCIE0SHADOW1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+//NB_PCIE0SHADOW1_EXT_BRIDGE_CNTL
+#define NB_PCIE0SHADOW1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define NB_PCIE0SHADOW1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//NB_PCIE0SHADOW1_PMI_STATUS_CNTL
+#define NB_PCIE0SHADOW1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define NB_PCIE0SHADOW1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L
+//NB_PCIE0SHADOW1_SLOT_CAP
+#define NB_PCIE0SHADOW1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define NB_PCIE0SHADOW1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define NB_PCIE0SHADOW1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define NB_PCIE0SHADOW1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+//NB_PCIE0SHADOW1_ROOT_CNTL
+#define NB_PCIE0SHADOW1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define NB_PCIE0SHADOW1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//NB_PCIE0SHADOW1_DEVICE_CNTL2
+#define NB_PCIE0SHADOW1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define NB_PCIE0SHADOW1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+
+
+// addressBlock: nbio_iohub_nb_PCIE0shadow2_pcieshadow_cfgdecp
+//NB_PCIE0SHADOW2_COMMAND
+#define NB_PCIE0SHADOW2_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define NB_PCIE0SHADOW2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define NB_PCIE0SHADOW2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define NB_PCIE0SHADOW2_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define NB_PCIE0SHADOW2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define NB_PCIE0SHADOW2_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+//NB_PCIE0SHADOW2_SUB_BUS_NUMBER_LATENCY
+#define NB_PCIE0SHADOW2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define NB_PCIE0SHADOW2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define NB_PCIE0SHADOW2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define NB_PCIE0SHADOW2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+//NB_PCIE0SHADOW2_IO_BASE_LIMIT
+#define NB_PCIE0SHADOW2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define NB_PCIE0SHADOW2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define NB_PCIE0SHADOW2_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define NB_PCIE0SHADOW2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//NB_PCIE0SHADOW2_MEM_BASE_LIMIT
+#define NB_PCIE0SHADOW2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define NB_PCIE0SHADOW2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define NB_PCIE0SHADOW2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define NB_PCIE0SHADOW2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//NB_PCIE0SHADOW2_PREF_BASE_LIMIT
+#define NB_PCIE0SHADOW2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define NB_PCIE0SHADOW2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define NB_PCIE0SHADOW2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define NB_PCIE0SHADOW2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//NB_PCIE0SHADOW2_PREF_BASE_UPPER
+#define NB_PCIE0SHADOW2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define NB_PCIE0SHADOW2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//NB_PCIE0SHADOW2_PREF_LIMIT_UPPER
+#define NB_PCIE0SHADOW2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define NB_PCIE0SHADOW2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//NB_PCIE0SHADOW2_IO_BASE_LIMIT_HI
+#define NB_PCIE0SHADOW2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define NB_PCIE0SHADOW2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define NB_PCIE0SHADOW2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define NB_PCIE0SHADOW2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//NB_PCIE0SHADOW2_IRQ_BRIDGE_CNTL
+#define NB_PCIE0SHADOW2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define NB_PCIE0SHADOW2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define NB_PCIE0SHADOW2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define NB_PCIE0SHADOW2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define NB_PCIE0SHADOW2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define NB_PCIE0SHADOW2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+//NB_PCIE0SHADOW2_EXT_BRIDGE_CNTL
+#define NB_PCIE0SHADOW2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define NB_PCIE0SHADOW2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//NB_PCIE0SHADOW2_PMI_STATUS_CNTL
+#define NB_PCIE0SHADOW2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define NB_PCIE0SHADOW2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L
+//NB_PCIE0SHADOW2_SLOT_CAP
+#define NB_PCIE0SHADOW2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define NB_PCIE0SHADOW2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define NB_PCIE0SHADOW2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define NB_PCIE0SHADOW2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+//NB_PCIE0SHADOW2_ROOT_CNTL
+#define NB_PCIE0SHADOW2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define NB_PCIE0SHADOW2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//NB_PCIE0SHADOW2_DEVICE_CNTL2
+#define NB_PCIE0SHADOW2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define NB_PCIE0SHADOW2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+
+
+// addressBlock: nbio_iohub_nb_PCIE0shadow3_pcieshadow_cfgdecp
+//NB_PCIE0SHADOW3_COMMAND
+#define NB_PCIE0SHADOW3_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define NB_PCIE0SHADOW3_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define NB_PCIE0SHADOW3_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define NB_PCIE0SHADOW3_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define NB_PCIE0SHADOW3_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define NB_PCIE0SHADOW3_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+//NB_PCIE0SHADOW3_SUB_BUS_NUMBER_LATENCY
+#define NB_PCIE0SHADOW3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define NB_PCIE0SHADOW3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define NB_PCIE0SHADOW3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define NB_PCIE0SHADOW3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+//NB_PCIE0SHADOW3_IO_BASE_LIMIT
+#define NB_PCIE0SHADOW3_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define NB_PCIE0SHADOW3_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define NB_PCIE0SHADOW3_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define NB_PCIE0SHADOW3_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//NB_PCIE0SHADOW3_MEM_BASE_LIMIT
+#define NB_PCIE0SHADOW3_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define NB_PCIE0SHADOW3_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define NB_PCIE0SHADOW3_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define NB_PCIE0SHADOW3_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//NB_PCIE0SHADOW3_PREF_BASE_LIMIT
+#define NB_PCIE0SHADOW3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define NB_PCIE0SHADOW3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define NB_PCIE0SHADOW3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define NB_PCIE0SHADOW3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//NB_PCIE0SHADOW3_PREF_BASE_UPPER
+#define NB_PCIE0SHADOW3_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define NB_PCIE0SHADOW3_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//NB_PCIE0SHADOW3_PREF_LIMIT_UPPER
+#define NB_PCIE0SHADOW3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define NB_PCIE0SHADOW3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//NB_PCIE0SHADOW3_IO_BASE_LIMIT_HI
+#define NB_PCIE0SHADOW3_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define NB_PCIE0SHADOW3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define NB_PCIE0SHADOW3_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define NB_PCIE0SHADOW3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//NB_PCIE0SHADOW3_IRQ_BRIDGE_CNTL
+#define NB_PCIE0SHADOW3_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define NB_PCIE0SHADOW3_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define NB_PCIE0SHADOW3_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define NB_PCIE0SHADOW3_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define NB_PCIE0SHADOW3_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define NB_PCIE0SHADOW3_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+//NB_PCIE0SHADOW3_EXT_BRIDGE_CNTL
+#define NB_PCIE0SHADOW3_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define NB_PCIE0SHADOW3_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//NB_PCIE0SHADOW3_PMI_STATUS_CNTL
+#define NB_PCIE0SHADOW3_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define NB_PCIE0SHADOW3_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L
+//NB_PCIE0SHADOW3_SLOT_CAP
+#define NB_PCIE0SHADOW3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define NB_PCIE0SHADOW3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define NB_PCIE0SHADOW3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define NB_PCIE0SHADOW3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+//NB_PCIE0SHADOW3_ROOT_CNTL
+#define NB_PCIE0SHADOW3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define NB_PCIE0SHADOW3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//NB_PCIE0SHADOW3_DEVICE_CNTL2
+#define NB_PCIE0SHADOW3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define NB_PCIE0SHADOW3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+
+
+// addressBlock: nbio_iohub_nb_PCIE0shadow4_pcieshadow_cfgdecp
+//NB_PCIE0SHADOW4_COMMAND
+#define NB_PCIE0SHADOW4_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define NB_PCIE0SHADOW4_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define NB_PCIE0SHADOW4_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define NB_PCIE0SHADOW4_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define NB_PCIE0SHADOW4_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define NB_PCIE0SHADOW4_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+//NB_PCIE0SHADOW4_SUB_BUS_NUMBER_LATENCY
+#define NB_PCIE0SHADOW4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define NB_PCIE0SHADOW4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define NB_PCIE0SHADOW4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define NB_PCIE0SHADOW4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+//NB_PCIE0SHADOW4_IO_BASE_LIMIT
+#define NB_PCIE0SHADOW4_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define NB_PCIE0SHADOW4_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define NB_PCIE0SHADOW4_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define NB_PCIE0SHADOW4_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//NB_PCIE0SHADOW4_MEM_BASE_LIMIT
+#define NB_PCIE0SHADOW4_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define NB_PCIE0SHADOW4_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define NB_PCIE0SHADOW4_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define NB_PCIE0SHADOW4_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//NB_PCIE0SHADOW4_PREF_BASE_LIMIT
+#define NB_PCIE0SHADOW4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define NB_PCIE0SHADOW4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define NB_PCIE0SHADOW4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define NB_PCIE0SHADOW4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//NB_PCIE0SHADOW4_PREF_BASE_UPPER
+#define NB_PCIE0SHADOW4_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define NB_PCIE0SHADOW4_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//NB_PCIE0SHADOW4_PREF_LIMIT_UPPER
+#define NB_PCIE0SHADOW4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define NB_PCIE0SHADOW4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//NB_PCIE0SHADOW4_IO_BASE_LIMIT_HI
+#define NB_PCIE0SHADOW4_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define NB_PCIE0SHADOW4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define NB_PCIE0SHADOW4_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define NB_PCIE0SHADOW4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//NB_PCIE0SHADOW4_IRQ_BRIDGE_CNTL
+#define NB_PCIE0SHADOW4_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define NB_PCIE0SHADOW4_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define NB_PCIE0SHADOW4_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define NB_PCIE0SHADOW4_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define NB_PCIE0SHADOW4_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define NB_PCIE0SHADOW4_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+//NB_PCIE0SHADOW4_EXT_BRIDGE_CNTL
+#define NB_PCIE0SHADOW4_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define NB_PCIE0SHADOW4_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//NB_PCIE0SHADOW4_PMI_STATUS_CNTL
+#define NB_PCIE0SHADOW4_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define NB_PCIE0SHADOW4_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L
+//NB_PCIE0SHADOW4_SLOT_CAP
+#define NB_PCIE0SHADOW4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define NB_PCIE0SHADOW4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define NB_PCIE0SHADOW4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define NB_PCIE0SHADOW4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+//NB_PCIE0SHADOW4_ROOT_CNTL
+#define NB_PCIE0SHADOW4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define NB_PCIE0SHADOW4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//NB_PCIE0SHADOW4_DEVICE_CNTL2
+#define NB_PCIE0SHADOW4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define NB_PCIE0SHADOW4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+
+
+// addressBlock: nbio_iohub_nb_PCIE0shadow5_pcieshadow_cfgdecp
+//NB_PCIE0SHADOW5_COMMAND
+#define NB_PCIE0SHADOW5_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define NB_PCIE0SHADOW5_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define NB_PCIE0SHADOW5_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define NB_PCIE0SHADOW5_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define NB_PCIE0SHADOW5_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define NB_PCIE0SHADOW5_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+//NB_PCIE0SHADOW5_SUB_BUS_NUMBER_LATENCY
+#define NB_PCIE0SHADOW5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define NB_PCIE0SHADOW5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define NB_PCIE0SHADOW5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define NB_PCIE0SHADOW5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+//NB_PCIE0SHADOW5_IO_BASE_LIMIT
+#define NB_PCIE0SHADOW5_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define NB_PCIE0SHADOW5_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define NB_PCIE0SHADOW5_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define NB_PCIE0SHADOW5_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//NB_PCIE0SHADOW5_MEM_BASE_LIMIT
+#define NB_PCIE0SHADOW5_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define NB_PCIE0SHADOW5_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define NB_PCIE0SHADOW5_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define NB_PCIE0SHADOW5_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//NB_PCIE0SHADOW5_PREF_BASE_LIMIT
+#define NB_PCIE0SHADOW5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define NB_PCIE0SHADOW5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define NB_PCIE0SHADOW5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define NB_PCIE0SHADOW5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//NB_PCIE0SHADOW5_PREF_BASE_UPPER
+#define NB_PCIE0SHADOW5_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define NB_PCIE0SHADOW5_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//NB_PCIE0SHADOW5_PREF_LIMIT_UPPER
+#define NB_PCIE0SHADOW5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define NB_PCIE0SHADOW5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//NB_PCIE0SHADOW5_IO_BASE_LIMIT_HI
+#define NB_PCIE0SHADOW5_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define NB_PCIE0SHADOW5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define NB_PCIE0SHADOW5_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define NB_PCIE0SHADOW5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//NB_PCIE0SHADOW5_IRQ_BRIDGE_CNTL
+#define NB_PCIE0SHADOW5_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define NB_PCIE0SHADOW5_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define NB_PCIE0SHADOW5_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define NB_PCIE0SHADOW5_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define NB_PCIE0SHADOW5_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define NB_PCIE0SHADOW5_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+//NB_PCIE0SHADOW5_EXT_BRIDGE_CNTL
+#define NB_PCIE0SHADOW5_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define NB_PCIE0SHADOW5_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//NB_PCIE0SHADOW5_PMI_STATUS_CNTL
+#define NB_PCIE0SHADOW5_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define NB_PCIE0SHADOW5_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L
+//NB_PCIE0SHADOW5_SLOT_CAP
+#define NB_PCIE0SHADOW5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define NB_PCIE0SHADOW5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define NB_PCIE0SHADOW5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define NB_PCIE0SHADOW5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+//NB_PCIE0SHADOW5_ROOT_CNTL
+#define NB_PCIE0SHADOW5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define NB_PCIE0SHADOW5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//NB_PCIE0SHADOW5_DEVICE_CNTL2
+#define NB_PCIE0SHADOW5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define NB_PCIE0SHADOW5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+
+
+// addressBlock: nbio_iohub_nb_PCIE0shadow6_pcieshadow_cfgdecp
+//NB_PCIE0SHADOW6_COMMAND
+#define NB_PCIE0SHADOW6_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define NB_PCIE0SHADOW6_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define NB_PCIE0SHADOW6_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define NB_PCIE0SHADOW6_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define NB_PCIE0SHADOW6_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define NB_PCIE0SHADOW6_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+//NB_PCIE0SHADOW6_SUB_BUS_NUMBER_LATENCY
+#define NB_PCIE0SHADOW6_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define NB_PCIE0SHADOW6_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define NB_PCIE0SHADOW6_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define NB_PCIE0SHADOW6_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+//NB_PCIE0SHADOW6_IO_BASE_LIMIT
+#define NB_PCIE0SHADOW6_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define NB_PCIE0SHADOW6_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define NB_PCIE0SHADOW6_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define NB_PCIE0SHADOW6_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//NB_PCIE0SHADOW6_MEM_BASE_LIMIT
+#define NB_PCIE0SHADOW6_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define NB_PCIE0SHADOW6_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define NB_PCIE0SHADOW6_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define NB_PCIE0SHADOW6_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//NB_PCIE0SHADOW6_PREF_BASE_LIMIT
+#define NB_PCIE0SHADOW6_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define NB_PCIE0SHADOW6_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define NB_PCIE0SHADOW6_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define NB_PCIE0SHADOW6_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//NB_PCIE0SHADOW6_PREF_BASE_UPPER
+#define NB_PCIE0SHADOW6_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define NB_PCIE0SHADOW6_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//NB_PCIE0SHADOW6_PREF_LIMIT_UPPER
+#define NB_PCIE0SHADOW6_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define NB_PCIE0SHADOW6_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//NB_PCIE0SHADOW6_IO_BASE_LIMIT_HI
+#define NB_PCIE0SHADOW6_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define NB_PCIE0SHADOW6_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define NB_PCIE0SHADOW6_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define NB_PCIE0SHADOW6_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//NB_PCIE0SHADOW6_IRQ_BRIDGE_CNTL
+#define NB_PCIE0SHADOW6_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define NB_PCIE0SHADOW6_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define NB_PCIE0SHADOW6_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define NB_PCIE0SHADOW6_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define NB_PCIE0SHADOW6_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define NB_PCIE0SHADOW6_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+//NB_PCIE0SHADOW6_EXT_BRIDGE_CNTL
+#define NB_PCIE0SHADOW6_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define NB_PCIE0SHADOW6_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//NB_PCIE0SHADOW6_PMI_STATUS_CNTL
+#define NB_PCIE0SHADOW6_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define NB_PCIE0SHADOW6_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L
+//NB_PCIE0SHADOW6_SLOT_CAP
+#define NB_PCIE0SHADOW6_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define NB_PCIE0SHADOW6_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define NB_PCIE0SHADOW6_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define NB_PCIE0SHADOW6_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+//NB_PCIE0SHADOW6_ROOT_CNTL
+#define NB_PCIE0SHADOW6_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define NB_PCIE0SHADOW6_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//NB_PCIE0SHADOW6_DEVICE_CNTL2
+#define NB_PCIE0SHADOW6_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define NB_PCIE0SHADOW6_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+
+
+// addressBlock: nbio_iohub_nb_NBIF1shadow0_pcieshadow_cfgdecp
+//NB_NBIF1SHADOW0_COMMAND
+#define NB_NBIF1SHADOW0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define NB_NBIF1SHADOW0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define NB_NBIF1SHADOW0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define NB_NBIF1SHADOW0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define NB_NBIF1SHADOW0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define NB_NBIF1SHADOW0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+//NB_NBIF1SHADOW0_SUB_BUS_NUMBER_LATENCY
+#define NB_NBIF1SHADOW0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define NB_NBIF1SHADOW0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define NB_NBIF1SHADOW0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define NB_NBIF1SHADOW0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+//NB_NBIF1SHADOW0_IO_BASE_LIMIT
+#define NB_NBIF1SHADOW0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define NB_NBIF1SHADOW0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define NB_NBIF1SHADOW0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define NB_NBIF1SHADOW0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//NB_NBIF1SHADOW0_MEM_BASE_LIMIT
+#define NB_NBIF1SHADOW0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define NB_NBIF1SHADOW0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define NB_NBIF1SHADOW0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define NB_NBIF1SHADOW0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//NB_NBIF1SHADOW0_PREF_BASE_LIMIT
+#define NB_NBIF1SHADOW0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define NB_NBIF1SHADOW0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define NB_NBIF1SHADOW0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define NB_NBIF1SHADOW0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//NB_NBIF1SHADOW0_PREF_BASE_UPPER
+#define NB_NBIF1SHADOW0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define NB_NBIF1SHADOW0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//NB_NBIF1SHADOW0_PREF_LIMIT_UPPER
+#define NB_NBIF1SHADOW0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define NB_NBIF1SHADOW0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//NB_NBIF1SHADOW0_IO_BASE_LIMIT_HI
+#define NB_NBIF1SHADOW0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define NB_NBIF1SHADOW0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define NB_NBIF1SHADOW0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define NB_NBIF1SHADOW0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//NB_NBIF1SHADOW0_IRQ_BRIDGE_CNTL
+#define NB_NBIF1SHADOW0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define NB_NBIF1SHADOW0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define NB_NBIF1SHADOW0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define NB_NBIF1SHADOW0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define NB_NBIF1SHADOW0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define NB_NBIF1SHADOW0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+//NB_NBIF1SHADOW0_EXT_BRIDGE_CNTL
+#define NB_NBIF1SHADOW0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define NB_NBIF1SHADOW0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//NB_NBIF1SHADOW0_PMI_STATUS_CNTL
+#define NB_NBIF1SHADOW0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define NB_NBIF1SHADOW0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L
+//NB_NBIF1SHADOW0_SLOT_CAP
+#define NB_NBIF1SHADOW0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define NB_NBIF1SHADOW0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define NB_NBIF1SHADOW0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define NB_NBIF1SHADOW0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+//NB_NBIF1SHADOW0_ROOT_CNTL
+#define NB_NBIF1SHADOW0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define NB_NBIF1SHADOW0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//NB_NBIF1SHADOW0_DEVICE_CNTL2
+#define NB_NBIF1SHADOW0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define NB_NBIF1SHADOW0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+
+
+// addressBlock: nbio_iohub_nb_NBIF1shadow1_pcieshadow_cfgdecp
+//NB_NBIF1SHADOW1_COMMAND
+#define NB_NBIF1SHADOW1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define NB_NBIF1SHADOW1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define NB_NBIF1SHADOW1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define NB_NBIF1SHADOW1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define NB_NBIF1SHADOW1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define NB_NBIF1SHADOW1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+//NB_NBIF1SHADOW1_SUB_BUS_NUMBER_LATENCY
+#define NB_NBIF1SHADOW1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define NB_NBIF1SHADOW1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define NB_NBIF1SHADOW1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define NB_NBIF1SHADOW1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+//NB_NBIF1SHADOW1_IO_BASE_LIMIT
+#define NB_NBIF1SHADOW1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define NB_NBIF1SHADOW1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define NB_NBIF1SHADOW1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define NB_NBIF1SHADOW1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//NB_NBIF1SHADOW1_MEM_BASE_LIMIT
+#define NB_NBIF1SHADOW1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define NB_NBIF1SHADOW1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define NB_NBIF1SHADOW1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define NB_NBIF1SHADOW1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//NB_NBIF1SHADOW1_PREF_BASE_LIMIT
+#define NB_NBIF1SHADOW1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define NB_NBIF1SHADOW1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define NB_NBIF1SHADOW1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define NB_NBIF1SHADOW1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//NB_NBIF1SHADOW1_PREF_BASE_UPPER
+#define NB_NBIF1SHADOW1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define NB_NBIF1SHADOW1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//NB_NBIF1SHADOW1_PREF_LIMIT_UPPER
+#define NB_NBIF1SHADOW1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define NB_NBIF1SHADOW1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//NB_NBIF1SHADOW1_IO_BASE_LIMIT_HI
+#define NB_NBIF1SHADOW1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define NB_NBIF1SHADOW1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define NB_NBIF1SHADOW1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define NB_NBIF1SHADOW1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//NB_NBIF1SHADOW1_IRQ_BRIDGE_CNTL
+#define NB_NBIF1SHADOW1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define NB_NBIF1SHADOW1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define NB_NBIF1SHADOW1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define NB_NBIF1SHADOW1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define NB_NBIF1SHADOW1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define NB_NBIF1SHADOW1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+//NB_NBIF1SHADOW1_EXT_BRIDGE_CNTL
+#define NB_NBIF1SHADOW1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define NB_NBIF1SHADOW1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//NB_NBIF1SHADOW1_PMI_STATUS_CNTL
+#define NB_NBIF1SHADOW1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define NB_NBIF1SHADOW1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L
+//NB_NBIF1SHADOW1_SLOT_CAP
+#define NB_NBIF1SHADOW1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define NB_NBIF1SHADOW1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define NB_NBIF1SHADOW1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define NB_NBIF1SHADOW1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+//NB_NBIF1SHADOW1_ROOT_CNTL
+#define NB_NBIF1SHADOW1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define NB_NBIF1SHADOW1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//NB_NBIF1SHADOW1_DEVICE_CNTL2
+#define NB_NBIF1SHADOW1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define NB_NBIF1SHADOW1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+
+
+// addressBlock: nbio_iohub_nb_fastreg_fastreg_cfgdec
+//FASTREG_APERTURE
+#define FASTREG_APERTURE__FASTREG_APERTURE_ID__SHIFT 0x0
+#define FASTREG_APERTURE__FASTREG_NODE_ID__SHIFT 0x10
+#define FASTREG_APERTURE__FASTREG_TRAN_POSTED__SHIFT 0x1f
+#define FASTREG_APERTURE__FASTREG_APERTURE_ID_MASK 0x00000FFFL
+#define FASTREG_APERTURE__FASTREG_NODE_ID_MASK 0x000F0000L
+#define FASTREG_APERTURE__FASTREG_TRAN_POSTED_MASK 0x80000000L
+
+
+// addressBlock: nbio_iohub_nb_misc_misc_cfgdec
+//NB_CNTL
+#define NB_CNTL__HWINIT_WR_LOCK__SHIFT 0x7
+#define NB_CNTL__HWINIT_WR_LOCK_MASK 0x00000080L
+//NB_SPARE1
+#define NB_SPARE1__NB_SPARE1_RW__SHIFT 0x0
+#define NB_SPARE1__NB_SPARE1_RW_MASK 0xFFFFFFFFL
+//NB_SPARE2
+#define NB_SPARE2__NB_SPARE2_RW1C_0__SHIFT 0x0
+#define NB_SPARE2__NB_SPARE2_RW1C_1__SHIFT 0x1
+#define NB_SPARE2__NB_SPARE2_RW1C_2__SHIFT 0x2
+#define NB_SPARE2__NB_SPARE2_RW1C_3__SHIFT 0x3
+#define NB_SPARE2__NB_SPARE2_RW1C_4__SHIFT 0x4
+#define NB_SPARE2__NB_SPARE2_RW1C_5__SHIFT 0x5
+#define NB_SPARE2__NB_SPARE2_RW1C_6__SHIFT 0x6
+#define NB_SPARE2__NB_SPARE2_RW1C_7__SHIFT 0x7
+#define NB_SPARE2__NB_SPARE2_RW1C_8__SHIFT 0x8
+#define NB_SPARE2__NB_SPARE2_RW1C_9__SHIFT 0x9
+#define NB_SPARE2__NB_SPARE2_RW1C_10__SHIFT 0xa
+#define NB_SPARE2__NB_SPARE2_RW1C_11__SHIFT 0xb
+#define NB_SPARE2__NB_SPARE2_RW1C_12__SHIFT 0xc
+#define NB_SPARE2__NB_SPARE2_RW1C_13__SHIFT 0xd
+#define NB_SPARE2__NB_SPARE2_RW1C_14__SHIFT 0xe
+#define NB_SPARE2__NB_SPARE2_RW1C_15__SHIFT 0xf
+#define NB_SPARE2__NB_SPARE2_RW1C_16__SHIFT 0x10
+#define NB_SPARE2__NB_SPARE2_RW1C_17__SHIFT 0x11
+#define NB_SPARE2__NB_SPARE2_RW1C_18__SHIFT 0x12
+#define NB_SPARE2__NB_SPARE2_RW1C_19__SHIFT 0x13
+#define NB_SPARE2__NB_SPARE2_RW1C_20__SHIFT 0x14
+#define NB_SPARE2__NB_SPARE2_RW1C_21__SHIFT 0x15
+#define NB_SPARE2__NB_SPARE2_RW1C_22__SHIFT 0x16
+#define NB_SPARE2__NB_SPARE2_RW1C_23__SHIFT 0x17
+#define NB_SPARE2__NB_SPARE2_RW1C_24__SHIFT 0x18
+#define NB_SPARE2__NB_SPARE2_RW1C_25__SHIFT 0x19
+#define NB_SPARE2__NB_SPARE2_RW1C_26__SHIFT 0x1a
+#define NB_SPARE2__NB_SPARE2_RW1C_27__SHIFT 0x1b
+#define NB_SPARE2__NB_SPARE2_RW1C_28__SHIFT 0x1c
+#define NB_SPARE2__NB_SPARE2_RW1C_29__SHIFT 0x1d
+#define NB_SPARE2__NB_SPARE2_RW1C_30__SHIFT 0x1e
+#define NB_SPARE2__NB_SPARE2_RW1C_31__SHIFT 0x1f
+#define NB_SPARE2__NB_SPARE2_RW1C_0_MASK 0x00000001L
+#define NB_SPARE2__NB_SPARE2_RW1C_1_MASK 0x00000002L
+#define NB_SPARE2__NB_SPARE2_RW1C_2_MASK 0x00000004L
+#define NB_SPARE2__NB_SPARE2_RW1C_3_MASK 0x00000008L
+#define NB_SPARE2__NB_SPARE2_RW1C_4_MASK 0x00000010L
+#define NB_SPARE2__NB_SPARE2_RW1C_5_MASK 0x00000020L
+#define NB_SPARE2__NB_SPARE2_RW1C_6_MASK 0x00000040L
+#define NB_SPARE2__NB_SPARE2_RW1C_7_MASK 0x00000080L
+#define NB_SPARE2__NB_SPARE2_RW1C_8_MASK 0x00000100L
+#define NB_SPARE2__NB_SPARE2_RW1C_9_MASK 0x00000200L
+#define NB_SPARE2__NB_SPARE2_RW1C_10_MASK 0x00000400L
+#define NB_SPARE2__NB_SPARE2_RW1C_11_MASK 0x00000800L
+#define NB_SPARE2__NB_SPARE2_RW1C_12_MASK 0x00001000L
+#define NB_SPARE2__NB_SPARE2_RW1C_13_MASK 0x00002000L
+#define NB_SPARE2__NB_SPARE2_RW1C_14_MASK 0x00004000L
+#define NB_SPARE2__NB_SPARE2_RW1C_15_MASK 0x00008000L
+#define NB_SPARE2__NB_SPARE2_RW1C_16_MASK 0x00010000L
+#define NB_SPARE2__NB_SPARE2_RW1C_17_MASK 0x00020000L
+#define NB_SPARE2__NB_SPARE2_RW1C_18_MASK 0x00040000L
+#define NB_SPARE2__NB_SPARE2_RW1C_19_MASK 0x00080000L
+#define NB_SPARE2__NB_SPARE2_RW1C_20_MASK 0x00100000L
+#define NB_SPARE2__NB_SPARE2_RW1C_21_MASK 0x00200000L
+#define NB_SPARE2__NB_SPARE2_RW1C_22_MASK 0x00400000L
+#define NB_SPARE2__NB_SPARE2_RW1C_23_MASK 0x00800000L
+#define NB_SPARE2__NB_SPARE2_RW1C_24_MASK 0x01000000L
+#define NB_SPARE2__NB_SPARE2_RW1C_25_MASK 0x02000000L
+#define NB_SPARE2__NB_SPARE2_RW1C_26_MASK 0x04000000L
+#define NB_SPARE2__NB_SPARE2_RW1C_27_MASK 0x08000000L
+#define NB_SPARE2__NB_SPARE2_RW1C_28_MASK 0x10000000L
+#define NB_SPARE2__NB_SPARE2_RW1C_29_MASK 0x20000000L
+#define NB_SPARE2__NB_SPARE2_RW1C_30_MASK 0x40000000L
+#define NB_SPARE2__NB_SPARE2_RW1C_31_MASK 0x80000000L
+//NB_REVID
+#define NB_REVID__REVISION_ID__SHIFT 0x0
+#define NB_REVID__REVISION_ID_MASK 0x000003FFL
+//IOHC_REFCLK_MODE
+#define IOHC_REFCLK_MODE__MODE_100MHZ__SHIFT 0x0
+#define IOHC_REFCLK_MODE__MODE_25MHZ__SHIFT 0x1
+#define IOHC_REFCLK_MODE__MODE_27MHZ__SHIFT 0x2
+#define IOHC_REFCLK_MODE__MODE_100MHZ_MASK 0x00000001L
+#define IOHC_REFCLK_MODE__MODE_25MHZ_MASK 0x00000002L
+#define IOHC_REFCLK_MODE__MODE_27MHZ_MASK 0x00000004L
+//IOHC_PCIE_CRS_Count
+#define IOHC_PCIE_CRS_Count__CrsDelayCount__SHIFT 0x0
+#define IOHC_PCIE_CRS_Count__CrsLimitCount__SHIFT 0x10
+#define IOHC_PCIE_CRS_Count__CrsDelayCount_MASK 0x0000FFFFL
+#define IOHC_PCIE_CRS_Count__CrsLimitCount_MASK 0x0FFF0000L
+//IOHC_P2P_CNTL
+#define IOHC_P2P_CNTL__DLDownResetEn__SHIFT 0xb
+#define IOHC_P2P_CNTL__DLDownResetEn_MASK 0x00000800L
+//CFG_IOHC_PCI
+#define CFG_IOHC_PCI__CFG_IOHC_PCI_Dev0Fn2RegEn__SHIFT 0x0
+#define CFG_IOHC_PCI__IOMMU_DIS__SHIFT 0x1f
+#define CFG_IOHC_PCI__CFG_IOHC_PCI_Dev0Fn2RegEn_MASK 0x00000001L
+#define CFG_IOHC_PCI__IOMMU_DIS_MASK 0x80000000L
+//NB_BUS_NUM_CNTL
+#define NB_BUS_NUM_CNTL__NB_BUS_NUM__SHIFT 0x0
+#define NB_BUS_NUM_CNTL__NB_BUS_LAT_Mode__SHIFT 0x8
+#define NB_BUS_NUM_CNTL__NB_BUS_NUM_MASK 0x000000FFL
+#define NB_BUS_NUM_CNTL__NB_BUS_LAT_Mode_MASK 0x00000100L
+//IOHC_AER_CNTL
+#define IOHC_AER_CNTL__CFG_IOHC_AER_COMPLIANCE_EN__SHIFT 0x1
+#define IOHC_AER_CNTL__CFG_IOHC_AER_COMPLIANCE_EN_MASK 0x00000002L
+//NB_MMIOBASE
+#define NB_MMIOBASE__MMIOBASE__SHIFT 0x0
+#define NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL
+//NB_MMIOLIMIT
+#define NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0
+#define NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL
+//NB_LOWER_TOP_OF_DRAM2
+#define NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0
+#define NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17
+#define NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L
+#define NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L
+//NB_UPPER_TOP_OF_DRAM2
+#define NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0
+#define NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x000001FFL
+//NB_LOWER_DRAM2_BASE
+#define NB_LOWER_DRAM2_BASE__LOWER_DRAM2_BASE__SHIFT 0x17
+#define NB_LOWER_DRAM2_BASE__LOWER_DRAM2_BASE_MASK 0xFF800000L
+//NB_UPPER_DRAM2_BASE
+#define NB_UPPER_DRAM2_BASE__UPPER_DRAM2_BASE__SHIFT 0x0
+#define NB_UPPER_DRAM2_BASE__UPPER_DRAM2_BASE_MASK 0x000001FFL
+//SB_LOCATION
+#define SB_LOCATION__SBlocated_Port__SHIFT 0x0
+#define SB_LOCATION__SBlocated_Core__SHIFT 0x10
+#define SB_LOCATION__SBlocated_Port_MASK 0x0000FFFFL
+#define SB_LOCATION__SBlocated_Core_MASK 0xFFFF0000L
+//IOHC_GLUE_CG_LCLK_CTRL_0
+#define IOHC_GLUE_CG_LCLK_CTRL_0__CG_OFF_HYSTERESIS__SHIFT 0x4
+#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK9__SHIFT 0x16
+#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK8__SHIFT 0x17
+#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK7__SHIFT 0x18
+#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK6__SHIFT 0x19
+#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK5__SHIFT 0x1a
+#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK4__SHIFT 0x1b
+#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK3__SHIFT 0x1c
+#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK2__SHIFT 0x1d
+#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK1__SHIFT 0x1e
+#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK0__SHIFT 0x1f
+#define IOHC_GLUE_CG_LCLK_CTRL_0__CG_OFF_HYSTERESIS_MASK 0x00000FF0L
+#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK9_MASK 0x00400000L
+#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK8_MASK 0x00800000L
+#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK7_MASK 0x01000000L
+#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK6_MASK 0x02000000L
+#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK5_MASK 0x04000000L
+#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK4_MASK 0x08000000L
+#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK3_MASK 0x10000000L
+#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK2_MASK 0x20000000L
+#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK1_MASK 0x40000000L
+#define IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK0_MASK 0x80000000L
+//IOHC_GLUE_CG_LCLK_CTRL_1
+#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK9__SHIFT 0x16
+#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK8__SHIFT 0x17
+#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK7__SHIFT 0x18
+#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK6__SHIFT 0x19
+#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK5__SHIFT 0x1a
+#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK4__SHIFT 0x1b
+#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK3__SHIFT 0x1c
+#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK2__SHIFT 0x1d
+#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK1__SHIFT 0x1e
+#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK0__SHIFT 0x1f
+#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK9_MASK 0x00400000L
+#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK8_MASK 0x00800000L
+#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK7_MASK 0x01000000L
+#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK6_MASK 0x02000000L
+#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK5_MASK 0x04000000L
+#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK4_MASK 0x08000000L
+#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK3_MASK 0x10000000L
+#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK2_MASK 0x20000000L
+#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK1_MASK 0x40000000L
+#define IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK0_MASK 0x80000000L
+//IOHC_GLUE_CG_LCLK_CTRL_2
+#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK9__SHIFT 0x16
+#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK8__SHIFT 0x17
+#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK7__SHIFT 0x18
+#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK6__SHIFT 0x19
+#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK5__SHIFT 0x1a
+#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK4__SHIFT 0x1b
+#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK3__SHIFT 0x1c
+#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK2__SHIFT 0x1d
+#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK1__SHIFT 0x1e
+#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK0__SHIFT 0x1f
+#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK9_MASK 0x00400000L
+#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK8_MASK 0x00800000L
+#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK7_MASK 0x01000000L
+#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK6_MASK 0x02000000L
+#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK5_MASK 0x04000000L
+#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK4_MASK 0x08000000L
+#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK3_MASK 0x10000000L
+#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK2_MASK 0x20000000L
+#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK1_MASK 0x40000000L
+#define IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK0_MASK 0x80000000L
+//IOHC_PERF_CNTL
+#define IOHC_PERF_CNTL__EVENT0_SEL__SHIFT 0x0
+#define IOHC_PERF_CNTL__EVENT1_SEL__SHIFT 0x8
+#define IOHC_PERF_CNTL__EVENT2_SEL__SHIFT 0x10
+#define IOHC_PERF_CNTL__EVENT3_SEL__SHIFT 0x18
+#define IOHC_PERF_CNTL__EVENT0_SEL_MASK 0x000000FFL
+#define IOHC_PERF_CNTL__EVENT1_SEL_MASK 0x0000FF00L
+#define IOHC_PERF_CNTL__EVENT2_SEL_MASK 0x00FF0000L
+#define IOHC_PERF_CNTL__EVENT3_SEL_MASK 0xFF000000L
+//IOHC_PERF_COUNT0
+#define IOHC_PERF_COUNT0__COUNTER0__SHIFT 0x0
+#define IOHC_PERF_COUNT0__COUNTER0_MASK 0xFFFFFFFFL
+//IOHC_PERF_COUNT0_UPPER
+#define IOHC_PERF_COUNT0_UPPER__COUNTER0_UPPER__SHIFT 0x0
+#define IOHC_PERF_COUNT0_UPPER__COUNTER0_UPPER_MASK 0x00FFFFFFL
+//IOHC_PERF_COUNT1
+#define IOHC_PERF_COUNT1__COUNTER1__SHIFT 0x0
+#define IOHC_PERF_COUNT1__COUNTER1_MASK 0xFFFFFFFFL
+//IOHC_PERF_COUNT1_UPPER
+#define IOHC_PERF_COUNT1_UPPER__COUNTER1_UPPER__SHIFT 0x0
+#define IOHC_PERF_COUNT1_UPPER__COUNTER1_UPPER_MASK 0x00FFFFFFL
+//IOHC_PERF_COUNT2
+#define IOHC_PERF_COUNT2__COUNTER2__SHIFT 0x0
+#define IOHC_PERF_COUNT2__COUNTER2_MASK 0xFFFFFFFFL
+//IOHC_PERF_COUNT2_UPPER
+#define IOHC_PERF_COUNT2_UPPER__COUNTER2_UPPER__SHIFT 0x0
+#define IOHC_PERF_COUNT2_UPPER__COUNTER2_UPPER_MASK 0x00FFFFFFL
+//IOHC_PERF_COUNT3
+#define IOHC_PERF_COUNT3__COUNTER3__SHIFT 0x0
+#define IOHC_PERF_COUNT3__COUNTER3_MASK 0xFFFFFFFFL
+//IOHC_PERF_COUNT3_UPPER
+#define IOHC_PERF_COUNT3_UPPER__COUNTER3_UPPER__SHIFT 0x0
+#define IOHC_PERF_COUNT3_UPPER__COUNTER3_UPPER_MASK 0x00FFFFFFL
+//NB_PROG_DEVICE_REMAP_PBr0
+#define NB_PROG_DEVICE_REMAP_PBr0__PBr0_DevFnMap__SHIFT 0x0
+#define NB_PROG_DEVICE_REMAP_PBr0__PBr0_DevFnMap_MASK 0x000000FFL
+//NB_PROG_DEVICE_REMAP_PBr1
+#define NB_PROG_DEVICE_REMAP_PBr1__PBr1_DevFnMap__SHIFT 0x0
+#define NB_PROG_DEVICE_REMAP_PBr1__PBr1_DevFnMap_MASK 0x000000FFL
+//NB_PROG_DEVICE_REMAP_PBr2
+#define NB_PROG_DEVICE_REMAP_PBr2__PBr2_DevFnMap__SHIFT 0x0
+#define NB_PROG_DEVICE_REMAP_PBr2__PBr2_DevFnMap_MASK 0x000000FFL
+//NB_PROG_DEVICE_REMAP_PBr3
+#define NB_PROG_DEVICE_REMAP_PBr3__PBr3_DevFnMap__SHIFT 0x0
+#define NB_PROG_DEVICE_REMAP_PBr3__PBr3_DevFnMap_MASK 0x000000FFL
+//NB_PROG_DEVICE_REMAP_PBr4
+#define NB_PROG_DEVICE_REMAP_PBr4__PBr4_DevFnMap__SHIFT 0x0
+#define NB_PROG_DEVICE_REMAP_PBr4__PBr4_DevFnMap_MASK 0x000000FFL
+//NB_PROG_DEVICE_REMAP_PBr5
+#define NB_PROG_DEVICE_REMAP_PBr5__PBr5_DevFnMap__SHIFT 0x0
+#define NB_PROG_DEVICE_REMAP_PBr5__PBr5_DevFnMap_MASK 0x000000FFL
+//NB_PROG_DEVICE_REMAP_PBr6
+#define NB_PROG_DEVICE_REMAP_PBr6__PBr6_DevFnMap__SHIFT 0x0
+#define NB_PROG_DEVICE_REMAP_PBr6__PBr6_DevFnMap_MASK 0x000000FFL
+//NB_PROG_DEVICE_REMAP_PBr7
+#define NB_PROG_DEVICE_REMAP_PBr7__PBr7_DevFnMap__SHIFT 0x0
+#define NB_PROG_DEVICE_REMAP_PBr7__PBr7_DevFnMap_MASK 0x000000FFL
+//NB_PROG_DEVICE_REMAP_PBr8
+#define NB_PROG_DEVICE_REMAP_PBr8__PBr8_DevFnMap__SHIFT 0x0
+#define NB_PROG_DEVICE_REMAP_PBr8__PBr8_DevFnMap_MASK 0x000000FFL
+//SW_NMI_CNTL
+#define SW_NMI_CNTL__SW_NMI_Status__SHIFT 0x0
+#define SW_NMI_CNTL__SW_NMI_Status_MASK 0xFFFFFFFFL
+//SW_SMI_CNTL
+#define SW_SMI_CNTL__SW_SMI_Status__SHIFT 0x0
+#define SW_SMI_CNTL__SW_SMI_Status_MASK 0xFFFFFFFFL
+//SW_SCI_CNTL
+#define SW_SCI_CNTL__SW_SCI_Status__SHIFT 0x0
+#define SW_SCI_CNTL__SW_SCI_Status_MASK 0xFFFFFFFFL
+//APML_SW_STATUS
+#define APML_SW_STATUS__APML_NMI_STATUS__SHIFT 0x0
+#define APML_SW_STATUS__APML_NMI_STATUS_MASK 0x00000001L
+//IOHC_FEATURE_CNTL
+#define IOHC_FEATURE_CNTL__HpPmpme_DevID_En__SHIFT 0x0
+#define IOHC_FEATURE_CNTL__P2P_mode__SHIFT 0x1
+#define IOHC_FEATURE_CNTL__IOHC_ARCH_MODE__SHIFT 0x3
+#define IOHC_FEATURE_CNTL__IOHC_ARI_SUPPORTED__SHIFT 0x16
+#define IOHC_FEATURE_CNTL__IOHC_dGPU_MODE__SHIFT 0x1c
+#define IOHC_FEATURE_CNTL__MISC_FEATURE_CNTL__SHIFT 0x1d
+#define IOHC_FEATURE_CNTL__HpPmpme_DevID_En_MASK 0x00000001L
+#define IOHC_FEATURE_CNTL__P2P_mode_MASK 0x00000006L
+#define IOHC_FEATURE_CNTL__IOHC_ARCH_MODE_MASK 0x00000008L
+#define IOHC_FEATURE_CNTL__IOHC_ARI_SUPPORTED_MASK 0x00400000L
+#define IOHC_FEATURE_CNTL__IOHC_dGPU_MODE_MASK 0x10000000L
+#define IOHC_FEATURE_CNTL__MISC_FEATURE_CNTL_MASK 0xE0000000L
+//SW_GIC_SPI_CNTL
+#define SW_GIC_SPI_CNTL__SW_NMI_GIC_SPI_Vector__SHIFT 0x0
+#define SW_GIC_SPI_CNTL__SW_SMI_GIC_SPI_Vector__SHIFT 0x8
+#define SW_GIC_SPI_CNTL__SW_SCI_GIC_SPI_Vector__SHIFT 0x10
+#define SW_GIC_SPI_CNTL__SW_NMI_GIC_SPI_Vector_MASK 0x000000FFL
+#define SW_GIC_SPI_CNTL__SW_SMI_GIC_SPI_Vector_MASK 0x0000FF00L
+#define SW_GIC_SPI_CNTL__SW_SCI_GIC_SPI_Vector_MASK 0x00FF0000L
+//IOHC_INTERRUPT_EOI
+#define IOHC_INTERRUPT_EOI__SMI_EOI__SHIFT 0x0
+#define IOHC_INTERRUPT_EOI__SCI_EOI__SHIFT 0x1
+#define IOHC_INTERRUPT_EOI__NMI_EOI__SHIFT 0x2
+#define IOHC_INTERRUPT_EOI__SMI_EOI_MASK 0x00000001L
+#define IOHC_INTERRUPT_EOI__SCI_EOI_MASK 0x00000002L
+#define IOHC_INTERRUPT_EOI__NMI_EOI_MASK 0x00000004L
+//SW_SYNCFLOOD_CNTL
+#define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_PRIVATE__SHIFT 0x0
+#define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_APML__SHIFT 0x1
+#define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_PRIVATE_MASK 0x00000001L
+#define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_APML_MASK 0x00000002L
+//IOHC_PIN_CNTL
+#define IOHC_PIN_CNTL__NMI_SYNCFLOOD_PIN_MODE__SHIFT 0x0
+#define IOHC_PIN_CNTL__NMI_SYNCFLOOD_PIN_MODE_MASK 0x00000001L
+//IOHC_INTR_CNTL
+#define IOHC_INTR_CNTL__NMI_DEST_ctrl__SHIFT 0x8
+#define IOHC_INTR_CNTL__NMI_DEST_ctrl_MASK 0x0000FF00L
+//IOHC_FEATURE_CNTL2
+#define IOHC_FEATURE_CNTL2__NMI_status__SHIFT 0x0
+#define IOHC_FEATURE_CNTL2__SErr_status__SHIFT 0x1
+#define IOHC_FEATURE_CNTL2__CrsStatus__SHIFT 0x10
+#define IOHC_FEATURE_CNTL2__P_DMA_DROPPED__SHIFT 0x11
+#define IOHC_FEATURE_CNTL2__NP_DMA_DROPPED__SHIFT 0x12
+#define IOHC_FEATURE_CNTL2__NMI_status_MASK 0x00000001L
+#define IOHC_FEATURE_CNTL2__SErr_status_MASK 0x00000002L
+#define IOHC_FEATURE_CNTL2__CrsStatus_MASK 0x00010000L
+#define IOHC_FEATURE_CNTL2__P_DMA_DROPPED_MASK 0x00020000L
+#define IOHC_FEATURE_CNTL2__NP_DMA_DROPPED_MASK 0x00040000L
+//NB_TOP_OF_DRAM3
+#define NB_TOP_OF_DRAM3__TOM3_LIMIT__SHIFT 0x0
+#define NB_TOP_OF_DRAM3__TOM3_ENABLE__SHIFT 0x1f
+#define NB_TOP_OF_DRAM3__TOM3_LIMIT_MASK 0x3FFFFFFFL
+#define NB_TOP_OF_DRAM3__TOM3_ENABLE_MASK 0x80000000L
+//CAM_CONTROL
+#define CAM_CONTROL__CAM_En__SHIFT 0x0
+#define CAM_CONTROL__Op__SHIFT 0x1
+#define CAM_CONTROL__AccessType__SHIFT 0x2
+#define CAM_CONTROL__DataMatchEn__SHIFT 0x3
+#define CAM_CONTROL__VC__SHIFT 0x4
+#define CAM_CONTROL__CrossTrigger__SHIFT 0x8
+#define CAM_CONTROL__CAM_En_MASK 0x00000001L
+#define CAM_CONTROL__Op_MASK 0x00000002L
+#define CAM_CONTROL__AccessType_MASK 0x00000004L
+#define CAM_CONTROL__DataMatchEn_MASK 0x00000008L
+#define CAM_CONTROL__VC_MASK 0x00000070L
+#define CAM_CONTROL__CrossTrigger_MASK 0x0000FF00L
+//CAM_TARGET_INDEX_ADDR_BOTTOM
+#define CAM_TARGET_INDEX_ADDR_BOTTOM__IndexAddrBottom__SHIFT 0x0
+#define CAM_TARGET_INDEX_ADDR_BOTTOM__IndexAddrBottom_MASK 0xFFFFFFFFL
+//CAM_TARGET_INDEX_ADDR_TOP
+#define CAM_TARGET_INDEX_ADDR_TOP__IndexAddrTop__SHIFT 0x0
+#define CAM_TARGET_INDEX_ADDR_TOP__IndexAddrTop_MASK 0xFFFFFFFFL
+//CAM_TARGET_INDEX_DATA
+#define CAM_TARGET_INDEX_DATA__IndexData__SHIFT 0x0
+#define CAM_TARGET_INDEX_DATA__IndexData_MASK 0xFFFFFFFFL
+//CAM_TARGET_INDEX_DATA_MASK
+#define CAM_TARGET_INDEX_DATA_MASK__IndexDataMask__SHIFT 0x0
+#define CAM_TARGET_INDEX_DATA_MASK__IndexDataMask_MASK 0xFFFFFFFFL
+//CAM_TARGET_DATA_ADDR_BOTTOM
+#define CAM_TARGET_DATA_ADDR_BOTTOM__DataAddrBottom__SHIFT 0x0
+#define CAM_TARGET_DATA_ADDR_BOTTOM__DataAddrBottom_MASK 0xFFFFFFFFL
+//CAM_TARGET_DATA_ADDR_TOP
+#define CAM_TARGET_DATA_ADDR_TOP__DataAddrTop__SHIFT 0x0
+#define CAM_TARGET_DATA_ADDR_TOP__DataAddrTop_MASK 0xFFFFFFFFL
+//CAM_TARGET_DATA
+#define CAM_TARGET_DATA__Data__SHIFT 0x0
+#define CAM_TARGET_DATA__Data_MASK 0xFFFFFFFFL
+//CAM_TARGET_DATA_MASK
+#define CAM_TARGET_DATA_MASK__DataMask__SHIFT 0x0
+#define CAM_TARGET_DATA_MASK__DataMask_MASK 0xFFFFFFFFL
+//P_DMA_DROPPED_LOG_LOWER
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_0__SHIFT 0x0
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_1__SHIFT 0x1
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_2__SHIFT 0x2
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_3__SHIFT 0x3
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_4__SHIFT 0x4
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_5__SHIFT 0x5
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_6__SHIFT 0x6
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_7__SHIFT 0x7
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_8__SHIFT 0x8
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_9__SHIFT 0x9
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_10__SHIFT 0xa
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_11__SHIFT 0xb
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_12__SHIFT 0xc
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_13__SHIFT 0xd
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_14__SHIFT 0xe
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_15__SHIFT 0xf
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_16__SHIFT 0x10
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_17__SHIFT 0x11
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_18__SHIFT 0x12
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_19__SHIFT 0x13
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_20__SHIFT 0x14
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_21__SHIFT 0x15
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_22__SHIFT 0x16
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_23__SHIFT 0x17
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_24__SHIFT 0x18
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_25__SHIFT 0x19
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_26__SHIFT 0x1a
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_27__SHIFT 0x1b
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_28__SHIFT 0x1c
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_29__SHIFT 0x1d
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_30__SHIFT 0x1e
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_31__SHIFT 0x1f
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_0_MASK 0x00000001L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_1_MASK 0x00000002L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_2_MASK 0x00000004L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_3_MASK 0x00000008L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_4_MASK 0x00000010L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_5_MASK 0x00000020L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_6_MASK 0x00000040L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_7_MASK 0x00000080L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_8_MASK 0x00000100L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_9_MASK 0x00000200L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_10_MASK 0x00000400L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_11_MASK 0x00000800L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_12_MASK 0x00001000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_13_MASK 0x00002000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_14_MASK 0x00004000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_15_MASK 0x00008000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_16_MASK 0x00010000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_17_MASK 0x00020000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_18_MASK 0x00040000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_19_MASK 0x00080000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_20_MASK 0x00100000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_21_MASK 0x00200000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_22_MASK 0x00400000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_23_MASK 0x00800000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_24_MASK 0x01000000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_25_MASK 0x02000000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_26_MASK 0x04000000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_27_MASK 0x08000000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_28_MASK 0x10000000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_29_MASK 0x20000000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_30_MASK 0x40000000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_31_MASK 0x80000000L
+//P_DMA_DROPPED_LOG_UPPER
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_0__SHIFT 0x0
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_1__SHIFT 0x1
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_2__SHIFT 0x2
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_3__SHIFT 0x3
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_4__SHIFT 0x4
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_5__SHIFT 0x5
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_6__SHIFT 0x6
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_7__SHIFT 0x7
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_8__SHIFT 0x8
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_9__SHIFT 0x9
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_10__SHIFT 0xa
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_11__SHIFT 0xb
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_12__SHIFT 0xc
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_13__SHIFT 0xd
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_14__SHIFT 0xe
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_15__SHIFT 0xf
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_16__SHIFT 0x10
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_17__SHIFT 0x11
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_18__SHIFT 0x12
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_19__SHIFT 0x13
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_20__SHIFT 0x14
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_21__SHIFT 0x15
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_22__SHIFT 0x16
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_23__SHIFT 0x17
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_24__SHIFT 0x18
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_25__SHIFT 0x19
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_26__SHIFT 0x1a
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_27__SHIFT 0x1b
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_28__SHIFT 0x1c
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_29__SHIFT 0x1d
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_30__SHIFT 0x1e
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_31__SHIFT 0x1f
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_0_MASK 0x00000001L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_1_MASK 0x00000002L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_2_MASK 0x00000004L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_3_MASK 0x00000008L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_4_MASK 0x00000010L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_5_MASK 0x00000020L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_6_MASK 0x00000040L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_7_MASK 0x00000080L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_8_MASK 0x00000100L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_9_MASK 0x00000200L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_10_MASK 0x00000400L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_11_MASK 0x00000800L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_12_MASK 0x00001000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_13_MASK 0x00002000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_14_MASK 0x00004000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_15_MASK 0x00008000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_16_MASK 0x00010000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_17_MASK 0x00020000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_18_MASK 0x00040000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_19_MASK 0x00080000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_20_MASK 0x00100000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_21_MASK 0x00200000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_22_MASK 0x00400000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_23_MASK 0x00800000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_24_MASK 0x01000000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_25_MASK 0x02000000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_26_MASK 0x04000000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_27_MASK 0x08000000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_28_MASK 0x10000000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_29_MASK 0x20000000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_30_MASK 0x40000000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_31_MASK 0x80000000L
+//NP_DMA_DROPPED_LOG_LOWER
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_0__SHIFT 0x0
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_1__SHIFT 0x1
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_2__SHIFT 0x2
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_3__SHIFT 0x3
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_4__SHIFT 0x4
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_5__SHIFT 0x5
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_6__SHIFT 0x6
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_7__SHIFT 0x7
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_8__SHIFT 0x8
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_9__SHIFT 0x9
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_10__SHIFT 0xa
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_11__SHIFT 0xb
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_12__SHIFT 0xc
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_13__SHIFT 0xd
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_14__SHIFT 0xe
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_15__SHIFT 0xf
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_16__SHIFT 0x10
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_17__SHIFT 0x11
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_18__SHIFT 0x12
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_19__SHIFT 0x13
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_20__SHIFT 0x14
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_21__SHIFT 0x15
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_22__SHIFT 0x16
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_23__SHIFT 0x17
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_24__SHIFT 0x18
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_25__SHIFT 0x19
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_26__SHIFT 0x1a
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_27__SHIFT 0x1b
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_28__SHIFT 0x1c
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_29__SHIFT 0x1d
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_30__SHIFT 0x1e
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_31__SHIFT 0x1f
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_0_MASK 0x00000001L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_1_MASK 0x00000002L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_2_MASK 0x00000004L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_3_MASK 0x00000008L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_4_MASK 0x00000010L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_5_MASK 0x00000020L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_6_MASK 0x00000040L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_7_MASK 0x00000080L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_8_MASK 0x00000100L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_9_MASK 0x00000200L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_10_MASK 0x00000400L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_11_MASK 0x00000800L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_12_MASK 0x00001000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_13_MASK 0x00002000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_14_MASK 0x00004000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_15_MASK 0x00008000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_16_MASK 0x00010000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_17_MASK 0x00020000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_18_MASK 0x00040000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_19_MASK 0x00080000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_20_MASK 0x00100000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_21_MASK 0x00200000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_22_MASK 0x00400000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_23_MASK 0x00800000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_24_MASK 0x01000000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_25_MASK 0x02000000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_26_MASK 0x04000000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_27_MASK 0x08000000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_28_MASK 0x10000000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_29_MASK 0x20000000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_30_MASK 0x40000000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_31_MASK 0x80000000L
+//NP_DMA_DROPPED_LOG_UPPER
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_0__SHIFT 0x0
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_1__SHIFT 0x1
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_2__SHIFT 0x2
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_3__SHIFT 0x3
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_4__SHIFT 0x4
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_5__SHIFT 0x5
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_6__SHIFT 0x6
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_7__SHIFT 0x7
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_8__SHIFT 0x8
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_9__SHIFT 0x9
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_10__SHIFT 0xa
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_11__SHIFT 0xb
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_12__SHIFT 0xc
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_13__SHIFT 0xd
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_14__SHIFT 0xe
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_15__SHIFT 0xf
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_16__SHIFT 0x10
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_17__SHIFT 0x11
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_18__SHIFT 0x12
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_19__SHIFT 0x13
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_20__SHIFT 0x14
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_21__SHIFT 0x15
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_22__SHIFT 0x16
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_23__SHIFT 0x17
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_24__SHIFT 0x18
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_25__SHIFT 0x19
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_26__SHIFT 0x1a
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_27__SHIFT 0x1b
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_28__SHIFT 0x1c
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_29__SHIFT 0x1d
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_30__SHIFT 0x1e
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_31__SHIFT 0x1f
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_0_MASK 0x00000001L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_1_MASK 0x00000002L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_2_MASK 0x00000004L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_3_MASK 0x00000008L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_4_MASK 0x00000010L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_5_MASK 0x00000020L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_6_MASK 0x00000040L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_7_MASK 0x00000080L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_8_MASK 0x00000100L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_9_MASK 0x00000200L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_10_MASK 0x00000400L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_11_MASK 0x00000800L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_12_MASK 0x00001000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_13_MASK 0x00002000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_14_MASK 0x00004000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_15_MASK 0x00008000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_16_MASK 0x00010000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_17_MASK 0x00020000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_18_MASK 0x00040000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_19_MASK 0x00080000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_20_MASK 0x00100000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_21_MASK 0x00200000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_22_MASK 0x00400000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_23_MASK 0x00800000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_24_MASK 0x01000000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_25_MASK 0x02000000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_26_MASK 0x04000000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_27_MASK 0x08000000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_28_MASK 0x10000000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_29_MASK 0x20000000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_30_MASK 0x40000000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_31_MASK 0x80000000L
+//PCIE_VDM_NODE0_CTRL4
+#define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_BASE__SHIFT 0x0
+#define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_LIMIT__SHIFT 0x8
+#define PCIE_VDM_NODE0_CTRL4__NODE0_PRESENT__SHIFT 0x1f
+#define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_BASE_MASK 0x000000FFL
+#define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_LIMIT_MASK 0x0000FF00L
+#define PCIE_VDM_NODE0_CTRL4__NODE0_PRESENT_MASK 0x80000000L
+//PCIE_VDM_CNTL2
+#define PCIE_VDM_CNTL2__VdmP2pMode__SHIFT 0x0
+#define PCIE_VDM_CNTL2__MCTPT2SMUEn__SHIFT 0x4
+#define PCIE_VDM_CNTL2__AMDVDM2SMUEn__SHIFT 0x5
+#define PCIE_VDM_CNTL2__OtherVDM2SMUEn__SHIFT 0x6
+#define PCIE_VDM_CNTL2__MCTPMasterValid__SHIFT 0xf
+#define PCIE_VDM_CNTL2__MCTPMasterID__SHIFT 0x10
+#define PCIE_VDM_CNTL2__VdmP2pMode_MASK 0x00000003L
+#define PCIE_VDM_CNTL2__MCTPT2SMUEn_MASK 0x00000010L
+#define PCIE_VDM_CNTL2__AMDVDM2SMUEn_MASK 0x00000020L
+#define PCIE_VDM_CNTL2__OtherVDM2SMUEn_MASK 0x00000040L
+#define PCIE_VDM_CNTL2__MCTPMasterValid_MASK 0x00008000L
+#define PCIE_VDM_CNTL2__MCTPMasterID_MASK 0xFFFF0000L
+//PCIE_VDM_CNTL3
+#define PCIE_VDM_CNTL3__APMTPMasterValid__SHIFT 0xf
+#define PCIE_VDM_CNTL3__APMTPMasterID__SHIFT 0x10
+#define PCIE_VDM_CNTL3__APMTPMasterValid_MASK 0x00008000L
+#define PCIE_VDM_CNTL3__APMTPMasterID_MASK 0xFFFF0000L
+//STALL_CONTROL_XBARPORT0_0
+#define STALL_CONTROL_XBARPORT0_0__StallVC0ReqEn__SHIFT 0x0
+#define STALL_CONTROL_XBARPORT0_0__StallVC1ReqEn__SHIFT 0x4
+#define STALL_CONTROL_XBARPORT0_0__StallVC2ReqEn__SHIFT 0x8
+#define STALL_CONTROL_XBARPORT0_0__StallVC3ReqEn__SHIFT 0xc
+#define STALL_CONTROL_XBARPORT0_0__StallVC4ReqEn__SHIFT 0x10
+#define STALL_CONTROL_XBARPORT0_0__StallVC7ReqEn__SHIFT 0x1c
+#define STALL_CONTROL_XBARPORT0_0__StallVC0ReqEn_MASK 0x00000003L
+#define STALL_CONTROL_XBARPORT0_0__StallVC1ReqEn_MASK 0x00000030L
+#define STALL_CONTROL_XBARPORT0_0__StallVC2ReqEn_MASK 0x00000300L
+#define STALL_CONTROL_XBARPORT0_0__StallVC3ReqEn_MASK 0x00003000L
+#define STALL_CONTROL_XBARPORT0_0__StallVC4ReqEn_MASK 0x00030000L
+#define STALL_CONTROL_XBARPORT0_0__StallVC7ReqEn_MASK 0x30000000L
+//STALL_CONTROL_XBARPORT0_1
+#define STALL_CONTROL_XBARPORT0_1__StallVC0RspEn__SHIFT 0x0
+#define STALL_CONTROL_XBARPORT0_1__StallVC1RspEn__SHIFT 0x4
+#define STALL_CONTROL_XBARPORT0_1__StallVC2RspEn__SHIFT 0x8
+#define STALL_CONTROL_XBARPORT0_1__StallVC3RspEn__SHIFT 0xc
+#define STALL_CONTROL_XBARPORT0_1__StallVC4RspEn__SHIFT 0x10
+#define STALL_CONTROL_XBARPORT0_1__StallVC7RspEn__SHIFT 0x1c
+#define STALL_CONTROL_XBARPORT0_1__StallVC0RspEn_MASK 0x00000003L
+#define STALL_CONTROL_XBARPORT0_1__StallVC1RspEn_MASK 0x00000030L
+#define STALL_CONTROL_XBARPORT0_1__StallVC2RspEn_MASK 0x00000300L
+#define STALL_CONTROL_XBARPORT0_1__StallVC3RspEn_MASK 0x00003000L
+#define STALL_CONTROL_XBARPORT0_1__StallVC4RspEn_MASK 0x00030000L
+#define STALL_CONTROL_XBARPORT0_1__StallVC7RspEn_MASK 0x30000000L
+//STALL_CONTROL_XBARPORT1_0
+#define STALL_CONTROL_XBARPORT1_0__StallVC0ReqEn__SHIFT 0x0
+#define STALL_CONTROL_XBARPORT1_0__StallVC1ReqEn__SHIFT 0x4
+#define STALL_CONTROL_XBARPORT1_0__StallVC2ReqEn__SHIFT 0x8
+#define STALL_CONTROL_XBARPORT1_0__StallVC3ReqEn__SHIFT 0xc
+#define STALL_CONTROL_XBARPORT1_0__StallVC4ReqEn__SHIFT 0x10
+#define STALL_CONTROL_XBARPORT1_0__StallVC7ReqEn__SHIFT 0x1c
+#define STALL_CONTROL_XBARPORT1_0__StallVC0ReqEn_MASK 0x00000003L
+#define STALL_CONTROL_XBARPORT1_0__StallVC1ReqEn_MASK 0x00000030L
+#define STALL_CONTROL_XBARPORT1_0__StallVC2ReqEn_MASK 0x00000300L
+#define STALL_CONTROL_XBARPORT1_0__StallVC3ReqEn_MASK 0x00003000L
+#define STALL_CONTROL_XBARPORT1_0__StallVC4ReqEn_MASK 0x00030000L
+#define STALL_CONTROL_XBARPORT1_0__StallVC7ReqEn_MASK 0x30000000L
+//STALL_CONTROL_XBARPORT1_1
+#define STALL_CONTROL_XBARPORT1_1__StallVC0RspEn__SHIFT 0x0
+#define STALL_CONTROL_XBARPORT1_1__StallVC1RspEn__SHIFT 0x4
+#define STALL_CONTROL_XBARPORT1_1__StallVC2RspEn__SHIFT 0x8
+#define STALL_CONTROL_XBARPORT1_1__StallVC3RspEn__SHIFT 0xc
+#define STALL_CONTROL_XBARPORT1_1__StallVC4RspEn__SHIFT 0x10
+#define STALL_CONTROL_XBARPORT1_1__StallVC7RspEn__SHIFT 0x1c
+#define STALL_CONTROL_XBARPORT1_1__StallVC0RspEn_MASK 0x00000003L
+#define STALL_CONTROL_XBARPORT1_1__StallVC1RspEn_MASK 0x00000030L
+#define STALL_CONTROL_XBARPORT1_1__StallVC2RspEn_MASK 0x00000300L
+#define STALL_CONTROL_XBARPORT1_1__StallVC3RspEn_MASK 0x00003000L
+#define STALL_CONTROL_XBARPORT1_1__StallVC4RspEn_MASK 0x00030000L
+#define STALL_CONTROL_XBARPORT1_1__StallVC7RspEn_MASK 0x30000000L
+//STALL_CONTROL_XBARPORT2_0
+#define STALL_CONTROL_XBARPORT2_0__StallVC0ReqEn__SHIFT 0x0
+#define STALL_CONTROL_XBARPORT2_0__StallVC1ReqEn__SHIFT 0x4
+#define STALL_CONTROL_XBARPORT2_0__StallVC2ReqEn__SHIFT 0x8
+#define STALL_CONTROL_XBARPORT2_0__StallVC3ReqEn__SHIFT 0xc
+#define STALL_CONTROL_XBARPORT2_0__StallVC4ReqEn__SHIFT 0x10
+#define STALL_CONTROL_XBARPORT2_0__StallVC7ReqEn__SHIFT 0x1c
+#define STALL_CONTROL_XBARPORT2_0__StallVC0ReqEn_MASK 0x00000003L
+#define STALL_CONTROL_XBARPORT2_0__StallVC1ReqEn_MASK 0x00000030L
+#define STALL_CONTROL_XBARPORT2_0__StallVC2ReqEn_MASK 0x00000300L
+#define STALL_CONTROL_XBARPORT2_0__StallVC3ReqEn_MASK 0x00003000L
+#define STALL_CONTROL_XBARPORT2_0__StallVC4ReqEn_MASK 0x00030000L
+#define STALL_CONTROL_XBARPORT2_0__StallVC7ReqEn_MASK 0x30000000L
+//STALL_CONTROL_XBARPORT2_1
+#define STALL_CONTROL_XBARPORT2_1__StallVC0RspEn__SHIFT 0x0
+#define STALL_CONTROL_XBARPORT2_1__StallVC1RspEn__SHIFT 0x4
+#define STALL_CONTROL_XBARPORT2_1__StallVC2RspEn__SHIFT 0x8
+#define STALL_CONTROL_XBARPORT2_1__StallVC3RspEn__SHIFT 0xc
+#define STALL_CONTROL_XBARPORT2_1__StallVC4RspEn__SHIFT 0x10
+#define STALL_CONTROL_XBARPORT2_1__StallVC7RspEn__SHIFT 0x1c
+#define STALL_CONTROL_XBARPORT2_1__StallVC0RspEn_MASK 0x00000003L
+#define STALL_CONTROL_XBARPORT2_1__StallVC1RspEn_MASK 0x00000030L
+#define STALL_CONTROL_XBARPORT2_1__StallVC2RspEn_MASK 0x00000300L
+#define STALL_CONTROL_XBARPORT2_1__StallVC3RspEn_MASK 0x00003000L
+#define STALL_CONTROL_XBARPORT2_1__StallVC4RspEn_MASK 0x00030000L
+#define STALL_CONTROL_XBARPORT2_1__StallVC7RspEn_MASK 0x30000000L
+//STALL_CONTROL_XBARPORT3_0
+#define STALL_CONTROL_XBARPORT3_0__StallVC0ReqEn__SHIFT 0x0
+#define STALL_CONTROL_XBARPORT3_0__StallVC1ReqEn__SHIFT 0x4
+#define STALL_CONTROL_XBARPORT3_0__StallVC2ReqEn__SHIFT 0x8
+#define STALL_CONTROL_XBARPORT3_0__StallVC3ReqEn__SHIFT 0xc
+#define STALL_CONTROL_XBARPORT3_0__StallVC4ReqEn__SHIFT 0x10
+#define STALL_CONTROL_XBARPORT3_0__StallVC7ReqEn__SHIFT 0x1c
+#define STALL_CONTROL_XBARPORT3_0__StallVC0ReqEn_MASK 0x00000003L
+#define STALL_CONTROL_XBARPORT3_0__StallVC1ReqEn_MASK 0x00000030L
+#define STALL_CONTROL_XBARPORT3_0__StallVC2ReqEn_MASK 0x00000300L
+#define STALL_CONTROL_XBARPORT3_0__StallVC3ReqEn_MASK 0x00003000L
+#define STALL_CONTROL_XBARPORT3_0__StallVC4ReqEn_MASK 0x00030000L
+#define STALL_CONTROL_XBARPORT3_0__StallVC7ReqEn_MASK 0x30000000L
+//STALL_CONTROL_XBARPORT3_1
+#define STALL_CONTROL_XBARPORT3_1__StallVC0RspEn__SHIFT 0x0
+#define STALL_CONTROL_XBARPORT3_1__StallVC1RspEn__SHIFT 0x4
+#define STALL_CONTROL_XBARPORT3_1__StallVC2RspEn__SHIFT 0x8
+#define STALL_CONTROL_XBARPORT3_1__StallVC3RspEn__SHIFT 0xc
+#define STALL_CONTROL_XBARPORT3_1__StallVC4RspEn__SHIFT 0x10
+#define STALL_CONTROL_XBARPORT3_1__StallVC7RspEn__SHIFT 0x1c
+#define STALL_CONTROL_XBARPORT3_1__StallVC0RspEn_MASK 0x00000003L
+#define STALL_CONTROL_XBARPORT3_1__StallVC1RspEn_MASK 0x00000030L
+#define STALL_CONTROL_XBARPORT3_1__StallVC2RspEn_MASK 0x00000300L
+#define STALL_CONTROL_XBARPORT3_1__StallVC3RspEn_MASK 0x00003000L
+#define STALL_CONTROL_XBARPORT3_1__StallVC4RspEn_MASK 0x00030000L
+#define STALL_CONTROL_XBARPORT3_1__StallVC7RspEn_MASK 0x30000000L
+//STALL_CONTROL_XBARPORT4_0
+#define STALL_CONTROL_XBARPORT4_0__StallVC0ReqEn__SHIFT 0x0
+#define STALL_CONTROL_XBARPORT4_0__StallVC1ReqEn__SHIFT 0x4
+#define STALL_CONTROL_XBARPORT4_0__StallVC2ReqEn__SHIFT 0x8
+#define STALL_CONTROL_XBARPORT4_0__StallVC3ReqEn__SHIFT 0xc
+#define STALL_CONTROL_XBARPORT4_0__StallVC4ReqEn__SHIFT 0x10
+#define STALL_CONTROL_XBARPORT4_0__StallVC7ReqEn__SHIFT 0x1c
+#define STALL_CONTROL_XBARPORT4_0__StallVC0ReqEn_MASK 0x00000003L
+#define STALL_CONTROL_XBARPORT4_0__StallVC1ReqEn_MASK 0x00000030L
+#define STALL_CONTROL_XBARPORT4_0__StallVC2ReqEn_MASK 0x00000300L
+#define STALL_CONTROL_XBARPORT4_0__StallVC3ReqEn_MASK 0x00003000L
+#define STALL_CONTROL_XBARPORT4_0__StallVC4ReqEn_MASK 0x00030000L
+#define STALL_CONTROL_XBARPORT4_0__StallVC7ReqEn_MASK 0x30000000L
+//STALL_CONTROL_XBARPORT4_1
+#define STALL_CONTROL_XBARPORT4_1__StallVC0RspEn__SHIFT 0x0
+#define STALL_CONTROL_XBARPORT4_1__StallVC1RspEn__SHIFT 0x4
+#define STALL_CONTROL_XBARPORT4_1__StallVC2RspEn__SHIFT 0x8
+#define STALL_CONTROL_XBARPORT4_1__StallVC3RspEn__SHIFT 0xc
+#define STALL_CONTROL_XBARPORT4_1__StallVC4RspEn__SHIFT 0x10
+#define STALL_CONTROL_XBARPORT4_1__StallVC7RspEn__SHIFT 0x1c
+#define STALL_CONTROL_XBARPORT4_1__StallVC0RspEn_MASK 0x00000003L
+#define STALL_CONTROL_XBARPORT4_1__StallVC1RspEn_MASK 0x00000030L
+#define STALL_CONTROL_XBARPORT4_1__StallVC2RspEn_MASK 0x00000300L
+#define STALL_CONTROL_XBARPORT4_1__StallVC3RspEn_MASK 0x00003000L
+#define STALL_CONTROL_XBARPORT4_1__StallVC4RspEn_MASK 0x00030000L
+#define STALL_CONTROL_XBARPORT4_1__StallVC7RspEn_MASK 0x30000000L
+//NB_DRAM3_BASE
+#define NB_DRAM3_BASE__DRAM3_BASE__SHIFT 0x0
+#define NB_DRAM3_BASE__DRAM3_BASE_MASK 0x3FFFFFFFL
+//PSP_BASE_ADDR_LO
+#define PSP_BASE_ADDR_LO__PSP_MMIO_EN__SHIFT 0x0
+#define PSP_BASE_ADDR_LO__PSP_MMIO_LOCK__SHIFT 0x8
+#define PSP_BASE_ADDR_LO__PSP_BASE_ADDR_LO__SHIFT 0x14
+#define PSP_BASE_ADDR_LO__PSP_MMIO_EN_MASK 0x00000001L
+#define PSP_BASE_ADDR_LO__PSP_MMIO_LOCK_MASK 0x00000100L
+#define PSP_BASE_ADDR_LO__PSP_BASE_ADDR_LO_MASK 0xFFF00000L
+//PSP_BASE_ADDR_HI
+#define PSP_BASE_ADDR_HI__PSP_BASE_ADDR_HI__SHIFT 0x0
+#define PSP_BASE_ADDR_HI__PSP_BASE_ADDR_HI_MASK 0x0000FFFFL
+//SMU_BASE_ADDR_LO
+#define SMU_BASE_ADDR_LO__SMU_MMIO_EN__SHIFT 0x0
+#define SMU_BASE_ADDR_LO__SMU_MMIO_LOCK__SHIFT 0x1
+#define SMU_BASE_ADDR_LO__SMU_BASE_ADDR_LO__SHIFT 0x14
+#define SMU_BASE_ADDR_LO__SMU_MMIO_EN_MASK 0x00000001L
+#define SMU_BASE_ADDR_LO__SMU_MMIO_LOCK_MASK 0x00000002L
+#define SMU_BASE_ADDR_LO__SMU_BASE_ADDR_LO_MASK 0xFFF00000L
+//SMU_BASE_ADDR_HI
+#define SMU_BASE_ADDR_HI__SMU_BASE_ADDR_HI__SHIFT 0x0
+#define SMU_BASE_ADDR_HI__SMU_BASE_ADDR_HI_MASK 0x0000FFFFL
+//IOAPIC_BASE_ADDR_LO
+#define IOAPIC_BASE_ADDR_LO__IOAPIC_MMIO_EN__SHIFT 0x0
+#define IOAPIC_BASE_ADDR_LO__IOAPIC_MMIO_LOCK__SHIFT 0x1
+#define IOAPIC_BASE_ADDR_LO__IOAPIC_BASE_ADDR_LO__SHIFT 0x8
+#define IOAPIC_BASE_ADDR_LO__IOAPIC_MMIO_EN_MASK 0x00000001L
+#define IOAPIC_BASE_ADDR_LO__IOAPIC_MMIO_LOCK_MASK 0x00000002L
+#define IOAPIC_BASE_ADDR_LO__IOAPIC_BASE_ADDR_LO_MASK 0xFFFFFF00L
+//IOAPIC_BASE_ADDR_HI
+#define IOAPIC_BASE_ADDR_HI__IOAPIC_BASE_ADDR_HI__SHIFT 0x0
+#define IOAPIC_BASE_ADDR_HI__IOAPIC_BASE_ADDR_HI_MASK 0x0000FFFFL
+//FASTREG_BASE_ADDR_LO
+#define FASTREG_BASE_ADDR_LO__FASTREG_MMIO_EN__SHIFT 0x0
+#define FASTREG_BASE_ADDR_LO__FASTREG_MMIO_LOCK__SHIFT 0x1
+#define FASTREG_BASE_ADDR_LO__FASTREG_BASE_ADDR_LO__SHIFT 0x14
+#define FASTREG_BASE_ADDR_LO__FASTREG_MMIO_EN_MASK 0x00000001L
+#define FASTREG_BASE_ADDR_LO__FASTREG_MMIO_LOCK_MASK 0x00000002L
+#define FASTREG_BASE_ADDR_LO__FASTREG_BASE_ADDR_LO_MASK 0xFFF00000L
+//FASTREG_BASE_ADDR_HI
+#define FASTREG_BASE_ADDR_HI__FASTREG_BASE_ADDR_HI__SHIFT 0x0
+#define FASTREG_BASE_ADDR_HI__FASTREG_BASE_ADDR_HI_MASK 0x0000FFFFL
+//FASTREGCNTL_BASE_ADDR_LO
+#define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_MMIO_EN__SHIFT 0x0
+#define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_MMIO_LOCK__SHIFT 0x1
+#define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_BASE_ADDR_LO__SHIFT 0xc
+#define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_MMIO_EN_MASK 0x00000001L
+#define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_MMIO_LOCK_MASK 0x00000002L
+#define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_BASE_ADDR_LO_MASK 0xFFFFF000L
+//FASTREGCNTL_BASE_ADDR_HI
+#define FASTREGCNTL_BASE_ADDR_HI__FASTREGCNTL_BASE_ADDR_HI__SHIFT 0x0
+#define FASTREGCNTL_BASE_ADDR_HI__FASTREGCNTL_BASE_ADDR_HI_MASK 0x0000FFFFL
+//SMMU_BASE_ADDR_LO
+#define SMMU_BASE_ADDR_LO__SMMU_MMIO_EN__SHIFT 0x0
+#define SMMU_BASE_ADDR_LO__SMMU_MMIO_LOCK__SHIFT 0x1
+#define SMMU_BASE_ADDR_LO__SMMU_BASE_ADDR_LO__SHIFT 0x13
+#define SMMU_BASE_ADDR_LO__SMMU_MMIO_EN_MASK 0x00000001L
+#define SMMU_BASE_ADDR_LO__SMMU_MMIO_LOCK_MASK 0x00000002L
+#define SMMU_BASE_ADDR_LO__SMMU_BASE_ADDR_LO_MASK 0xFFF80000L
+//SMMU_BASE_ADDR_HI
+#define SMMU_BASE_ADDR_HI__SMMU_BASE_ADDR_HI__SHIFT 0x0
+#define SMMU_BASE_ADDR_HI__SMMU_BASE_ADDR_HI_MASK 0x0000FFFFL
+//IOHC_PGMST_CNTL
+#define IOHC_PGMST_CNTL__CFG_PG_HYSTERESIS__SHIFT 0x0
+#define IOHC_PGMST_CNTL__CFG_PG_EN__SHIFT 0x8
+#define IOHC_PGMST_CNTL__CFG_IDLENESS_COUNT_EN__SHIFT 0xa
+#define IOHC_PGMST_CNTL__CFG_FW_PG_EXIT_EN__SHIFT 0xe
+#define IOHC_PGMST_CNTL__CFG_PG_HYSTERESIS_MASK 0x000000FFL
+#define IOHC_PGMST_CNTL__CFG_PG_EN_MASK 0x00000100L
+#define IOHC_PGMST_CNTL__CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L
+#define IOHC_PGMST_CNTL__CFG_FW_PG_EXIT_EN_MASK 0x0000C000L
+//IOHC_SDP_PORT_CONTROL
+#define IOHC_SDP_PORT_CONTROL__Port_Disconnect_Hysteresis__SHIFT 0x0
+#define IOHC_SDP_PORT_CONTROL__SDF_Port_Disconnect_Real_Time_Hysteresis__SHIFT 0x6
+#define IOHC_SDP_PORT_CONTROL__DMAEnableEarlyClkReq__SHIFT 0xf
+#define IOHC_SDP_PORT_CONTROL__HostEnableEarlyClkReq__SHIFT 0x10
+#define IOHC_SDP_PORT_CONTROL__Port_Disconnect_Hysteresis_MASK 0x0000003FL
+#define IOHC_SDP_PORT_CONTROL__SDF_Port_Disconnect_Real_Time_Hysteresis_MASK 0x00000FC0L
+#define IOHC_SDP_PORT_CONTROL__DMAEnableEarlyClkReq_MASK 0x00008000L
+#define IOHC_SDP_PORT_CONTROL__HostEnableEarlyClkReq_MASK 0xFFFF0000L
+//IOHC_SDP_PARITY_CONTROL
+#define IOHC_SDP_PARITY_CONTROL__SDP_ParityDis__SHIFT 0x0
+#define IOHC_SDP_PARITY_CONTROL__SDP_ParityDis_MASK 0x00000001L
+//IOHC_PGSLV_CNTL
+#define IOHC_PGSLV_CNTL__CFG_IDLE_HYSTERESIS__SHIFT 0x0
+#define IOHC_PGSLV_CNTL__CFG_IDLE_HYSTERESIS_MASK 0x0000001FL
+//SCRATCH_4
+#define SCRATCH_4__SCRATCH_4__SHIFT 0x0
+#define SCRATCH_4__SCRATCH_4_MASK 0xFFFFFFFFL
+//SCRATCH_5
+#define SCRATCH_5__SCRATCH_5__SHIFT 0x0
+#define SCRATCH_5__SCRATCH_5_MASK 0xFFFFFFFFL
+//SMU_BLOCK_CPU
+#define SMU_BLOCK_CPU__SMUBlockCPU_Valid__SHIFT 0x0
+#define SMU_BLOCK_CPU__SMUBlockCPU_Valid_MASK 0x00000001L
+//SMU_BLOCK_CPU_STATUS
+#define SMU_BLOCK_CPU_STATUS__SMUBlockCPU_Status__SHIFT 0x0
+#define SMU_BLOCK_CPU_STATUS__SMUBlockCPU_Status_MASK 0x00000001L
+//TRAP_STATUS
+#define TRAP_STATUS__TrapReqValid__SHIFT 0x0
+#define TRAP_STATUS__TrapNumber__SHIFT 0x8
+#define TRAP_STATUS__TrapReqValid_MASK 0x00000001L
+#define TRAP_STATUS__TrapNumber_MASK 0x00000F00L
+//TRAP_REQUEST0
+#define TRAP_REQUEST0__TrapReqAddrLo__SHIFT 0x2
+#define TRAP_REQUEST0__TrapReqAddrLo_MASK 0xFFFFFFFCL
+//TRAP_REQUEST1
+#define TRAP_REQUEST1__TrapReqAddrHi__SHIFT 0x0
+#define TRAP_REQUEST1__TrapReqAddrHi_MASK 0xFFFFFFFFL
+//TRAP_REQUEST2
+#define TRAP_REQUEST2__TrapReqCmd__SHIFT 0x0
+#define TRAP_REQUEST2__TrapAttr__SHIFT 0x8
+#define TRAP_REQUEST2__TrapReqLen__SHIFT 0x10
+#define TRAP_REQUEST2__TrapReqCmd_MASK 0x0000003FL
+#define TRAP_REQUEST2__TrapAttr_MASK 0x0000FF00L
+#define TRAP_REQUEST2__TrapReqLen_MASK 0x003F0000L
+//TRAP_REQUEST3
+#define TRAP_REQUEST3__TrapReqVC__SHIFT 0x0
+#define TRAP_REQUEST3__TrapReqBlockLevel__SHIFT 0x4
+#define TRAP_REQUEST3__TrapReqChain__SHIFT 0x6
+#define TRAP_REQUEST3__TrapReqIO__SHIFT 0x7
+#define TRAP_REQUEST3__TrapReqPassPW__SHIFT 0x8
+#define TRAP_REQUEST3__TrapReqRspPassPW__SHIFT 0x9
+#define TRAP_REQUEST3__TrapReqUnitID__SHIFT 0x10
+#define TRAP_REQUEST3__TrapReqVC_MASK 0x00000007L
+#define TRAP_REQUEST3__TrapReqBlockLevel_MASK 0x00000030L
+#define TRAP_REQUEST3__TrapReqChain_MASK 0x00000040L
+#define TRAP_REQUEST3__TrapReqIO_MASK 0x00000080L
+#define TRAP_REQUEST3__TrapReqPassPW_MASK 0x00000100L
+#define TRAP_REQUEST3__TrapReqRspPassPW_MASK 0x00000200L
+#define TRAP_REQUEST3__TrapReqUnitID_MASK 0x003F0000L
+//TRAP_REQUEST4
+#define TRAP_REQUEST4__TrapReqSecLevel__SHIFT 0x0
+#define TRAP_REQUEST4__TrapReqSecLevel_MASK 0x00000007L
+//TRAP_REQUEST5
+#define TRAP_REQUEST5__TrapReqDataVC__SHIFT 0x0
+#define TRAP_REQUEST5__TrapReqDataErr__SHIFT 0x4
+#define TRAP_REQUEST5__TrapReqDataParity__SHIFT 0x8
+#define TRAP_REQUEST5__TrapReqDataVC_MASK 0x00000007L
+#define TRAP_REQUEST5__TrapReqDataErr_MASK 0x00000010L
+#define TRAP_REQUEST5__TrapReqDataParity_MASK 0x0000FF00L
+//TRAP_REQUEST_DATASTRB0
+#define TRAP_REQUEST_DATASTRB0__TrapReqDataBytEn0__SHIFT 0x0
+#define TRAP_REQUEST_DATASTRB0__TrapReqDataBytEn0_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATASTRB1
+#define TRAP_REQUEST_DATASTRB1__TrapReqDataBytEn1__SHIFT 0x0
+#define TRAP_REQUEST_DATASTRB1__TrapReqDataBytEn1_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATA0
+#define TRAP_REQUEST_DATA0__TrapReqData0__SHIFT 0x0
+#define TRAP_REQUEST_DATA0__TrapReqData0_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATA1
+#define TRAP_REQUEST_DATA1__TrapReqData1__SHIFT 0x0
+#define TRAP_REQUEST_DATA1__TrapReqData1_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATA2
+#define TRAP_REQUEST_DATA2__TrapReqData2__SHIFT 0x0
+#define TRAP_REQUEST_DATA2__TrapReqData2_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATA3
+#define TRAP_REQUEST_DATA3__TrapReqData3__SHIFT 0x0
+#define TRAP_REQUEST_DATA3__TrapReqData3_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATA4
+#define TRAP_REQUEST_DATA4__TrapReqData4__SHIFT 0x0
+#define TRAP_REQUEST_DATA4__TrapReqData4_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATA5
+#define TRAP_REQUEST_DATA5__TrapReqData5__SHIFT 0x0
+#define TRAP_REQUEST_DATA5__TrapReqData5_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATA6
+#define TRAP_REQUEST_DATA6__TrapReqData6__SHIFT 0x0
+#define TRAP_REQUEST_DATA6__TrapReqData6_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATA7
+#define TRAP_REQUEST_DATA7__TrapReqData7__SHIFT 0x0
+#define TRAP_REQUEST_DATA7__TrapReqData7_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATA8
+#define TRAP_REQUEST_DATA8__TrapReqData8__SHIFT 0x0
+#define TRAP_REQUEST_DATA8__TrapReqData8_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATA9
+#define TRAP_REQUEST_DATA9__TrapReqData9__SHIFT 0x0
+#define TRAP_REQUEST_DATA9__TrapReqData9_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATA10
+#define TRAP_REQUEST_DATA10__TrapReqData10__SHIFT 0x0
+#define TRAP_REQUEST_DATA10__TrapReqData10_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATA11
+#define TRAP_REQUEST_DATA11__TrapReqData11__SHIFT 0x0
+#define TRAP_REQUEST_DATA11__TrapReqData11_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATA12
+#define TRAP_REQUEST_DATA12__TrapReqData12__SHIFT 0x0
+#define TRAP_REQUEST_DATA12__TrapReqData12_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATA13
+#define TRAP_REQUEST_DATA13__TrapReqData13__SHIFT 0x0
+#define TRAP_REQUEST_DATA13__TrapReqData13_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATA14
+#define TRAP_REQUEST_DATA14__TrapReqData14__SHIFT 0x0
+#define TRAP_REQUEST_DATA14__TrapReqData14_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATA15
+#define TRAP_REQUEST_DATA15__TrapReqData15__SHIFT 0x0
+#define TRAP_REQUEST_DATA15__TrapReqData15_MASK 0xFFFFFFFFL
+//TRAP_RESPONSE_CONTROL
+#define TRAP_RESPONSE_CONTROL__TrapRspTrigger__SHIFT 0x0
+#define TRAP_RESPONSE_CONTROL__TrapRspTrigger_MASK 0x00000001L
+//TRAP_RESPONSE0
+#define TRAP_RESPONSE0__TrapRspPassPW__SHIFT 0x0
+#define TRAP_RESPONSE0__TrapRspStatus__SHIFT 0x4
+#define TRAP_RESPONSE0__TrapRspDataStatus__SHIFT 0x10
+#define TRAP_RESPONSE0__TrapRspPassPW_MASK 0x00000001L
+#define TRAP_RESPONSE0__TrapRspStatus_MASK 0x000000F0L
+#define TRAP_RESPONSE0__TrapRspDataStatus_MASK 0x000F0000L
+//TRAP_RESPONSE_DATA0
+#define TRAP_RESPONSE_DATA0__TrapRdRspData0__SHIFT 0x0
+#define TRAP_RESPONSE_DATA0__TrapRdRspData0_MASK 0xFFFFFFFFL
+//TRAP_RESPONSE_DATA1
+#define TRAP_RESPONSE_DATA1__TrapRdRspData1__SHIFT 0x0
+#define TRAP_RESPONSE_DATA1__TrapRdRspData1_MASK 0xFFFFFFFFL
+//TRAP_RESPONSE_DATA2
+#define TRAP_RESPONSE_DATA2__TrapRdRspData2__SHIFT 0x0
+#define TRAP_RESPONSE_DATA2__TrapRdRspData2_MASK 0xFFFFFFFFL
+//TRAP_RESPONSE_DATA3
+#define TRAP_RESPONSE_DATA3__TrapRdRspData3__SHIFT 0x0
+#define TRAP_RESPONSE_DATA3__TrapRdRspData3_MASK 0xFFFFFFFFL
+//TRAP_RESPONSE_DATA4
+#define TRAP_RESPONSE_DATA4__TrapRdRspData4__SHIFT 0x0
+#define TRAP_RESPONSE_DATA4__TrapRdRspData4_MASK 0xFFFFFFFFL
+//TRAP_RESPONSE_DATA5
+#define TRAP_RESPONSE_DATA5__TrapRdRspData5__SHIFT 0x0
+#define TRAP_RESPONSE_DATA5__TrapRdRspData5_MASK 0xFFFFFFFFL
+//TRAP_RESPONSE_DATA6
+#define TRAP_RESPONSE_DATA6__TrapRdRspData6__SHIFT 0x0
+#define TRAP_RESPONSE_DATA6__TrapRdRspData6_MASK 0xFFFFFFFFL
+//TRAP_RESPONSE_DATA7
+#define TRAP_RESPONSE_DATA7__TrapRdRspData7__SHIFT 0x0
+#define TRAP_RESPONSE_DATA7__TrapRdRspData7_MASK 0xFFFFFFFFL
+//TRAP_RESPONSE_DATA8
+#define TRAP_RESPONSE_DATA8__TrapRdRspData8__SHIFT 0x0
+#define TRAP_RESPONSE_DATA8__TrapRdRspData8_MASK 0xFFFFFFFFL
+//TRAP_RESPONSE_DATA9
+#define TRAP_RESPONSE_DATA9__TrapRdRspData9__SHIFT 0x0
+#define TRAP_RESPONSE_DATA9__TrapRdRspData9_MASK 0xFFFFFFFFL
+//TRAP_RESPONSE_DATA10
+#define TRAP_RESPONSE_DATA10__TrapRdRspData10__SHIFT 0x0
+#define TRAP_RESPONSE_DATA10__TrapRdRspData10_MASK 0xFFFFFFFFL
+//TRAP_RESPONSE_DATA11
+#define TRAP_RESPONSE_DATA11__TrapRdRspData11__SHIFT 0x0
+#define TRAP_RESPONSE_DATA11__TrapRdRspData11_MASK 0xFFFFFFFFL
+//TRAP_RESPONSE_DATA12
+#define TRAP_RESPONSE_DATA12__TrapRdRspData12__SHIFT 0x0
+#define TRAP_RESPONSE_DATA12__TrapRdRspData12_MASK 0xFFFFFFFFL
+//TRAP_RESPONSE_DATA13
+#define TRAP_RESPONSE_DATA13__TrapRdRspData13__SHIFT 0x0
+#define TRAP_RESPONSE_DATA13__TrapRdRspData13_MASK 0xFFFFFFFFL
+//TRAP_RESPONSE_DATA14
+#define TRAP_RESPONSE_DATA14__TrapRdRspData14__SHIFT 0x0
+#define TRAP_RESPONSE_DATA14__TrapRdRspData14_MASK 0xFFFFFFFFL
+//TRAP_RESPONSE_DATA15
+#define TRAP_RESPONSE_DATA15__TrapRdRspData15__SHIFT 0x0
+#define TRAP_RESPONSE_DATA15__TrapRdRspData15_MASK 0xFFFFFFFFL
+//TRAP0_CONTROL0
+#define TRAP0_CONTROL0__Trap0En__SHIFT 0x0
+#define TRAP0_CONTROL0__Trap0SMUIntr__SHIFT 0x3
+#define TRAP0_CONTROL0__Trap0CrossTrigger__SHIFT 0x18
+#define TRAP0_CONTROL0__Trap0En_MASK 0x00000001L
+#define TRAP0_CONTROL0__Trap0SMUIntr_MASK 0x00000008L
+#define TRAP0_CONTROL0__Trap0CrossTrigger_MASK 0xFF000000L
+//TRAP0_ADDRESS_LO
+#define TRAP0_ADDRESS_LO__Trap0AddrLo__SHIFT 0x2
+#define TRAP0_ADDRESS_LO__Trap0AddrLo_MASK 0xFFFFFFFCL
+//TRAP0_ADDRESS_HI
+#define TRAP0_ADDRESS_HI__Trap0AddrHi__SHIFT 0x0
+#define TRAP0_ADDRESS_HI__Trap0AddrHi_MASK 0x0000FFFFL
+//TRAP0_COMMAND
+#define TRAP0_COMMAND__Trap0Cmd0__SHIFT 0x0
+#define TRAP0_COMMAND__Trap0Cmd1__SHIFT 0x8
+#define TRAP0_COMMAND__Trap0Cmd0_MASK 0x0000003FL
+#define TRAP0_COMMAND__Trap0Cmd1_MASK 0x00003F00L
+//TRAP0_ADDRESS_LO_MASK
+#define TRAP0_ADDRESS_LO_MASK__Trap0AddrLoMask__SHIFT 0x2
+#define TRAP0_ADDRESS_LO_MASK__Trap0AddrLoMask_MASK 0xFFFFFFFCL
+//TRAP0_ADDRESS_HI_MASK
+#define TRAP0_ADDRESS_HI_MASK__Trap0AddrHiMask__SHIFT 0x0
+#define TRAP0_ADDRESS_HI_MASK__Trap0AddrHiMask_MASK 0x0000FFFFL
+//TRAP0_COMMAND_MASK
+#define TRAP0_COMMAND_MASK__Trap0Cmd0Mask__SHIFT 0x0
+#define TRAP0_COMMAND_MASK__Trap0Cmd1Mask__SHIFT 0x8
+#define TRAP0_COMMAND_MASK__Trap0Cmd0Mask_MASK 0x0000003FL
+#define TRAP0_COMMAND_MASK__Trap0Cmd1Mask_MASK 0x00003F00L
+//TRAP1_CONTROL0
+#define TRAP1_CONTROL0__Trap1En__SHIFT 0x0
+#define TRAP1_CONTROL0__Trap1SMUIntr__SHIFT 0x3
+#define TRAP1_CONTROL0__Trap1CrossTrigger__SHIFT 0x18
+#define TRAP1_CONTROL0__Trap1En_MASK 0x00000001L
+#define TRAP1_CONTROL0__Trap1SMUIntr_MASK 0x00000008L
+#define TRAP1_CONTROL0__Trap1CrossTrigger_MASK 0xFF000000L
+//TRAP1_ADDRESS_LO
+#define TRAP1_ADDRESS_LO__Trap1AddrLo__SHIFT 0x2
+#define TRAP1_ADDRESS_LO__Trap1AddrLo_MASK 0xFFFFFFFCL
+//TRAP1_ADDRESS_HI
+#define TRAP1_ADDRESS_HI__Trap1AddrHi__SHIFT 0x0
+#define TRAP1_ADDRESS_HI__Trap1AddrHi_MASK 0x0000FFFFL
+//TRAP1_COMMAND
+#define TRAP1_COMMAND__Trap1Cmd0__SHIFT 0x0
+#define TRAP1_COMMAND__Trap1Cmd1__SHIFT 0x8
+#define TRAP1_COMMAND__Trap1Cmd0_MASK 0x0000003FL
+#define TRAP1_COMMAND__Trap1Cmd1_MASK 0x00003F00L
+//TRAP1_ADDRESS_LO_MASK
+#define TRAP1_ADDRESS_LO_MASK__Trap1AddrLoMask__SHIFT 0x2
+#define TRAP1_ADDRESS_LO_MASK__Trap1AddrLoMask_MASK 0xFFFFFFFCL
+//TRAP1_ADDRESS_HI_MASK
+#define TRAP1_ADDRESS_HI_MASK__Trap1AddrHiMask__SHIFT 0x0
+#define TRAP1_ADDRESS_HI_MASK__Trap1AddrHiMask_MASK 0x0000FFFFL
+//TRAP1_COMMAND_MASK
+#define TRAP1_COMMAND_MASK__Trap1Cmd0Mask__SHIFT 0x0
+#define TRAP1_COMMAND_MASK__Trap1Cmd1Mask__SHIFT 0x8
+#define TRAP1_COMMAND_MASK__Trap1Cmd0Mask_MASK 0x0000003FL
+#define TRAP1_COMMAND_MASK__Trap1Cmd1Mask_MASK 0x00003F00L
+//TRAP2_CONTROL0
+#define TRAP2_CONTROL0__Trap2En__SHIFT 0x0
+#define TRAP2_CONTROL0__Trap2SMUIntr__SHIFT 0x3
+#define TRAP2_CONTROL0__Trap2CrossTrigger__SHIFT 0x18
+#define TRAP2_CONTROL0__Trap2En_MASK 0x00000001L
+#define TRAP2_CONTROL0__Trap2SMUIntr_MASK 0x00000008L
+#define TRAP2_CONTROL0__Trap2CrossTrigger_MASK 0xFF000000L
+//TRAP2_ADDRESS_LO
+#define TRAP2_ADDRESS_LO__Trap2AddrLo__SHIFT 0x2
+#define TRAP2_ADDRESS_LO__Trap2AddrLo_MASK 0xFFFFFFFCL
+//TRAP2_ADDRESS_HI
+#define TRAP2_ADDRESS_HI__Trap2AddrHi__SHIFT 0x0
+#define TRAP2_ADDRESS_HI__Trap2AddrHi_MASK 0x0000FFFFL
+//TRAP2_COMMAND
+#define TRAP2_COMMAND__Trap2Cmd0__SHIFT 0x0
+#define TRAP2_COMMAND__Trap2Cmd1__SHIFT 0x8
+#define TRAP2_COMMAND__Trap2Cmd0_MASK 0x0000003FL
+#define TRAP2_COMMAND__Trap2Cmd1_MASK 0x00003F00L
+//TRAP2_ADDRESS_LO_MASK
+#define TRAP2_ADDRESS_LO_MASK__Trap2AddrLoMask__SHIFT 0x2
+#define TRAP2_ADDRESS_LO_MASK__Trap2AddrLoMask_MASK 0xFFFFFFFCL
+//TRAP2_ADDRESS_HI_MASK
+#define TRAP2_ADDRESS_HI_MASK__Trap2AddrHiMask__SHIFT 0x0
+#define TRAP2_ADDRESS_HI_MASK__Trap2AddrHiMask_MASK 0x0000FFFFL
+//TRAP2_COMMAND_MASK
+#define TRAP2_COMMAND_MASK__Trap2Cmd0Mask__SHIFT 0x0
+#define TRAP2_COMMAND_MASK__Trap2Cmd1Mask__SHIFT 0x8
+#define TRAP2_COMMAND_MASK__Trap2Cmd0Mask_MASK 0x0000003FL
+#define TRAP2_COMMAND_MASK__Trap2Cmd1Mask_MASK 0x00003F00L
+//TRAP3_CONTROL0
+#define TRAP3_CONTROL0__Trap3En__SHIFT 0x0
+#define TRAP3_CONTROL0__Trap3SMUIntr__SHIFT 0x3
+#define TRAP3_CONTROL0__Trap3CrossTrigger__SHIFT 0x18
+#define TRAP3_CONTROL0__Trap3En_MASK 0x00000001L
+#define TRAP3_CONTROL0__Trap3SMUIntr_MASK 0x00000008L
+#define TRAP3_CONTROL0__Trap3CrossTrigger_MASK 0xFF000000L
+//TRAP3_ADDRESS_LO
+#define TRAP3_ADDRESS_LO__Trap3AddrLo__SHIFT 0x2
+#define TRAP3_ADDRESS_LO__Trap3AddrLo_MASK 0xFFFFFFFCL
+//TRAP3_ADDRESS_HI
+#define TRAP3_ADDRESS_HI__Trap3AddrHi__SHIFT 0x0
+#define TRAP3_ADDRESS_HI__Trap3AddrHi_MASK 0x0000FFFFL
+//TRAP3_COMMAND
+#define TRAP3_COMMAND__Trap3Cmd0__SHIFT 0x0
+#define TRAP3_COMMAND__Trap3Cmd1__SHIFT 0x8
+#define TRAP3_COMMAND__Trap3Cmd0_MASK 0x0000003FL
+#define TRAP3_COMMAND__Trap3Cmd1_MASK 0x00003F00L
+//TRAP3_ADDRESS_LO_MASK
+#define TRAP3_ADDRESS_LO_MASK__Trap3AddrLoMask__SHIFT 0x2
+#define TRAP3_ADDRESS_LO_MASK__Trap3AddrLoMask_MASK 0xFFFFFFFCL
+//TRAP3_ADDRESS_HI_MASK
+#define TRAP3_ADDRESS_HI_MASK__Trap3AddrHiMask__SHIFT 0x0
+#define TRAP3_ADDRESS_HI_MASK__Trap3AddrHiMask_MASK 0x0000FFFFL
+//TRAP3_COMMAND_MASK
+#define TRAP3_COMMAND_MASK__Trap3Cmd0Mask__SHIFT 0x0
+#define TRAP3_COMMAND_MASK__Trap3Cmd1Mask__SHIFT 0x8
+#define TRAP3_COMMAND_MASK__Trap3Cmd0Mask_MASK 0x0000003FL
+#define TRAP3_COMMAND_MASK__Trap3Cmd1Mask_MASK 0x00003F00L
+//TRAP4_CONTROL0
+#define TRAP4_CONTROL0__Trap4En__SHIFT 0x0
+#define TRAP4_CONTROL0__Trap4SMUIntr__SHIFT 0x3
+#define TRAP4_CONTROL0__Trap4CrossTrigger__SHIFT 0x18
+#define TRAP4_CONTROL0__Trap4En_MASK 0x00000001L
+#define TRAP4_CONTROL0__Trap4SMUIntr_MASK 0x00000008L
+#define TRAP4_CONTROL0__Trap4CrossTrigger_MASK 0xFF000000L
+//TRAP4_ADDRESS_LO
+#define TRAP4_ADDRESS_LO__Trap4AddrLo__SHIFT 0x2
+#define TRAP4_ADDRESS_LO__Trap4AddrLo_MASK 0xFFFFFFFCL
+//TRAP4_ADDRESS_HI
+#define TRAP4_ADDRESS_HI__Trap4AddrHi__SHIFT 0x0
+#define TRAP4_ADDRESS_HI__Trap4AddrHi_MASK 0x0000FFFFL
+//TRAP4_COMMAND
+#define TRAP4_COMMAND__Trap4Cmd0__SHIFT 0x0
+#define TRAP4_COMMAND__Trap4Cmd1__SHIFT 0x8
+#define TRAP4_COMMAND__Trap4Cmd0_MASK 0x0000003FL
+#define TRAP4_COMMAND__Trap4Cmd1_MASK 0x00003F00L
+//TRAP4_ADDRESS_LO_MASK
+#define TRAP4_ADDRESS_LO_MASK__Trap4AddrLoMask__SHIFT 0x2
+#define TRAP4_ADDRESS_LO_MASK__Trap4AddrLoMask_MASK 0xFFFFFFFCL
+//TRAP4_ADDRESS_HI_MASK
+#define TRAP4_ADDRESS_HI_MASK__Trap4AddrHiMask__SHIFT 0x0
+#define TRAP4_ADDRESS_HI_MASK__Trap4AddrHiMask_MASK 0x0000FFFFL
+//TRAP4_COMMAND_MASK
+#define TRAP4_COMMAND_MASK__Trap4Cmd0Mask__SHIFT 0x0
+#define TRAP4_COMMAND_MASK__Trap4Cmd1Mask__SHIFT 0x8
+#define TRAP4_COMMAND_MASK__Trap4Cmd0Mask_MASK 0x0000003FL
+#define TRAP4_COMMAND_MASK__Trap4Cmd1Mask_MASK 0x00003F00L
+//TRAP5_CONTROL0
+#define TRAP5_CONTROL0__Trap5En__SHIFT 0x0
+#define TRAP5_CONTROL0__Trap5SMUIntr__SHIFT 0x3
+#define TRAP5_CONTROL0__Trap5CrossTrigger__SHIFT 0x18
+#define TRAP5_CONTROL0__Trap5En_MASK 0x00000001L
+#define TRAP5_CONTROL0__Trap5SMUIntr_MASK 0x00000008L
+#define TRAP5_CONTROL0__Trap5CrossTrigger_MASK 0xFF000000L
+//TRAP5_ADDRESS_LO
+#define TRAP5_ADDRESS_LO__Trap5AddrLo__SHIFT 0x2
+#define TRAP5_ADDRESS_LO__Trap5AddrLo_MASK 0xFFFFFFFCL
+//TRAP5_ADDRESS_HI
+#define TRAP5_ADDRESS_HI__Trap5AddrHi__SHIFT 0x0
+#define TRAP5_ADDRESS_HI__Trap5AddrHi_MASK 0x0000FFFFL
+//TRAP5_COMMAND
+#define TRAP5_COMMAND__Trap5Cmd0__SHIFT 0x0
+#define TRAP5_COMMAND__Trap5Cmd1__SHIFT 0x8
+#define TRAP5_COMMAND__Trap5Cmd0_MASK 0x0000003FL
+#define TRAP5_COMMAND__Trap5Cmd1_MASK 0x00003F00L
+//TRAP5_ADDRESS_LO_MASK
+#define TRAP5_ADDRESS_LO_MASK__Trap5AddrLoMask__SHIFT 0x2
+#define TRAP5_ADDRESS_LO_MASK__Trap5AddrLoMask_MASK 0xFFFFFFFCL
+//TRAP5_ADDRESS_HI_MASK
+#define TRAP5_ADDRESS_HI_MASK__Trap5AddrHiMask__SHIFT 0x0
+#define TRAP5_ADDRESS_HI_MASK__Trap5AddrHiMask_MASK 0x0000FFFFL
+//TRAP5_COMMAND_MASK
+#define TRAP5_COMMAND_MASK__Trap5Cmd0Mask__SHIFT 0x0
+#define TRAP5_COMMAND_MASK__Trap5Cmd1Mask__SHIFT 0x8
+#define TRAP5_COMMAND_MASK__Trap5Cmd0Mask_MASK 0x0000003FL
+#define TRAP5_COMMAND_MASK__Trap5Cmd1Mask_MASK 0x00003F00L
+//TRAP6_CONTROL0
+#define TRAP6_CONTROL0__Trap6En__SHIFT 0x0
+#define TRAP6_CONTROL0__Trap6SMUIntr__SHIFT 0x3
+#define TRAP6_CONTROL0__Trap6CrossTrigger__SHIFT 0x18
+#define TRAP6_CONTROL0__Trap6En_MASK 0x00000001L
+#define TRAP6_CONTROL0__Trap6SMUIntr_MASK 0x00000008L
+#define TRAP6_CONTROL0__Trap6CrossTrigger_MASK 0xFF000000L
+//TRAP6_ADDRESS_LO
+#define TRAP6_ADDRESS_LO__Trap6AddrLo__SHIFT 0x2
+#define TRAP6_ADDRESS_LO__Trap6AddrLo_MASK 0xFFFFFFFCL
+//TRAP6_ADDRESS_HI
+#define TRAP6_ADDRESS_HI__Trap6AddrHi__SHIFT 0x0
+#define TRAP6_ADDRESS_HI__Trap6AddrHi_MASK 0x0000FFFFL
+//TRAP6_COMMAND
+#define TRAP6_COMMAND__Trap6Cmd0__SHIFT 0x0
+#define TRAP6_COMMAND__Trap6Cmd1__SHIFT 0x8
+#define TRAP6_COMMAND__Trap6Cmd0_MASK 0x0000003FL
+#define TRAP6_COMMAND__Trap6Cmd1_MASK 0x00003F00L
+//TRAP6_ADDRESS_LO_MASK
+#define TRAP6_ADDRESS_LO_MASK__Trap6AddrLoMask__SHIFT 0x2
+#define TRAP6_ADDRESS_LO_MASK__Trap6AddrLoMask_MASK 0xFFFFFFFCL
+//TRAP6_ADDRESS_HI_MASK
+#define TRAP6_ADDRESS_HI_MASK__Trap6AddrHiMask__SHIFT 0x0
+#define TRAP6_ADDRESS_HI_MASK__Trap6AddrHiMask_MASK 0x0000FFFFL
+//TRAP6_COMMAND_MASK
+#define TRAP6_COMMAND_MASK__Trap6Cmd0Mask__SHIFT 0x0
+#define TRAP6_COMMAND_MASK__Trap6Cmd1Mask__SHIFT 0x8
+#define TRAP6_COMMAND_MASK__Trap6Cmd0Mask_MASK 0x0000003FL
+#define TRAP6_COMMAND_MASK__Trap6Cmd1Mask_MASK 0x00003F00L
+//TRAP7_CONTROL0
+#define TRAP7_CONTROL0__Trap7En__SHIFT 0x0
+#define TRAP7_CONTROL0__Trap7SMUIntr__SHIFT 0x3
+#define TRAP7_CONTROL0__Trap7CrossTrigger__SHIFT 0x18
+#define TRAP7_CONTROL0__Trap7En_MASK 0x00000001L
+#define TRAP7_CONTROL0__Trap7SMUIntr_MASK 0x00000008L
+#define TRAP7_CONTROL0__Trap7CrossTrigger_MASK 0xFF000000L
+//TRAP7_ADDRESS_LO
+#define TRAP7_ADDRESS_LO__Trap7AddrLo__SHIFT 0x2
+#define TRAP7_ADDRESS_LO__Trap7AddrLo_MASK 0xFFFFFFFCL
+//TRAP7_ADDRESS_HI
+#define TRAP7_ADDRESS_HI__Trap7AddrHi__SHIFT 0x0
+#define TRAP7_ADDRESS_HI__Trap7AddrHi_MASK 0x0000FFFFL
+//TRAP7_COMMAND
+#define TRAP7_COMMAND__Trap7Cmd0__SHIFT 0x0
+#define TRAP7_COMMAND__Trap7Cmd1__SHIFT 0x8
+#define TRAP7_COMMAND__Trap7Cmd0_MASK 0x0000003FL
+#define TRAP7_COMMAND__Trap7Cmd1_MASK 0x00003F00L
+//TRAP7_ADDRESS_LO_MASK
+#define TRAP7_ADDRESS_LO_MASK__Trap7AddrLoMask__SHIFT 0x2
+#define TRAP7_ADDRESS_LO_MASK__Trap7AddrLoMask_MASK 0xFFFFFFFCL
+//TRAP7_ADDRESS_HI_MASK
+#define TRAP7_ADDRESS_HI_MASK__Trap7AddrHiMask__SHIFT 0x0
+#define TRAP7_ADDRESS_HI_MASK__Trap7AddrHiMask_MASK 0x0000FFFFL
+//TRAP7_COMMAND_MASK
+#define TRAP7_COMMAND_MASK__Trap7Cmd0Mask__SHIFT 0x0
+#define TRAP7_COMMAND_MASK__Trap7Cmd1Mask__SHIFT 0x8
+#define TRAP7_COMMAND_MASK__Trap7Cmd0Mask_MASK 0x0000003FL
+#define TRAP7_COMMAND_MASK__Trap7Cmd1Mask_MASK 0x00003F00L
+//TRAP8_CONTROL0
+#define TRAP8_CONTROL0__Trap8En__SHIFT 0x0
+#define TRAP8_CONTROL0__Trap8SMUIntr__SHIFT 0x3
+#define TRAP8_CONTROL0__Trap8CrossTrigger__SHIFT 0x18
+#define TRAP8_CONTROL0__Trap8En_MASK 0x00000001L
+#define TRAP8_CONTROL0__Trap8SMUIntr_MASK 0x00000008L
+#define TRAP8_CONTROL0__Trap8CrossTrigger_MASK 0xFF000000L
+//TRAP8_ADDRESS_LO
+#define TRAP8_ADDRESS_LO__Trap8AddrLo__SHIFT 0x2
+#define TRAP8_ADDRESS_LO__Trap8AddrLo_MASK 0xFFFFFFFCL
+//TRAP8_ADDRESS_HI
+#define TRAP8_ADDRESS_HI__Trap8AddrHi__SHIFT 0x0
+#define TRAP8_ADDRESS_HI__Trap8AddrHi_MASK 0x0000FFFFL
+//TRAP8_COMMAND
+#define TRAP8_COMMAND__Trap8Cmd0__SHIFT 0x0
+#define TRAP8_COMMAND__Trap8Cmd1__SHIFT 0x8
+#define TRAP8_COMMAND__Trap8Cmd0_MASK 0x0000003FL
+#define TRAP8_COMMAND__Trap8Cmd1_MASK 0x00003F00L
+//TRAP8_ADDRESS_LO_MASK
+#define TRAP8_ADDRESS_LO_MASK__Trap8AddrLoMask__SHIFT 0x2
+#define TRAP8_ADDRESS_LO_MASK__Trap8AddrLoMask_MASK 0xFFFFFFFCL
+//TRAP8_ADDRESS_HI_MASK
+#define TRAP8_ADDRESS_HI_MASK__Trap8AddrHiMask__SHIFT 0x0
+#define TRAP8_ADDRESS_HI_MASK__Trap8AddrHiMask_MASK 0x0000FFFFL
+//TRAP8_COMMAND_MASK
+#define TRAP8_COMMAND_MASK__Trap8Cmd0Mask__SHIFT 0x0
+#define TRAP8_COMMAND_MASK__Trap8Cmd1Mask__SHIFT 0x8
+#define TRAP8_COMMAND_MASK__Trap8Cmd0Mask_MASK 0x0000003FL
+#define TRAP8_COMMAND_MASK__Trap8Cmd1Mask_MASK 0x00003F00L
+//TRAP9_CONTROL0
+#define TRAP9_CONTROL0__Trap9En__SHIFT 0x0
+#define TRAP9_CONTROL0__Trap9SMUIntr__SHIFT 0x3
+#define TRAP9_CONTROL0__Trap9CrossTrigger__SHIFT 0x18
+#define TRAP9_CONTROL0__Trap9En_MASK 0x00000001L
+#define TRAP9_CONTROL0__Trap9SMUIntr_MASK 0x00000008L
+#define TRAP9_CONTROL0__Trap9CrossTrigger_MASK 0xFF000000L
+//TRAP9_ADDRESS_LO
+#define TRAP9_ADDRESS_LO__Trap9AddrLo__SHIFT 0x2
+#define TRAP9_ADDRESS_LO__Trap9AddrLo_MASK 0xFFFFFFFCL
+//TRAP9_ADDRESS_HI
+#define TRAP9_ADDRESS_HI__Trap9AddrHi__SHIFT 0x0
+#define TRAP9_ADDRESS_HI__Trap9AddrHi_MASK 0x0000FFFFL
+//TRAP9_COMMAND
+#define TRAP9_COMMAND__Trap9Cmd0__SHIFT 0x0
+#define TRAP9_COMMAND__Trap9Cmd1__SHIFT 0x8
+#define TRAP9_COMMAND__Trap9Cmd0_MASK 0x0000003FL
+#define TRAP9_COMMAND__Trap9Cmd1_MASK 0x00003F00L
+//TRAP9_ADDRESS_LO_MASK
+#define TRAP9_ADDRESS_LO_MASK__Trap9AddrLoMask__SHIFT 0x2
+#define TRAP9_ADDRESS_LO_MASK__Trap9AddrLoMask_MASK 0xFFFFFFFCL
+//TRAP9_ADDRESS_HI_MASK
+#define TRAP9_ADDRESS_HI_MASK__Trap9AddrHiMask__SHIFT 0x0
+#define TRAP9_ADDRESS_HI_MASK__Trap9AddrHiMask_MASK 0x0000FFFFL
+//TRAP9_COMMAND_MASK
+#define TRAP9_COMMAND_MASK__Trap9Cmd0Mask__SHIFT 0x0
+#define TRAP9_COMMAND_MASK__Trap9Cmd1Mask__SHIFT 0x8
+#define TRAP9_COMMAND_MASK__Trap9Cmd0Mask_MASK 0x0000003FL
+#define TRAP9_COMMAND_MASK__Trap9Cmd1Mask_MASK 0x00003F00L
+//TRAP10_CONTROL0
+#define TRAP10_CONTROL0__Trap10En__SHIFT 0x0
+#define TRAP10_CONTROL0__Trap10SMUIntr__SHIFT 0x3
+#define TRAP10_CONTROL0__Trap10CrossTrigger__SHIFT 0x18
+#define TRAP10_CONTROL0__Trap10En_MASK 0x00000001L
+#define TRAP10_CONTROL0__Trap10SMUIntr_MASK 0x00000008L
+#define TRAP10_CONTROL0__Trap10CrossTrigger_MASK 0xFF000000L
+//TRAP10_ADDRESS_LO
+#define TRAP10_ADDRESS_LO__Trap10AddrLo__SHIFT 0x2
+#define TRAP10_ADDRESS_LO__Trap10AddrLo_MASK 0xFFFFFFFCL
+//TRAP10_ADDRESS_HI
+#define TRAP10_ADDRESS_HI__Trap10AddrHi__SHIFT 0x0
+#define TRAP10_ADDRESS_HI__Trap10AddrHi_MASK 0x0000FFFFL
+//TRAP10_COMMAND
+#define TRAP10_COMMAND__Trap10Cmd0__SHIFT 0x0
+#define TRAP10_COMMAND__Trap10Cmd1__SHIFT 0x8
+#define TRAP10_COMMAND__Trap10Cmd0_MASK 0x0000003FL
+#define TRAP10_COMMAND__Trap10Cmd1_MASK 0x00003F00L
+//TRAP10_ADDRESS_LO_MASK
+#define TRAP10_ADDRESS_LO_MASK__Trap10AddrLoMask__SHIFT 0x2
+#define TRAP10_ADDRESS_LO_MASK__Trap10AddrLoMask_MASK 0xFFFFFFFCL
+//TRAP10_ADDRESS_HI_MASK
+#define TRAP10_ADDRESS_HI_MASK__Trap10AddrHiMask__SHIFT 0x0
+#define TRAP10_ADDRESS_HI_MASK__Trap10AddrHiMask_MASK 0x0000FFFFL
+//TRAP10_COMMAND_MASK
+#define TRAP10_COMMAND_MASK__Trap10Cmd0Mask__SHIFT 0x0
+#define TRAP10_COMMAND_MASK__Trap10Cmd1Mask__SHIFT 0x8
+#define TRAP10_COMMAND_MASK__Trap10Cmd0Mask_MASK 0x0000003FL
+#define TRAP10_COMMAND_MASK__Trap10Cmd1Mask_MASK 0x00003F00L
+//TRAP11_CONTROL0
+#define TRAP11_CONTROL0__Trap11En__SHIFT 0x0
+#define TRAP11_CONTROL0__Trap11SMUIntr__SHIFT 0x3
+#define TRAP11_CONTROL0__Trap11CrossTrigger__SHIFT 0x18
+#define TRAP11_CONTROL0__Trap11En_MASK 0x00000001L
+#define TRAP11_CONTROL0__Trap11SMUIntr_MASK 0x00000008L
+#define TRAP11_CONTROL0__Trap11CrossTrigger_MASK 0xFF000000L
+//TRAP11_ADDRESS_LO
+#define TRAP11_ADDRESS_LO__Trap11AddrLo__SHIFT 0x2
+#define TRAP11_ADDRESS_LO__Trap11AddrLo_MASK 0xFFFFFFFCL
+//TRAP11_ADDRESS_HI
+#define TRAP11_ADDRESS_HI__Trap11AddrHi__SHIFT 0x0
+#define TRAP11_ADDRESS_HI__Trap11AddrHi_MASK 0x0000FFFFL
+//TRAP11_COMMAND
+#define TRAP11_COMMAND__Trap11Cmd0__SHIFT 0x0
+#define TRAP11_COMMAND__Trap11Cmd1__SHIFT 0x8
+#define TRAP11_COMMAND__Trap11Cmd0_MASK 0x0000003FL
+#define TRAP11_COMMAND__Trap11Cmd1_MASK 0x00003F00L
+//TRAP11_ADDRESS_LO_MASK
+#define TRAP11_ADDRESS_LO_MASK__Trap11AddrLoMask__SHIFT 0x2
+#define TRAP11_ADDRESS_LO_MASK__Trap11AddrLoMask_MASK 0xFFFFFFFCL
+//TRAP11_ADDRESS_HI_MASK
+#define TRAP11_ADDRESS_HI_MASK__Trap11AddrHiMask__SHIFT 0x0
+#define TRAP11_ADDRESS_HI_MASK__Trap11AddrHiMask_MASK 0x0000FFFFL
+//TRAP11_COMMAND_MASK
+#define TRAP11_COMMAND_MASK__Trap11Cmd0Mask__SHIFT 0x0
+#define TRAP11_COMMAND_MASK__Trap11Cmd1Mask__SHIFT 0x8
+#define TRAP11_COMMAND_MASK__Trap11Cmd0Mask_MASK 0x0000003FL
+#define TRAP11_COMMAND_MASK__Trap11Cmd1Mask_MASK 0x00003F00L
+//TRAP12_CONTROL0
+#define TRAP12_CONTROL0__Trap12En__SHIFT 0x0
+#define TRAP12_CONTROL0__Trap12SMUIntr__SHIFT 0x3
+#define TRAP12_CONTROL0__Trap12CrossTrigger__SHIFT 0x18
+#define TRAP12_CONTROL0__Trap12En_MASK 0x00000001L
+#define TRAP12_CONTROL0__Trap12SMUIntr_MASK 0x00000008L
+#define TRAP12_CONTROL0__Trap12CrossTrigger_MASK 0xFF000000L
+//TRAP12_ADDRESS_LO
+#define TRAP12_ADDRESS_LO__Trap12AddrLo__SHIFT 0x2
+#define TRAP12_ADDRESS_LO__Trap12AddrLo_MASK 0xFFFFFFFCL
+//TRAP12_ADDRESS_HI
+#define TRAP12_ADDRESS_HI__Trap12AddrHi__SHIFT 0x0
+#define TRAP12_ADDRESS_HI__Trap12AddrHi_MASK 0x0000FFFFL
+//TRAP12_COMMAND
+#define TRAP12_COMMAND__Trap12Cmd0__SHIFT 0x0
+#define TRAP12_COMMAND__Trap12Cmd1__SHIFT 0x8
+#define TRAP12_COMMAND__Trap12Cmd0_MASK 0x0000003FL
+#define TRAP12_COMMAND__Trap12Cmd1_MASK 0x00003F00L
+//TRAP12_ADDRESS_LO_MASK
+#define TRAP12_ADDRESS_LO_MASK__Trap12AddrLoMask__SHIFT 0x2
+#define TRAP12_ADDRESS_LO_MASK__Trap12AddrLoMask_MASK 0xFFFFFFFCL
+//TRAP12_ADDRESS_HI_MASK
+#define TRAP12_ADDRESS_HI_MASK__Trap12AddrHiMask__SHIFT 0x0
+#define TRAP12_ADDRESS_HI_MASK__Trap12AddrHiMask_MASK 0x0000FFFFL
+//TRAP12_COMMAND_MASK
+#define TRAP12_COMMAND_MASK__Trap12Cmd0Mask__SHIFT 0x0
+#define TRAP12_COMMAND_MASK__Trap12Cmd1Mask__SHIFT 0x8
+#define TRAP12_COMMAND_MASK__Trap12Cmd0Mask_MASK 0x0000003FL
+#define TRAP12_COMMAND_MASK__Trap12Cmd1Mask_MASK 0x00003F00L
+//TRAP13_CONTROL0
+#define TRAP13_CONTROL0__Trap13En__SHIFT 0x0
+#define TRAP13_CONTROL0__Trap13SMUIntr__SHIFT 0x3
+#define TRAP13_CONTROL0__Trap13CrossTrigger__SHIFT 0x18
+#define TRAP13_CONTROL0__Trap13En_MASK 0x00000001L
+#define TRAP13_CONTROL0__Trap13SMUIntr_MASK 0x00000008L
+#define TRAP13_CONTROL0__Trap13CrossTrigger_MASK 0xFF000000L
+//TRAP13_ADDRESS_LO
+#define TRAP13_ADDRESS_LO__Trap13AddrLo__SHIFT 0x2
+#define TRAP13_ADDRESS_LO__Trap13AddrLo_MASK 0xFFFFFFFCL
+//TRAP13_ADDRESS_HI
+#define TRAP13_ADDRESS_HI__Trap13AddrHi__SHIFT 0x0
+#define TRAP13_ADDRESS_HI__Trap13AddrHi_MASK 0x0000FFFFL
+//TRAP13_COMMAND
+#define TRAP13_COMMAND__Trap13Cmd0__SHIFT 0x0
+#define TRAP13_COMMAND__Trap13Cmd1__SHIFT 0x8
+#define TRAP13_COMMAND__Trap13Cmd0_MASK 0x0000003FL
+#define TRAP13_COMMAND__Trap13Cmd1_MASK 0x00003F00L
+//TRAP13_ADDRESS_LO_MASK
+#define TRAP13_ADDRESS_LO_MASK__Trap13AddrLoMask__SHIFT 0x2
+#define TRAP13_ADDRESS_LO_MASK__Trap13AddrLoMask_MASK 0xFFFFFFFCL
+//TRAP13_ADDRESS_HI_MASK
+#define TRAP13_ADDRESS_HI_MASK__Trap13AddrHiMask__SHIFT 0x0
+#define TRAP13_ADDRESS_HI_MASK__Trap13AddrHiMask_MASK 0x0000FFFFL
+//TRAP13_COMMAND_MASK
+#define TRAP13_COMMAND_MASK__Trap13Cmd0Mask__SHIFT 0x0
+#define TRAP13_COMMAND_MASK__Trap13Cmd1Mask__SHIFT 0x8
+#define TRAP13_COMMAND_MASK__Trap13Cmd0Mask_MASK 0x0000003FL
+#define TRAP13_COMMAND_MASK__Trap13Cmd1Mask_MASK 0x00003F00L
+//TRAP14_CONTROL0
+#define TRAP14_CONTROL0__Trap14En__SHIFT 0x0
+#define TRAP14_CONTROL0__Trap14SMUIntr__SHIFT 0x3
+#define TRAP14_CONTROL0__Trap14CrossTrigger__SHIFT 0x18
+#define TRAP14_CONTROL0__Trap14En_MASK 0x00000001L
+#define TRAP14_CONTROL0__Trap14SMUIntr_MASK 0x00000008L
+#define TRAP14_CONTROL0__Trap14CrossTrigger_MASK 0xFF000000L
+//TRAP14_ADDRESS_LO
+#define TRAP14_ADDRESS_LO__Trap14AddrLo__SHIFT 0x2
+#define TRAP14_ADDRESS_LO__Trap14AddrLo_MASK 0xFFFFFFFCL
+//TRAP14_ADDRESS_HI
+#define TRAP14_ADDRESS_HI__Trap14AddrHi__SHIFT 0x0
+#define TRAP14_ADDRESS_HI__Trap14AddrHi_MASK 0x0000FFFFL
+//TRAP14_COMMAND
+#define TRAP14_COMMAND__Trap14Cmd0__SHIFT 0x0
+#define TRAP14_COMMAND__Trap14Cmd1__SHIFT 0x8
+#define TRAP14_COMMAND__Trap14Cmd0_MASK 0x0000003FL
+#define TRAP14_COMMAND__Trap14Cmd1_MASK 0x00003F00L
+//TRAP14_ADDRESS_LO_MASK
+#define TRAP14_ADDRESS_LO_MASK__Trap14AddrLoMask__SHIFT 0x2
+#define TRAP14_ADDRESS_LO_MASK__Trap14AddrLoMask_MASK 0xFFFFFFFCL
+//TRAP14_ADDRESS_HI_MASK
+#define TRAP14_ADDRESS_HI_MASK__Trap14AddrHiMask__SHIFT 0x0
+#define TRAP14_ADDRESS_HI_MASK__Trap14AddrHiMask_MASK 0x0000FFFFL
+//TRAP14_COMMAND_MASK
+#define TRAP14_COMMAND_MASK__Trap14Cmd0Mask__SHIFT 0x0
+#define TRAP14_COMMAND_MASK__Trap14Cmd1Mask__SHIFT 0x8
+#define TRAP14_COMMAND_MASK__Trap14Cmd0Mask_MASK 0x0000003FL
+#define TRAP14_COMMAND_MASK__Trap14Cmd1Mask_MASK 0x00003F00L
+//TRAP15_CONTROL0
+#define TRAP15_CONTROL0__Trap15En__SHIFT 0x0
+#define TRAP15_CONTROL0__Trap15SMUIntr__SHIFT 0x3
+#define TRAP15_CONTROL0__Trap15CrossTrigger__SHIFT 0x18
+#define TRAP15_CONTROL0__Trap15En_MASK 0x00000001L
+#define TRAP15_CONTROL0__Trap15SMUIntr_MASK 0x00000008L
+#define TRAP15_CONTROL0__Trap15CrossTrigger_MASK 0xFF000000L
+//TRAP15_ADDRESS_LO
+#define TRAP15_ADDRESS_LO__Trap15AddrLo__SHIFT 0x2
+#define TRAP15_ADDRESS_LO__Trap15AddrLo_MASK 0xFFFFFFFCL
+//TRAP15_ADDRESS_HI
+#define TRAP15_ADDRESS_HI__Trap15AddrHi__SHIFT 0x0
+#define TRAP15_ADDRESS_HI__Trap15AddrHi_MASK 0x0000FFFFL
+//TRAP15_COMMAND
+#define TRAP15_COMMAND__Trap15Cmd0__SHIFT 0x0
+#define TRAP15_COMMAND__Trap15Cmd1__SHIFT 0x8
+#define TRAP15_COMMAND__Trap15Cmd0_MASK 0x0000003FL
+#define TRAP15_COMMAND__Trap15Cmd1_MASK 0x00003F00L
+//TRAP15_ADDRESS_LO_MASK
+#define TRAP15_ADDRESS_LO_MASK__Trap15AddrLoMask__SHIFT 0x2
+#define TRAP15_ADDRESS_LO_MASK__Trap15AddrLoMask_MASK 0xFFFFFFFCL
+//TRAP15_ADDRESS_HI_MASK
+#define TRAP15_ADDRESS_HI_MASK__Trap15AddrHiMask__SHIFT 0x0
+#define TRAP15_ADDRESS_HI_MASK__Trap15AddrHiMask_MASK 0x0000FFFFL
+//TRAP15_COMMAND_MASK
+#define TRAP15_COMMAND_MASK__Trap15Cmd0Mask__SHIFT 0x0
+#define TRAP15_COMMAND_MASK__Trap15Cmd1Mask__SHIFT 0x8
+#define TRAP15_COMMAND_MASK__Trap15Cmd0Mask_MASK 0x0000003FL
+#define TRAP15_COMMAND_MASK__Trap15Cmd1Mask_MASK 0x00003F00L
+//IOHC_REQDECODE_OVERRIDE
+#define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client0__SHIFT 0x0
+#define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client1__SHIFT 0x4
+#define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client2__SHIFT 0x8
+#define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client3__SHIFT 0xc
+#define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client4__SHIFT 0x10
+#define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client5__SHIFT 0x14
+#define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client6__SHIFT 0x18
+#define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client7__SHIFT 0x1c
+#define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client0_MASK 0x0000000FL
+#define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client1_MASK 0x000000F0L
+#define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client2_MASK 0x00000F00L
+#define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client3_MASK 0x0000F000L
+#define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client4_MASK 0x000F0000L
+#define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client5_MASK 0x00F00000L
+#define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client6_MASK 0x0F000000L
+#define IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client7_MASK 0xF0000000L
+//IOHC_RSPDECODE_OVERRIDE
+#define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client0__SHIFT 0x0
+#define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client1__SHIFT 0x4
+#define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client2__SHIFT 0x8
+#define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client3__SHIFT 0xc
+#define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client4__SHIFT 0x10
+#define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client5__SHIFT 0x14
+#define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client6__SHIFT 0x18
+#define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client7__SHIFT 0x1c
+#define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client0_MASK 0x0000000FL
+#define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client1_MASK 0x000000F0L
+#define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client2_MASK 0x00000F00L
+#define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client3_MASK 0x0000F000L
+#define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client4_MASK 0x000F0000L
+#define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client5_MASK 0x00F00000L
+#define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client6_MASK 0x0F000000L
+#define IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client7_MASK 0xF0000000L
+//IOHC_RSPPASSPW_OVERRIDE
+#define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client0__SHIFT 0x0
+#define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client1__SHIFT 0x4
+#define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client2__SHIFT 0x8
+#define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client3__SHIFT 0xc
+#define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client4__SHIFT 0x10
+#define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client5__SHIFT 0x14
+#define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client6__SHIFT 0x18
+#define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client7__SHIFT 0x1c
+#define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client0_MASK 0x0000000FL
+#define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client1_MASK 0x000000F0L
+#define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client2_MASK 0x00000F00L
+#define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client3_MASK 0x0000F000L
+#define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client4_MASK 0x000F0000L
+#define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client5_MASK 0x00F00000L
+#define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client6_MASK 0x0F000000L
+#define IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client7_MASK 0xF0000000L
+//IOHC_USERBIT_BYPASS
+#define IOHC_USERBIT_BYPASS__Userbit_Bypass__SHIFT 0x0
+#define IOHC_USERBIT_BYPASS__Userbit_Bypass_MASK 0x00000001L
+//IOHC_SMN_MASTER_CNTL
+#define IOHC_SMN_MASTER_CNTL__SmnErrRspMap__SHIFT 0x0
+#define IOHC_SMN_MASTER_CNTL__SmnErrRspMap_MASK 0x00000001L
+//IOHC_SMN_MASTER_STATUS
+#define IOHC_SMN_MASTER_STATUS__SmnPoisonErrStatus__SHIFT 0x0
+#define IOHC_SMN_MASTER_STATUS__SmnPoisonErrStatus_MASK 0x00000001L
+//SB_COMMAND
+#define SB_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define SB_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define SB_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define SB_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define SB_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define SB_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+//SB_SUB_BUS_NUMBER_LATENCY
+#define SB_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define SB_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define SB_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define SB_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+//SB_IO_BASE_LIMIT
+#define SB_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define SB_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define SB_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define SB_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//SB_MEM_BASE_LIMIT
+#define SB_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define SB_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define SB_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define SB_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//SB_PREF_BASE_LIMIT
+#define SB_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define SB_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define SB_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define SB_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//SB_PREF_BASE_UPPER
+#define SB_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define SB_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//SB_PREF_LIMIT_UPPER
+#define SB_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define SB_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//SB_IO_BASE_LIMIT_HI
+#define SB_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define SB_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define SB_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define SB_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//SB_IRQ_BRIDGE_CNTL
+#define SB_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define SB_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define SB_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define SB_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define SB_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define SB_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+//SB_EXT_BRIDGE_CNTL
+#define SB_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define SB_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//SB_PMI_STATUS_CNTL
+#define SB_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define SB_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L
+//SB_SLOT_CAP
+#define SB_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define SB_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define SB_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define SB_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+//SB_ROOT_CNTL
+#define SB_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define SB_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//SB_DEVICE_CNTL2
+#define SB_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define SB_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+//IOHC_QOS_CONTROL
+#define IOHC_QOS_CONTROL__VC0QoSPriority__SHIFT 0x0
+#define IOHC_QOS_CONTROL__VC1QoSPriority__SHIFT 0x4
+#define IOHC_QOS_CONTROL__VC2QoSPriority__SHIFT 0x8
+#define IOHC_QOS_CONTROL__VC3QoSPriority__SHIFT 0xc
+#define IOHC_QOS_CONTROL__VC4QoSPriority__SHIFT 0x10
+#define IOHC_QOS_CONTROL__VC5QoSPriority__SHIFT 0x14
+#define IOHC_QOS_CONTROL__VC6QoSPriority__SHIFT 0x18
+#define IOHC_QOS_CONTROL__VC7QoSPriority__SHIFT 0x1c
+#define IOHC_QOS_CONTROL__VC0QoSPriority_MASK 0x0000000FL
+#define IOHC_QOS_CONTROL__VC1QoSPriority_MASK 0x000000F0L
+#define IOHC_QOS_CONTROL__VC2QoSPriority_MASK 0x00000F00L
+#define IOHC_QOS_CONTROL__VC3QoSPriority_MASK 0x0000F000L
+#define IOHC_QOS_CONTROL__VC4QoSPriority_MASK 0x000F0000L
+#define IOHC_QOS_CONTROL__VC5QoSPriority_MASK 0x00F00000L
+#define IOHC_QOS_CONTROL__VC6QoSPriority_MASK 0x0F000000L
+#define IOHC_QOS_CONTROL__VC7QoSPriority_MASK 0xF0000000L
+//USB_QoS_CNTL
+#define USB_QoS_CNTL__UnitID0__SHIFT 0x0
+#define USB_QoS_CNTL__UnitID0QoSPriority__SHIFT 0x8
+#define USB_QoS_CNTL__UnitID0Enable__SHIFT 0xc
+#define USB_QoS_CNTL__UnitID1__SHIFT 0x10
+#define USB_QoS_CNTL__UnitID1QoSPriority__SHIFT 0x18
+#define USB_QoS_CNTL__UnitID1Enable__SHIFT 0x1c
+#define USB_QoS_CNTL__UnitID0_MASK 0x0000007FL
+#define USB_QoS_CNTL__UnitID0QoSPriority_MASK 0x00000F00L
+#define USB_QoS_CNTL__UnitID0Enable_MASK 0x00001000L
+#define USB_QoS_CNTL__UnitID1_MASK 0x007F0000L
+#define USB_QoS_CNTL__UnitID1QoSPriority_MASK 0x0F000000L
+#define USB_QoS_CNTL__UnitID1Enable_MASK 0x10000000L
+//IOHC_SION_S0_Client0_Req_BurstTarget_Lower
+#define IOHC_SION_S0_Client0_Req_BurstTarget_Lower__IOHC_SION_S0_Client0_Req_BurstTarget_Lower__SHIFT 0x0
+#define IOHC_SION_S0_Client0_Req_BurstTarget_Lower__IOHC_SION_S0_Client0_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client0_Req_BurstTarget_Upper
+#define IOHC_SION_S0_Client0_Req_BurstTarget_Upper__IOHC_SION_S0_Client0_Req_BurstTarget_Upper__SHIFT 0x0
+#define IOHC_SION_S0_Client0_Req_BurstTarget_Upper__IOHC_SION_S0_Client0_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client0_Req_TimeSlot_Lower
+#define IOHC_SION_S0_Client0_Req_TimeSlot_Lower__IOHC_SION_S0_Client0_Req_TimeSlot_Lower__SHIFT 0x0
+#define IOHC_SION_S0_Client0_Req_TimeSlot_Lower__IOHC_SION_S0_Client0_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client0_Req_TimeSlot_Upper
+#define IOHC_SION_S0_Client0_Req_TimeSlot_Upper__IOHC_SION_S0_Client0_Req_TimeSlot_Upper__SHIFT 0x0
+#define IOHC_SION_S0_Client0_Req_TimeSlot_Upper__IOHC_SION_S0_Client0_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client0_RdRsp_BurstTarget_Lower
+#define IOHC_SION_S0_Client0_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client0_RdRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOHC_SION_S0_Client0_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client0_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client0_RdRsp_BurstTarget_Upper
+#define IOHC_SION_S0_Client0_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client0_RdRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOHC_SION_S0_Client0_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client0_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client0_RdRsp_TimeSlot_Lower
+#define IOHC_SION_S0_Client0_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client0_RdRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOHC_SION_S0_Client0_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client0_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client0_RdRsp_TimeSlot_Upper
+#define IOHC_SION_S0_Client0_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client0_RdRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOHC_SION_S0_Client0_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client0_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client0_WrRsp_BurstTarget_Lower
+#define IOHC_SION_S0_Client0_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client0_WrRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOHC_SION_S0_Client0_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client0_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client0_WrRsp_BurstTarget_Upper
+#define IOHC_SION_S0_Client0_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client0_WrRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOHC_SION_S0_Client0_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client0_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client0_WrRsp_TimeSlot_Lower
+#define IOHC_SION_S0_Client0_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client0_WrRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOHC_SION_S0_Client0_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client0_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client0_WrRsp_TimeSlot_Upper
+#define IOHC_SION_S0_Client0_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client0_WrRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOHC_SION_S0_Client0_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client0_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client0_Req_BurstTarget_Lower
+#define IOHC_SION_S1_Client0_Req_BurstTarget_Lower__IOHC_SION_S1_Client0_Req_BurstTarget_Lower__SHIFT 0x0
+#define IOHC_SION_S1_Client0_Req_BurstTarget_Lower__IOHC_SION_S1_Client0_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client0_Req_BurstTarget_Upper
+#define IOHC_SION_S1_Client0_Req_BurstTarget_Upper__IOHC_SION_S1_Client0_Req_BurstTarget_Upper__SHIFT 0x0
+#define IOHC_SION_S1_Client0_Req_BurstTarget_Upper__IOHC_SION_S1_Client0_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client0_Req_TimeSlot_Lower
+#define IOHC_SION_S1_Client0_Req_TimeSlot_Lower__IOHC_SION_S1_Client0_Req_TimeSlot_Lower__SHIFT 0x0
+#define IOHC_SION_S1_Client0_Req_TimeSlot_Lower__IOHC_SION_S1_Client0_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client0_Req_TimeSlot_Upper
+#define IOHC_SION_S1_Client0_Req_TimeSlot_Upper__IOHC_SION_S1_Client0_Req_TimeSlot_Upper__SHIFT 0x0
+#define IOHC_SION_S1_Client0_Req_TimeSlot_Upper__IOHC_SION_S1_Client0_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client0_RdRsp_BurstTarget_Lower
+#define IOHC_SION_S1_Client0_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client0_RdRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOHC_SION_S1_Client0_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client0_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client0_RdRsp_BurstTarget_Upper
+#define IOHC_SION_S1_Client0_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client0_RdRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOHC_SION_S1_Client0_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client0_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client0_RdRsp_TimeSlot_Lower
+#define IOHC_SION_S1_Client0_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client0_RdRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOHC_SION_S1_Client0_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client0_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client0_RdRsp_TimeSlot_Upper
+#define IOHC_SION_S1_Client0_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client0_RdRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOHC_SION_S1_Client0_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client0_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client0_WrRsp_BurstTarget_Lower
+#define IOHC_SION_S1_Client0_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client0_WrRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOHC_SION_S1_Client0_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client0_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client0_WrRsp_BurstTarget_Upper
+#define IOHC_SION_S1_Client0_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client0_WrRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOHC_SION_S1_Client0_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client0_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client0_WrRsp_TimeSlot_Lower
+#define IOHC_SION_S1_Client0_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client0_WrRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOHC_SION_S1_Client0_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client0_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client0_WrRsp_TimeSlot_Upper
+#define IOHC_SION_S1_Client0_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client0_WrRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOHC_SION_S1_Client0_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client0_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_Client0_ReqPoolCredit_Alloc_Lower
+#define IOHC_SION_Client0_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client0_ReqPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOHC_SION_Client0_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client0_ReqPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_Client0_ReqPoolCredit_Alloc_Upper
+#define IOHC_SION_Client0_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client0_ReqPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOHC_SION_Client0_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client0_ReqPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_Client0_DataPoolCredit_Alloc_Lower
+#define IOHC_SION_Client0_DataPoolCredit_Alloc_Lower__IOHC_SION_Client0_DataPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOHC_SION_Client0_DataPoolCredit_Alloc_Lower__IOHC_SION_Client0_DataPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_Client0_DataPoolCredit_Alloc_Upper
+#define IOHC_SION_Client0_DataPoolCredit_Alloc_Upper__IOHC_SION_Client0_DataPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOHC_SION_Client0_DataPoolCredit_Alloc_Upper__IOHC_SION_Client0_DataPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_Client0_RdRspPoolCredit_Alloc_Lower
+#define IOHC_SION_Client0_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client0_RdRspPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOHC_SION_Client0_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client0_RdRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_Client0_RdRspPoolCredit_Alloc_Upper
+#define IOHC_SION_Client0_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client0_RdRspPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOHC_SION_Client0_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client0_RdRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_Client0_WrRspPoolCredit_Alloc_Lower
+#define IOHC_SION_Client0_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client0_WrRspPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOHC_SION_Client0_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client0_WrRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_Client0_WrRspPoolCredit_Alloc_Upper
+#define IOHC_SION_Client0_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client0_WrRspPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOHC_SION_Client0_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client0_WrRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client1_Req_BurstTarget_Lower
+#define IOHC_SION_S0_Client1_Req_BurstTarget_Lower__IOHC_SION_S0_Client1_Req_BurstTarget_Lower__SHIFT 0x0
+#define IOHC_SION_S0_Client1_Req_BurstTarget_Lower__IOHC_SION_S0_Client1_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client1_Req_BurstTarget_Upper
+#define IOHC_SION_S0_Client1_Req_BurstTarget_Upper__IOHC_SION_S0_Client1_Req_BurstTarget_Upper__SHIFT 0x0
+#define IOHC_SION_S0_Client1_Req_BurstTarget_Upper__IOHC_SION_S0_Client1_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client1_Req_TimeSlot_Lower
+#define IOHC_SION_S0_Client1_Req_TimeSlot_Lower__IOHC_SION_S0_Client1_Req_TimeSlot_Lower__SHIFT 0x0
+#define IOHC_SION_S0_Client1_Req_TimeSlot_Lower__IOHC_SION_S0_Client1_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client1_Req_TimeSlot_Upper
+#define IOHC_SION_S0_Client1_Req_TimeSlot_Upper__IOHC_SION_S0_Client1_Req_TimeSlot_Upper__SHIFT 0x0
+#define IOHC_SION_S0_Client1_Req_TimeSlot_Upper__IOHC_SION_S0_Client1_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client1_RdRsp_BurstTarget_Lower
+#define IOHC_SION_S0_Client1_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client1_RdRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOHC_SION_S0_Client1_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client1_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client1_RdRsp_BurstTarget_Upper
+#define IOHC_SION_S0_Client1_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client1_RdRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOHC_SION_S0_Client1_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client1_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client1_RdRsp_TimeSlot_Lower
+#define IOHC_SION_S0_Client1_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client1_RdRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOHC_SION_S0_Client1_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client1_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client1_RdRsp_TimeSlot_Upper
+#define IOHC_SION_S0_Client1_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client1_RdRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOHC_SION_S0_Client1_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client1_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client1_WrRsp_BurstTarget_Lower
+#define IOHC_SION_S0_Client1_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client1_WrRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOHC_SION_S0_Client1_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client1_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client1_WrRsp_BurstTarget_Upper
+#define IOHC_SION_S0_Client1_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client1_WrRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOHC_SION_S0_Client1_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client1_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client1_WrRsp_TimeSlot_Lower
+#define IOHC_SION_S0_Client1_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client1_WrRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOHC_SION_S0_Client1_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client1_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client1_WrRsp_TimeSlot_Upper
+#define IOHC_SION_S0_Client1_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client1_WrRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOHC_SION_S0_Client1_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client1_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client1_Req_BurstTarget_Lower
+#define IOHC_SION_S1_Client1_Req_BurstTarget_Lower__IOHC_SION_S1_Client1_Req_BurstTarget_Lower__SHIFT 0x0
+#define IOHC_SION_S1_Client1_Req_BurstTarget_Lower__IOHC_SION_S1_Client1_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client1_Req_BurstTarget_Upper
+#define IOHC_SION_S1_Client1_Req_BurstTarget_Upper__IOHC_SION_S1_Client1_Req_BurstTarget_Upper__SHIFT 0x0
+#define IOHC_SION_S1_Client1_Req_BurstTarget_Upper__IOHC_SION_S1_Client1_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client1_Req_TimeSlot_Lower
+#define IOHC_SION_S1_Client1_Req_TimeSlot_Lower__IOHC_SION_S1_Client1_Req_TimeSlot_Lower__SHIFT 0x0
+#define IOHC_SION_S1_Client1_Req_TimeSlot_Lower__IOHC_SION_S1_Client1_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client1_Req_TimeSlot_Upper
+#define IOHC_SION_S1_Client1_Req_TimeSlot_Upper__IOHC_SION_S1_Client1_Req_TimeSlot_Upper__SHIFT 0x0
+#define IOHC_SION_S1_Client1_Req_TimeSlot_Upper__IOHC_SION_S1_Client1_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client1_RdRsp_BurstTarget_Lower
+#define IOHC_SION_S1_Client1_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client1_RdRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOHC_SION_S1_Client1_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client1_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client1_RdRsp_BurstTarget_Upper
+#define IOHC_SION_S1_Client1_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client1_RdRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOHC_SION_S1_Client1_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client1_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client1_RdRsp_TimeSlot_Lower
+#define IOHC_SION_S1_Client1_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client1_RdRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOHC_SION_S1_Client1_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client1_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client1_RdRsp_TimeSlot_Upper
+#define IOHC_SION_S1_Client1_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client1_RdRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOHC_SION_S1_Client1_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client1_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client1_WrRsp_BurstTarget_Lower
+#define IOHC_SION_S1_Client1_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client1_WrRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOHC_SION_S1_Client1_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client1_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client1_WrRsp_BurstTarget_Upper
+#define IOHC_SION_S1_Client1_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client1_WrRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOHC_SION_S1_Client1_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client1_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client1_WrRsp_TimeSlot_Lower
+#define IOHC_SION_S1_Client1_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client1_WrRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOHC_SION_S1_Client1_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client1_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client1_WrRsp_TimeSlot_Upper
+#define IOHC_SION_S1_Client1_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client1_WrRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOHC_SION_S1_Client1_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client1_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_Client1_ReqPoolCredit_Alloc_Lower
+#define IOHC_SION_Client1_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client1_ReqPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOHC_SION_Client1_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client1_ReqPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_Client1_ReqPoolCredit_Alloc_Upper
+#define IOHC_SION_Client1_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client1_ReqPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOHC_SION_Client1_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client1_ReqPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_Client1_DataPoolCredit_Alloc_Lower
+#define IOHC_SION_Client1_DataPoolCredit_Alloc_Lower__IOHC_SION_Client1_DataPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOHC_SION_Client1_DataPoolCredit_Alloc_Lower__IOHC_SION_Client1_DataPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_Client1_DataPoolCredit_Alloc_Upper
+#define IOHC_SION_Client1_DataPoolCredit_Alloc_Upper__IOHC_SION_Client1_DataPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOHC_SION_Client1_DataPoolCredit_Alloc_Upper__IOHC_SION_Client1_DataPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_Client1_RdRspPoolCredit_Alloc_Lower
+#define IOHC_SION_Client1_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client1_RdRspPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOHC_SION_Client1_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client1_RdRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_Client1_RdRspPoolCredit_Alloc_Upper
+#define IOHC_SION_Client1_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client1_RdRspPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOHC_SION_Client1_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client1_RdRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_Client1_WrRspPoolCredit_Alloc_Lower
+#define IOHC_SION_Client1_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client1_WrRspPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOHC_SION_Client1_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client1_WrRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_Client1_WrRspPoolCredit_Alloc_Upper
+#define IOHC_SION_Client1_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client1_WrRspPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOHC_SION_Client1_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client1_WrRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client2_Req_BurstTarget_Lower
+#define IOHC_SION_S0_Client2_Req_BurstTarget_Lower__IOHC_SION_S0_Client2_Req_BurstTarget_Lower__SHIFT 0x0
+#define IOHC_SION_S0_Client2_Req_BurstTarget_Lower__IOHC_SION_S0_Client2_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client2_Req_BurstTarget_Upper
+#define IOHC_SION_S0_Client2_Req_BurstTarget_Upper__IOHC_SION_S0_Client2_Req_BurstTarget_Upper__SHIFT 0x0
+#define IOHC_SION_S0_Client2_Req_BurstTarget_Upper__IOHC_SION_S0_Client2_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client2_Req_TimeSlot_Lower
+#define IOHC_SION_S0_Client2_Req_TimeSlot_Lower__IOHC_SION_S0_Client2_Req_TimeSlot_Lower__SHIFT 0x0
+#define IOHC_SION_S0_Client2_Req_TimeSlot_Lower__IOHC_SION_S0_Client2_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client2_Req_TimeSlot_Upper
+#define IOHC_SION_S0_Client2_Req_TimeSlot_Upper__IOHC_SION_S0_Client2_Req_TimeSlot_Upper__SHIFT 0x0
+#define IOHC_SION_S0_Client2_Req_TimeSlot_Upper__IOHC_SION_S0_Client2_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client2_RdRsp_BurstTarget_Lower
+#define IOHC_SION_S0_Client2_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client2_RdRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOHC_SION_S0_Client2_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client2_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client2_RdRsp_BurstTarget_Upper
+#define IOHC_SION_S0_Client2_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client2_RdRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOHC_SION_S0_Client2_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client2_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client2_RdRsp_TimeSlot_Lower
+#define IOHC_SION_S0_Client2_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client2_RdRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOHC_SION_S0_Client2_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client2_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client2_RdRsp_TimeSlot_Upper
+#define IOHC_SION_S0_Client2_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client2_RdRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOHC_SION_S0_Client2_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client2_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client2_WrRsp_BurstTarget_Lower
+#define IOHC_SION_S0_Client2_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client2_WrRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOHC_SION_S0_Client2_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client2_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client2_WrRsp_BurstTarget_Upper
+#define IOHC_SION_S0_Client2_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client2_WrRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOHC_SION_S0_Client2_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client2_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client2_WrRsp_TimeSlot_Lower
+#define IOHC_SION_S0_Client2_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client2_WrRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOHC_SION_S0_Client2_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client2_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client2_WrRsp_TimeSlot_Upper
+#define IOHC_SION_S0_Client2_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client2_WrRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOHC_SION_S0_Client2_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client2_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client2_Req_BurstTarget_Lower
+#define IOHC_SION_S1_Client2_Req_BurstTarget_Lower__IOHC_SION_S1_Client2_Req_BurstTarget_Lower__SHIFT 0x0
+#define IOHC_SION_S1_Client2_Req_BurstTarget_Lower__IOHC_SION_S1_Client2_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client2_Req_BurstTarget_Upper
+#define IOHC_SION_S1_Client2_Req_BurstTarget_Upper__IOHC_SION_S1_Client2_Req_BurstTarget_Upper__SHIFT 0x0
+#define IOHC_SION_S1_Client2_Req_BurstTarget_Upper__IOHC_SION_S1_Client2_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client2_Req_TimeSlot_Lower
+#define IOHC_SION_S1_Client2_Req_TimeSlot_Lower__IOHC_SION_S1_Client2_Req_TimeSlot_Lower__SHIFT 0x0
+#define IOHC_SION_S1_Client2_Req_TimeSlot_Lower__IOHC_SION_S1_Client2_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client2_Req_TimeSlot_Upper
+#define IOHC_SION_S1_Client2_Req_TimeSlot_Upper__IOHC_SION_S1_Client2_Req_TimeSlot_Upper__SHIFT 0x0
+#define IOHC_SION_S1_Client2_Req_TimeSlot_Upper__IOHC_SION_S1_Client2_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client2_RdRsp_BurstTarget_Lower
+#define IOHC_SION_S1_Client2_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client2_RdRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOHC_SION_S1_Client2_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client2_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client2_RdRsp_BurstTarget_Upper
+#define IOHC_SION_S1_Client2_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client2_RdRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOHC_SION_S1_Client2_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client2_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client2_RdRsp_TimeSlot_Lower
+#define IOHC_SION_S1_Client2_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client2_RdRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOHC_SION_S1_Client2_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client2_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client2_RdRsp_TimeSlot_Upper
+#define IOHC_SION_S1_Client2_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client2_RdRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOHC_SION_S1_Client2_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client2_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client2_WrRsp_BurstTarget_Lower
+#define IOHC_SION_S1_Client2_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client2_WrRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOHC_SION_S1_Client2_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client2_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client2_WrRsp_BurstTarget_Upper
+#define IOHC_SION_S1_Client2_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client2_WrRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOHC_SION_S1_Client2_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client2_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client2_WrRsp_TimeSlot_Lower
+#define IOHC_SION_S1_Client2_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client2_WrRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOHC_SION_S1_Client2_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client2_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client2_WrRsp_TimeSlot_Upper
+#define IOHC_SION_S1_Client2_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client2_WrRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOHC_SION_S1_Client2_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client2_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_Client2_ReqPoolCredit_Alloc_Lower
+#define IOHC_SION_Client2_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client2_ReqPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOHC_SION_Client2_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client2_ReqPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_Client2_ReqPoolCredit_Alloc_Upper
+#define IOHC_SION_Client2_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client2_ReqPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOHC_SION_Client2_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client2_ReqPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_Client2_DataPoolCredit_Alloc_Lower
+#define IOHC_SION_Client2_DataPoolCredit_Alloc_Lower__IOHC_SION_Client2_DataPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOHC_SION_Client2_DataPoolCredit_Alloc_Lower__IOHC_SION_Client2_DataPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_Client2_DataPoolCredit_Alloc_Upper
+#define IOHC_SION_Client2_DataPoolCredit_Alloc_Upper__IOHC_SION_Client2_DataPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOHC_SION_Client2_DataPoolCredit_Alloc_Upper__IOHC_SION_Client2_DataPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_Client2_RdRspPoolCredit_Alloc_Lower
+#define IOHC_SION_Client2_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client2_RdRspPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOHC_SION_Client2_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client2_RdRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_Client2_RdRspPoolCredit_Alloc_Upper
+#define IOHC_SION_Client2_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client2_RdRspPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOHC_SION_Client2_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client2_RdRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_Client2_WrRspPoolCredit_Alloc_Lower
+#define IOHC_SION_Client2_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client2_WrRspPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOHC_SION_Client2_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client2_WrRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_Client2_WrRspPoolCredit_Alloc_Upper
+#define IOHC_SION_Client2_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client2_WrRspPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOHC_SION_Client2_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client2_WrRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client3_Req_BurstTarget_Lower
+#define IOHC_SION_S0_Client3_Req_BurstTarget_Lower__IOHC_SION_S0_Client3_Req_BurstTarget_Lower__SHIFT 0x0
+#define IOHC_SION_S0_Client3_Req_BurstTarget_Lower__IOHC_SION_S0_Client3_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client3_Req_BurstTarget_Upper
+#define IOHC_SION_S0_Client3_Req_BurstTarget_Upper__IOHC_SION_S0_Client3_Req_BurstTarget_Upper__SHIFT 0x0
+#define IOHC_SION_S0_Client3_Req_BurstTarget_Upper__IOHC_SION_S0_Client3_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client3_Req_TimeSlot_Lower
+#define IOHC_SION_S0_Client3_Req_TimeSlot_Lower__IOHC_SION_S0_Client3_Req_TimeSlot_Lower__SHIFT 0x0
+#define IOHC_SION_S0_Client3_Req_TimeSlot_Lower__IOHC_SION_S0_Client3_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client3_Req_TimeSlot_Upper
+#define IOHC_SION_S0_Client3_Req_TimeSlot_Upper__IOHC_SION_S0_Client3_Req_TimeSlot_Upper__SHIFT 0x0
+#define IOHC_SION_S0_Client3_Req_TimeSlot_Upper__IOHC_SION_S0_Client3_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client3_RdRsp_BurstTarget_Lower
+#define IOHC_SION_S0_Client3_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client3_RdRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOHC_SION_S0_Client3_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client3_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client3_RdRsp_BurstTarget_Upper
+#define IOHC_SION_S0_Client3_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client3_RdRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOHC_SION_S0_Client3_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client3_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client3_RdRsp_TimeSlot_Lower
+#define IOHC_SION_S0_Client3_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client3_RdRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOHC_SION_S0_Client3_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client3_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client3_RdRsp_TimeSlot_Upper
+#define IOHC_SION_S0_Client3_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client3_RdRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOHC_SION_S0_Client3_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client3_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client3_WrRsp_BurstTarget_Lower
+#define IOHC_SION_S0_Client3_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client3_WrRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOHC_SION_S0_Client3_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client3_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client3_WrRsp_BurstTarget_Upper
+#define IOHC_SION_S0_Client3_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client3_WrRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOHC_SION_S0_Client3_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client3_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client3_WrRsp_TimeSlot_Lower
+#define IOHC_SION_S0_Client3_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client3_WrRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOHC_SION_S0_Client3_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client3_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client3_WrRsp_TimeSlot_Upper
+#define IOHC_SION_S0_Client3_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client3_WrRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOHC_SION_S0_Client3_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client3_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client3_Req_BurstTarget_Lower
+#define IOHC_SION_S1_Client3_Req_BurstTarget_Lower__IOHC_SION_S1_Client3_Req_BurstTarget_Lower__SHIFT 0x0
+#define IOHC_SION_S1_Client3_Req_BurstTarget_Lower__IOHC_SION_S1_Client3_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client3_Req_BurstTarget_Upper
+#define IOHC_SION_S1_Client3_Req_BurstTarget_Upper__IOHC_SION_S1_Client3_Req_BurstTarget_Upper__SHIFT 0x0
+#define IOHC_SION_S1_Client3_Req_BurstTarget_Upper__IOHC_SION_S1_Client3_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client3_Req_TimeSlot_Lower
+#define IOHC_SION_S1_Client3_Req_TimeSlot_Lower__IOHC_SION_S1_Client3_Req_TimeSlot_Lower__SHIFT 0x0
+#define IOHC_SION_S1_Client3_Req_TimeSlot_Lower__IOHC_SION_S1_Client3_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client3_Req_TimeSlot_Upper
+#define IOHC_SION_S1_Client3_Req_TimeSlot_Upper__IOHC_SION_S1_Client3_Req_TimeSlot_Upper__SHIFT 0x0
+#define IOHC_SION_S1_Client3_Req_TimeSlot_Upper__IOHC_SION_S1_Client3_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client3_RdRsp_BurstTarget_Lower
+#define IOHC_SION_S1_Client3_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client3_RdRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOHC_SION_S1_Client3_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client3_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client3_RdRsp_BurstTarget_Upper
+#define IOHC_SION_S1_Client3_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client3_RdRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOHC_SION_S1_Client3_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client3_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client3_RdRsp_TimeSlot_Lower
+#define IOHC_SION_S1_Client3_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client3_RdRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOHC_SION_S1_Client3_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client3_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client3_RdRsp_TimeSlot_Upper
+#define IOHC_SION_S1_Client3_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client3_RdRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOHC_SION_S1_Client3_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client3_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client3_WrRsp_BurstTarget_Lower
+#define IOHC_SION_S1_Client3_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client3_WrRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOHC_SION_S1_Client3_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client3_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client3_WrRsp_BurstTarget_Upper
+#define IOHC_SION_S1_Client3_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client3_WrRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOHC_SION_S1_Client3_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client3_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client3_WrRsp_TimeSlot_Lower
+#define IOHC_SION_S1_Client3_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client3_WrRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOHC_SION_S1_Client3_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client3_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client3_WrRsp_TimeSlot_Upper
+#define IOHC_SION_S1_Client3_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client3_WrRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOHC_SION_S1_Client3_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client3_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_Client3_ReqPoolCredit_Alloc_Lower
+#define IOHC_SION_Client3_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client3_ReqPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOHC_SION_Client3_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client3_ReqPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_Client3_ReqPoolCredit_Alloc_Upper
+#define IOHC_SION_Client3_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client3_ReqPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOHC_SION_Client3_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client3_ReqPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_Client3_DataPoolCredit_Alloc_Lower
+#define IOHC_SION_Client3_DataPoolCredit_Alloc_Lower__IOHC_SION_Client3_DataPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOHC_SION_Client3_DataPoolCredit_Alloc_Lower__IOHC_SION_Client3_DataPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_Client3_DataPoolCredit_Alloc_Upper
+#define IOHC_SION_Client3_DataPoolCredit_Alloc_Upper__IOHC_SION_Client3_DataPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOHC_SION_Client3_DataPoolCredit_Alloc_Upper__IOHC_SION_Client3_DataPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_Client3_RdRspPoolCredit_Alloc_Lower
+#define IOHC_SION_Client3_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client3_RdRspPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOHC_SION_Client3_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client3_RdRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_Client3_RdRspPoolCredit_Alloc_Upper
+#define IOHC_SION_Client3_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client3_RdRspPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOHC_SION_Client3_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client3_RdRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_Client3_WrRspPoolCredit_Alloc_Lower
+#define IOHC_SION_Client3_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client3_WrRspPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOHC_SION_Client3_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client3_WrRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_Client3_WrRspPoolCredit_Alloc_Upper
+#define IOHC_SION_Client3_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client3_WrRspPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOHC_SION_Client3_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client3_WrRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client4_Req_BurstTarget_Lower
+#define IOHC_SION_S0_Client4_Req_BurstTarget_Lower__IOHC_SION_S0_Client4_Req_BurstTarget_Lower__SHIFT 0x0
+#define IOHC_SION_S0_Client4_Req_BurstTarget_Lower__IOHC_SION_S0_Client4_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client4_Req_BurstTarget_Upper
+#define IOHC_SION_S0_Client4_Req_BurstTarget_Upper__IOHC_SION_S0_Client4_Req_BurstTarget_Upper__SHIFT 0x0
+#define IOHC_SION_S0_Client4_Req_BurstTarget_Upper__IOHC_SION_S0_Client4_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client4_Req_TimeSlot_Lower
+#define IOHC_SION_S0_Client4_Req_TimeSlot_Lower__IOHC_SION_S0_Client4_Req_TimeSlot_Lower__SHIFT 0x0
+#define IOHC_SION_S0_Client4_Req_TimeSlot_Lower__IOHC_SION_S0_Client4_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client4_Req_TimeSlot_Upper
+#define IOHC_SION_S0_Client4_Req_TimeSlot_Upper__IOHC_SION_S0_Client4_Req_TimeSlot_Upper__SHIFT 0x0
+#define IOHC_SION_S0_Client4_Req_TimeSlot_Upper__IOHC_SION_S0_Client4_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client4_RdRsp_BurstTarget_Lower
+#define IOHC_SION_S0_Client4_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client4_RdRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOHC_SION_S0_Client4_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client4_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client4_RdRsp_BurstTarget_Upper
+#define IOHC_SION_S0_Client4_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client4_RdRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOHC_SION_S0_Client4_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client4_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client4_RdRsp_TimeSlot_Lower
+#define IOHC_SION_S0_Client4_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client4_RdRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOHC_SION_S0_Client4_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client4_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client4_RdRsp_TimeSlot_Upper
+#define IOHC_SION_S0_Client4_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client4_RdRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOHC_SION_S0_Client4_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client4_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client4_WrRsp_BurstTarget_Lower
+#define IOHC_SION_S0_Client4_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client4_WrRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOHC_SION_S0_Client4_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client4_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client4_WrRsp_BurstTarget_Upper
+#define IOHC_SION_S0_Client4_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client4_WrRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOHC_SION_S0_Client4_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client4_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client4_WrRsp_TimeSlot_Lower
+#define IOHC_SION_S0_Client4_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client4_WrRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOHC_SION_S0_Client4_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client4_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S0_Client4_WrRsp_TimeSlot_Upper
+#define IOHC_SION_S0_Client4_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client4_WrRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOHC_SION_S0_Client4_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client4_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client4_Req_BurstTarget_Lower
+#define IOHC_SION_S1_Client4_Req_BurstTarget_Lower__IOHC_SION_S1_Client4_Req_BurstTarget_Lower__SHIFT 0x0
+#define IOHC_SION_S1_Client4_Req_BurstTarget_Lower__IOHC_SION_S1_Client4_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client4_Req_BurstTarget_Upper
+#define IOHC_SION_S1_Client4_Req_BurstTarget_Upper__IOHC_SION_S1_Client4_Req_BurstTarget_Upper__SHIFT 0x0
+#define IOHC_SION_S1_Client4_Req_BurstTarget_Upper__IOHC_SION_S1_Client4_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client4_Req_TimeSlot_Lower
+#define IOHC_SION_S1_Client4_Req_TimeSlot_Lower__IOHC_SION_S1_Client4_Req_TimeSlot_Lower__SHIFT 0x0
+#define IOHC_SION_S1_Client4_Req_TimeSlot_Lower__IOHC_SION_S1_Client4_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client4_Req_TimeSlot_Upper
+#define IOHC_SION_S1_Client4_Req_TimeSlot_Upper__IOHC_SION_S1_Client4_Req_TimeSlot_Upper__SHIFT 0x0
+#define IOHC_SION_S1_Client4_Req_TimeSlot_Upper__IOHC_SION_S1_Client4_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client4_RdRsp_BurstTarget_Lower
+#define IOHC_SION_S1_Client4_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client4_RdRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOHC_SION_S1_Client4_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client4_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client4_RdRsp_BurstTarget_Upper
+#define IOHC_SION_S1_Client4_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client4_RdRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOHC_SION_S1_Client4_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client4_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client4_RdRsp_TimeSlot_Lower
+#define IOHC_SION_S1_Client4_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client4_RdRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOHC_SION_S1_Client4_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client4_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client4_RdRsp_TimeSlot_Upper
+#define IOHC_SION_S1_Client4_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client4_RdRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOHC_SION_S1_Client4_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client4_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client4_WrRsp_BurstTarget_Lower
+#define IOHC_SION_S1_Client4_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client4_WrRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOHC_SION_S1_Client4_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client4_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client4_WrRsp_BurstTarget_Upper
+#define IOHC_SION_S1_Client4_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client4_WrRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOHC_SION_S1_Client4_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client4_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client4_WrRsp_TimeSlot_Lower
+#define IOHC_SION_S1_Client4_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client4_WrRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOHC_SION_S1_Client4_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client4_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_S1_Client4_WrRsp_TimeSlot_Upper
+#define IOHC_SION_S1_Client4_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client4_WrRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOHC_SION_S1_Client4_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client4_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_Client4_ReqPoolCredit_Alloc_Lower
+#define IOHC_SION_Client4_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client4_ReqPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOHC_SION_Client4_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client4_ReqPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_Client4_ReqPoolCredit_Alloc_Upper
+#define IOHC_SION_Client4_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client4_ReqPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOHC_SION_Client4_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client4_ReqPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_Client4_DataPoolCredit_Alloc_Lower
+#define IOHC_SION_Client4_DataPoolCredit_Alloc_Lower__IOHC_SION_Client4_DataPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOHC_SION_Client4_DataPoolCredit_Alloc_Lower__IOHC_SION_Client4_DataPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_Client4_DataPoolCredit_Alloc_Upper
+#define IOHC_SION_Client4_DataPoolCredit_Alloc_Upper__IOHC_SION_Client4_DataPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOHC_SION_Client4_DataPoolCredit_Alloc_Upper__IOHC_SION_Client4_DataPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_Client4_RdRspPoolCredit_Alloc_Lower
+#define IOHC_SION_Client4_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client4_RdRspPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOHC_SION_Client4_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client4_RdRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_Client4_RdRspPoolCredit_Alloc_Upper
+#define IOHC_SION_Client4_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client4_RdRspPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOHC_SION_Client4_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client4_RdRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_Client4_WrRspPoolCredit_Alloc_Lower
+#define IOHC_SION_Client4_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client4_WrRspPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOHC_SION_Client4_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client4_WrRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOHC_SION_Client4_WrRspPoolCredit_Alloc_Upper
+#define IOHC_SION_Client4_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client4_WrRspPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOHC_SION_Client4_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client4_WrRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOHC_SION_LiveLock_WatchDog_Threshold
+#define IOHC_SION_LiveLock_WatchDog_Threshold__IOHC_SION_LiveLock_WatchDog_Threshold__SHIFT 0x0
+#define IOHC_SION_LiveLock_WatchDog_Threshold__IOHC_SION_LiveLock_WatchDog_Threshold_MASK 0x000000FFL
+
+
+// addressBlock: nbio_iohub_nb_rascfg_ras_cfgdec
+//PARITY_CONTROL_0
+#define PARITY_CONTROL_0__ParityCorrThreshold__SHIFT 0x0
+#define PARITY_CONTROL_0__ParityUCPThreshold__SHIFT 0x10
+#define PARITY_CONTROL_0__ParityCorrThreshold_MASK 0x0000FFFFL
+#define PARITY_CONTROL_0__ParityUCPThreshold_MASK 0xFFFF0000L
+//PARITY_CONTROL_1
+#define PARITY_CONTROL_1__ParityErrGenGroupSel__SHIFT 0x0
+#define PARITY_CONTROL_1__ParityErrGenGroupTypeSel__SHIFT 0x8
+#define PARITY_CONTROL_1__ParityErrGenIdSel__SHIFT 0xb
+#define PARITY_CONTROL_1__ParityErrGenCmd__SHIFT 0x10
+#define PARITY_CONTROL_1__ParityErrGenTrigger__SHIFT 0x1e
+#define PARITY_CONTROL_1__ParityErrGenInjectAllow__SHIFT 0x1f
+#define PARITY_CONTROL_1__ParityErrGenGroupSel_MASK 0x000000FFL
+#define PARITY_CONTROL_1__ParityErrGenGroupTypeSel_MASK 0x00000100L
+#define PARITY_CONTROL_1__ParityErrGenIdSel_MASK 0x0000F800L
+#define PARITY_CONTROL_1__ParityErrGenCmd_MASK 0x000F0000L
+#define PARITY_CONTROL_1__ParityErrGenTrigger_MASK 0x40000000L
+#define PARITY_CONTROL_1__ParityErrGenInjectAllow_MASK 0x80000000L
+//PARITY_SEVERITY_CONTROL_UNCORR_0
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp0__SHIFT 0x0
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp1__SHIFT 0x2
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp2__SHIFT 0x4
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp3__SHIFT 0x6
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp4__SHIFT 0x8
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp0_MASK 0x00000003L
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp1_MASK 0x0000000CL
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp2_MASK 0x00000030L
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp3_MASK 0x000000C0L
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp4_MASK 0x00000300L
+//PARITY_SEVERITY_CONTROL_CORR_0
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp0__SHIFT 0x0
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp1__SHIFT 0x2
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp2__SHIFT 0x4
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp3__SHIFT 0x6
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp4__SHIFT 0x8
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp0_MASK 0x00000003L
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp1_MASK 0x0000000CL
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp2_MASK 0x00000030L
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp3_MASK 0x000000C0L
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp4_MASK 0x00000300L
+//PARITY_SEVERITY_CONTROL_UCP_0
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp0__SHIFT 0x0
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp1__SHIFT 0x2
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp2__SHIFT 0x4
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp3__SHIFT 0x6
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp4__SHIFT 0x8
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp0_MASK 0x00000003L
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp1_MASK 0x0000000CL
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp2_MASK 0x00000030L
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp3_MASK 0x000000C0L
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp4_MASK 0x00000300L
+//RAS_GLOBAL_STATUS_LO
+#define RAS_GLOBAL_STATUS_LO__ParityErrCorr__SHIFT 0x0
+#define RAS_GLOBAL_STATUS_LO__ParityErrNonFatal__SHIFT 0x1
+#define RAS_GLOBAL_STATUS_LO__ParityErrFatal__SHIFT 0x2
+#define RAS_GLOBAL_STATUS_LO__ParityErrSerr__SHIFT 0x3
+#define RAS_GLOBAL_STATUS_LO__HPLGWA_NMI__SHIFT 0x6
+#define RAS_GLOBAL_STATUS_LO__HPLGWA_SCI__SHIFT 0x7
+#define RAS_GLOBAL_STATUS_LO__HPLGWA_SMI__SHIFT 0x8
+#define RAS_GLOBAL_STATUS_LO__SW_SMI__SHIFT 0x9
+#define RAS_GLOBAL_STATUS_LO__SW_SCI__SHIFT 0xa
+#define RAS_GLOBAL_STATUS_LO__SW_NMI__SHIFT 0xb
+#define RAS_GLOBAL_STATUS_LO__APML_NMI__SHIFT 0xc
+#define RAS_GLOBAL_STATUS_LO__APML_SyncFld__SHIFT 0xd
+#define RAS_GLOBAL_STATUS_LO__PIN_SyncFld_NMI__SHIFT 0xe
+#define RAS_GLOBAL_STATUS_LO__APML_SyncFld_Private__SHIFT 0xf
+#define RAS_GLOBAL_STATUS_LO__ParityErrCorr_MASK 0x00000001L
+#define RAS_GLOBAL_STATUS_LO__ParityErrNonFatal_MASK 0x00000002L
+#define RAS_GLOBAL_STATUS_LO__ParityErrFatal_MASK 0x00000004L
+#define RAS_GLOBAL_STATUS_LO__ParityErrSerr_MASK 0x00000008L
+#define RAS_GLOBAL_STATUS_LO__HPLGWA_NMI_MASK 0x00000040L
+#define RAS_GLOBAL_STATUS_LO__HPLGWA_SCI_MASK 0x00000080L
+#define RAS_GLOBAL_STATUS_LO__HPLGWA_SMI_MASK 0x00000100L
+#define RAS_GLOBAL_STATUS_LO__SW_SMI_MASK 0x00000200L
+#define RAS_GLOBAL_STATUS_LO__SW_SCI_MASK 0x00000400L
+#define RAS_GLOBAL_STATUS_LO__SW_NMI_MASK 0x00000800L
+#define RAS_GLOBAL_STATUS_LO__APML_NMI_MASK 0x00001000L
+#define RAS_GLOBAL_STATUS_LO__APML_SyncFld_MASK 0x00002000L
+#define RAS_GLOBAL_STATUS_LO__PIN_SyncFld_NMI_MASK 0x00004000L
+#define RAS_GLOBAL_STATUS_LO__APML_SyncFld_Private_MASK 0x00008000L
+//RAS_GLOBAL_STATUS_HI
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortAErr__SHIFT 0x0
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortBErr__SHIFT 0x1
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortCErr__SHIFT 0x2
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortDErr__SHIFT 0x3
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortEErr__SHIFT 0x4
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortFErr__SHIFT 0x5
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortGErr__SHIFT 0x6
+#define RAS_GLOBAL_STATUS_HI__NBIF1PortAErr__SHIFT 0x7
+#define RAS_GLOBAL_STATUS_HI__NBIF1PortBErr__SHIFT 0x8
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortAErr_MASK 0x00000001L
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortBErr_MASK 0x00000002L
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortCErr_MASK 0x00000004L
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortDErr_MASK 0x00000008L
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortEErr_MASK 0x00000010L
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortFErr_MASK 0x00000020L
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortGErr_MASK 0x00000040L
+#define RAS_GLOBAL_STATUS_HI__NBIF1PortAErr_MASK 0x00000080L
+#define RAS_GLOBAL_STATUS_HI__NBIF1PortBErr_MASK 0x00000100L
+//PARITY_ERROR_STATUS_UNCORR_GRP0
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_UNCORR_GRP1
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_UNCORR_GRP2
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_UNCORR_GRP3
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_UNCORR_GRP4
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_CORR_GRP0
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_CORR_GRP1
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_CORR_GRP2
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_CORR_GRP3
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_CORR_GRP4
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_COUNTER_CORR_GRP0
+#define PARITY_COUNTER_CORR_GRP0__ThresholdCounter__SHIFT 0x0
+#define PARITY_COUNTER_CORR_GRP0__ResetEn__SHIFT 0x1f
+#define PARITY_COUNTER_CORR_GRP0__ThresholdCounter_MASK 0x0000FFFFL
+#define PARITY_COUNTER_CORR_GRP0__ResetEn_MASK 0x80000000L
+//PARITY_COUNTER_CORR_GRP1
+#define PARITY_COUNTER_CORR_GRP1__ThresholdCounter__SHIFT 0x0
+#define PARITY_COUNTER_CORR_GRP1__ResetEn__SHIFT 0x1f
+#define PARITY_COUNTER_CORR_GRP1__ThresholdCounter_MASK 0x0000FFFFL
+#define PARITY_COUNTER_CORR_GRP1__ResetEn_MASK 0x80000000L
+//PARITY_COUNTER_CORR_GRP2
+#define PARITY_COUNTER_CORR_GRP2__ThresholdCounter__SHIFT 0x0
+#define PARITY_COUNTER_CORR_GRP2__ResetEn__SHIFT 0x1f
+#define PARITY_COUNTER_CORR_GRP2__ThresholdCounter_MASK 0x0000FFFFL
+#define PARITY_COUNTER_CORR_GRP2__ResetEn_MASK 0x80000000L
+//PARITY_COUNTER_CORR_GRP3
+#define PARITY_COUNTER_CORR_GRP3__ThresholdCounter__SHIFT 0x0
+#define PARITY_COUNTER_CORR_GRP3__ResetEn__SHIFT 0x1f
+#define PARITY_COUNTER_CORR_GRP3__ThresholdCounter_MASK 0x0000FFFFL
+#define PARITY_COUNTER_CORR_GRP3__ResetEn_MASK 0x80000000L
+//PARITY_COUNTER_CORR_GRP4
+#define PARITY_COUNTER_CORR_GRP4__ThresholdCounter__SHIFT 0x0
+#define PARITY_COUNTER_CORR_GRP4__ResetEn__SHIFT 0x1f
+#define PARITY_COUNTER_CORR_GRP4__ThresholdCounter_MASK 0x0000FFFFL
+#define PARITY_COUNTER_CORR_GRP4__ResetEn_MASK 0x80000000L
+//PARITY_ERROR_STATUS_UCP_GRP0
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_UCP_GRP1
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_UCP_GRP2
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_UCP_GRP3
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_UCP_GRP4
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_COUNTER_UCP_GRP0
+#define PARITY_COUNTER_UCP_GRP0__ThresholdCounter__SHIFT 0x0
+#define PARITY_COUNTER_UCP_GRP0__ResetEn__SHIFT 0x1f
+#define PARITY_COUNTER_UCP_GRP0__ThresholdCounter_MASK 0x0000FFFFL
+#define PARITY_COUNTER_UCP_GRP0__ResetEn_MASK 0x80000000L
+//PARITY_COUNTER_UCP_GRP1
+#define PARITY_COUNTER_UCP_GRP1__ThresholdCounter__SHIFT 0x0
+#define PARITY_COUNTER_UCP_GRP1__ResetEn__SHIFT 0x1f
+#define PARITY_COUNTER_UCP_GRP1__ThresholdCounter_MASK 0x0000FFFFL
+#define PARITY_COUNTER_UCP_GRP1__ResetEn_MASK 0x80000000L
+//PARITY_COUNTER_UCP_GRP2
+#define PARITY_COUNTER_UCP_GRP2__ThresholdCounter__SHIFT 0x0
+#define PARITY_COUNTER_UCP_GRP2__ResetEn__SHIFT 0x1f
+#define PARITY_COUNTER_UCP_GRP2__ThresholdCounter_MASK 0x0000FFFFL
+#define PARITY_COUNTER_UCP_GRP2__ResetEn_MASK 0x80000000L
+//PARITY_COUNTER_UCP_GRP3
+#define PARITY_COUNTER_UCP_GRP3__ThresholdCounter__SHIFT 0x0
+#define PARITY_COUNTER_UCP_GRP3__ResetEn__SHIFT 0x1f
+#define PARITY_COUNTER_UCP_GRP3__ThresholdCounter_MASK 0x0000FFFFL
+#define PARITY_COUNTER_UCP_GRP3__ResetEn_MASK 0x80000000L
+//PARITY_COUNTER_UCP_GRP4
+#define PARITY_COUNTER_UCP_GRP4__ThresholdCounter__SHIFT 0x0
+#define PARITY_COUNTER_UCP_GRP4__ResetEn__SHIFT 0x1f
+#define PARITY_COUNTER_UCP_GRP4__ThresholdCounter_MASK 0x0000FFFFL
+#define PARITY_COUNTER_UCP_GRP4__ResetEn_MASK 0x80000000L
+//MISC_SEVERITY_CONTROL
+#define MISC_SEVERITY_CONTROL__ErrEventErrSev__SHIFT 0x4
+#define MISC_SEVERITY_CONTROL__PcieParityErrSev__SHIFT 0x6
+#define MISC_SEVERITY_CONTROL__ErrEventErrSev_MASK 0x00000030L
+#define MISC_SEVERITY_CONTROL__PcieParityErrSev_MASK 0x000000C0L
+//MISC_RAS_CONTROL
+#define MISC_RAS_CONTROL__PIN_NMI_SyncFlood_En__SHIFT 0x2
+#define MISC_RAS_CONTROL__GNB_SB_LinkNeverDis__SHIFT 0x3
+#define MISC_RAS_CONTROL__InterruptOutputDis__SHIFT 0x9
+#define MISC_RAS_CONTROL__LinkDisOutputDis__SHIFT 0xa
+#define MISC_RAS_CONTROL__SyncFldOutputDis__SHIFT 0xb
+#define MISC_RAS_CONTROL__PCIe_NMI_En__SHIFT 0xc
+#define MISC_RAS_CONTROL__PCIe_SCI_En__SHIFT 0xd
+#define MISC_RAS_CONTROL__PCIe_SMI_En__SHIFT 0xe
+#define MISC_RAS_CONTROL__SW_SCI_En__SHIFT 0xf
+#define MISC_RAS_CONTROL__SW_SMI_En__SHIFT 0x10
+#define MISC_RAS_CONTROL__SW_NMI_En__SHIFT 0x11
+#define MISC_RAS_CONTROL__PIN_NMI_SyncFlood_En_MASK 0x00000004L
+#define MISC_RAS_CONTROL__GNB_SB_LinkNeverDis_MASK 0x00000008L
+#define MISC_RAS_CONTROL__InterruptOutputDis_MASK 0x00000200L
+#define MISC_RAS_CONTROL__LinkDisOutputDis_MASK 0x00000400L
+#define MISC_RAS_CONTROL__SyncFldOutputDis_MASK 0x00000800L
+#define MISC_RAS_CONTROL__PCIe_NMI_En_MASK 0x00001000L
+#define MISC_RAS_CONTROL__PCIe_SCI_En_MASK 0x00002000L
+#define MISC_RAS_CONTROL__PCIe_SMI_En_MASK 0x00004000L
+#define MISC_RAS_CONTROL__SW_SCI_En_MASK 0x00008000L
+#define MISC_RAS_CONTROL__SW_SMI_En_MASK 0x00010000L
+#define MISC_RAS_CONTROL__SW_NMI_En_MASK 0x00020000L
+//RAS_SCRATCH_0
+#define RAS_SCRATCH_0__SCRATCH_0__SHIFT 0x0
+#define RAS_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL
+//RAS_SCRATCH_1
+#define RAS_SCRATCH_1__SCRATCH_1__SHIFT 0x0
+#define RAS_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL
+//ErrEvent_ACTION_CONTROL
+#define ErrEvent_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define ErrEvent_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define ErrEvent_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define ErrEvent_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define ErrEvent_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define ErrEvent_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define ErrEvent_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define ErrEvent_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//ParitySerr_ACTION_CONTROL
+#define ParitySerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define ParitySerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define ParitySerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define ParitySerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define ParitySerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define ParitySerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define ParitySerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define ParitySerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//ParityFatal_ACTION_CONTROL
+#define ParityFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define ParityFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define ParityFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define ParityFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define ParityFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define ParityFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define ParityFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define ParityFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//ParityNonFatal_ACTION_CONTROL
+#define ParityNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define ParityNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define ParityNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define ParityNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define ParityNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define ParityNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define ParityNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define ParityNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//ParityCorr_ACTION_CONTROL
+#define ParityCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define ParityCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define ParityCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define ParityCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define ParityCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define ParityCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define ParityCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define ParityCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortASerr_ACTION_CONTROL
+#define PCIE0PortASerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortASerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortASerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortASerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortASerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortASerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortASerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortASerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortAIntFatal_ACTION_CONTROL
+#define PCIE0PortAIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortAIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortAIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortAIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortAIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortAIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortAIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortAIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortAIntNonFatal_ACTION_CONTROL
+#define PCIE0PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortAIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortAIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortAIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortAIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortAIntCorr_ACTION_CONTROL
+#define PCIE0PortAIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortAIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortAIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortAIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortAIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortAIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortAIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortAIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortAExtFatal_ACTION_CONTROL
+#define PCIE0PortAExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortAExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortAExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortAExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortAExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortAExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortAExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortAExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortAExtNonFatal_ACTION_CONTROL
+#define PCIE0PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortAExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortAExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortAExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortAExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortAExtCorr_ACTION_CONTROL
+#define PCIE0PortAExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortAExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortAExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortAExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortAExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortAExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortAExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortAExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortAParityErr_ACTION_CONTROL
+#define PCIE0PortAParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortAParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortAParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortAParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortAParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortAParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortAParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortAParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortBSerr_ACTION_CONTROL
+#define PCIE0PortBSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortBSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortBSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortBSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortBSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortBSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortBSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortBSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortBIntFatal_ACTION_CONTROL
+#define PCIE0PortBIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortBIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortBIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortBIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortBIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortBIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortBIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortBIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortBIntNonFatal_ACTION_CONTROL
+#define PCIE0PortBIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortBIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortBIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortBIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortBIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortBIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortBIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortBIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortBIntCorr_ACTION_CONTROL
+#define PCIE0PortBIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortBIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortBIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortBIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortBIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortBIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortBIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortBIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortBExtFatal_ACTION_CONTROL
+#define PCIE0PortBExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortBExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortBExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortBExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortBExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortBExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortBExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortBExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortBExtNonFatal_ACTION_CONTROL
+#define PCIE0PortBExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortBExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortBExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortBExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortBExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortBExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortBExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortBExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortBExtCorr_ACTION_CONTROL
+#define PCIE0PortBExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortBExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortBExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortBExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortBExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortBExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortBExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortBExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortBParityErr_ACTION_CONTROL
+#define PCIE0PortBParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortBParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortBParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortBParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortBParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortBParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortBParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortBParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortCSerr_ACTION_CONTROL
+#define PCIE0PortCSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortCSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortCSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortCSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortCSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortCSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortCSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortCSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortCIntFatal_ACTION_CONTROL
+#define PCIE0PortCIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortCIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortCIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortCIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortCIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortCIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortCIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortCIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortCIntNonFatal_ACTION_CONTROL
+#define PCIE0PortCIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortCIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortCIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortCIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortCIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortCIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortCIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortCIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortCIntCorr_ACTION_CONTROL
+#define PCIE0PortCIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortCIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortCIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortCIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortCIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortCIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortCIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortCIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortCExtFatal_ACTION_CONTROL
+#define PCIE0PortCExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortCExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortCExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortCExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortCExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortCExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortCExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortCExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortCExtNonFatal_ACTION_CONTROL
+#define PCIE0PortCExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortCExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortCExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortCExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortCExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortCExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortCExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortCExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortCExtCorr_ACTION_CONTROL
+#define PCIE0PortCExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortCExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortCExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortCExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortCExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortCExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortCExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortCExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortCParityErr_ACTION_CONTROL
+#define PCIE0PortCParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortCParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortCParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortCParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortCParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortCParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortCParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortCParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortDSerr_ACTION_CONTROL
+#define PCIE0PortDSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortDSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortDSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortDSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortDSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortDSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortDSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortDSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortDIntFatal_ACTION_CONTROL
+#define PCIE0PortDIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortDIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortDIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortDIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortDIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortDIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortDIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortDIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortDIntNonFatal_ACTION_CONTROL
+#define PCIE0PortDIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortDIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortDIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortDIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortDIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortDIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortDIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortDIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortDIntCorr_ACTION_CONTROL
+#define PCIE0PortDIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortDIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortDIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortDIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortDIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortDIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortDIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortDIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortDExtFatal_ACTION_CONTROL
+#define PCIE0PortDExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortDExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortDExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortDExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortDExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortDExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortDExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortDExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortDExtNonFatal_ACTION_CONTROL
+#define PCIE0PortDExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortDExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortDExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortDExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortDExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortDExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortDExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortDExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortDExtCorr_ACTION_CONTROL
+#define PCIE0PortDExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortDExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortDExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortDExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortDExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortDExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortDExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortDExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortDParityErr_ACTION_CONTROL
+#define PCIE0PortDParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortDParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortDParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortDParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortDParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortDParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortDParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortDParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortESerr_ACTION_CONTROL
+#define PCIE0PortESerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortESerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortESerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortESerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortESerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortESerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortESerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortESerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortEIntFatal_ACTION_CONTROL
+#define PCIE0PortEIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortEIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortEIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortEIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortEIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortEIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortEIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortEIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortEIntNonFatal_ACTION_CONTROL
+#define PCIE0PortEIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortEIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortEIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortEIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortEIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortEIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortEIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortEIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortEIntCorr_ACTION_CONTROL
+#define PCIE0PortEIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortEIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortEIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortEIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortEIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortEIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortEIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortEIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortEExtFatal_ACTION_CONTROL
+#define PCIE0PortEExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortEExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortEExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortEExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortEExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortEExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortEExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortEExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortEExtNonFatal_ACTION_CONTROL
+#define PCIE0PortEExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortEExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortEExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortEExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortEExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortEExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortEExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortEExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortEExtCorr_ACTION_CONTROL
+#define PCIE0PortEExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortEExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortEExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortEExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortEExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortEExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortEExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortEExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortEParityErr_ACTION_CONTROL
+#define PCIE0PortEParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortEParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortEParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortEParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortEParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortEParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortEParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortEParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortFSerr_ACTION_CONTROL
+#define PCIE0PortFSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortFSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortFSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortFSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortFSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortFSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortFSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortFSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortFIntFatal_ACTION_CONTROL
+#define PCIE0PortFIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortFIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortFIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortFIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortFIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortFIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortFIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortFIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortFIntNonFatal_ACTION_CONTROL
+#define PCIE0PortFIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortFIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortFIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortFIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortFIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortFIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortFIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortFIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortFIntCorr_ACTION_CONTROL
+#define PCIE0PortFIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortFIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortFIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortFIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortFIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortFIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortFIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortFIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortFExtFatal_ACTION_CONTROL
+#define PCIE0PortFExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortFExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortFExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortFExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortFExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortFExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortFExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortFExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortFExtNonFatal_ACTION_CONTROL
+#define PCIE0PortFExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortFExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortFExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortFExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortFExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortFExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortFExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortFExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortFExtCorr_ACTION_CONTROL
+#define PCIE0PortFExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortFExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortFExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortFExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortFExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortFExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortFExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortFExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortFParityErr_ACTION_CONTROL
+#define PCIE0PortFParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortFParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortFParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortFParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortFParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortFParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortFParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortFParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortGSerr_ACTION_CONTROL
+#define PCIE0PortGSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortGSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortGSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortGSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortGSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortGSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortGSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortGSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortGIntFatal_ACTION_CONTROL
+#define PCIE0PortGIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortGIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortGIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortGIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortGIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortGIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortGIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortGIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortGIntNonFatal_ACTION_CONTROL
+#define PCIE0PortGIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortGIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortGIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortGIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortGIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortGIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortGIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortGIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortGIntCorr_ACTION_CONTROL
+#define PCIE0PortGIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortGIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortGIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortGIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortGIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortGIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortGIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortGIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortGExtFatal_ACTION_CONTROL
+#define PCIE0PortGExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortGExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortGExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortGExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortGExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortGExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortGExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortGExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortGExtNonFatal_ACTION_CONTROL
+#define PCIE0PortGExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortGExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortGExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortGExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortGExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortGExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortGExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortGExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortGExtCorr_ACTION_CONTROL
+#define PCIE0PortGExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortGExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortGExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortGExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortGExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortGExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortGExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortGExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortGParityErr_ACTION_CONTROL
+#define PCIE0PortGParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortGParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortGParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortGParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortGParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortGParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortGParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortGParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortASerr_ACTION_CONTROL
+#define NBIF1PortASerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortASerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortASerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortASerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortASerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortASerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortASerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortASerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortAIntFatal_ACTION_CONTROL
+#define NBIF1PortAIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortAIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortAIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortAIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortAIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortAIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortAIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortAIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortAIntNonFatal_ACTION_CONTROL
+#define NBIF1PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortAIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortAIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortAIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortAIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortAIntCorr_ACTION_CONTROL
+#define NBIF1PortAIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortAIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortAIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortAIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortAIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortAIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortAIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortAIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortAExtFatal_ACTION_CONTROL
+#define NBIF1PortAExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortAExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortAExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortAExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortAExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortAExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortAExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortAExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortAExtNonFatal_ACTION_CONTROL
+#define NBIF1PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortAExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortAExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortAExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortAExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortAExtCorr_ACTION_CONTROL
+#define NBIF1PortAExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortAExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortAExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortAExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortAExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortAExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortAExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortAExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortAParityErr_ACTION_CONTROL
+#define NBIF1PortAParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortAParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortAParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortAParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortAParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortAParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortAParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortAParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortBSerr_ACTION_CONTROL
+#define NBIF1PortBSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortBSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortBSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortBSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortBSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortBSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortBSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortBSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortBIntFatal_ACTION_CONTROL
+#define NBIF1PortBIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortBIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortBIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortBIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortBIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortBIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortBIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortBIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortBIntNonFatal_ACTION_CONTROL
+#define NBIF1PortBIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortBIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortBIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortBIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortBIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortBIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortBIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortBIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortBIntCorr_ACTION_CONTROL
+#define NBIF1PortBIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortBIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortBIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortBIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortBIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortBIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortBIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortBIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortBExtFatal_ACTION_CONTROL
+#define NBIF1PortBExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortBExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortBExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortBExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortBExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortBExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortBExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortBExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortBExtNonFatal_ACTION_CONTROL
+#define NBIF1PortBExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortBExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortBExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortBExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortBExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortBExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortBExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortBExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortBExtCorr_ACTION_CONTROL
+#define NBIF1PortBExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortBExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortBExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortBExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortBExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortBExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortBExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortBExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortBParityErr_ACTION_CONTROL
+#define NBIF1PortBParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortBParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortBParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortBParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortBParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortBParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortBParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortBParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//SYNCFLOOD_STATUS
+#define SYNCFLOOD_STATUS__SyncfloodFromRASCntl__SHIFT 0x0
+#define SYNCFLOOD_STATUS__SyncfloodFromAPML__SHIFT 0x1
+#define SYNCFLOOD_STATUS__SyncfloodFromPin__SHIFT 0x2
+#define SYNCFLOOD_STATUS__SyncfloodFromPrivate__SHIFT 0x4
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_8__SHIFT 0x8
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_9__SHIFT 0x9
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_10__SHIFT 0xa
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_11__SHIFT 0xb
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_12__SHIFT 0xc
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_13__SHIFT 0xd
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_14__SHIFT 0xe
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_15__SHIFT 0xf
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_16__SHIFT 0x10
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_17__SHIFT 0x11
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_18__SHIFT 0x12
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_19__SHIFT 0x13
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_20__SHIFT 0x14
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_21__SHIFT 0x15
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_22__SHIFT 0x16
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_23__SHIFT 0x17
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_24__SHIFT 0x18
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_25__SHIFT 0x19
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_26__SHIFT 0x1a
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_27__SHIFT 0x1b
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_28__SHIFT 0x1c
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_29__SHIFT 0x1d
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_30__SHIFT 0x1e
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_31__SHIFT 0x1f
+#define SYNCFLOOD_STATUS__SyncfloodFromRASCntl_MASK 0x00000001L
+#define SYNCFLOOD_STATUS__SyncfloodFromAPML_MASK 0x00000002L
+#define SYNCFLOOD_STATUS__SyncfloodFromPin_MASK 0x00000004L
+#define SYNCFLOOD_STATUS__SyncfloodFromPrivate_MASK 0x00000010L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_8_MASK 0x00000100L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_9_MASK 0x00000200L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_10_MASK 0x00000400L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_11_MASK 0x00000800L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_12_MASK 0x00001000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_13_MASK 0x00002000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_14_MASK 0x00004000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_15_MASK 0x00008000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_16_MASK 0x00010000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_17_MASK 0x00020000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_18_MASK 0x00040000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_19_MASK 0x00080000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_20_MASK 0x00100000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_21_MASK 0x00200000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_22_MASK 0x00400000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_23_MASK 0x00800000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_24_MASK 0x01000000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_25_MASK 0x02000000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_26_MASK 0x04000000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_27_MASK 0x08000000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_28_MASK 0x10000000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_29_MASK 0x20000000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_30_MASK 0x40000000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_31_MASK 0x80000000L
+//NMI_STATUS
+#define NMI_STATUS__NMIFromPin__SHIFT 0x0
+#define NMI_STATUS__NMIFromPin_MASK 0x00000001L
+//POISON_ACTION_CONTROL
+#define POISON_ACTION_CONTROL__IntPoisonAPMLErrEn__SHIFT 0x0
+#define POISON_ACTION_CONTROL__IntPoisonIntrGenSel__SHIFT 0x1
+#define POISON_ACTION_CONTROL__IntPoisonLinkDisEn__SHIFT 0x3
+#define POISON_ACTION_CONTROL__IntPoisonSyncFloodEn__SHIFT 0x4
+#define POISON_ACTION_CONTROL__EgressPoisonLSAPMLErrEn__SHIFT 0x8
+#define POISON_ACTION_CONTROL__EgressPoisonLSIntrGenSel__SHIFT 0x9
+#define POISON_ACTION_CONTROL__EgressPoisonLSLinkDisEn__SHIFT 0xb
+#define POISON_ACTION_CONTROL__EgressPoisonLSSyncFloodEn__SHIFT 0xc
+#define POISON_ACTION_CONTROL__EgressPoisonHSAPMLErrEn__SHIFT 0x10
+#define POISON_ACTION_CONTROL__EgressPoisonHSIntrGenSel__SHIFT 0x11
+#define POISON_ACTION_CONTROL__EgressPoisonHSLinkDisEn__SHIFT 0x13
+#define POISON_ACTION_CONTROL__EgressPoisonHSSyncFloodEn__SHIFT 0x14
+#define POISON_ACTION_CONTROL__IntPoisonAPMLErrEn_MASK 0x00000001L
+#define POISON_ACTION_CONTROL__IntPoisonIntrGenSel_MASK 0x00000006L
+#define POISON_ACTION_CONTROL__IntPoisonLinkDisEn_MASK 0x00000008L
+#define POISON_ACTION_CONTROL__IntPoisonSyncFloodEn_MASK 0x00000010L
+#define POISON_ACTION_CONTROL__EgressPoisonLSAPMLErrEn_MASK 0x00000100L
+#define POISON_ACTION_CONTROL__EgressPoisonLSIntrGenSel_MASK 0x00000600L
+#define POISON_ACTION_CONTROL__EgressPoisonLSLinkDisEn_MASK 0x00000800L
+#define POISON_ACTION_CONTROL__EgressPoisonLSSyncFloodEn_MASK 0x00001000L
+#define POISON_ACTION_CONTROL__EgressPoisonHSAPMLErrEn_MASK 0x00010000L
+#define POISON_ACTION_CONTROL__EgressPoisonHSIntrGenSel_MASK 0x00060000L
+#define POISON_ACTION_CONTROL__EgressPoisonHSLinkDisEn_MASK 0x00080000L
+#define POISON_ACTION_CONTROL__EgressPoisonHSSyncFloodEn_MASK 0x00100000L
+//INTERNAL_POISON_STATUS
+#define INTERNAL_POISON_STATUS__IntPoisonStatus_0__SHIFT 0x0
+#define INTERNAL_POISON_STATUS__IntPoisonStatus_1__SHIFT 0x1
+#define INTERNAL_POISON_STATUS__IntPoisonStatus_2__SHIFT 0x2
+#define INTERNAL_POISON_STATUS__IntPoisonStatus_3__SHIFT 0x3
+#define INTERNAL_POISON_STATUS__IntPoisonStatus_4__SHIFT 0x4
+#define INTERNAL_POISON_STATUS__IntPoisonStatus_5__SHIFT 0x5
+#define INTERNAL_POISON_STATUS__IntPoisonStatus_6__SHIFT 0x6
+#define INTERNAL_POISON_STATUS__IntPoisonStatus_7__SHIFT 0x7
+#define INTERNAL_POISON_STATUS__IntPoisonStatus_0_MASK 0x00000001L
+#define INTERNAL_POISON_STATUS__IntPoisonStatus_1_MASK 0x00000002L
+#define INTERNAL_POISON_STATUS__IntPoisonStatus_2_MASK 0x00000004L
+#define INTERNAL_POISON_STATUS__IntPoisonStatus_3_MASK 0x00000008L
+#define INTERNAL_POISON_STATUS__IntPoisonStatus_4_MASK 0x00000010L
+#define INTERNAL_POISON_STATUS__IntPoisonStatus_5_MASK 0x00000020L
+#define INTERNAL_POISON_STATUS__IntPoisonStatus_6_MASK 0x00000040L
+#define INTERNAL_POISON_STATUS__IntPoisonStatus_7_MASK 0x00000080L
+//INTERNAL_POISON_MASK
+#define INTERNAL_POISON_MASK__IntPoisonMask__SHIFT 0x0
+#define INTERNAL_POISON_MASK__IntPoisonMask_MASK 0x000000FFL
+//EGRESS_POISON_STATUS_LO
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_0__SHIFT 0x0
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_1__SHIFT 0x1
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_2__SHIFT 0x2
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_3__SHIFT 0x3
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_4__SHIFT 0x4
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_5__SHIFT 0x5
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_6__SHIFT 0x6
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_7__SHIFT 0x7
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_8__SHIFT 0x8
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_9__SHIFT 0x9
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_10__SHIFT 0xa
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_11__SHIFT 0xb
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_12__SHIFT 0xc
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_13__SHIFT 0xd
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_14__SHIFT 0xe
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_15__SHIFT 0xf
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_16__SHIFT 0x10
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_17__SHIFT 0x11
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_18__SHIFT 0x12
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_19__SHIFT 0x13
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_20__SHIFT 0x14
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_21__SHIFT 0x15
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_22__SHIFT 0x16
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_23__SHIFT 0x17
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_24__SHIFT 0x18
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_25__SHIFT 0x19
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_26__SHIFT 0x1a
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_27__SHIFT 0x1b
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_28__SHIFT 0x1c
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_29__SHIFT 0x1d
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_30__SHIFT 0x1e
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_31__SHIFT 0x1f
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_0_MASK 0x00000001L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_1_MASK 0x00000002L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_2_MASK 0x00000004L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_3_MASK 0x00000008L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_4_MASK 0x00000010L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_5_MASK 0x00000020L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_6_MASK 0x00000040L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_7_MASK 0x00000080L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_8_MASK 0x00000100L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_9_MASK 0x00000200L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_10_MASK 0x00000400L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_11_MASK 0x00000800L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_12_MASK 0x00001000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_13_MASK 0x00002000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_14_MASK 0x00004000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_15_MASK 0x00008000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_16_MASK 0x00010000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_17_MASK 0x00020000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_18_MASK 0x00040000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_19_MASK 0x00080000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_20_MASK 0x00100000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_21_MASK 0x00200000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_22_MASK 0x00400000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_23_MASK 0x00800000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_24_MASK 0x01000000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_25_MASK 0x02000000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_26_MASK 0x04000000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_27_MASK 0x08000000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_28_MASK 0x10000000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_29_MASK 0x20000000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_30_MASK 0x40000000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_31_MASK 0x80000000L
+//EGRESS_POISON_STATUS_HI
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_0__SHIFT 0x0
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_1__SHIFT 0x1
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_2__SHIFT 0x2
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_3__SHIFT 0x3
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_4__SHIFT 0x4
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_5__SHIFT 0x5
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_6__SHIFT 0x6
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_7__SHIFT 0x7
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_8__SHIFT 0x8
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_9__SHIFT 0x9
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_10__SHIFT 0xa
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_11__SHIFT 0xb
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_12__SHIFT 0xc
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_13__SHIFT 0xd
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_14__SHIFT 0xe
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_15__SHIFT 0xf
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_16__SHIFT 0x10
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_17__SHIFT 0x11
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_18__SHIFT 0x12
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_19__SHIFT 0x13
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_20__SHIFT 0x14
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_21__SHIFT 0x15
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_22__SHIFT 0x16
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_23__SHIFT 0x17
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_24__SHIFT 0x18
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_25__SHIFT 0x19
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_26__SHIFT 0x1a
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_27__SHIFT 0x1b
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_28__SHIFT 0x1c
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_29__SHIFT 0x1d
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_30__SHIFT 0x1e
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_31__SHIFT 0x1f
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_0_MASK 0x00000001L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_1_MASK 0x00000002L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_2_MASK 0x00000004L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_3_MASK 0x00000008L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_4_MASK 0x00000010L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_5_MASK 0x00000020L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_6_MASK 0x00000040L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_7_MASK 0x00000080L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_8_MASK 0x00000100L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_9_MASK 0x00000200L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_10_MASK 0x00000400L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_11_MASK 0x00000800L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_12_MASK 0x00001000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_13_MASK 0x00002000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_14_MASK 0x00004000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_15_MASK 0x00008000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_16_MASK 0x00010000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_17_MASK 0x00020000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_18_MASK 0x00040000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_19_MASK 0x00080000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_20_MASK 0x00100000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_21_MASK 0x00200000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_22_MASK 0x00400000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_23_MASK 0x00800000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_24_MASK 0x01000000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_25_MASK 0x02000000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_26_MASK 0x04000000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_27_MASK 0x08000000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_28_MASK 0x10000000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_29_MASK 0x20000000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_30_MASK 0x40000000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_31_MASK 0x80000000L
+//EGRESS_POISON_MASK_LO
+#define EGRESS_POISON_MASK_LO__EgressPoisonMaskLo__SHIFT 0x0
+#define EGRESS_POISON_MASK_LO__EgressPoisonMaskLo_MASK 0xFFFFFFFFL
+//EGRESS_POISON_MASK_HI
+#define EGRESS_POISON_MASK_HI__EgressPoisonMaskHi__SHIFT 0x0
+#define EGRESS_POISON_MASK_HI__EgressPoisonMaskHi_MASK 0xFFFFFFFFL
+//EGRESS_POISON_SEVERITY_DOWN
+#define EGRESS_POISON_SEVERITY_DOWN__EgressPoisonSeverityDown__SHIFT 0x0
+#define EGRESS_POISON_SEVERITY_DOWN__EgressPoisonSeverityDown_MASK 0xFFFFFFFFL
+//EGRESS_POISON_SEVERITY_UPPER
+#define EGRESS_POISON_SEVERITY_UPPER__EgressPoisonSeverityUpper__SHIFT 0x0
+#define EGRESS_POISON_SEVERITY_UPPER__EgressPoisonSeverityUpper_MASK 0xFFFFFFFFL
+//APML_STATUS
+#define APML_STATUS__APML_Corr__SHIFT 0x0
+#define APML_STATUS__APML_NonFatal__SHIFT 0x1
+#define APML_STATUS__APML_Fatal__SHIFT 0x2
+#define APML_STATUS__APML_Serr__SHIFT 0x3
+#define APML_STATUS__APML_IntPoisonErr__SHIFT 0x4
+#define APML_STATUS__APML_EgressPoisonErrLo__SHIFT 0x5
+#define APML_STATUS__APML_EgressPoisonErrHi__SHIFT 0x6
+#define APML_STATUS__APML_Corr_MASK 0x00000001L
+#define APML_STATUS__APML_NonFatal_MASK 0x00000002L
+#define APML_STATUS__APML_Fatal_MASK 0x00000004L
+#define APML_STATUS__APML_Serr_MASK 0x00000008L
+#define APML_STATUS__APML_IntPoisonErr_MASK 0x00000010L
+#define APML_STATUS__APML_EgressPoisonErrLo_MASK 0x00000020L
+#define APML_STATUS__APML_EgressPoisonErrHi_MASK 0x00000040L
+//APML_CONTROL
+#define APML_CONTROL__APML_NMI_En__SHIFT 0x0
+#define APML_CONTROL__APML_SyncFlood_En__SHIFT 0x1
+#define APML_CONTROL__APML_OutputDis__SHIFT 0x8
+#define APML_CONTROL__APML_NMI_En_MASK 0x00000001L
+#define APML_CONTROL__APML_SyncFlood_En_MASK 0x00000002L
+#define APML_CONTROL__APML_OutputDis_MASK 0x00000100L
+//APML_TRIGGER
+#define APML_TRIGGER__APML_NMI_TRIGGER__SHIFT 0x0
+#define APML_TRIGGER__APML_NMI_TRIGGER_MASK 0x00000001L
+
+
+// addressBlock: nbio_iohub_nb_psprascfg_pspras_cfgdec
+//PSP_SYNCFLOOD_STATUS
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromRASCntl__SHIFT 0x0
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromAPML__SHIFT 0x1
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromPin__SHIFT 0x2
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromPrivate__SHIFT 0x4
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_8__SHIFT 0x8
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_9__SHIFT 0x9
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_10__SHIFT 0xa
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_11__SHIFT 0xb
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_12__SHIFT 0xc
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_13__SHIFT 0xd
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_14__SHIFT 0xe
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_15__SHIFT 0xf
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_16__SHIFT 0x10
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_17__SHIFT 0x11
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_18__SHIFT 0x12
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_19__SHIFT 0x13
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_20__SHIFT 0x14
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_21__SHIFT 0x15
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_22__SHIFT 0x16
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_23__SHIFT 0x17
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_24__SHIFT 0x18
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_25__SHIFT 0x19
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_26__SHIFT 0x1a
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_27__SHIFT 0x1b
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_28__SHIFT 0x1c
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_29__SHIFT 0x1d
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_30__SHIFT 0x1e
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_31__SHIFT 0x1f
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromRASCntl_MASK 0x00000001L
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromAPML_MASK 0x00000002L
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromPin_MASK 0x00000004L
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromPrivate_MASK 0x00000010L
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_8_MASK 0x00000100L
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_9_MASK 0x00000200L
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_10_MASK 0x00000400L
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_11_MASK 0x00000800L
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_12_MASK 0x00001000L
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_13_MASK 0x00002000L
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_14_MASK 0x00004000L
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_15_MASK 0x00008000L
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_16_MASK 0x00010000L
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_17_MASK 0x00020000L
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_18_MASK 0x00040000L
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_19_MASK 0x00080000L
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_20_MASK 0x00100000L
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_21_MASK 0x00200000L
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_22_MASK 0x00400000L
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_23_MASK 0x00800000L
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_24_MASK 0x01000000L
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_25_MASK 0x02000000L
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_26_MASK 0x04000000L
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_27_MASK 0x08000000L
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_28_MASK 0x10000000L
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_29_MASK 0x20000000L
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_30_MASK 0x40000000L
+#define PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_31_MASK 0x80000000L
+//PSP_INTERNAL_POISON_STATUS
+#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_0__SHIFT 0x0
+#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_1__SHIFT 0x1
+#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_2__SHIFT 0x2
+#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_3__SHIFT 0x3
+#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_4__SHIFT 0x4
+#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_5__SHIFT 0x5
+#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_6__SHIFT 0x6
+#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_7__SHIFT 0x7
+#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_0_MASK 0x00000001L
+#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_1_MASK 0x00000002L
+#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_2_MASK 0x00000004L
+#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_3_MASK 0x00000008L
+#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_4_MASK 0x00000010L
+#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_5_MASK 0x00000020L
+#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_6_MASK 0x00000040L
+#define PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_7_MASK 0x00000080L
+//PSP_EGRESS_POISON_STATUS_LO
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_0__SHIFT 0x0
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_1__SHIFT 0x1
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_2__SHIFT 0x2
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_3__SHIFT 0x3
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_4__SHIFT 0x4
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_5__SHIFT 0x5
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_6__SHIFT 0x6
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_7__SHIFT 0x7
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_8__SHIFT 0x8
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_9__SHIFT 0x9
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_10__SHIFT 0xa
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_11__SHIFT 0xb
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_12__SHIFT 0xc
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_13__SHIFT 0xd
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_14__SHIFT 0xe
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_15__SHIFT 0xf
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_16__SHIFT 0x10
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_17__SHIFT 0x11
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_18__SHIFT 0x12
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_19__SHIFT 0x13
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_20__SHIFT 0x14
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_21__SHIFT 0x15
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_22__SHIFT 0x16
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_23__SHIFT 0x17
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_24__SHIFT 0x18
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_25__SHIFT 0x19
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_26__SHIFT 0x1a
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_27__SHIFT 0x1b
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_28__SHIFT 0x1c
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_29__SHIFT 0x1d
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_30__SHIFT 0x1e
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_31__SHIFT 0x1f
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_0_MASK 0x00000001L
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_1_MASK 0x00000002L
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_2_MASK 0x00000004L
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_3_MASK 0x00000008L
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_4_MASK 0x00000010L
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_5_MASK 0x00000020L
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_6_MASK 0x00000040L
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_7_MASK 0x00000080L
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_8_MASK 0x00000100L
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_9_MASK 0x00000200L
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_10_MASK 0x00000400L
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_11_MASK 0x00000800L
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_12_MASK 0x00001000L
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_13_MASK 0x00002000L
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_14_MASK 0x00004000L
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_15_MASK 0x00008000L
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_16_MASK 0x00010000L
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_17_MASK 0x00020000L
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_18_MASK 0x00040000L
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_19_MASK 0x00080000L
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_20_MASK 0x00100000L
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_21_MASK 0x00200000L
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_22_MASK 0x00400000L
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_23_MASK 0x00800000L
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_24_MASK 0x01000000L
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_25_MASK 0x02000000L
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_26_MASK 0x04000000L
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_27_MASK 0x08000000L
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_28_MASK 0x10000000L
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_29_MASK 0x20000000L
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_30_MASK 0x40000000L
+#define PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_31_MASK 0x80000000L
+//PSP_EGRESS_POISON_STATUS_HI
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_0__SHIFT 0x0
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_1__SHIFT 0x1
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_2__SHIFT 0x2
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_3__SHIFT 0x3
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_4__SHIFT 0x4
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_5__SHIFT 0x5
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_6__SHIFT 0x6
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_7__SHIFT 0x7
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_8__SHIFT 0x8
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_9__SHIFT 0x9
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_10__SHIFT 0xa
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_11__SHIFT 0xb
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_12__SHIFT 0xc
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_13__SHIFT 0xd
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_14__SHIFT 0xe
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_15__SHIFT 0xf
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_16__SHIFT 0x10
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_17__SHIFT 0x11
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_18__SHIFT 0x12
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_19__SHIFT 0x13
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_20__SHIFT 0x14
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_21__SHIFT 0x15
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_22__SHIFT 0x16
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_23__SHIFT 0x17
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_24__SHIFT 0x18
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_25__SHIFT 0x19
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_26__SHIFT 0x1a
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_27__SHIFT 0x1b
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_28__SHIFT 0x1c
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_29__SHIFT 0x1d
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_30__SHIFT 0x1e
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_31__SHIFT 0x1f
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_0_MASK 0x00000001L
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_1_MASK 0x00000002L
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_2_MASK 0x00000004L
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_3_MASK 0x00000008L
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_4_MASK 0x00000010L
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_5_MASK 0x00000020L
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_6_MASK 0x00000040L
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_7_MASK 0x00000080L
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_8_MASK 0x00000100L
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_9_MASK 0x00000200L
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_10_MASK 0x00000400L
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_11_MASK 0x00000800L
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_12_MASK 0x00001000L
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_13_MASK 0x00002000L
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_14_MASK 0x00004000L
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_15_MASK 0x00008000L
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_16_MASK 0x00010000L
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_17_MASK 0x00020000L
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_18_MASK 0x00040000L
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_19_MASK 0x00080000L
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_20_MASK 0x00100000L
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_21_MASK 0x00200000L
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_22_MASK 0x00400000L
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_23_MASK 0x00800000L
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_24_MASK 0x01000000L
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_25_MASK 0x02000000L
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_26_MASK 0x04000000L
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_27_MASK 0x08000000L
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_28_MASK 0x10000000L
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_29_MASK 0x20000000L
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_30_MASK 0x40000000L
+#define PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_31_MASK 0x80000000L
+//PSP_PARITY_CONTROL_0
+#define PSP_PARITY_CONTROL_0__PspParityCorrThreshold__SHIFT 0x0
+#define PSP_PARITY_CONTROL_0__PspParityUCPThreshold__SHIFT 0x10
+#define PSP_PARITY_CONTROL_0__PspParityCorrThreshold_MASK 0x0000FFFFL
+#define PSP_PARITY_CONTROL_0__PspParityUCPThreshold_MASK 0xFFFF0000L
+//PSP_PARITY_STATUS
+#define PSP_PARITY_STATUS__ParityErrCorr__SHIFT 0x0
+#define PSP_PARITY_STATUS__ParityErrNonFatal__SHIFT 0x1
+#define PSP_PARITY_STATUS__ParityErrFatal__SHIFT 0x2
+#define PSP_PARITY_STATUS__ParityErrSerr__SHIFT 0x3
+#define PSP_PARITY_STATUS__ParityErrCorr_MASK 0x00000001L
+#define PSP_PARITY_STATUS__ParityErrNonFatal_MASK 0x00000002L
+#define PSP_PARITY_STATUS__ParityErrFatal_MASK 0x00000004L
+#define PSP_PARITY_STATUS__ParityErrSerr_MASK 0x00000008L
+//PSP_PARITY_ERROR_STATUS_UNCORR_GRP0
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id0__SHIFT 0x0
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id1__SHIFT 0x1
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id2__SHIFT 0x2
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id3__SHIFT 0x3
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id4__SHIFT 0x4
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id5__SHIFT 0x5
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id6__SHIFT 0x6
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id7__SHIFT 0x7
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id8__SHIFT 0x8
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id9__SHIFT 0x9
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id10__SHIFT 0xa
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id11__SHIFT 0xb
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id12__SHIFT 0xc
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id13__SHIFT 0xd
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id14__SHIFT 0xe
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id15__SHIFT 0xf
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id16__SHIFT 0x10
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id17__SHIFT 0x11
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id18__SHIFT 0x12
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id19__SHIFT 0x13
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id20__SHIFT 0x14
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id21__SHIFT 0x15
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id22__SHIFT 0x16
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id23__SHIFT 0x17
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id24__SHIFT 0x18
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id25__SHIFT 0x19
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id26__SHIFT 0x1a
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id27__SHIFT 0x1b
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id28__SHIFT 0x1c
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id29__SHIFT 0x1d
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id30__SHIFT 0x1e
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id31__SHIFT 0x1f
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id0_MASK 0x00000001L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id1_MASK 0x00000002L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id2_MASK 0x00000004L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id3_MASK 0x00000008L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id4_MASK 0x00000010L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id5_MASK 0x00000020L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id6_MASK 0x00000040L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id7_MASK 0x00000080L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id8_MASK 0x00000100L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id9_MASK 0x00000200L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id10_MASK 0x00000400L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id11_MASK 0x00000800L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id12_MASK 0x00001000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id13_MASK 0x00002000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id14_MASK 0x00004000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id15_MASK 0x00008000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id16_MASK 0x00010000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id17_MASK 0x00020000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id18_MASK 0x00040000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id19_MASK 0x00080000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id20_MASK 0x00100000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id21_MASK 0x00200000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id22_MASK 0x00400000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id23_MASK 0x00800000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id24_MASK 0x01000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id25_MASK 0x02000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id26_MASK 0x04000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id27_MASK 0x08000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id28_MASK 0x10000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id29_MASK 0x20000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id30_MASK 0x40000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id31_MASK 0x80000000L
+//PSP_PARITY_ERROR_STATUS_UNCORR_GRP1
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id0__SHIFT 0x0
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id1__SHIFT 0x1
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id2__SHIFT 0x2
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id3__SHIFT 0x3
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id4__SHIFT 0x4
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id5__SHIFT 0x5
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id6__SHIFT 0x6
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id7__SHIFT 0x7
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id8__SHIFT 0x8
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id9__SHIFT 0x9
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id10__SHIFT 0xa
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id11__SHIFT 0xb
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id12__SHIFT 0xc
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id13__SHIFT 0xd
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id14__SHIFT 0xe
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id15__SHIFT 0xf
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id16__SHIFT 0x10
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id17__SHIFT 0x11
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id18__SHIFT 0x12
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id19__SHIFT 0x13
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id20__SHIFT 0x14
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id21__SHIFT 0x15
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id22__SHIFT 0x16
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id23__SHIFT 0x17
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id24__SHIFT 0x18
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id25__SHIFT 0x19
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id26__SHIFT 0x1a
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id27__SHIFT 0x1b
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id28__SHIFT 0x1c
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id29__SHIFT 0x1d
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id30__SHIFT 0x1e
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id31__SHIFT 0x1f
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id0_MASK 0x00000001L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id1_MASK 0x00000002L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id2_MASK 0x00000004L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id3_MASK 0x00000008L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id4_MASK 0x00000010L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id5_MASK 0x00000020L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id6_MASK 0x00000040L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id7_MASK 0x00000080L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id8_MASK 0x00000100L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id9_MASK 0x00000200L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id10_MASK 0x00000400L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id11_MASK 0x00000800L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id12_MASK 0x00001000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id13_MASK 0x00002000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id14_MASK 0x00004000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id15_MASK 0x00008000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id16_MASK 0x00010000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id17_MASK 0x00020000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id18_MASK 0x00040000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id19_MASK 0x00080000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id20_MASK 0x00100000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id21_MASK 0x00200000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id22_MASK 0x00400000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id23_MASK 0x00800000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id24_MASK 0x01000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id25_MASK 0x02000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id26_MASK 0x04000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id27_MASK 0x08000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id28_MASK 0x10000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id29_MASK 0x20000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id30_MASK 0x40000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id31_MASK 0x80000000L
+//PSP_PARITY_ERROR_STATUS_UNCORR_GRP2
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id0__SHIFT 0x0
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id1__SHIFT 0x1
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id2__SHIFT 0x2
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id3__SHIFT 0x3
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id4__SHIFT 0x4
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id5__SHIFT 0x5
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id6__SHIFT 0x6
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id7__SHIFT 0x7
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id8__SHIFT 0x8
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id9__SHIFT 0x9
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id10__SHIFT 0xa
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id11__SHIFT 0xb
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id12__SHIFT 0xc
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id13__SHIFT 0xd
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id14__SHIFT 0xe
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id15__SHIFT 0xf
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id16__SHIFT 0x10
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id17__SHIFT 0x11
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id18__SHIFT 0x12
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id19__SHIFT 0x13
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id20__SHIFT 0x14
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id21__SHIFT 0x15
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id22__SHIFT 0x16
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id23__SHIFT 0x17
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id24__SHIFT 0x18
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id25__SHIFT 0x19
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id26__SHIFT 0x1a
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id27__SHIFT 0x1b
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id28__SHIFT 0x1c
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id29__SHIFT 0x1d
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id30__SHIFT 0x1e
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id31__SHIFT 0x1f
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id0_MASK 0x00000001L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id1_MASK 0x00000002L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id2_MASK 0x00000004L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id3_MASK 0x00000008L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id4_MASK 0x00000010L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id5_MASK 0x00000020L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id6_MASK 0x00000040L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id7_MASK 0x00000080L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id8_MASK 0x00000100L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id9_MASK 0x00000200L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id10_MASK 0x00000400L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id11_MASK 0x00000800L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id12_MASK 0x00001000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id13_MASK 0x00002000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id14_MASK 0x00004000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id15_MASK 0x00008000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id16_MASK 0x00010000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id17_MASK 0x00020000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id18_MASK 0x00040000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id19_MASK 0x00080000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id20_MASK 0x00100000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id21_MASK 0x00200000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id22_MASK 0x00400000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id23_MASK 0x00800000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id24_MASK 0x01000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id25_MASK 0x02000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id26_MASK 0x04000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id27_MASK 0x08000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id28_MASK 0x10000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id29_MASK 0x20000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id30_MASK 0x40000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id31_MASK 0x80000000L
+//PSP_PARITY_ERROR_STATUS_UNCORR_GRP3
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id0__SHIFT 0x0
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id1__SHIFT 0x1
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id2__SHIFT 0x2
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id3__SHIFT 0x3
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id4__SHIFT 0x4
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id5__SHIFT 0x5
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id6__SHIFT 0x6
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id7__SHIFT 0x7
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id8__SHIFT 0x8
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id9__SHIFT 0x9
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id10__SHIFT 0xa
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id11__SHIFT 0xb
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id12__SHIFT 0xc
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id13__SHIFT 0xd
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id14__SHIFT 0xe
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id15__SHIFT 0xf
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id16__SHIFT 0x10
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id17__SHIFT 0x11
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id18__SHIFT 0x12
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id19__SHIFT 0x13
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id20__SHIFT 0x14
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id21__SHIFT 0x15
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id22__SHIFT 0x16
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id23__SHIFT 0x17
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id24__SHIFT 0x18
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id25__SHIFT 0x19
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id26__SHIFT 0x1a
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id27__SHIFT 0x1b
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id28__SHIFT 0x1c
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id29__SHIFT 0x1d
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id30__SHIFT 0x1e
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id31__SHIFT 0x1f
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id0_MASK 0x00000001L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id1_MASK 0x00000002L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id2_MASK 0x00000004L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id3_MASK 0x00000008L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id4_MASK 0x00000010L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id5_MASK 0x00000020L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id6_MASK 0x00000040L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id7_MASK 0x00000080L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id8_MASK 0x00000100L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id9_MASK 0x00000200L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id10_MASK 0x00000400L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id11_MASK 0x00000800L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id12_MASK 0x00001000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id13_MASK 0x00002000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id14_MASK 0x00004000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id15_MASK 0x00008000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id16_MASK 0x00010000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id17_MASK 0x00020000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id18_MASK 0x00040000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id19_MASK 0x00080000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id20_MASK 0x00100000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id21_MASK 0x00200000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id22_MASK 0x00400000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id23_MASK 0x00800000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id24_MASK 0x01000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id25_MASK 0x02000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id26_MASK 0x04000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id27_MASK 0x08000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id28_MASK 0x10000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id29_MASK 0x20000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id30_MASK 0x40000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id31_MASK 0x80000000L
+//PSP_PARITY_ERROR_STATUS_UNCORR_GRP4
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id0__SHIFT 0x0
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id1__SHIFT 0x1
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id2__SHIFT 0x2
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id3__SHIFT 0x3
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id4__SHIFT 0x4
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id5__SHIFT 0x5
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id6__SHIFT 0x6
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id7__SHIFT 0x7
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id8__SHIFT 0x8
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id9__SHIFT 0x9
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id10__SHIFT 0xa
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id11__SHIFT 0xb
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id12__SHIFT 0xc
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id13__SHIFT 0xd
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id14__SHIFT 0xe
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id15__SHIFT 0xf
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id16__SHIFT 0x10
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id17__SHIFT 0x11
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id18__SHIFT 0x12
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id19__SHIFT 0x13
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id20__SHIFT 0x14
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id21__SHIFT 0x15
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id22__SHIFT 0x16
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id23__SHIFT 0x17
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id24__SHIFT 0x18
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id25__SHIFT 0x19
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id26__SHIFT 0x1a
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id27__SHIFT 0x1b
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id28__SHIFT 0x1c
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id29__SHIFT 0x1d
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id30__SHIFT 0x1e
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id31__SHIFT 0x1f
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id0_MASK 0x00000001L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id1_MASK 0x00000002L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id2_MASK 0x00000004L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id3_MASK 0x00000008L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id4_MASK 0x00000010L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id5_MASK 0x00000020L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id6_MASK 0x00000040L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id7_MASK 0x00000080L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id8_MASK 0x00000100L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id9_MASK 0x00000200L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id10_MASK 0x00000400L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id11_MASK 0x00000800L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id12_MASK 0x00001000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id13_MASK 0x00002000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id14_MASK 0x00004000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id15_MASK 0x00008000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id16_MASK 0x00010000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id17_MASK 0x00020000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id18_MASK 0x00040000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id19_MASK 0x00080000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id20_MASK 0x00100000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id21_MASK 0x00200000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id22_MASK 0x00400000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id23_MASK 0x00800000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id24_MASK 0x01000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id25_MASK 0x02000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id26_MASK 0x04000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id27_MASK 0x08000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id28_MASK 0x10000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id29_MASK 0x20000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id30_MASK 0x40000000L
+#define PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id31_MASK 0x80000000L
+//PSP_PARITY_ERROR_STATUS_UCP_GRP0
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id0__SHIFT 0x0
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id1__SHIFT 0x1
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id2__SHIFT 0x2
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id3__SHIFT 0x3
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id4__SHIFT 0x4
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id5__SHIFT 0x5
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id6__SHIFT 0x6
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id7__SHIFT 0x7
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id8__SHIFT 0x8
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id9__SHIFT 0x9
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id10__SHIFT 0xa
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id11__SHIFT 0xb
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id12__SHIFT 0xc
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id13__SHIFT 0xd
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id14__SHIFT 0xe
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id15__SHIFT 0xf
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id16__SHIFT 0x10
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id17__SHIFT 0x11
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id18__SHIFT 0x12
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id19__SHIFT 0x13
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id20__SHIFT 0x14
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id21__SHIFT 0x15
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id22__SHIFT 0x16
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id23__SHIFT 0x17
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id24__SHIFT 0x18
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id25__SHIFT 0x19
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id26__SHIFT 0x1a
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id27__SHIFT 0x1b
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id28__SHIFT 0x1c
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id29__SHIFT 0x1d
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id30__SHIFT 0x1e
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id31__SHIFT 0x1f
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id0_MASK 0x00000001L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id1_MASK 0x00000002L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id2_MASK 0x00000004L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id3_MASK 0x00000008L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id4_MASK 0x00000010L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id5_MASK 0x00000020L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id6_MASK 0x00000040L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id7_MASK 0x00000080L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id8_MASK 0x00000100L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id9_MASK 0x00000200L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id10_MASK 0x00000400L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id11_MASK 0x00000800L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id12_MASK 0x00001000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id13_MASK 0x00002000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id14_MASK 0x00004000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id15_MASK 0x00008000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id16_MASK 0x00010000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id17_MASK 0x00020000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id18_MASK 0x00040000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id19_MASK 0x00080000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id20_MASK 0x00100000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id21_MASK 0x00200000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id22_MASK 0x00400000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id23_MASK 0x00800000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id24_MASK 0x01000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id25_MASK 0x02000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id26_MASK 0x04000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id27_MASK 0x08000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id28_MASK 0x10000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id29_MASK 0x20000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id30_MASK 0x40000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id31_MASK 0x80000000L
+//PSP_PARITY_ERROR_STATUS_UCP_GRP1
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id0__SHIFT 0x0
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id1__SHIFT 0x1
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id2__SHIFT 0x2
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id3__SHIFT 0x3
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id4__SHIFT 0x4
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id5__SHIFT 0x5
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id6__SHIFT 0x6
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id7__SHIFT 0x7
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id8__SHIFT 0x8
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id9__SHIFT 0x9
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id10__SHIFT 0xa
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id11__SHIFT 0xb
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id12__SHIFT 0xc
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id13__SHIFT 0xd
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id14__SHIFT 0xe
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id15__SHIFT 0xf
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id16__SHIFT 0x10
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id17__SHIFT 0x11
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id18__SHIFT 0x12
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id19__SHIFT 0x13
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id20__SHIFT 0x14
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id21__SHIFT 0x15
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id22__SHIFT 0x16
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id23__SHIFT 0x17
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id24__SHIFT 0x18
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id25__SHIFT 0x19
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id26__SHIFT 0x1a
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id27__SHIFT 0x1b
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id28__SHIFT 0x1c
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id29__SHIFT 0x1d
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id30__SHIFT 0x1e
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id31__SHIFT 0x1f
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id0_MASK 0x00000001L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id1_MASK 0x00000002L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id2_MASK 0x00000004L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id3_MASK 0x00000008L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id4_MASK 0x00000010L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id5_MASK 0x00000020L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id6_MASK 0x00000040L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id7_MASK 0x00000080L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id8_MASK 0x00000100L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id9_MASK 0x00000200L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id10_MASK 0x00000400L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id11_MASK 0x00000800L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id12_MASK 0x00001000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id13_MASK 0x00002000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id14_MASK 0x00004000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id15_MASK 0x00008000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id16_MASK 0x00010000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id17_MASK 0x00020000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id18_MASK 0x00040000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id19_MASK 0x00080000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id20_MASK 0x00100000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id21_MASK 0x00200000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id22_MASK 0x00400000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id23_MASK 0x00800000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id24_MASK 0x01000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id25_MASK 0x02000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id26_MASK 0x04000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id27_MASK 0x08000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id28_MASK 0x10000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id29_MASK 0x20000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id30_MASK 0x40000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id31_MASK 0x80000000L
+//PSP_PARITY_ERROR_STATUS_UCP_GRP2
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id0__SHIFT 0x0
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id1__SHIFT 0x1
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id2__SHIFT 0x2
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id3__SHIFT 0x3
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id4__SHIFT 0x4
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id5__SHIFT 0x5
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id6__SHIFT 0x6
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id7__SHIFT 0x7
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id8__SHIFT 0x8
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id9__SHIFT 0x9
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id10__SHIFT 0xa
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id11__SHIFT 0xb
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id12__SHIFT 0xc
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id13__SHIFT 0xd
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id14__SHIFT 0xe
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id15__SHIFT 0xf
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id16__SHIFT 0x10
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id17__SHIFT 0x11
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id18__SHIFT 0x12
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id19__SHIFT 0x13
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id20__SHIFT 0x14
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id21__SHIFT 0x15
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id22__SHIFT 0x16
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id23__SHIFT 0x17
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id24__SHIFT 0x18
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id25__SHIFT 0x19
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id26__SHIFT 0x1a
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id27__SHIFT 0x1b
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id28__SHIFT 0x1c
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id29__SHIFT 0x1d
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id30__SHIFT 0x1e
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id31__SHIFT 0x1f
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id0_MASK 0x00000001L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id1_MASK 0x00000002L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id2_MASK 0x00000004L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id3_MASK 0x00000008L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id4_MASK 0x00000010L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id5_MASK 0x00000020L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id6_MASK 0x00000040L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id7_MASK 0x00000080L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id8_MASK 0x00000100L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id9_MASK 0x00000200L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id10_MASK 0x00000400L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id11_MASK 0x00000800L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id12_MASK 0x00001000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id13_MASK 0x00002000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id14_MASK 0x00004000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id15_MASK 0x00008000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id16_MASK 0x00010000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id17_MASK 0x00020000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id18_MASK 0x00040000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id19_MASK 0x00080000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id20_MASK 0x00100000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id21_MASK 0x00200000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id22_MASK 0x00400000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id23_MASK 0x00800000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id24_MASK 0x01000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id25_MASK 0x02000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id26_MASK 0x04000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id27_MASK 0x08000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id28_MASK 0x10000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id29_MASK 0x20000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id30_MASK 0x40000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id31_MASK 0x80000000L
+//PSP_PARITY_ERROR_STATUS_UCP_GRP3
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id0__SHIFT 0x0
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id1__SHIFT 0x1
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id2__SHIFT 0x2
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id3__SHIFT 0x3
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id4__SHIFT 0x4
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id5__SHIFT 0x5
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id6__SHIFT 0x6
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id7__SHIFT 0x7
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id8__SHIFT 0x8
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id9__SHIFT 0x9
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id10__SHIFT 0xa
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id11__SHIFT 0xb
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id12__SHIFT 0xc
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id13__SHIFT 0xd
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id14__SHIFT 0xe
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id15__SHIFT 0xf
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id16__SHIFT 0x10
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id17__SHIFT 0x11
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id18__SHIFT 0x12
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id19__SHIFT 0x13
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id20__SHIFT 0x14
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id21__SHIFT 0x15
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id22__SHIFT 0x16
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id23__SHIFT 0x17
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id24__SHIFT 0x18
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id25__SHIFT 0x19
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id26__SHIFT 0x1a
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id27__SHIFT 0x1b
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id28__SHIFT 0x1c
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id29__SHIFT 0x1d
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id30__SHIFT 0x1e
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id31__SHIFT 0x1f
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id0_MASK 0x00000001L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id1_MASK 0x00000002L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id2_MASK 0x00000004L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id3_MASK 0x00000008L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id4_MASK 0x00000010L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id5_MASK 0x00000020L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id6_MASK 0x00000040L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id7_MASK 0x00000080L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id8_MASK 0x00000100L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id9_MASK 0x00000200L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id10_MASK 0x00000400L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id11_MASK 0x00000800L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id12_MASK 0x00001000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id13_MASK 0x00002000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id14_MASK 0x00004000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id15_MASK 0x00008000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id16_MASK 0x00010000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id17_MASK 0x00020000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id18_MASK 0x00040000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id19_MASK 0x00080000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id20_MASK 0x00100000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id21_MASK 0x00200000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id22_MASK 0x00400000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id23_MASK 0x00800000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id24_MASK 0x01000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id25_MASK 0x02000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id26_MASK 0x04000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id27_MASK 0x08000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id28_MASK 0x10000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id29_MASK 0x20000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id30_MASK 0x40000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id31_MASK 0x80000000L
+//PSP_PARITY_ERROR_STATUS_UCP_GRP4
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id0__SHIFT 0x0
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id1__SHIFT 0x1
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id2__SHIFT 0x2
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id3__SHIFT 0x3
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id4__SHIFT 0x4
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id5__SHIFT 0x5
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id6__SHIFT 0x6
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id7__SHIFT 0x7
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id8__SHIFT 0x8
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id9__SHIFT 0x9
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id10__SHIFT 0xa
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id11__SHIFT 0xb
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id12__SHIFT 0xc
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id13__SHIFT 0xd
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id14__SHIFT 0xe
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id15__SHIFT 0xf
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id16__SHIFT 0x10
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id17__SHIFT 0x11
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id18__SHIFT 0x12
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id19__SHIFT 0x13
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id20__SHIFT 0x14
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id21__SHIFT 0x15
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id22__SHIFT 0x16
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id23__SHIFT 0x17
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id24__SHIFT 0x18
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id25__SHIFT 0x19
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id26__SHIFT 0x1a
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id27__SHIFT 0x1b
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id28__SHIFT 0x1c
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id29__SHIFT 0x1d
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id30__SHIFT 0x1e
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id31__SHIFT 0x1f
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id0_MASK 0x00000001L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id1_MASK 0x00000002L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id2_MASK 0x00000004L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id3_MASK 0x00000008L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id4_MASK 0x00000010L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id5_MASK 0x00000020L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id6_MASK 0x00000040L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id7_MASK 0x00000080L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id8_MASK 0x00000100L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id9_MASK 0x00000200L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id10_MASK 0x00000400L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id11_MASK 0x00000800L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id12_MASK 0x00001000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id13_MASK 0x00002000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id14_MASK 0x00004000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id15_MASK 0x00008000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id16_MASK 0x00010000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id17_MASK 0x00020000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id18_MASK 0x00040000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id19_MASK 0x00080000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id20_MASK 0x00100000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id21_MASK 0x00200000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id22_MASK 0x00400000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id23_MASK 0x00800000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id24_MASK 0x01000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id25_MASK 0x02000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id26_MASK 0x04000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id27_MASK 0x08000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id28_MASK 0x10000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id29_MASK 0x20000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id30_MASK 0x40000000L
+#define PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id31_MASK 0x80000000L
+//PSP_PARITY_COUNTER_UCP_GRP0
+#define PSP_PARITY_COUNTER_UCP_GRP0__ThresholdCounter__SHIFT 0x0
+#define PSP_PARITY_COUNTER_UCP_GRP0__ResetEn__SHIFT 0x1f
+#define PSP_PARITY_COUNTER_UCP_GRP0__ThresholdCounter_MASK 0x0000FFFFL
+#define PSP_PARITY_COUNTER_UCP_GRP0__ResetEn_MASK 0x80000000L
+//PSP_PARITY_COUNTER_UCP_GRP1
+#define PSP_PARITY_COUNTER_UCP_GRP1__ThresholdCounter__SHIFT 0x0
+#define PSP_PARITY_COUNTER_UCP_GRP1__ResetEn__SHIFT 0x1f
+#define PSP_PARITY_COUNTER_UCP_GRP1__ThresholdCounter_MASK 0x0000FFFFL
+#define PSP_PARITY_COUNTER_UCP_GRP1__ResetEn_MASK 0x80000000L
+//PSP_PARITY_COUNTER_UCP_GRP2
+#define PSP_PARITY_COUNTER_UCP_GRP2__ThresholdCounter__SHIFT 0x0
+#define PSP_PARITY_COUNTER_UCP_GRP2__ResetEn__SHIFT 0x1f
+#define PSP_PARITY_COUNTER_UCP_GRP2__ThresholdCounter_MASK 0x0000FFFFL
+#define PSP_PARITY_COUNTER_UCP_GRP2__ResetEn_MASK 0x80000000L
+//PSP_PARITY_COUNTER_UCP_GRP3
+#define PSP_PARITY_COUNTER_UCP_GRP3__ThresholdCounter__SHIFT 0x0
+#define PSP_PARITY_COUNTER_UCP_GRP3__ResetEn__SHIFT 0x1f
+#define PSP_PARITY_COUNTER_UCP_GRP3__ThresholdCounter_MASK 0x0000FFFFL
+#define PSP_PARITY_COUNTER_UCP_GRP3__ResetEn_MASK 0x80000000L
+//PSP_PARITY_COUNTER_UCP_GRP4
+#define PSP_PARITY_COUNTER_UCP_GRP4__ThresholdCounter__SHIFT 0x0
+#define PSP_PARITY_COUNTER_UCP_GRP4__ResetEn__SHIFT 0x1f
+#define PSP_PARITY_COUNTER_UCP_GRP4__ThresholdCounter_MASK 0x0000FFFFL
+#define PSP_PARITY_COUNTER_UCP_GRP4__ResetEn_MASK 0x80000000L
+//PSP_PARITY_ERROR_STATUS_CORR_GRP0
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id0__SHIFT 0x0
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id1__SHIFT 0x1
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id2__SHIFT 0x2
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id3__SHIFT 0x3
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id4__SHIFT 0x4
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id5__SHIFT 0x5
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id6__SHIFT 0x6
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id7__SHIFT 0x7
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id8__SHIFT 0x8
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id9__SHIFT 0x9
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id10__SHIFT 0xa
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id11__SHIFT 0xb
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id12__SHIFT 0xc
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id13__SHIFT 0xd
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id14__SHIFT 0xe
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id15__SHIFT 0xf
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id16__SHIFT 0x10
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id17__SHIFT 0x11
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id18__SHIFT 0x12
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id19__SHIFT 0x13
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id20__SHIFT 0x14
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id21__SHIFT 0x15
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id22__SHIFT 0x16
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id23__SHIFT 0x17
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id24__SHIFT 0x18
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id25__SHIFT 0x19
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id26__SHIFT 0x1a
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id27__SHIFT 0x1b
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id28__SHIFT 0x1c
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id29__SHIFT 0x1d
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id30__SHIFT 0x1e
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id31__SHIFT 0x1f
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id0_MASK 0x00000001L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id1_MASK 0x00000002L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id2_MASK 0x00000004L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id3_MASK 0x00000008L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id4_MASK 0x00000010L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id5_MASK 0x00000020L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id6_MASK 0x00000040L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id7_MASK 0x00000080L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id8_MASK 0x00000100L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id9_MASK 0x00000200L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id10_MASK 0x00000400L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id11_MASK 0x00000800L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id12_MASK 0x00001000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id13_MASK 0x00002000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id14_MASK 0x00004000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id15_MASK 0x00008000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id16_MASK 0x00010000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id17_MASK 0x00020000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id18_MASK 0x00040000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id19_MASK 0x00080000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id20_MASK 0x00100000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id21_MASK 0x00200000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id22_MASK 0x00400000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id23_MASK 0x00800000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id24_MASK 0x01000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id25_MASK 0x02000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id26_MASK 0x04000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id27_MASK 0x08000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id28_MASK 0x10000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id29_MASK 0x20000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id30_MASK 0x40000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id31_MASK 0x80000000L
+//PSP_PARITY_ERROR_STATUS_CORR_GRP1
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id0__SHIFT 0x0
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id1__SHIFT 0x1
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id2__SHIFT 0x2
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id3__SHIFT 0x3
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id4__SHIFT 0x4
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id5__SHIFT 0x5
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id6__SHIFT 0x6
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id7__SHIFT 0x7
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id8__SHIFT 0x8
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id9__SHIFT 0x9
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id10__SHIFT 0xa
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id11__SHIFT 0xb
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id12__SHIFT 0xc
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id13__SHIFT 0xd
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id14__SHIFT 0xe
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id15__SHIFT 0xf
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id16__SHIFT 0x10
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id17__SHIFT 0x11
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id18__SHIFT 0x12
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id19__SHIFT 0x13
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id20__SHIFT 0x14
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id21__SHIFT 0x15
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id22__SHIFT 0x16
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id23__SHIFT 0x17
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id24__SHIFT 0x18
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id25__SHIFT 0x19
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id26__SHIFT 0x1a
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id27__SHIFT 0x1b
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id28__SHIFT 0x1c
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id29__SHIFT 0x1d
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id30__SHIFT 0x1e
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id31__SHIFT 0x1f
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id0_MASK 0x00000001L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id1_MASK 0x00000002L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id2_MASK 0x00000004L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id3_MASK 0x00000008L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id4_MASK 0x00000010L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id5_MASK 0x00000020L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id6_MASK 0x00000040L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id7_MASK 0x00000080L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id8_MASK 0x00000100L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id9_MASK 0x00000200L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id10_MASK 0x00000400L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id11_MASK 0x00000800L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id12_MASK 0x00001000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id13_MASK 0x00002000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id14_MASK 0x00004000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id15_MASK 0x00008000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id16_MASK 0x00010000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id17_MASK 0x00020000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id18_MASK 0x00040000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id19_MASK 0x00080000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id20_MASK 0x00100000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id21_MASK 0x00200000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id22_MASK 0x00400000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id23_MASK 0x00800000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id24_MASK 0x01000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id25_MASK 0x02000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id26_MASK 0x04000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id27_MASK 0x08000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id28_MASK 0x10000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id29_MASK 0x20000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id30_MASK 0x40000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id31_MASK 0x80000000L
+//PSP_PARITY_ERROR_STATUS_CORR_GRP2
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id0__SHIFT 0x0
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id1__SHIFT 0x1
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id2__SHIFT 0x2
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id3__SHIFT 0x3
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id4__SHIFT 0x4
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id5__SHIFT 0x5
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id6__SHIFT 0x6
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id7__SHIFT 0x7
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id8__SHIFT 0x8
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id9__SHIFT 0x9
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id10__SHIFT 0xa
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id11__SHIFT 0xb
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id12__SHIFT 0xc
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id13__SHIFT 0xd
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id14__SHIFT 0xe
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id15__SHIFT 0xf
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id16__SHIFT 0x10
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id17__SHIFT 0x11
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id18__SHIFT 0x12
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id19__SHIFT 0x13
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id20__SHIFT 0x14
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id21__SHIFT 0x15
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id22__SHIFT 0x16
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id23__SHIFT 0x17
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id24__SHIFT 0x18
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id25__SHIFT 0x19
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id26__SHIFT 0x1a
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id27__SHIFT 0x1b
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id28__SHIFT 0x1c
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id29__SHIFT 0x1d
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id30__SHIFT 0x1e
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id31__SHIFT 0x1f
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id0_MASK 0x00000001L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id1_MASK 0x00000002L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id2_MASK 0x00000004L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id3_MASK 0x00000008L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id4_MASK 0x00000010L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id5_MASK 0x00000020L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id6_MASK 0x00000040L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id7_MASK 0x00000080L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id8_MASK 0x00000100L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id9_MASK 0x00000200L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id10_MASK 0x00000400L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id11_MASK 0x00000800L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id12_MASK 0x00001000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id13_MASK 0x00002000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id14_MASK 0x00004000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id15_MASK 0x00008000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id16_MASK 0x00010000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id17_MASK 0x00020000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id18_MASK 0x00040000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id19_MASK 0x00080000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id20_MASK 0x00100000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id21_MASK 0x00200000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id22_MASK 0x00400000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id23_MASK 0x00800000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id24_MASK 0x01000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id25_MASK 0x02000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id26_MASK 0x04000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id27_MASK 0x08000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id28_MASK 0x10000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id29_MASK 0x20000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id30_MASK 0x40000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id31_MASK 0x80000000L
+//PSP_PARITY_ERROR_STATUS_CORR_GRP3
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id0__SHIFT 0x0
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id1__SHIFT 0x1
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id2__SHIFT 0x2
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id3__SHIFT 0x3
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id4__SHIFT 0x4
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id5__SHIFT 0x5
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id6__SHIFT 0x6
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id7__SHIFT 0x7
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id8__SHIFT 0x8
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id9__SHIFT 0x9
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id10__SHIFT 0xa
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id11__SHIFT 0xb
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id12__SHIFT 0xc
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id13__SHIFT 0xd
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id14__SHIFT 0xe
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id15__SHIFT 0xf
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id16__SHIFT 0x10
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id17__SHIFT 0x11
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id18__SHIFT 0x12
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id19__SHIFT 0x13
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id20__SHIFT 0x14
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id21__SHIFT 0x15
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id22__SHIFT 0x16
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id23__SHIFT 0x17
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id24__SHIFT 0x18
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id25__SHIFT 0x19
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id26__SHIFT 0x1a
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id27__SHIFT 0x1b
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id28__SHIFT 0x1c
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id29__SHIFT 0x1d
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id30__SHIFT 0x1e
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id31__SHIFT 0x1f
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id0_MASK 0x00000001L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id1_MASK 0x00000002L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id2_MASK 0x00000004L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id3_MASK 0x00000008L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id4_MASK 0x00000010L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id5_MASK 0x00000020L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id6_MASK 0x00000040L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id7_MASK 0x00000080L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id8_MASK 0x00000100L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id9_MASK 0x00000200L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id10_MASK 0x00000400L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id11_MASK 0x00000800L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id12_MASK 0x00001000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id13_MASK 0x00002000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id14_MASK 0x00004000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id15_MASK 0x00008000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id16_MASK 0x00010000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id17_MASK 0x00020000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id18_MASK 0x00040000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id19_MASK 0x00080000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id20_MASK 0x00100000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id21_MASK 0x00200000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id22_MASK 0x00400000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id23_MASK 0x00800000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id24_MASK 0x01000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id25_MASK 0x02000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id26_MASK 0x04000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id27_MASK 0x08000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id28_MASK 0x10000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id29_MASK 0x20000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id30_MASK 0x40000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id31_MASK 0x80000000L
+//PSP_PARITY_ERROR_STATUS_CORR_GRP4
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id0__SHIFT 0x0
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id1__SHIFT 0x1
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id2__SHIFT 0x2
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id3__SHIFT 0x3
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id4__SHIFT 0x4
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id5__SHIFT 0x5
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id6__SHIFT 0x6
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id7__SHIFT 0x7
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id8__SHIFT 0x8
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id9__SHIFT 0x9
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id10__SHIFT 0xa
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id11__SHIFT 0xb
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id12__SHIFT 0xc
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id13__SHIFT 0xd
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id14__SHIFT 0xe
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id15__SHIFT 0xf
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id16__SHIFT 0x10
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id17__SHIFT 0x11
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id18__SHIFT 0x12
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id19__SHIFT 0x13
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id20__SHIFT 0x14
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id21__SHIFT 0x15
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id22__SHIFT 0x16
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id23__SHIFT 0x17
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id24__SHIFT 0x18
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id25__SHIFT 0x19
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id26__SHIFT 0x1a
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id27__SHIFT 0x1b
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id28__SHIFT 0x1c
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id29__SHIFT 0x1d
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id30__SHIFT 0x1e
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id31__SHIFT 0x1f
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id0_MASK 0x00000001L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id1_MASK 0x00000002L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id2_MASK 0x00000004L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id3_MASK 0x00000008L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id4_MASK 0x00000010L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id5_MASK 0x00000020L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id6_MASK 0x00000040L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id7_MASK 0x00000080L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id8_MASK 0x00000100L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id9_MASK 0x00000200L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id10_MASK 0x00000400L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id11_MASK 0x00000800L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id12_MASK 0x00001000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id13_MASK 0x00002000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id14_MASK 0x00004000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id15_MASK 0x00008000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id16_MASK 0x00010000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id17_MASK 0x00020000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id18_MASK 0x00040000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id19_MASK 0x00080000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id20_MASK 0x00100000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id21_MASK 0x00200000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id22_MASK 0x00400000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id23_MASK 0x00800000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id24_MASK 0x01000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id25_MASK 0x02000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id26_MASK 0x04000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id27_MASK 0x08000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id28_MASK 0x10000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id29_MASK 0x20000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id30_MASK 0x40000000L
+#define PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id31_MASK 0x80000000L
+//PSP_PARITY_COUNTER_CORR_GRP0
+#define PSP_PARITY_COUNTER_CORR_GRP0__ThresholdCounter__SHIFT 0x0
+#define PSP_PARITY_COUNTER_CORR_GRP0__ResetEn__SHIFT 0x1f
+#define PSP_PARITY_COUNTER_CORR_GRP0__ThresholdCounter_MASK 0x0000FFFFL
+#define PSP_PARITY_COUNTER_CORR_GRP0__ResetEn_MASK 0x80000000L
+//PSP_PARITY_COUNTER_CORR_GRP1
+#define PSP_PARITY_COUNTER_CORR_GRP1__ThresholdCounter__SHIFT 0x0
+#define PSP_PARITY_COUNTER_CORR_GRP1__ResetEn__SHIFT 0x1f
+#define PSP_PARITY_COUNTER_CORR_GRP1__ThresholdCounter_MASK 0x0000FFFFL
+#define PSP_PARITY_COUNTER_CORR_GRP1__ResetEn_MASK 0x80000000L
+//PSP_PARITY_COUNTER_CORR_GRP2
+#define PSP_PARITY_COUNTER_CORR_GRP2__ThresholdCounter__SHIFT 0x0
+#define PSP_PARITY_COUNTER_CORR_GRP2__ResetEn__SHIFT 0x1f
+#define PSP_PARITY_COUNTER_CORR_GRP2__ThresholdCounter_MASK 0x0000FFFFL
+#define PSP_PARITY_COUNTER_CORR_GRP2__ResetEn_MASK 0x80000000L
+//PSP_PARITY_COUNTER_CORR_GRP3
+#define PSP_PARITY_COUNTER_CORR_GRP3__ThresholdCounter__SHIFT 0x0
+#define PSP_PARITY_COUNTER_CORR_GRP3__ResetEn__SHIFT 0x1f
+#define PSP_PARITY_COUNTER_CORR_GRP3__ThresholdCounter_MASK 0x0000FFFFL
+#define PSP_PARITY_COUNTER_CORR_GRP3__ResetEn_MASK 0x80000000L
+//PSP_PARITY_COUNTER_CORR_GRP4
+#define PSP_PARITY_COUNTER_CORR_GRP4__ThresholdCounter__SHIFT 0x0
+#define PSP_PARITY_COUNTER_CORR_GRP4__ResetEn__SHIFT 0x1f
+#define PSP_PARITY_COUNTER_CORR_GRP4__ThresholdCounter_MASK 0x0000FFFFL
+#define PSP_PARITY_COUNTER_CORR_GRP4__ResetEn_MASK 0x80000000L
+//PSP_ParitySerr_ACTION_CONTROL
+#define PSP_ParitySerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PSP_ParitySerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+//PSP_ParityFatal_ACTION_CONTROL
+#define PSP_ParityFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PSP_ParityFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+//PSP_ParityNonFatal_ACTION_CONTROL
+#define PSP_ParityNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PSP_ParityNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+//PSP_ParityCorr_ACTION_CONTROL
+#define PSP_ParityCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PSP_ParityCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+
+
+// addressBlock: nbio_iohub_nb_PCIE0devindcfg0_devind_cfgdecp
+//NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__BridgeDis__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__BusMasterDis__SHIFT 0x1
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__CfgDis__SHIFT 0x2
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__P2pDis__SHIFT 0x3
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__VDMDis__SHIFT 0x5
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__MaskUR_Enable__SHIFT 0x6
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__PassPWDis__SHIFT 0x7
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__NoSnoopDis__SHIFT 0x8
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__ForceRspPassPw__SHIFT 0x9
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__IDOMode__SHIFT 0xa
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__ExtDevPlug__SHIFT 0x10
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__ExtDevCrsEn__SHIFT 0x11
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__CrsEnable__SHIFT 0x12
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__APIC_Enable__SHIFT 0x17
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__APIC_Range__SHIFT 0x18
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__BridgeDis_MASK 0x00000001L
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__BusMasterDis_MASK 0x00000002L
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__CfgDis_MASK 0x00000004L
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__P2pDis_MASK 0x00000008L
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__VDMDis_MASK 0x00000020L
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__MaskUR_Enable_MASK 0x00000040L
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__PassPWDis_MASK 0x00000080L
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__NoSnoopDis_MASK 0x00000100L
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__ForceRspPassPw_MASK 0x00000200L
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__IDOMode_MASK 0x00000C00L
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__ExtDevPlug_MASK 0x00010000L
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__ExtDevCrsEn_MASK 0x00020000L
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__CrsEnable_MASK 0x00040000L
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__APIC_Enable_MASK 0x00800000L
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL__APIC_Range_MASK 0xFF000000L
+//NB_PCIE0DEVINDCFG0_IOHC_Bridge_STATUS
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_STATUS__MaskUR_Status__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_STATUS__MaskUR_Status_MASK 0x00000001L
+//NB_PCIE0DEVINDCFG0_STEERING_CNTL
+#define NB_PCIE0DEVINDCFG0_STEERING_CNTL__ForceSteering__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG0_STEERING_CNTL__SteeringValue__SHIFT 0x8
+#define NB_PCIE0DEVINDCFG0_STEERING_CNTL__ForceSteering_MASK 0x00000001L
+#define NB_PCIE0DEVINDCFG0_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L
+//NB_PCIE0DEVINDCFG0_IOHC_Bridge_SCRATCH_0
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_SCRATCH_0__SCRATCH_0__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL
+//NB_PCIE0DEVINDCFG0_IOHC_Bridge_SCRATCH_1
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_SCRATCH_1__SCRATCH_1__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG0_IOHC_Bridge_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_iohub_nb_PCIE0devindcfg1_devind_cfgdecp
+//NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__BridgeDis__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__BusMasterDis__SHIFT 0x1
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__CfgDis__SHIFT 0x2
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__P2pDis__SHIFT 0x3
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__VDMDis__SHIFT 0x5
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__MaskUR_Enable__SHIFT 0x6
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__PassPWDis__SHIFT 0x7
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__NoSnoopDis__SHIFT 0x8
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__ForceRspPassPw__SHIFT 0x9
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__IDOMode__SHIFT 0xa
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__ExtDevPlug__SHIFT 0x10
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__ExtDevCrsEn__SHIFT 0x11
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__CrsEnable__SHIFT 0x12
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__APIC_Enable__SHIFT 0x17
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__APIC_Range__SHIFT 0x18
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__BridgeDis_MASK 0x00000001L
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__BusMasterDis_MASK 0x00000002L
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__CfgDis_MASK 0x00000004L
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__P2pDis_MASK 0x00000008L
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__VDMDis_MASK 0x00000020L
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__MaskUR_Enable_MASK 0x00000040L
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__PassPWDis_MASK 0x00000080L
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__NoSnoopDis_MASK 0x00000100L
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__ForceRspPassPw_MASK 0x00000200L
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__IDOMode_MASK 0x00000C00L
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__ExtDevPlug_MASK 0x00010000L
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__ExtDevCrsEn_MASK 0x00020000L
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__CrsEnable_MASK 0x00040000L
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__APIC_Enable_MASK 0x00800000L
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL__APIC_Range_MASK 0xFF000000L
+//NB_PCIE0DEVINDCFG1_IOHC_Bridge_STATUS
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_STATUS__MaskUR_Status__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_STATUS__MaskUR_Status_MASK 0x00000001L
+//NB_PCIE0DEVINDCFG1_STEERING_CNTL
+#define NB_PCIE0DEVINDCFG1_STEERING_CNTL__ForceSteering__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG1_STEERING_CNTL__SteeringValue__SHIFT 0x8
+#define NB_PCIE0DEVINDCFG1_STEERING_CNTL__ForceSteering_MASK 0x00000001L
+#define NB_PCIE0DEVINDCFG1_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L
+//NB_PCIE0DEVINDCFG1_IOHC_Bridge_SCRATCH_0
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_SCRATCH_0__SCRATCH_0__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL
+//NB_PCIE0DEVINDCFG1_IOHC_Bridge_SCRATCH_1
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_SCRATCH_1__SCRATCH_1__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG1_IOHC_Bridge_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_iohub_nb_PCIE0devindcfg2_devind_cfgdecp
+//NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__BridgeDis__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__BusMasterDis__SHIFT 0x1
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__CfgDis__SHIFT 0x2
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__P2pDis__SHIFT 0x3
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__VDMDis__SHIFT 0x5
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__MaskUR_Enable__SHIFT 0x6
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__PassPWDis__SHIFT 0x7
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__NoSnoopDis__SHIFT 0x8
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__ForceRspPassPw__SHIFT 0x9
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__IDOMode__SHIFT 0xa
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__ExtDevPlug__SHIFT 0x10
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__ExtDevCrsEn__SHIFT 0x11
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__CrsEnable__SHIFT 0x12
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__APIC_Enable__SHIFT 0x17
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__APIC_Range__SHIFT 0x18
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__BridgeDis_MASK 0x00000001L
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__BusMasterDis_MASK 0x00000002L
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__CfgDis_MASK 0x00000004L
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__P2pDis_MASK 0x00000008L
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__VDMDis_MASK 0x00000020L
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__MaskUR_Enable_MASK 0x00000040L
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__PassPWDis_MASK 0x00000080L
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__NoSnoopDis_MASK 0x00000100L
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__ForceRspPassPw_MASK 0x00000200L
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__IDOMode_MASK 0x00000C00L
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__ExtDevPlug_MASK 0x00010000L
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__ExtDevCrsEn_MASK 0x00020000L
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__CrsEnable_MASK 0x00040000L
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__APIC_Enable_MASK 0x00800000L
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL__APIC_Range_MASK 0xFF000000L
+//NB_PCIE0DEVINDCFG2_IOHC_Bridge_STATUS
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_STATUS__MaskUR_Status__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_STATUS__MaskUR_Status_MASK 0x00000001L
+//NB_PCIE0DEVINDCFG2_STEERING_CNTL
+#define NB_PCIE0DEVINDCFG2_STEERING_CNTL__ForceSteering__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG2_STEERING_CNTL__SteeringValue__SHIFT 0x8
+#define NB_PCIE0DEVINDCFG2_STEERING_CNTL__ForceSteering_MASK 0x00000001L
+#define NB_PCIE0DEVINDCFG2_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L
+//NB_PCIE0DEVINDCFG2_IOHC_Bridge_SCRATCH_0
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_SCRATCH_0__SCRATCH_0__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL
+//NB_PCIE0DEVINDCFG2_IOHC_Bridge_SCRATCH_1
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_SCRATCH_1__SCRATCH_1__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG2_IOHC_Bridge_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_iohub_nb_PCIE0devindcfg3_devind_cfgdecp
+//NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__BridgeDis__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__BusMasterDis__SHIFT 0x1
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__CfgDis__SHIFT 0x2
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__P2pDis__SHIFT 0x3
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__VDMDis__SHIFT 0x5
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__MaskUR_Enable__SHIFT 0x6
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__PassPWDis__SHIFT 0x7
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__NoSnoopDis__SHIFT 0x8
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__ForceRspPassPw__SHIFT 0x9
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__IDOMode__SHIFT 0xa
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__ExtDevPlug__SHIFT 0x10
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__ExtDevCrsEn__SHIFT 0x11
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__CrsEnable__SHIFT 0x12
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__APIC_Enable__SHIFT 0x17
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__APIC_Range__SHIFT 0x18
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__BridgeDis_MASK 0x00000001L
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__BusMasterDis_MASK 0x00000002L
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__CfgDis_MASK 0x00000004L
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__P2pDis_MASK 0x00000008L
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__VDMDis_MASK 0x00000020L
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__MaskUR_Enable_MASK 0x00000040L
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__PassPWDis_MASK 0x00000080L
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__NoSnoopDis_MASK 0x00000100L
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__ForceRspPassPw_MASK 0x00000200L
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__IDOMode_MASK 0x00000C00L
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__ExtDevPlug_MASK 0x00010000L
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__ExtDevCrsEn_MASK 0x00020000L
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__CrsEnable_MASK 0x00040000L
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__APIC_Enable_MASK 0x00800000L
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL__APIC_Range_MASK 0xFF000000L
+//NB_PCIE0DEVINDCFG3_IOHC_Bridge_STATUS
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_STATUS__MaskUR_Status__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_STATUS__MaskUR_Status_MASK 0x00000001L
+//NB_PCIE0DEVINDCFG3_STEERING_CNTL
+#define NB_PCIE0DEVINDCFG3_STEERING_CNTL__ForceSteering__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG3_STEERING_CNTL__SteeringValue__SHIFT 0x8
+#define NB_PCIE0DEVINDCFG3_STEERING_CNTL__ForceSteering_MASK 0x00000001L
+#define NB_PCIE0DEVINDCFG3_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L
+//NB_PCIE0DEVINDCFG3_IOHC_Bridge_SCRATCH_0
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_SCRATCH_0__SCRATCH_0__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL
+//NB_PCIE0DEVINDCFG3_IOHC_Bridge_SCRATCH_1
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_SCRATCH_1__SCRATCH_1__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG3_IOHC_Bridge_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_iohub_nb_PCIE0devindcfg4_devind_cfgdecp
+//NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__BridgeDis__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__BusMasterDis__SHIFT 0x1
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__CfgDis__SHIFT 0x2
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__P2pDis__SHIFT 0x3
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__VDMDis__SHIFT 0x5
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__MaskUR_Enable__SHIFT 0x6
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__PassPWDis__SHIFT 0x7
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__NoSnoopDis__SHIFT 0x8
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__ForceRspPassPw__SHIFT 0x9
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__IDOMode__SHIFT 0xa
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__ExtDevPlug__SHIFT 0x10
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__ExtDevCrsEn__SHIFT 0x11
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__CrsEnable__SHIFT 0x12
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__APIC_Enable__SHIFT 0x17
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__APIC_Range__SHIFT 0x18
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__BridgeDis_MASK 0x00000001L
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__BusMasterDis_MASK 0x00000002L
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__CfgDis_MASK 0x00000004L
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__P2pDis_MASK 0x00000008L
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__VDMDis_MASK 0x00000020L
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__MaskUR_Enable_MASK 0x00000040L
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__PassPWDis_MASK 0x00000080L
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__NoSnoopDis_MASK 0x00000100L
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__ForceRspPassPw_MASK 0x00000200L
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__IDOMode_MASK 0x00000C00L
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__ExtDevPlug_MASK 0x00010000L
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__ExtDevCrsEn_MASK 0x00020000L
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__CrsEnable_MASK 0x00040000L
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__APIC_Enable_MASK 0x00800000L
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL__APIC_Range_MASK 0xFF000000L
+//NB_PCIE0DEVINDCFG4_IOHC_Bridge_STATUS
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_STATUS__MaskUR_Status__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_STATUS__MaskUR_Status_MASK 0x00000001L
+//NB_PCIE0DEVINDCFG4_STEERING_CNTL
+#define NB_PCIE0DEVINDCFG4_STEERING_CNTL__ForceSteering__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG4_STEERING_CNTL__SteeringValue__SHIFT 0x8
+#define NB_PCIE0DEVINDCFG4_STEERING_CNTL__ForceSteering_MASK 0x00000001L
+#define NB_PCIE0DEVINDCFG4_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L
+//NB_PCIE0DEVINDCFG4_IOHC_Bridge_SCRATCH_0
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_SCRATCH_0__SCRATCH_0__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL
+//NB_PCIE0DEVINDCFG4_IOHC_Bridge_SCRATCH_1
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_SCRATCH_1__SCRATCH_1__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG4_IOHC_Bridge_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_iohub_nb_PCIE0devindcfg5_devind_cfgdecp
+//NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__BridgeDis__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__BusMasterDis__SHIFT 0x1
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__CfgDis__SHIFT 0x2
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__P2pDis__SHIFT 0x3
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__VDMDis__SHIFT 0x5
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__MaskUR_Enable__SHIFT 0x6
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__PassPWDis__SHIFT 0x7
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__NoSnoopDis__SHIFT 0x8
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__ForceRspPassPw__SHIFT 0x9
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__IDOMode__SHIFT 0xa
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__ExtDevPlug__SHIFT 0x10
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__ExtDevCrsEn__SHIFT 0x11
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__CrsEnable__SHIFT 0x12
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__APIC_Enable__SHIFT 0x17
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__APIC_Range__SHIFT 0x18
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__BridgeDis_MASK 0x00000001L
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__BusMasterDis_MASK 0x00000002L
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__CfgDis_MASK 0x00000004L
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__P2pDis_MASK 0x00000008L
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__VDMDis_MASK 0x00000020L
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__MaskUR_Enable_MASK 0x00000040L
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__PassPWDis_MASK 0x00000080L
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__NoSnoopDis_MASK 0x00000100L
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__ForceRspPassPw_MASK 0x00000200L
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__IDOMode_MASK 0x00000C00L
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__ExtDevPlug_MASK 0x00010000L
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__ExtDevCrsEn_MASK 0x00020000L
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__CrsEnable_MASK 0x00040000L
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__APIC_Enable_MASK 0x00800000L
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL__APIC_Range_MASK 0xFF000000L
+//NB_PCIE0DEVINDCFG5_IOHC_Bridge_STATUS
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_STATUS__MaskUR_Status__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_STATUS__MaskUR_Status_MASK 0x00000001L
+//NB_PCIE0DEVINDCFG5_STEERING_CNTL
+#define NB_PCIE0DEVINDCFG5_STEERING_CNTL__ForceSteering__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG5_STEERING_CNTL__SteeringValue__SHIFT 0x8
+#define NB_PCIE0DEVINDCFG5_STEERING_CNTL__ForceSteering_MASK 0x00000001L
+#define NB_PCIE0DEVINDCFG5_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L
+//NB_PCIE0DEVINDCFG5_IOHC_Bridge_SCRATCH_0
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_SCRATCH_0__SCRATCH_0__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL
+//NB_PCIE0DEVINDCFG5_IOHC_Bridge_SCRATCH_1
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_SCRATCH_1__SCRATCH_1__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG5_IOHC_Bridge_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_iohub_nb_PCIE0devindcfg6_devind_cfgdecp
+//NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__BridgeDis__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__BusMasterDis__SHIFT 0x1
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__CfgDis__SHIFT 0x2
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__P2pDis__SHIFT 0x3
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__VDMDis__SHIFT 0x5
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__MaskUR_Enable__SHIFT 0x6
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__PassPWDis__SHIFT 0x7
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__NoSnoopDis__SHIFT 0x8
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__ForceRspPassPw__SHIFT 0x9
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__IDOMode__SHIFT 0xa
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__ExtDevPlug__SHIFT 0x10
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__ExtDevCrsEn__SHIFT 0x11
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__CrsEnable__SHIFT 0x12
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__APIC_Enable__SHIFT 0x17
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__APIC_Range__SHIFT 0x18
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__BridgeDis_MASK 0x00000001L
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__BusMasterDis_MASK 0x00000002L
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__CfgDis_MASK 0x00000004L
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__P2pDis_MASK 0x00000008L
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__VDMDis_MASK 0x00000020L
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__MaskUR_Enable_MASK 0x00000040L
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__PassPWDis_MASK 0x00000080L
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__NoSnoopDis_MASK 0x00000100L
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__ForceRspPassPw_MASK 0x00000200L
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__IDOMode_MASK 0x00000C00L
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__ExtDevPlug_MASK 0x00010000L
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__ExtDevCrsEn_MASK 0x00020000L
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__CrsEnable_MASK 0x00040000L
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__APIC_Enable_MASK 0x00800000L
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL__APIC_Range_MASK 0xFF000000L
+//NB_PCIE0DEVINDCFG6_IOHC_Bridge_STATUS
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_STATUS__MaskUR_Status__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_STATUS__MaskUR_Status_MASK 0x00000001L
+//NB_PCIE0DEVINDCFG6_STEERING_CNTL
+#define NB_PCIE0DEVINDCFG6_STEERING_CNTL__ForceSteering__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG6_STEERING_CNTL__SteeringValue__SHIFT 0x8
+#define NB_PCIE0DEVINDCFG6_STEERING_CNTL__ForceSteering_MASK 0x00000001L
+#define NB_PCIE0DEVINDCFG6_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L
+//NB_PCIE0DEVINDCFG6_IOHC_Bridge_SCRATCH_0
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_SCRATCH_0__SCRATCH_0__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL
+//NB_PCIE0DEVINDCFG6_IOHC_Bridge_SCRATCH_1
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_SCRATCH_1__SCRATCH_1__SHIFT 0x0
+#define NB_PCIE0DEVINDCFG6_IOHC_Bridge_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_iohub_nb_NBIF1devindcfg0_devind_cfgdecp
+//NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__BridgeDis__SHIFT 0x0
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__BusMasterDis__SHIFT 0x1
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__CfgDis__SHIFT 0x2
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__P2pDis__SHIFT 0x3
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__VDMDis__SHIFT 0x5
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__MaskUR_Enable__SHIFT 0x6
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__PassPWDis__SHIFT 0x7
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__NoSnoopDis__SHIFT 0x8
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__ForceRspPassPw__SHIFT 0x9
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__IDOMode__SHIFT 0xa
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__ExtDevPlug__SHIFT 0x10
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__ExtDevCrsEn__SHIFT 0x11
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__CrsEnable__SHIFT 0x12
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__APIC_Enable__SHIFT 0x17
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__APIC_Range__SHIFT 0x18
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__BridgeDis_MASK 0x00000001L
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__BusMasterDis_MASK 0x00000002L
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__CfgDis_MASK 0x00000004L
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__P2pDis_MASK 0x00000008L
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__VDMDis_MASK 0x00000020L
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__MaskUR_Enable_MASK 0x00000040L
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__PassPWDis_MASK 0x00000080L
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__NoSnoopDis_MASK 0x00000100L
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__ForceRspPassPw_MASK 0x00000200L
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__IDOMode_MASK 0x00000C00L
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__ExtDevPlug_MASK 0x00010000L
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__ExtDevCrsEn_MASK 0x00020000L
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__CrsEnable_MASK 0x00040000L
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__APIC_Enable_MASK 0x00800000L
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL__APIC_Range_MASK 0xFF000000L
+//NB_NBIF1DEVINDCFG0_IOHC_Bridge_STATUS
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_STATUS__MaskUR_Status__SHIFT 0x0
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_STATUS__MaskUR_Status_MASK 0x00000001L
+//NB_NBIF1DEVINDCFG0_STEERING_CNTL
+#define NB_NBIF1DEVINDCFG0_STEERING_CNTL__ForceSteering__SHIFT 0x0
+#define NB_NBIF1DEVINDCFG0_STEERING_CNTL__SteeringValue__SHIFT 0x8
+#define NB_NBIF1DEVINDCFG0_STEERING_CNTL__ForceSteering_MASK 0x00000001L
+#define NB_NBIF1DEVINDCFG0_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L
+//NB_NBIF1DEVINDCFG0_IOHC_Bridge_SCRATCH_0
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_SCRATCH_0__SCRATCH_0__SHIFT 0x0
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL
+//NB_NBIF1DEVINDCFG0_IOHC_Bridge_SCRATCH_1
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_SCRATCH_1__SCRATCH_1__SHIFT 0x0
+#define NB_NBIF1DEVINDCFG0_IOHC_Bridge_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_iohub_nb_NBIF1devindcfg1_devind_cfgdecp
+//NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__BridgeDis__SHIFT 0x0
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__BusMasterDis__SHIFT 0x1
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__CfgDis__SHIFT 0x2
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__P2pDis__SHIFT 0x3
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__VDMDis__SHIFT 0x5
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__MaskUR_Enable__SHIFT 0x6
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__PassPWDis__SHIFT 0x7
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__NoSnoopDis__SHIFT 0x8
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__ForceRspPassPw__SHIFT 0x9
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__IDOMode__SHIFT 0xa
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__ExtDevPlug__SHIFT 0x10
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__ExtDevCrsEn__SHIFT 0x11
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__CrsEnable__SHIFT 0x12
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__APIC_Enable__SHIFT 0x17
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__APIC_Range__SHIFT 0x18
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__BridgeDis_MASK 0x00000001L
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__BusMasterDis_MASK 0x00000002L
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__CfgDis_MASK 0x00000004L
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__P2pDis_MASK 0x00000008L
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__VDMDis_MASK 0x00000020L
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__MaskUR_Enable_MASK 0x00000040L
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__PassPWDis_MASK 0x00000080L
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__NoSnoopDis_MASK 0x00000100L
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__ForceRspPassPw_MASK 0x00000200L
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__IDOMode_MASK 0x00000C00L
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__ExtDevPlug_MASK 0x00010000L
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__ExtDevCrsEn_MASK 0x00020000L
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__CrsEnable_MASK 0x00040000L
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__APIC_Enable_MASK 0x00800000L
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL__APIC_Range_MASK 0xFF000000L
+//NB_NBIF1DEVINDCFG1_IOHC_Bridge_STATUS
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_STATUS__MaskUR_Status__SHIFT 0x0
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_STATUS__MaskUR_Status_MASK 0x00000001L
+//NB_NBIF1DEVINDCFG1_STEERING_CNTL
+#define NB_NBIF1DEVINDCFG1_STEERING_CNTL__ForceSteering__SHIFT 0x0
+#define NB_NBIF1DEVINDCFG1_STEERING_CNTL__SteeringValue__SHIFT 0x8
+#define NB_NBIF1DEVINDCFG1_STEERING_CNTL__ForceSteering_MASK 0x00000001L
+#define NB_NBIF1DEVINDCFG1_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L
+//NB_NBIF1DEVINDCFG1_IOHC_Bridge_SCRATCH_0
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_SCRATCH_0__SCRATCH_0__SHIFT 0x0
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL
+//NB_NBIF1DEVINDCFG1_IOHC_Bridge_SCRATCH_1
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_SCRATCH_1__SCRATCH_1__SHIFT 0x0
+#define NB_NBIF1DEVINDCFG1_IOHC_Bridge_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_iohub_nb_intSBdevindcfg0_devind_cfgdecp
+//NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__BridgeDis__SHIFT 0x0
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__BusMasterDis__SHIFT 0x1
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__CfgDis__SHIFT 0x2
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__P2pDis__SHIFT 0x3
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__VDMDis__SHIFT 0x5
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__MaskUR_Enable__SHIFT 0x6
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__PassPWDis__SHIFT 0x7
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__NoSnoopDis__SHIFT 0x8
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__ForceRspPassPw__SHIFT 0x9
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__IDOMode__SHIFT 0xa
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__ExtDevPlug__SHIFT 0x10
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__ExtDevCrsEn__SHIFT 0x11
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__CrsEnable__SHIFT 0x12
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__APIC_Enable__SHIFT 0x17
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__APIC_Range__SHIFT 0x18
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__BridgeDis_MASK 0x00000001L
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__BusMasterDis_MASK 0x00000002L
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__CfgDis_MASK 0x00000004L
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__P2pDis_MASK 0x00000008L
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__VDMDis_MASK 0x00000020L
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__MaskUR_Enable_MASK 0x00000040L
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__PassPWDis_MASK 0x00000080L
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__NoSnoopDis_MASK 0x00000100L
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__ForceRspPassPw_MASK 0x00000200L
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__IDOMode_MASK 0x00000C00L
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__ExtDevPlug_MASK 0x00010000L
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__ExtDevCrsEn_MASK 0x00020000L
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__CrsEnable_MASK 0x00040000L
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__APIC_Enable_MASK 0x00800000L
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL__APIC_Range_MASK 0xFF000000L
+//NB_INTSBDEVINDCFG0_IOHC_Bridge_STATUS
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_STATUS__MaskUR_Status__SHIFT 0x0
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_STATUS__MaskUR_Status_MASK 0x00000001L
+//NB_INTSBDEVINDCFG0_STEERING_CNTL
+#define NB_INTSBDEVINDCFG0_STEERING_CNTL__ForceSteering__SHIFT 0x0
+#define NB_INTSBDEVINDCFG0_STEERING_CNTL__SteeringValue__SHIFT 0x8
+#define NB_INTSBDEVINDCFG0_STEERING_CNTL__ForceSteering_MASK 0x00000001L
+#define NB_INTSBDEVINDCFG0_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L
+//NB_INTSBDEVINDCFG0_IOHC_Bridge_SCRATCH_0
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_SCRATCH_0__SCRATCH_0__SHIFT 0x0
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL
+//NB_INTSBDEVINDCFG0_IOHC_Bridge_SCRATCH_1
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_SCRATCH_1__SCRATCH_1__SHIFT 0x0
+#define NB_INTSBDEVINDCFG0_IOHC_Bridge_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_iohub_nb_pciedummy0_pciedummy_cfgdec
+//NB_PCIEDUMMY0_1_DEVICE_VENDOR_ID
+#define NB_PCIEDUMMY0_1_DEVICE_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define NB_PCIEDUMMY0_1_DEVICE_VENDOR_ID__DEVICE_ID__SHIFT 0x10
+#define NB_PCIEDUMMY0_1_DEVICE_VENDOR_ID__VENDOR_ID_MASK 0x0000FFFFL
+#define NB_PCIEDUMMY0_1_DEVICE_VENDOR_ID__DEVICE_ID_MASK 0xFFFF0000L
+//NB_PCIEDUMMY0_1_STATUS_COMMAND
+#define NB_PCIEDUMMY0_1_STATUS_COMMAND__COMMAND__SHIFT 0x0
+#define NB_PCIEDUMMY0_1_STATUS_COMMAND__STATUS__SHIFT 0x10
+#define NB_PCIEDUMMY0_1_STATUS_COMMAND__COMMAND_MASK 0x0000FFFFL
+#define NB_PCIEDUMMY0_1_STATUS_COMMAND__STATUS_MASK 0xFFFF0000L
+//NB_PCIEDUMMY0_1_CLASS_CODE_REVID
+#define NB_PCIEDUMMY0_1_CLASS_CODE_REVID__REVID__SHIFT 0x0
+#define NB_PCIEDUMMY0_1_CLASS_CODE_REVID__CLASS_CODE__SHIFT 0x8
+#define NB_PCIEDUMMY0_1_CLASS_CODE_REVID__REVID_MASK 0x000000FFL
+#define NB_PCIEDUMMY0_1_CLASS_CODE_REVID__CLASS_CODE_MASK 0xFFFFFF00L
+//NB_PCIEDUMMY0_1_HEADER_TYPE
+#define NB_PCIEDUMMY0_1_HEADER_TYPE__HEADER_TYPE__SHIFT 0x10
+#define NB_PCIEDUMMY0_1_HEADER_TYPE__DEVICE_TYPE__SHIFT 0x17
+#define NB_PCIEDUMMY0_1_HEADER_TYPE__HEADER_TYPE_MASK 0x007F0000L
+#define NB_PCIEDUMMY0_1_HEADER_TYPE__DEVICE_TYPE_MASK 0x00800000L
+//NB_PCIEDUMMY0_1_HEADER_TYPE_W
+#define NB_PCIEDUMMY0_1_HEADER_TYPE_W__DEVICE_TYPE__SHIFT 0x7
+#define NB_PCIEDUMMY0_1_HEADER_TYPE_W__DEVICE_TYPE_MASK 0x00000080L
+
+
+// addressBlock: nbio_iohub_nb_pciedummy1_pciedummy_cfgdec
+//NB_PCIEDUMMY1_1_DEVICE_VENDOR_ID
+#define NB_PCIEDUMMY1_1_DEVICE_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define NB_PCIEDUMMY1_1_DEVICE_VENDOR_ID__DEVICE_ID__SHIFT 0x10
+#define NB_PCIEDUMMY1_1_DEVICE_VENDOR_ID__VENDOR_ID_MASK 0x0000FFFFL
+#define NB_PCIEDUMMY1_1_DEVICE_VENDOR_ID__DEVICE_ID_MASK 0xFFFF0000L
+//NB_PCIEDUMMY1_1_STATUS_COMMAND
+#define NB_PCIEDUMMY1_1_STATUS_COMMAND__COMMAND__SHIFT 0x0
+#define NB_PCIEDUMMY1_1_STATUS_COMMAND__STATUS__SHIFT 0x10
+#define NB_PCIEDUMMY1_1_STATUS_COMMAND__COMMAND_MASK 0x0000FFFFL
+#define NB_PCIEDUMMY1_1_STATUS_COMMAND__STATUS_MASK 0xFFFF0000L
+//NB_PCIEDUMMY1_1_CLASS_CODE_REVID
+#define NB_PCIEDUMMY1_1_CLASS_CODE_REVID__REVID__SHIFT 0x0
+#define NB_PCIEDUMMY1_1_CLASS_CODE_REVID__CLASS_CODE__SHIFT 0x8
+#define NB_PCIEDUMMY1_1_CLASS_CODE_REVID__REVID_MASK 0x000000FFL
+#define NB_PCIEDUMMY1_1_CLASS_CODE_REVID__CLASS_CODE_MASK 0xFFFFFF00L
+//NB_PCIEDUMMY1_1_HEADER_TYPE
+#define NB_PCIEDUMMY1_1_HEADER_TYPE__HEADER_TYPE__SHIFT 0x10
+#define NB_PCIEDUMMY1_1_HEADER_TYPE__DEVICE_TYPE__SHIFT 0x17
+#define NB_PCIEDUMMY1_1_HEADER_TYPE__HEADER_TYPE_MASK 0x007F0000L
+#define NB_PCIEDUMMY1_1_HEADER_TYPE__DEVICE_TYPE_MASK 0x00800000L
+//NB_PCIEDUMMY1_1_HEADER_TYPE_W
+#define NB_PCIEDUMMY1_1_HEADER_TYPE_W__DEVICE_TYPE__SHIFT 0x7
+#define NB_PCIEDUMMY1_1_HEADER_TYPE_W__DEVICE_TYPE_MASK 0x00000080L
+
+
+// addressBlock: nbio_iohub_iommu_indcfg_iommuind_cfgdec
+//IOMMU_SMN_INDEX_0
+#define IOMMU_SMN_INDEX_0__IOMMU_SMN_INDEX_0__SHIFT 0x0
+#define IOMMU_SMN_INDEX_0__IOMMU_SMN_INDEX_0_MASK 0xFFFFFFFFL
+//IOMMU_SMN_DATA_0
+#define IOMMU_SMN_DATA_0__IOMMU_SMN_DATA_0__SHIFT 0x0
+#define IOMMU_SMN_DATA_0__IOMMU_SMN_DATA_0_MASK 0xFFFFFFFFL
+//IOMMU_SMN_INDEX_1
+#define IOMMU_SMN_INDEX_1__IOMMU_SMN_INDEX_1__SHIFT 0x0
+#define IOMMU_SMN_INDEX_1__IOMMU_SMN_INDEX_1_MASK 0xFFFFFFFFL
+//IOMMU_SMN_DATA_1
+#define IOMMU_SMN_DATA_1__IOMMU_SMN_DATA_1__SHIFT 0x0
+#define IOMMU_SMN_DATA_1__IOMMU_SMN_DATA_1_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_iohub_ioapic_indcfg_ioapicind_cfgdec
+//IOAPIC_MIO_INDEX
+#define IOAPIC_MIO_INDEX__IOAPIC_MIO_INDEX_data__SHIFT 0x0
+#define IOAPIC_MIO_INDEX__IOAPIC_MIO_INDEX_data_MASK 0xFFFFFFFFL
+//IOAPIC_MIO_DATA
+#define IOAPIC_MIO_DATA__IOAPIC_MIO_DATA__SHIFT 0x0
+#define IOAPIC_MIO_DATA__IOAPIC_MIO_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg0_pciercbdgind_cfgdec
+//NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX
+#define NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0
+#define NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL
+//NB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA
+#define NB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0
+#define NB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg1_pciercbdgind_cfgdec
+//NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX
+#define NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0
+#define NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL
+//NB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA
+#define NB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0
+#define NB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg2_pciercbdgind_cfgdec
+//NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX
+#define NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0
+#define NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL
+//NB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA
+#define NB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0
+#define NB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg3_pciercbdgind_cfgdec
+//NB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX
+#define NB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0
+#define NB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL
+//NB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA
+#define NB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0
+#define NB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg4_pciercbdgind_cfgdec
+//NB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX
+#define NB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0
+#define NB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL
+//NB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA
+#define NB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0
+#define NB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg5_pciercbdgind_cfgdec
+//NB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX
+#define NB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0
+#define NB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL
+//NB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA
+#define NB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0
+#define NB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg6_pciercbdgind_cfgdec
+//NB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX
+#define NB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0
+#define NB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL
+//NB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA
+#define NB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0
+#define NB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_iohub_nb_NBIF1rcbdg_indcfg0_pciercbdgind_cfgdec
+//NB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX
+#define NB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0
+#define NB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL
+//NB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA
+#define NB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0
+#define NB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_iohub_nb_NBIF1rcbdg_indcfg1_pciercbdgind_cfgdec
+//NB_NBIF1RCBDG_INDCFG1_RC_SMN_INDEX
+#define NB_NBIF1RCBDG_INDCFG1_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0
+#define NB_NBIF1RCBDG_INDCFG1_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL
+//NB_NBIF1RCBDG_INDCFG1_RC_SMN_DATA
+#define NB_NBIF1RCBDG_INDCFG1_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0
+#define NB_NBIF1RCBDG_INDCFG1_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_iohub_iommu_l2_iommul2cfg
+//IOMMU_L2_1_IOMMU_VENDOR_ID
+#define IOMMU_L2_1_IOMMU_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//IOMMU_L2_1_IOMMU_DEVICE_ID
+#define IOMMU_L2_1_IOMMU_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//IOMMU_L2_1_IOMMU_COMMAND
+#define IOMMU_L2_1_IOMMU_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define IOMMU_L2_1_IOMMU_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define IOMMU_L2_1_IOMMU_COMMAND__Reserved1__SHIFT 0x3
+#define IOMMU_L2_1_IOMMU_COMMAND__PARITY_ERROR_EN__SHIFT 0x6
+#define IOMMU_L2_1_IOMMU_COMMAND__Reserved0__SHIFT 0x7
+#define IOMMU_L2_1_IOMMU_COMMAND__SERR_EN__SHIFT 0x8
+#define IOMMU_L2_1_IOMMU_COMMAND__Reserved2__SHIFT 0x9
+#define IOMMU_L2_1_IOMMU_COMMAND__INTERRUPT_DIS__SHIFT 0xa
+#define IOMMU_L2_1_IOMMU_COMMAND__Reserved__SHIFT 0xb
+#define IOMMU_L2_1_IOMMU_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define IOMMU_L2_1_IOMMU_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define IOMMU_L2_1_IOMMU_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define IOMMU_L2_1_IOMMU_COMMAND__Reserved1_MASK 0x0038L
+#define IOMMU_L2_1_IOMMU_COMMAND__PARITY_ERROR_EN_MASK 0x0040L
+#define IOMMU_L2_1_IOMMU_COMMAND__Reserved0_MASK 0x0080L
+#define IOMMU_L2_1_IOMMU_COMMAND__SERR_EN_MASK 0x0100L
+#define IOMMU_L2_1_IOMMU_COMMAND__Reserved2_MASK 0x0200L
+#define IOMMU_L2_1_IOMMU_COMMAND__INTERRUPT_DIS_MASK 0x0400L
+#define IOMMU_L2_1_IOMMU_COMMAND__Reserved_MASK 0xF800L
+//IOMMU_L2_1_IOMMU_STATUS
+#define IOMMU_L2_1_IOMMU_STATUS__Reserved__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_STATUS__INT_Status__SHIFT 0x3
+#define IOMMU_L2_1_IOMMU_STATUS__CAP_LIST__SHIFT 0x4
+#define IOMMU_L2_1_IOMMU_STATUS__Reserved1__SHIFT 0x5
+#define IOMMU_L2_1_IOMMU_STATUS__MASTER_DATA_ERROR__SHIFT 0x8
+#define IOMMU_L2_1_IOMMU_STATUS__Reserved2__SHIFT 0x9
+#define IOMMU_L2_1_IOMMU_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define IOMMU_L2_1_IOMMU_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define IOMMU_L2_1_IOMMU_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define IOMMU_L2_1_IOMMU_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define IOMMU_L2_1_IOMMU_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define IOMMU_L2_1_IOMMU_STATUS__Reserved_MASK 0x0007L
+#define IOMMU_L2_1_IOMMU_STATUS__INT_Status_MASK 0x0008L
+#define IOMMU_L2_1_IOMMU_STATUS__CAP_LIST_MASK 0x0010L
+#define IOMMU_L2_1_IOMMU_STATUS__Reserved1_MASK 0x00E0L
+#define IOMMU_L2_1_IOMMU_STATUS__MASTER_DATA_ERROR_MASK 0x0100L
+#define IOMMU_L2_1_IOMMU_STATUS__Reserved2_MASK 0x0600L
+#define IOMMU_L2_1_IOMMU_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define IOMMU_L2_1_IOMMU_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define IOMMU_L2_1_IOMMU_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define IOMMU_L2_1_IOMMU_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define IOMMU_L2_1_IOMMU_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//IOMMU_L2_1_IOMMU_REVISION_ID
+#define IOMMU_L2_1_IOMMU_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define IOMMU_L2_1_IOMMU_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define IOMMU_L2_1_IOMMU_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//IOMMU_L2_1_IOMMU_REGPROG_INF
+#define IOMMU_L2_1_IOMMU_REGPROG_INF__REG_LEVEL_PROG_INF__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_REGPROG_INF__REG_LEVEL_PROG_INF_MASK 0xFFL
+//IOMMU_L2_1_IOMMU_SUB_CLASS
+#define IOMMU_L2_1_IOMMU_SUB_CLASS__SUB_CLASS_INF__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_SUB_CLASS__SUB_CLASS_INF_MASK 0xFFL
+//IOMMU_L2_1_IOMMU_BASE_CODE
+#define IOMMU_L2_1_IOMMU_BASE_CODE__BASE_CLASS_CODE__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_BASE_CODE__BASE_CLASS_CODE_MASK 0xFFL
+//IOMMU_L2_1_IOMMU_CACHE_LINE
+#define IOMMU_L2_1_IOMMU_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//IOMMU_L2_1_IOMMU_LATENCY
+#define IOMMU_L2_1_IOMMU_LATENCY__LATENCY__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_LATENCY__LATENCY_MASK 0xFFL
+//IOMMU_L2_1_IOMMU_HEADER
+#define IOMMU_L2_1_IOMMU_HEADER__HEADER_TYPE__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_HEADER__HEADER_TYPE_MASK 0xFFL
+//IOMMU_L2_1_IOMMU_BIST
+#define IOMMU_L2_1_IOMMU_BIST__BIST_COMP__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_BIST__BIST_STRT__SHIFT 0x6
+#define IOMMU_L2_1_IOMMU_BIST__BIST_CAP__SHIFT 0x7
+#define IOMMU_L2_1_IOMMU_BIST__BIST_COMP_MASK 0x0FL
+#define IOMMU_L2_1_IOMMU_BIST__BIST_STRT_MASK 0x40L
+#define IOMMU_L2_1_IOMMU_BIST__BIST_CAP_MASK 0x80L
+//IOMMU_L2_1_IOMMU_ADAPTER_ID
+#define IOMMU_L2_1_IOMMU_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define IOMMU_L2_1_IOMMU_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define IOMMU_L2_1_IOMMU_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//IOMMU_L2_1_IOMMU_CAPABILITIES_PTR
+#define IOMMU_L2_1_IOMMU_CAPABILITIES_PTR__CAP_PTR__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_CAPABILITIES_PTR__CAP_PTR_MASK 0x000000FFL
+//IOMMU_L2_1_IOMMU_INTERRUPT_LINE
+#define IOMMU_L2_1_IOMMU_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//IOMMU_L2_1_IOMMU_INTERRUPT_PIN
+#define IOMMU_L2_1_IOMMU_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//IOMMU_L2_1_IOMMU_CAP_HEADER
+#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_ID__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_PTR__SHIFT 0x8
+#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_TYPE__SHIFT 0x10
+#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_REV__SHIFT 0x13
+#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_IO_TLBSUP__SHIFT 0x18
+#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_HT_TUNNEL_SUP__SHIFT 0x19
+#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_NP_CACHE__SHIFT 0x1a
+#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_EFR_SUP__SHIFT 0x1b
+#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_EXT__SHIFT 0x1c
+#define IOMMU_L2_1_IOMMU_CAP_HEADER__Reserved__SHIFT 0x1d
+#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_ID_MASK 0x000000FFL
+#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_PTR_MASK 0x0000FF00L
+#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_TYPE_MASK 0x00070000L
+#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_REV_MASK 0x00F80000L
+#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_IO_TLBSUP_MASK 0x01000000L
+#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_HT_TUNNEL_SUP_MASK 0x02000000L
+#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_NP_CACHE_MASK 0x04000000L
+#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_EFR_SUP_MASK 0x08000000L
+#define IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_EXT_MASK 0x10000000L
+#define IOMMU_L2_1_IOMMU_CAP_HEADER__Reserved_MASK 0xE0000000L
+//IOMMU_L2_1_IOMMU_CAP_BASE_LO
+#define IOMMU_L2_1_IOMMU_CAP_BASE_LO__IOMMU_ENABLE__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_CAP_BASE_LO__Reserved__SHIFT 0x1
+#define IOMMU_L2_1_IOMMU_CAP_BASE_LO__IOMMU_BASE_ADDR_LO__SHIFT 0x13
+#define IOMMU_L2_1_IOMMU_CAP_BASE_LO__IOMMU_ENABLE_MASK 0x00000001L
+#define IOMMU_L2_1_IOMMU_CAP_BASE_LO__Reserved_MASK 0x00003FFEL
+#define IOMMU_L2_1_IOMMU_CAP_BASE_LO__IOMMU_BASE_ADDR_LO_MASK 0xFFF80000L
+//IOMMU_L2_1_IOMMU_CAP_BASE_HI
+#define IOMMU_L2_1_IOMMU_CAP_BASE_HI__IOMMU_BASE_ADDR_HI__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_CAP_BASE_HI__IOMMU_BASE_ADDR_HI_MASK 0xFFFFFFFFL
+//IOMMU_L2_1_IOMMU_CAP_RANGE
+#define IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_UNIT_ID__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_CAP_RANGE__Reserved__SHIFT 0x5
+#define IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_RNG_VALID__SHIFT 0x7
+#define IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_BUS_NUMBER__SHIFT 0x8
+#define IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_FIRST_DEVICE__SHIFT 0x10
+#define IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_LAST_DEVICE__SHIFT 0x18
+#define IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_UNIT_ID_MASK 0x0000001FL
+#define IOMMU_L2_1_IOMMU_CAP_RANGE__Reserved_MASK 0x00000060L
+#define IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_RNG_VALID_MASK 0x00000080L
+#define IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_BUS_NUMBER_MASK 0x0000FF00L
+#define IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_FIRST_DEVICE_MASK 0x00FF0000L
+#define IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_LAST_DEVICE_MASK 0xFF000000L
+//IOMMU_L2_1_IOMMU_CAP_MISC
+#define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_MSI_NUM__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_GVA_SIZE__SHIFT 0x5
+#define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_PA_SIZE__SHIFT 0x8
+#define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_VA_SIZE__SHIFT 0xf
+#define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV__SHIFT 0x16
+#define IOMMU_L2_1_IOMMU_CAP_MISC__Reserved1__SHIFT 0x17
+#define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_MSI_NUM_PPR__SHIFT 0x1b
+#define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_MSI_NUM_MASK 0x0000001FL
+#define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_GVA_SIZE_MASK 0x000000E0L
+#define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_PA_SIZE_MASK 0x00007F00L
+#define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_VA_SIZE_MASK 0x003F8000L
+#define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV_MASK 0x00400000L
+#define IOMMU_L2_1_IOMMU_CAP_MISC__Reserved1_MASK 0x07800000L
+#define IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_MSI_NUM_PPR_MASK 0xF8000000L
+//IOMMU_L2_1_IOMMU_CAP_MISC_1
+#define IOMMU_L2_1_IOMMU_CAP_MISC_1__IOMMU_MSI_NUM_GA__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE__SHIFT 0x5
+#define IOMMU_L2_1_IOMMU_CAP_MISC_1__DVM_MODE__SHIFT 0x6
+#define IOMMU_L2_1_IOMMU_CAP_MISC_1__SMMUMMIO_EN__SHIFT 0xf
+#define IOMMU_L2_1_IOMMU_CAP_MISC_1__SMMUMMIO_LOCK__SHIFT 0x1f
+#define IOMMU_L2_1_IOMMU_CAP_MISC_1__IOMMU_MSI_NUM_GA_MASK 0x0000001FL
+#define IOMMU_L2_1_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE_MASK 0x00000020L
+#define IOMMU_L2_1_IOMMU_CAP_MISC_1__DVM_MODE_MASK 0x000000C0L
+#define IOMMU_L2_1_IOMMU_CAP_MISC_1__SMMUMMIO_EN_MASK 0x00008000L
+#define IOMMU_L2_1_IOMMU_CAP_MISC_1__SMMUMMIO_LOCK_MASK 0x80000000L
+//IOMMU_L2_1_IOMMU_MSI_CAP
+#define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_CAP_ID__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_CAP_PTR__SHIFT 0x8
+#define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_EN__SHIFT 0x10
+#define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_MULT_MESS_CAP__SHIFT 0x11
+#define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_MULT_MESS_EN__SHIFT 0x14
+#define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_64_EN__SHIFT 0x17
+#define IOMMU_L2_1_IOMMU_MSI_CAP__Reserved__SHIFT 0x18
+#define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_CAP_ID_MASK 0x000000FFL
+#define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_CAP_PTR_MASK 0x0000FF00L
+#define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_EN_MASK 0x00010000L
+#define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_MULT_MESS_CAP_MASK 0x000E0000L
+#define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_MULT_MESS_EN_MASK 0x00700000L
+#define IOMMU_L2_1_IOMMU_MSI_CAP__MSI_64_EN_MASK 0x00800000L
+#define IOMMU_L2_1_IOMMU_MSI_CAP__Reserved_MASK 0xFF000000L
+//IOMMU_L2_1_IOMMU_MSI_ADDR_LO
+#define IOMMU_L2_1_IOMMU_MSI_ADDR_LO__Reserved__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_MSI_ADDR_LO__MSI_ADDR_LO__SHIFT 0x2
+#define IOMMU_L2_1_IOMMU_MSI_ADDR_LO__Reserved_MASK 0x00000003L
+#define IOMMU_L2_1_IOMMU_MSI_ADDR_LO__MSI_ADDR_LO_MASK 0xFFFFFFFCL
+//IOMMU_L2_1_IOMMU_MSI_ADDR_HI
+#define IOMMU_L2_1_IOMMU_MSI_ADDR_HI__MSI_ADDR_HI__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_MSI_ADDR_HI__MSI_ADDR_HI_MASK 0xFFFFFFFFL
+//IOMMU_L2_1_IOMMU_MSI_DATA
+#define IOMMU_L2_1_IOMMU_MSI_DATA__MSI_DATA__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_MSI_DATA__Reserved__SHIFT 0x10
+#define IOMMU_L2_1_IOMMU_MSI_DATA__MSI_DATA_MASK 0x0000FFFFL
+#define IOMMU_L2_1_IOMMU_MSI_DATA__Reserved_MASK 0xFFFF0000L
+//IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP
+#define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_ID__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR__SHIFT 0x8
+#define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_EN__SHIFT 0x10
+#define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_FIXD__SHIFT 0x11
+#define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_RSV__SHIFT 0x12
+#define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE__SHIFT 0x1b
+#define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_ID_MASK 0x000000FFL
+#define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR_MASK 0x0000FF00L
+#define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_EN_MASK 0x00010000L
+#define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_FIXD_MASK 0x00020000L
+#define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_RSV_MASK 0x07FC0000L
+#define IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE_MASK 0xF8000000L
+//IOMMU_L2_1_IOMMU_ADAPTER_ID_W
+#define IOMMU_L2_1_IOMMU_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_W__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_ADAPTER_ID_W__SUBSYSTEM_ID_W__SHIFT 0x10
+#define IOMMU_L2_1_IOMMU_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_W_MASK 0x0000FFFFL
+#define IOMMU_L2_1_IOMMU_ADAPTER_ID_W__SUBSYSTEM_ID_W_MASK 0xFFFF0000L
+//IOMMU_L2_1_IOMMU_CONTROL_W
+#define IOMMU_L2_1_IOMMU_CONTROL_W__INTERRUPT_PIN_W__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_CONTROL_W__MINOR_REV_ID_W__SHIFT 0x4
+#define IOMMU_L2_1_IOMMU_CONTROL_W__IO_TLBSUP_W__SHIFT 0x8
+#define IOMMU_L2_1_IOMMU_CONTROL_W__EFR_SUP_W__SHIFT 0x9
+#define IOMMU_L2_1_IOMMU_CONTROL_W__MSI_MULT_MESS_CAP_W__SHIFT 0xa
+#define IOMMU_L2_1_IOMMU_CONTROL_W__IOMMU_CAP_EXT_W__SHIFT 0xd
+#define IOMMU_L2_1_IOMMU_CONTROL_W__INTERRUPT_PIN_W_MASK 0x00000007L
+#define IOMMU_L2_1_IOMMU_CONTROL_W__MINOR_REV_ID_W_MASK 0x000000F0L
+#define IOMMU_L2_1_IOMMU_CONTROL_W__IO_TLBSUP_W_MASK 0x00000100L
+#define IOMMU_L2_1_IOMMU_CONTROL_W__EFR_SUP_W_MASK 0x00000200L
+#define IOMMU_L2_1_IOMMU_CONTROL_W__MSI_MULT_MESS_CAP_W_MASK 0x00001C00L
+#define IOMMU_L2_1_IOMMU_CONTROL_W__IOMMU_CAP_EXT_W_MASK 0x00002000L
+//IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__PREF_SUP_W__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__PPR_SUP_W__SHIFT 0x1
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__Reserved3__SHIFT 0x2
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__NX_SUP_W__SHIFT 0x3
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__GT_SUP_W__SHIFT 0x4
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__Reserved2__SHIFT 0x5
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__IA_SUP_W__SHIFT 0x6
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__GA_SUP_W__SHIFT 0x7
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__HE_SUP_W__SHIFT 0x8
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__PC_SUP_W__SHIFT 0x9
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__HATS_W__SHIFT 0xa
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__US_SUP_W__SHIFT 0xc
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__Reserved5__SHIFT 0xd
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__GAM_SUP_W__SHIFT 0x15
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__PPRF_W__SHIFT 0x18
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__Reserved6__SHIFT 0x1a
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__EVENTF_W__SHIFT 0x1c
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__GLX_SUP_W__SHIFT 0x1e
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__PREF_SUP_W_MASK 0x00000001L
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__PPR_SUP_W_MASK 0x00000002L
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__Reserved3_MASK 0x00000004L
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__NX_SUP_W_MASK 0x00000008L
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__GT_SUP_W_MASK 0x00000010L
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__Reserved2_MASK 0x00000020L
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__IA_SUP_W_MASK 0x00000040L
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__GA_SUP_W_MASK 0x00000080L
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__HE_SUP_W_MASK 0x00000100L
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__PC_SUP_W_MASK 0x00000200L
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__HATS_W_MASK 0x00000C00L
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__US_SUP_W_MASK 0x00001000L
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__Reserved5_MASK 0x001FE000L
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__GAM_SUP_W_MASK 0x00E00000L
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__PPRF_W_MASK 0x03000000L
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__Reserved6_MASK 0x0C000000L
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__EVENTF_W_MASK 0x30000000L
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__GLX_SUP_W_MASK 0xC0000000L
+//IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__PAS_MAX_W__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__Reserved1__SHIFT 0x4
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__DTE_seg_W__SHIFT 0x6
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__PPR_OVERFLOW_EARLY_SUP_W__SHIFT 0x8
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__PPR_AUTORESP_SUP_W__SHIFT 0x9
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__BLOCK_STOPMARK_SUP_W__SHIFT 0xa
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__MARCnum_SUP_W__SHIFT 0xb
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__SNOOP_ATTRS_SUP_W__SHIFT 0xd
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__GIo_SUP_W__SHIFT 0xe
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__HA_SUP_W__SHIFT 0xf
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__EPH_SUP_W__SHIFT 0x10
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__ATTRFW_SUP_W__SHIFT 0x11
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__V2_HD_DIS_SUP_W__SHIFT 0x12
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__InvIotlbTypeSup_W__SHIFT 0x13
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__HD_SUP_W__SHIFT 0x14
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__Reserved__SHIFT 0x15
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__PAS_MAX_W_MASK 0x0000000FL
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__Reserved1_MASK 0x00000030L
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__DTE_seg_W_MASK 0x000000C0L
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__PPR_OVERFLOW_EARLY_SUP_W_MASK 0x00000100L
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__PPR_AUTORESP_SUP_W_MASK 0x00000200L
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__BLOCK_STOPMARK_SUP_W_MASK 0x00000400L
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__MARCnum_SUP_W_MASK 0x00001800L
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__SNOOP_ATTRS_SUP_W_MASK 0x00002000L
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__GIo_SUP_W_MASK 0x00004000L
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__HA_SUP_W_MASK 0x00008000L
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__EPH_SUP_W_MASK 0x00010000L
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__ATTRFW_SUP_W_MASK 0x00020000L
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__V2_HD_DIS_SUP_W_MASK 0x00040000L
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__InvIotlbTypeSup_W_MASK 0x00080000L
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__HD_SUP_W_MASK 0x00100000L
+#define IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__Reserved_MASK 0xFFE00000L
+//IOMMU_L2_1_IOMMU_RANGE_W
+#define IOMMU_L2_1_IOMMU_RANGE_W__Reserved__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_RANGE_W__RNG_VALID_W__SHIFT 0x7
+#define IOMMU_L2_1_IOMMU_RANGE_W__BUS_NUMBER_W__SHIFT 0x8
+#define IOMMU_L2_1_IOMMU_RANGE_W__FIRST_DEVICE_W__SHIFT 0x10
+#define IOMMU_L2_1_IOMMU_RANGE_W__LAST_DEVICE_W__SHIFT 0x18
+#define IOMMU_L2_1_IOMMU_RANGE_W__Reserved_MASK 0x0000007FL
+#define IOMMU_L2_1_IOMMU_RANGE_W__RNG_VALID_W_MASK 0x00000080L
+#define IOMMU_L2_1_IOMMU_RANGE_W__BUS_NUMBER_W_MASK 0x0000FF00L
+#define IOMMU_L2_1_IOMMU_RANGE_W__FIRST_DEVICE_W_MASK 0x00FF0000L
+#define IOMMU_L2_1_IOMMU_RANGE_W__LAST_DEVICE_W_MASK 0xFF000000L
+//IOMMU_L2_1_IOMMU_DSFX_CONTROL
+#define IOMMU_L2_1_IOMMU_DSFX_CONTROL__DSFXSup__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_DSFX_CONTROL__REVISION_MINOR__SHIFT 0x18
+#define IOMMU_L2_1_IOMMU_DSFX_CONTROL__REVISION_MAJOR__SHIFT 0x1c
+#define IOMMU_L2_1_IOMMU_DSFX_CONTROL__DSFXSup_MASK 0x00FFFFFFL
+#define IOMMU_L2_1_IOMMU_DSFX_CONTROL__REVISION_MINOR_MASK 0x0F000000L
+#define IOMMU_L2_1_IOMMU_DSFX_CONTROL__REVISION_MAJOR_MASK 0xF0000000L
+//IOMMU_L2_1_IOMMU_DSSX_DUMMY_0
+#define IOMMU_L2_1_IOMMU_DSSX_DUMMY_0__DSSX_status_set__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_DSSX_DUMMY_0__Reserved__SHIFT 0x18
+#define IOMMU_L2_1_IOMMU_DSSX_DUMMY_0__DSSX_status_set_MASK 0x00FFFFFFL
+#define IOMMU_L2_1_IOMMU_DSSX_DUMMY_0__Reserved_MASK 0xFF000000L
+//IOMMU_L2_1_IOMMU_DSCX_DUMMY_0
+#define IOMMU_L2_1_IOMMU_DSCX_DUMMY_0__DSCX_CNTRL_set__SHIFT 0x0
+#define IOMMU_L2_1_IOMMU_DSCX_DUMMY_0__Reserved__SHIFT 0x18
+#define IOMMU_L2_1_IOMMU_DSCX_DUMMY_0__DSCX_CNTRL_set_MASK 0x00FFFFFFL
+#define IOMMU_L2_1_IOMMU_DSCX_DUMMY_0__Reserved_MASK 0xFF000000L
+//IOMMU_L2_1_L2B_POISON_DVM_CNTRL
+#define IOMMU_L2_1_L2B_POISON_DVM_CNTRL__DVM_POISON_RESP_MODE__SHIFT 0x0
+#define IOMMU_L2_1_L2B_POISON_DVM_CNTRL__DVM_POISON_RESP_MODE_MASK 0x00000003L
+//IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control
+#define IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control__StallNPReqEn__SHIFT 0x0
+#define IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control__StallPReqEn__SHIFT 0x2
+#define IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control__StallMemReqEn__SHIFT 0x8
+#define IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn__SHIFT 0xe
+#define IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control__StallNPReqEn_MASK 0x00000003L
+#define IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control__StallPReqEn_MASK 0x0000000CL
+#define IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control__StallMemReqEn_MASK 0x00000300L
+#define IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn_MASK 0x0000C000L
+//IOMMU_L2_1_IOHC_L2_HostRsp_Stall_Control
+#define IOMMU_L2_1_IOHC_L2_HostRsp_Stall_Control__StallUpRdRspEn__SHIFT 0x4
+#define IOMMU_L2_1_IOHC_L2_HostRsp_Stall_Control__StallUpRdRspEn_MASK 0x00000030L
+//IOMMU_L2_1_SMMU_MMIO_IDR0_W
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__S2P_W__SHIFT 0x0
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__S1P_W__SHIFT 0x1
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__TTF_W__SHIFT 0x2
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__COHACC_W__SHIFT 0x4
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__BTM_W__SHIFT 0x5
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__HTTU_W__SHIFT 0x6
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__DORMHINT_W__SHIFT 0x8
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__Hyp_W__SHIFT 0x9
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__ATS_W__SHIFT 0xa
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__PERFCTRS_W__SHIFT 0xb
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__ASID16_W__SHIFT 0xc
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__MSI_W__SHIFT 0xd
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__SEV_W__SHIFT 0xe
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__ATOS_W__SHIFT 0xf
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__PRI_W__SHIFT 0x10
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__VMW_W__SHIFT 0x11
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__VMID16_W__SHIFT 0x12
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__CD2L_W__SHIFT 0x13
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__VATOS_W__SHIFT 0x14
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__TTENDIAN_W__SHIFT 0x15
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__STALL_MODEL_W__SHIFT 0x18
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__TERM_MODEL_W__SHIFT 0x1a
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__ST_LEVEL_W__SHIFT 0x1b
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__RAS_W__SHIFT 0x1d
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__S2P_W_MASK 0x00000001L
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__S1P_W_MASK 0x00000002L
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__TTF_W_MASK 0x0000000CL
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__COHACC_W_MASK 0x00000010L
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__BTM_W_MASK 0x00000020L
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__HTTU_W_MASK 0x000000C0L
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__DORMHINT_W_MASK 0x00000100L
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__Hyp_W_MASK 0x00000200L
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__ATS_W_MASK 0x00000400L
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__PERFCTRS_W_MASK 0x00000800L
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__ASID16_W_MASK 0x00001000L
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__MSI_W_MASK 0x00002000L
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__SEV_W_MASK 0x00004000L
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__ATOS_W_MASK 0x00008000L
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__PRI_W_MASK 0x00010000L
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__VMW_W_MASK 0x00020000L
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__VMID16_W_MASK 0x00040000L
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__CD2L_W_MASK 0x00080000L
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__VATOS_W_MASK 0x00100000L
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__TTENDIAN_W_MASK 0x00600000L
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__STALL_MODEL_W_MASK 0x03000000L
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__TERM_MODEL_W_MASK 0x04000000L
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__ST_LEVEL_W_MASK 0x18000000L
+#define IOMMU_L2_1_SMMU_MMIO_IDR0_W__RAS_W_MASK 0x20000000L
+//IOMMU_L2_1_SMMU_MMIO_IDR1_W
+#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__SIDSIZE_W__SHIFT 0x0
+#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__SSIDSIZE_W__SHIFT 0x6
+#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__PRIQS_W__SHIFT 0xb
+#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__EVENTQS_W__SHIFT 0x10
+#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__CMDQS_W__SHIFT 0x15
+#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__ATTR_PERMS_OVR_W__SHIFT 0x1a
+#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__ATTR_TYPES_OVR_W__SHIFT 0x1b
+#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__REL_W__SHIFT 0x1c
+#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__QUEUES_PRESET_W__SHIFT 0x1d
+#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__TABLES_PRESET_W__SHIFT 0x1e
+#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__SIDSIZE_W_MASK 0x0000003FL
+#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__SSIDSIZE_W_MASK 0x000007C0L
+#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__PRIQS_W_MASK 0x0000F800L
+#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__EVENTQS_W_MASK 0x001F0000L
+#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__CMDQS_W_MASK 0x03E00000L
+#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__ATTR_PERMS_OVR_W_MASK 0x04000000L
+#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__ATTR_TYPES_OVR_W_MASK 0x08000000L
+#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__REL_W_MASK 0x10000000L
+#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__QUEUES_PRESET_W_MASK 0x20000000L
+#define IOMMU_L2_1_SMMU_MMIO_IDR1_W__TABLES_PRESET_W_MASK 0x40000000L
+//IOMMU_L2_1_SMMU_MMIO_IDR2_W
+#define IOMMU_L2_1_SMMU_MMIO_IDR2_W__BA_VATOS_W__SHIFT 0x0
+#define IOMMU_L2_1_SMMU_MMIO_IDR2_W__BA_RAS_W__SHIFT 0xa
+#define IOMMU_L2_1_SMMU_MMIO_IDR2_W__BA_VATOS_W_MASK 0x000003FFL
+#define IOMMU_L2_1_SMMU_MMIO_IDR2_W__BA_RAS_W_MASK 0x000FFC00L
+//IOMMU_L2_1_SMMU_MMIO_IDR3_W
+#define IOMMU_L2_1_SMMU_MMIO_IDR3_W__HAD_W__SHIFT 0x2
+#define IOMMU_L2_1_SMMU_MMIO_IDR3_W__HAD_W_MASK 0x00000004L
+//IOMMU_L2_1_SMMU_MMIO_IDR5_W
+#define IOMMU_L2_1_SMMU_MMIO_IDR5_W__OAS_W__SHIFT 0x0
+#define IOMMU_L2_1_SMMU_MMIO_IDR5_W__GRAN4K_W__SHIFT 0x4
+#define IOMMU_L2_1_SMMU_MMIO_IDR5_W__GRAN16K_W__SHIFT 0x5
+#define IOMMU_L2_1_SMMU_MMIO_IDR5_W__GRAN64K_W__SHIFT 0x6
+#define IOMMU_L2_1_SMMU_MMIO_IDR5_W__STALL_MAX_W__SHIFT 0x10
+#define IOMMU_L2_1_SMMU_MMIO_IDR5_W__OAS_W_MASK 0x00000007L
+#define IOMMU_L2_1_SMMU_MMIO_IDR5_W__GRAN4K_W_MASK 0x00000010L
+#define IOMMU_L2_1_SMMU_MMIO_IDR5_W__GRAN16K_W_MASK 0x00000020L
+#define IOMMU_L2_1_SMMU_MMIO_IDR5_W__GRAN64K_W_MASK 0x00000040L
+#define IOMMU_L2_1_SMMU_MMIO_IDR5_W__STALL_MAX_W_MASK 0xFFFF0000L
+//IOMMU_L2_1_SMMU_MMIO_IIDR_W
+#define IOMMU_L2_1_SMMU_MMIO_IIDR_W__Implementer_W__SHIFT 0x0
+#define IOMMU_L2_1_SMMU_MMIO_IIDR_W__Revision_W__SHIFT 0xc
+#define IOMMU_L2_1_SMMU_MMIO_IIDR_W__Variant_W__SHIFT 0x10
+#define IOMMU_L2_1_SMMU_MMIO_IIDR_W__ProductID_W__SHIFT 0x14
+#define IOMMU_L2_1_SMMU_MMIO_IIDR_W__Implementer_W_MASK 0x00000FFFL
+#define IOMMU_L2_1_SMMU_MMIO_IIDR_W__Revision_W_MASK 0x0000F000L
+#define IOMMU_L2_1_SMMU_MMIO_IIDR_W__Variant_W_MASK 0x000F0000L
+#define IOMMU_L2_1_SMMU_MMIO_IIDR_W__ProductID_W_MASK 0xFFF00000L
+//IOMMU_L2_1_SMMU_AIDR_W
+#define IOMMU_L2_1_SMMU_AIDR_W__ArchMinorRev_W__SHIFT 0x0
+#define IOMMU_L2_1_SMMU_AIDR_W__ArchMajorRev_W__SHIFT 0x4
+#define IOMMU_L2_1_SMMU_AIDR_W__ArchMinorRev_W_MASK 0x0000000FL
+#define IOMMU_L2_1_SMMU_AIDR_W__ArchMajorRev_W_MASK 0x000000F0L
+
+
+// addressBlock: nbio_iohub_iommu_l2indx_l2indxcfg
+//L2_STATUS_1
+#define L2_STATUS_1__L2STATUS1__SHIFT 0x0
+#define L2_STATUS_1__L2STATUS1_MASK 0xFFFFFFFFL
+//L2_SB_LOCATION
+#define L2_SB_LOCATION__SBlocated_Port__SHIFT 0x0
+#define L2_SB_LOCATION__SBlocated_Core__SHIFT 0x10
+#define L2_SB_LOCATION__SBlocated_Port_MASK 0x0000FFFFL
+#define L2_SB_LOCATION__SBlocated_Core_MASK 0xFFFF0000L
+//L2_CONTROL_5
+#define L2_CONTROL_5__QueueArbFBPri__SHIFT 0x0
+#define L2_CONTROL_5__FC1Dis__SHIFT 0x2
+#define L2_CONTROL_5__DTCUpdateVOneIVZero__SHIFT 0x3
+#define L2_CONTROL_5__DTCUpdateVZeroIVOne__SHIFT 0x4
+#define L2_CONTROL_5__FC3Dis__SHIFT 0x6
+#define L2_CONTROL_5__RESERVED__SHIFT 0x7
+#define L2_CONTROL_5__ForceTWonVC7__SHIFT 0xb
+#define L2_CONTROL_5__GST_partial_ptc_cntrl__SHIFT 0xc
+#define L2_CONTROL_5__PCTRL_hysteresis__SHIFT 0x13
+#define L2_CONTROL_5__DTCUpdatePri__SHIFT 0x19
+#define L2_CONTROL_5__QueueArbFBPri_MASK 0x00000001L
+#define L2_CONTROL_5__FC1Dis_MASK 0x00000004L
+#define L2_CONTROL_5__DTCUpdateVOneIVZero_MASK 0x00000008L
+#define L2_CONTROL_5__DTCUpdateVZeroIVOne_MASK 0x00000010L
+#define L2_CONTROL_5__FC3Dis_MASK 0x00000040L
+#define L2_CONTROL_5__RESERVED_MASK 0x00000780L
+#define L2_CONTROL_5__ForceTWonVC7_MASK 0x00000800L
+#define L2_CONTROL_5__GST_partial_ptc_cntrl_MASK 0x0007F000L
+#define L2_CONTROL_5__PCTRL_hysteresis_MASK 0x01F80000L
+#define L2_CONTROL_5__DTCUpdatePri_MASK 0x02000000L
+//L2_CONTROL_6
+#define L2_CONTROL_6__SeqInvBurstLimitInv__SHIFT 0x0
+#define L2_CONTROL_6__SeqInvBurstLimitPDCReq__SHIFT 0x8
+#define L2_CONTROL_6__SeqInvBurstLimitEn__SHIFT 0x10
+#define L2_CONTROL_6__Perf2Threshold__SHIFT 0x18
+#define L2_CONTROL_6__SeqInvBurstLimitInv_MASK 0x000000FFL
+#define L2_CONTROL_6__SeqInvBurstLimitPDCReq_MASK 0x0000FF00L
+#define L2_CONTROL_6__SeqInvBurstLimitEn_MASK 0x00010000L
+#define L2_CONTROL_6__Perf2Threshold_MASK 0xFF000000L
+//L2_PDC_CONTROL
+#define L2_PDC_CONTROL__RESERVED__SHIFT 0x0
+#define L2_PDC_CONTROL__PDCLRUUpdatePri__SHIFT 0x3
+#define L2_PDC_CONTROL__PDCParityEn__SHIFT 0x4
+#define L2_PDC_CONTROL__PDCInvalidationSel__SHIFT 0x8
+#define L2_PDC_CONTROL__PDCSoftInvalidate__SHIFT 0xa
+#define L2_PDC_CONTROL__PDCSearchDirection__SHIFT 0xc
+#define L2_PDC_CONTROL__PDCBypass__SHIFT 0xd
+#define L2_PDC_CONTROL__PDCParitySupport__SHIFT 0xf
+#define L2_PDC_CONTROL__PDCWays__SHIFT 0x10
+#define L2_PDC_CONTROL__PDCEntries__SHIFT 0x1c
+#define L2_PDC_CONTROL__RESERVED_MASK 0x00000003L
+#define L2_PDC_CONTROL__PDCLRUUpdatePri_MASK 0x00000008L
+#define L2_PDC_CONTROL__PDCParityEn_MASK 0x00000010L
+#define L2_PDC_CONTROL__PDCInvalidationSel_MASK 0x00000300L
+#define L2_PDC_CONTROL__PDCSoftInvalidate_MASK 0x00000400L
+#define L2_PDC_CONTROL__PDCSearchDirection_MASK 0x00001000L
+#define L2_PDC_CONTROL__PDCBypass_MASK 0x00002000L
+#define L2_PDC_CONTROL__PDCParitySupport_MASK 0x00008000L
+#define L2_PDC_CONTROL__PDCWays_MASK 0x00FF0000L
+#define L2_PDC_CONTROL__PDCEntries_MASK 0xF0000000L
+//L2_PDC_HASH_CONTROL
+#define L2_PDC_HASH_CONTROL__PDCAddressMask__SHIFT 0x10
+#define L2_PDC_HASH_CONTROL__PDCAddressMask_MASK 0xFFFF0000L
+//L2_PDC_WAY_CONTROL
+#define L2_PDC_WAY_CONTROL__PDCWayDisable__SHIFT 0x0
+#define L2_PDC_WAY_CONTROL__PDCWayAccessDisable__SHIFT 0x10
+#define L2_PDC_WAY_CONTROL__PDCWayDisable_MASK 0x0000FFFFL
+#define L2_PDC_WAY_CONTROL__PDCWayAccessDisable_MASK 0xFFFF0000L
+//L2B_UPDATE_FILTER_CNTL
+#define L2B_UPDATE_FILTER_CNTL__L2b_Update_Filter_Bypass__SHIFT 0x0
+#define L2B_UPDATE_FILTER_CNTL__L2b_Update_Filter_RdLatency__SHIFT 0x1
+#define L2B_UPDATE_FILTER_CNTL__L2b_Update_Filter_Bypass_MASK 0x00000001L
+#define L2B_UPDATE_FILTER_CNTL__L2b_Update_Filter_RdLatency_MASK 0x0000001EL
+//L2_TW_CONTROL
+#define L2_TW_CONTROL__RESERVED__SHIFT 0x0
+#define L2_TW_CONTROL__TWForceCoherent__SHIFT 0x6
+#define L2_TW_CONTROL__TWPrefetchEn__SHIFT 0x8
+#define L2_TW_CONTROL__TWPrefetchOnly4KDis__SHIFT 0x9
+#define L2_TW_CONTROL__TWPTEOnUntransExcl__SHIFT 0xa
+#define L2_TW_CONTROL__TWPTEOnAddrTransExcl__SHIFT 0xb
+#define L2_TW_CONTROL__TWPrefetchRange__SHIFT 0xc
+#define L2_TW_CONTROL__TWFilter_Dis__SHIFT 0x10
+#define L2_TW_CONTROL__TWFilter_64B_Dis__SHIFT 0x11
+#define L2_TW_CONTROL__TWContWalkOnPErrDis__SHIFT 0x12
+#define L2_TW_CONTROL__TWSetAccessBit_Dis__SHIFT 0x13
+#define L2_TW_CONTROL__TWClearAPBit_Dis__SHIFT 0x14
+#define L2_TW_CONTROL__TWGuestPrefetchEn__SHIFT 0x15
+#define L2_TW_CONTROL__TWGuestPrefetchRange__SHIFT 0x16
+#define L2_TW_CONTROL__RESERVED_MASK 0x0000003FL
+#define L2_TW_CONTROL__TWForceCoherent_MASK 0x00000040L
+#define L2_TW_CONTROL__TWPrefetchEn_MASK 0x00000100L
+#define L2_TW_CONTROL__TWPrefetchOnly4KDis_MASK 0x00000200L
+#define L2_TW_CONTROL__TWPTEOnUntransExcl_MASK 0x00000400L
+#define L2_TW_CONTROL__TWPTEOnAddrTransExcl_MASK 0x00000800L
+#define L2_TW_CONTROL__TWPrefetchRange_MASK 0x00007000L
+#define L2_TW_CONTROL__TWFilter_Dis_MASK 0x00010000L
+#define L2_TW_CONTROL__TWFilter_64B_Dis_MASK 0x00020000L
+#define L2_TW_CONTROL__TWContWalkOnPErrDis_MASK 0x00040000L
+#define L2_TW_CONTROL__TWSetAccessBit_Dis_MASK 0x00080000L
+#define L2_TW_CONTROL__TWClearAPBit_Dis_MASK 0x00100000L
+#define L2_TW_CONTROL__TWGuestPrefetchEn_MASK 0x00200000L
+#define L2_TW_CONTROL__TWGuestPrefetchRange_MASK 0x01C00000L
+//L2_CP_CONTROL
+#define L2_CP_CONTROL__CPPrefetchDis__SHIFT 0x0
+#define L2_CP_CONTROL__CPFlushOnWait__SHIFT 0x1
+#define L2_CP_CONTROL__CPFlushOnInv__SHIFT 0x2
+#define L2_CP_CONTROL__CPRdDelay__SHIFT 0x10
+#define L2_CP_CONTROL__CPPrefetchDis_MASK 0x00000001L
+#define L2_CP_CONTROL__CPFlushOnWait_MASK 0x00000002L
+#define L2_CP_CONTROL__CPFlushOnInv_MASK 0x00000004L
+#define L2_CP_CONTROL__CPRdDelay_MASK 0xFFFF0000L
+//L2_CP_CONTROL_1
+#define L2_CP_CONTROL_1__CPL1Off__SHIFT 0x0
+#define L2_CP_CONTROL_1__Reserved__SHIFT 0x10
+#define L2_CP_CONTROL_1__CPL1Off_MASK 0x0000FFFFL
+#define L2_CP_CONTROL_1__Reserved_MASK 0xFFFF0000L
+//IOMMU_L2_GUEST_ADDR_CNTRL
+#define IOMMU_L2_GUEST_ADDR_CNTRL__IOMMU_L2_GUEST_ADDR_MASK__SHIFT 0x0
+#define IOMMU_L2_GUEST_ADDR_CNTRL__Reserved__SHIFT 0x18
+#define IOMMU_L2_GUEST_ADDR_CNTRL__IOMMU_L2_GUEST_ADDR_MASK_MASK 0x00FFFFFFL
+#define IOMMU_L2_GUEST_ADDR_CNTRL__Reserved_MASK 0xFF000000L
+//L2_TW_CONTROL_1
+#define L2_TW_CONTROL_1__TWDebugEn__SHIFT 0x0
+#define L2_TW_CONTROL_1__TWDebugNoWrap__SHIFT 0x1
+#define L2_TW_CONTROL_1__TWDebugForceDisable__SHIFT 0x2
+#define L2_TW_CONTROL_1__TWDebugMask__SHIFT 0xf
+#define L2_TW_CONTROL_1__TWDebugEn_MASK 0x00000001L
+#define L2_TW_CONTROL_1__TWDebugNoWrap_MASK 0x00000002L
+#define L2_TW_CONTROL_1__TWDebugForceDisable_MASK 0x00000004L
+#define L2_TW_CONTROL_1__TWDebugMask_MASK 0xFFFF8000L
+//L2_TW_CONTROL_2
+#define L2_TW_CONTROL_2__TWDebugAddrLo__SHIFT 0xc
+#define L2_TW_CONTROL_2__TWDebugAddrLo_MASK 0xFFFFF000L
+//L2_TW_CONTROL_3
+#define L2_TW_CONTROL_3__TWDebugAddrHi__SHIFT 0x0
+#define L2_TW_CONTROL_3__TWDebugAddrHi_MASK 0xFFFFFFFFL
+//L2_CREDIT_CONTROL_0
+#define L2_CREDIT_CONTROL_0__FC1Credits__SHIFT 0x0
+#define L2_CREDIT_CONTROL_0__FC1Override__SHIFT 0x7
+#define L2_CREDIT_CONTROL_0__FC2Credits__SHIFT 0x8
+#define L2_CREDIT_CONTROL_0__FC2Override__SHIFT 0xe
+#define L2_CREDIT_CONTROL_0__FC3Credits__SHIFT 0xf
+#define L2_CREDIT_CONTROL_0__FC3Override__SHIFT 0x15
+#define L2_CREDIT_CONTROL_0__MultATSCredits__SHIFT 0x16
+#define L2_CREDIT_CONTROL_0__FC1Credits_MASK 0x0000007FL
+#define L2_CREDIT_CONTROL_0__FC1Override_MASK 0x00000080L
+#define L2_CREDIT_CONTROL_0__FC2Credits_MASK 0x00003F00L
+#define L2_CREDIT_CONTROL_0__FC2Override_MASK 0x00004000L
+#define L2_CREDIT_CONTROL_0__FC3Credits_MASK 0x001F8000L
+#define L2_CREDIT_CONTROL_0__FC3Override_MASK 0x00200000L
+#define L2_CREDIT_CONTROL_0__MultATSCredits_MASK 0xFFC00000L
+//L2_CREDIT_CONTROL_1
+#define L2_CREDIT_CONTROL_1__PDTIECredits__SHIFT 0x0
+#define L2_CREDIT_CONTROL_1__RESERVED__SHIFT 0x7
+#define L2_CREDIT_CONTROL_1__TWELCredits__SHIFT 0x8
+#define L2_CREDIT_CONTROL_1__CP_PREFETCH_credits__SHIFT 0x10
+#define L2_CREDIT_CONTROL_1__PPR_MCIF_credits__SHIFT 0x14
+#define L2_CREDIT_CONTROL_1__PDTIECredits_MASK 0x0000003FL
+#define L2_CREDIT_CONTROL_1__RESERVED_MASK 0x00000080L
+#define L2_CREDIT_CONTROL_1__TWELCredits_MASK 0x00003F00L
+#define L2_CREDIT_CONTROL_1__CP_PREFETCH_credits_MASK 0x000F0000L
+#define L2_CREDIT_CONTROL_1__PPR_MCIF_credits_MASK 0x00F00000L
+//L2_ERR_RULE_CONTROL_0
+#define L2_ERR_RULE_CONTROL_0__ERRRuleLock0__SHIFT 0x0
+#define L2_ERR_RULE_CONTROL_0__ERRRuleDisable0__SHIFT 0x4
+#define L2_ERR_RULE_CONTROL_0__ERRRuleLock0_MASK 0x00000001L
+#define L2_ERR_RULE_CONTROL_0__ERRRuleDisable0_MASK 0xFFFFFFF0L
+//L2_ERR_RULE_CONTROL_1
+#define L2_ERR_RULE_CONTROL_1__ERRRuleDisable1__SHIFT 0x0
+#define L2_ERR_RULE_CONTROL_1__ERRRuleDisable1_MASK 0xFFFFFFFFL
+//L2_ERR_RULE_CONTROL_2
+#define L2_ERR_RULE_CONTROL_2__ERRRuleDisable2__SHIFT 0x0
+#define L2_ERR_RULE_CONTROL_2__ERRRuleDisable2_MASK 0xFFFFFFFFL
+//L2_L2B_CK_GATE_CONTROL
+#define L2_L2B_CK_GATE_CONTROL__CKGateL2BRegsDisable__SHIFT 0x0
+#define L2_L2B_CK_GATE_CONTROL__CKGateL2BDynamicDisable__SHIFT 0x1
+#define L2_L2B_CK_GATE_CONTROL__CKGateL2BMiscDisable__SHIFT 0x2
+#define L2_L2B_CK_GATE_CONTROL__CKGateL2BCacheDisable__SHIFT 0x3
+#define L2_L2B_CK_GATE_CONTROL__CKGateL2BLength__SHIFT 0x4
+#define L2_L2B_CK_GATE_CONTROL__CKGateL2BStop__SHIFT 0x6
+#define L2_L2B_CK_GATE_CONTROL__Reserved__SHIFT 0x8
+#define L2_L2B_CK_GATE_CONTROL__CKGateL2BRegsDisable_MASK 0x00000001L
+#define L2_L2B_CK_GATE_CONTROL__CKGateL2BDynamicDisable_MASK 0x00000002L
+#define L2_L2B_CK_GATE_CONTROL__CKGateL2BMiscDisable_MASK 0x00000004L
+#define L2_L2B_CK_GATE_CONTROL__CKGateL2BCacheDisable_MASK 0x00000008L
+#define L2_L2B_CK_GATE_CONTROL__CKGateL2BLength_MASK 0x00000030L
+#define L2_L2B_CK_GATE_CONTROL__CKGateL2BStop_MASK 0x000000C0L
+#define L2_L2B_CK_GATE_CONTROL__Reserved_MASK 0xFFFFFF00L
+//PPR_CONTROL
+#define PPR_CONTROL__PPR_IntTimeDelay__SHIFT 0x0
+#define PPR_CONTROL__PPR_IntReqDelay__SHIFT 0x8
+#define PPR_CONTROL__PPR_IntCoallesce_En__SHIFT 0x10
+#define PPR_CONTROL__Reserved__SHIFT 0x11
+#define PPR_CONTROL__PPR_IntTimeDelay_MASK 0x000000FFL
+#define PPR_CONTROL__PPR_IntReqDelay_MASK 0x0000FF00L
+#define PPR_CONTROL__PPR_IntCoallesce_En_MASK 0x00010000L
+#define PPR_CONTROL__Reserved_MASK 0xFFFE0000L
+//L2_L2B_PGSIZE_CONTROL
+#define L2_L2B_PGSIZE_CONTROL__L2BREG_GST_PGSIZE__SHIFT 0x0
+#define L2_L2B_PGSIZE_CONTROL__L2BREG_HOST_PGSIZE__SHIFT 0x8
+#define L2_L2B_PGSIZE_CONTROL__L2BREG_GST_PGSIZE_MASK 0x0000007FL
+#define L2_L2B_PGSIZE_CONTROL__L2BREG_HOST_PGSIZE_MASK 0x00007F00L
+//L2_L2B_MEMPWR_GATE_1
+#define L2_L2B_MEMPWR_GATE_1__L2BREG_LS_EN__SHIFT 0x0
+#define L2_L2B_MEMPWR_GATE_1__L2BREG_DS_EN__SHIFT 0x1
+#define L2_L2B_MEMPWR_GATE_1__L2BREG_SD_EN__SHIFT 0x2
+#define L2_L2B_MEMPWR_GATE_1__L2B_IP_PGMEM_SEL__SHIFT 0x3
+#define L2_L2B_MEMPWR_GATE_1__L2BREG_CACHE_PGMEM_SEL__SHIFT 0x4
+#define L2_L2B_MEMPWR_GATE_1__L2BREG_LS_EN_MASK 0x00000001L
+#define L2_L2B_MEMPWR_GATE_1__L2BREG_DS_EN_MASK 0x00000002L
+#define L2_L2B_MEMPWR_GATE_1__L2BREG_SD_EN_MASK 0x00000004L
+#define L2_L2B_MEMPWR_GATE_1__L2B_IP_PGMEM_SEL_MASK 0x00000008L
+#define L2_L2B_MEMPWR_GATE_1__L2BREG_CACHE_PGMEM_SEL_MASK 0x00000010L
+//L2_L2B_MEMPWR_GATE_2
+#define L2_L2B_MEMPWR_GATE_2__L2BREG_LS_thres__SHIFT 0x0
+#define L2_L2B_MEMPWR_GATE_2__L2BREG_LS_thres_MASK 0xFFFFFFFFL
+//L2_L2B_MEMPWR_GATE_3
+#define L2_L2B_MEMPWR_GATE_3__L2BREG_DS_thres__SHIFT 0x0
+#define L2_L2B_MEMPWR_GATE_3__L2BREG_DS_thres_MASK 0xFFFFFFFFL
+//L2_L2B_MEMPWR_GATE_4
+#define L2_L2B_MEMPWR_GATE_4__L2BREG_SD_thres__SHIFT 0x0
+#define L2_L2B_MEMPWR_GATE_4__L2BREG_SD_thres_MASK 0xFFFFFFFFL
+//L2_PERF_CNTL_2
+#define L2_PERF_CNTL_2__L2PerfEvent4__SHIFT 0x0
+#define L2_PERF_CNTL_2__L2PerfEvent5__SHIFT 0x8
+#define L2_PERF_CNTL_2__L2PerfCountUpper4__SHIFT 0x10
+#define L2_PERF_CNTL_2__L2PerfCountUpper5__SHIFT 0x18
+#define L2_PERF_CNTL_2__L2PerfEvent4_MASK 0x000000FFL
+#define L2_PERF_CNTL_2__L2PerfEvent5_MASK 0x0000FF00L
+#define L2_PERF_CNTL_2__L2PerfCountUpper4_MASK 0x00FF0000L
+#define L2_PERF_CNTL_2__L2PerfCountUpper5_MASK 0xFF000000L
+//L2_PERF_COUNT_4
+#define L2_PERF_COUNT_4__L2PerfCount4__SHIFT 0x0
+#define L2_PERF_COUNT_4__L2PerfCount4_MASK 0xFFFFFFFFL
+//L2_PERF_COUNT_5
+#define L2_PERF_COUNT_5__L2PerfCount5__SHIFT 0x0
+#define L2_PERF_COUNT_5__L2PerfCount5_MASK 0xFFFFFFFFL
+//L2_PERF_CNTL_3
+#define L2_PERF_CNTL_3__L2PerfEvent6__SHIFT 0x0
+#define L2_PERF_CNTL_3__L2PerfEvent7__SHIFT 0x8
+#define L2_PERF_CNTL_3__L2PerfCountUpper6__SHIFT 0x10
+#define L2_PERF_CNTL_3__L2PerfCountUpper7__SHIFT 0x18
+#define L2_PERF_CNTL_3__L2PerfEvent6_MASK 0x000000FFL
+#define L2_PERF_CNTL_3__L2PerfEvent7_MASK 0x0000FF00L
+#define L2_PERF_CNTL_3__L2PerfCountUpper6_MASK 0x00FF0000L
+#define L2_PERF_CNTL_3__L2PerfCountUpper7_MASK 0xFF000000L
+//L2_PERF_COUNT_6
+#define L2_PERF_COUNT_6__L2PerfCount6__SHIFT 0x0
+#define L2_PERF_COUNT_6__L2PerfCount6_MASK 0xFFFFFFFFL
+//L2_PERF_COUNT_7
+#define L2_PERF_COUNT_7__L2PerfCount7__SHIFT 0x0
+#define L2_PERF_COUNT_7__L2PerfCount7_MASK 0xFFFFFFFFL
+//L2_L2B_DVM_CTRL_0
+#define L2_L2B_DVM_CTRL_0__DVM_INTGFX_REQID__SHIFT 0x0
+#define L2_L2B_DVM_CTRL_0__DVM_INTGFX_QUEUEID__SHIFT 0x10
+#define L2_L2B_DVM_CTRL_0__DVM_INTGFX_REQID_MASK 0x0000FFFFL
+#define L2_L2B_DVM_CTRL_0__DVM_INTGFX_QUEUEID_MASK 0xFFFF0000L
+//L2_L2B_DVM_CTRL_1
+#define L2_L2B_DVM_CTRL_1__DVM_INTGFX_MAXPEND__SHIFT 0x0
+#define L2_L2B_DVM_CTRL_1__DVM_IOTLB_INV_PGSIZE__SHIFT 0x8
+#define L2_L2B_DVM_CTRL_1__DVM_TLB_INV_PGSIZE__SHIFT 0xb
+#define L2_L2B_DVM_CTRL_1__DVM_V1_Disable__SHIFT 0xe
+#define L2_L2B_DVM_CTRL_1__DVM_REMAP_TYPE__SHIFT 0xf
+#define L2_L2B_DVM_CTRL_1__DVM_INTGFX_MAXPEND_MASK 0x000000FFL
+#define L2_L2B_DVM_CTRL_1__DVM_IOTLB_INV_PGSIZE_MASK 0x00000700L
+#define L2_L2B_DVM_CTRL_1__DVM_TLB_INV_PGSIZE_MASK 0x00003800L
+#define L2_L2B_DVM_CTRL_1__DVM_V1_Disable_MASK 0x00004000L
+#define L2_L2B_DVM_CTRL_1__DVM_REMAP_TYPE_MASK 0x00FF8000L
+//L2B_SDP_MAXCRED
+#define L2B_SDP_MAXCRED__L2B_RDRSP_MAXCRED__SHIFT 0x0
+#define L2B_SDP_MAXCRED__L2B_WRRSP_MAXCRED__SHIFT 0xc
+#define L2B_SDP_MAXCRED__L2B_REQ_MAXCRED__SHIFT 0x14
+#define L2B_SDP_MAXCRED__L2B_DATA_MAXCRED__SHIFT 0x18
+#define L2B_SDP_MAXCRED__L2B_RDRSP_MAXCRED_MASK 0x00000FFFL
+#define L2B_SDP_MAXCRED__L2B_WRRSP_MAXCRED_MASK 0x000FF000L
+#define L2B_SDP_MAXCRED__L2B_REQ_MAXCRED_MASK 0x00F00000L
+#define L2B_SDP_MAXCRED__L2B_DATA_MAXCRED_MASK 0x0F000000L
+//L2B_SDP_PARITY_ERROR_EN
+#define L2B_SDP_PARITY_ERROR_EN__DVM_PARITY_ERROR_EN__SHIFT 0x0
+#define L2B_SDP_PARITY_ERROR_EN__CP_PARITY_ERROR_EN__SHIFT 0x1
+#define L2B_SDP_PARITY_ERROR_EN__TWW_PARITY_ERROR_EN__SHIFT 0x2
+#define L2B_SDP_PARITY_ERROR_EN__DVM_PARITY_ERROR_EN_MASK 0x00000001L
+#define L2B_SDP_PARITY_ERROR_EN__CP_PARITY_ERROR_EN_MASK 0x00000002L
+#define L2B_SDP_PARITY_ERROR_EN__TWW_PARITY_ERROR_EN_MASK 0x00000004L
+//L2_ECO_CNTRL_1
+#define L2_ECO_CNTRL_1__L2_ECO_1__SHIFT 0x0
+#define L2_ECO_CNTRL_1__L2_ECO_1_MASK 0xFFFFFFFFL
+//L2_L2B_MEMPWR_GATE_5
+#define L2_L2B_MEMPWR_GATE_5__L2BREG_LS_Req_Maintain_Cnt__SHIFT 0x0
+#define L2_L2B_MEMPWR_GATE_5__L2BREG_LS_Req_Maintain_Cnt_MASK 0xFFFFFFFFL
+//L2_L2B_MEMPWR_GATE_6
+#define L2_L2B_MEMPWR_GATE_6__L2BREG_LS_Exit_Maintain_Cnt__SHIFT 0x0
+#define L2_L2B_MEMPWR_GATE_6__L2BREG_LS_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL
+//L2_L2B_MEMPWR_GATE_7
+#define L2_L2B_MEMPWR_GATE_7__L2BREG_DS_Req_Maintain_Cnt__SHIFT 0x0
+#define L2_L2B_MEMPWR_GATE_7__L2BREG_DS_Req_Maintain_Cnt_MASK 0xFFFFFFFFL
+//L2_L2B_MEMPWR_GATE_8
+#define L2_L2B_MEMPWR_GATE_8__L2BREG_DS_Exit_Maintain_Cnt__SHIFT 0x0
+#define L2_L2B_MEMPWR_GATE_8__L2BREG_DS_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL
+//L2_L2B_MEMPWR_GATE_9
+#define L2_L2B_MEMPWR_GATE_9__L2BREG_SD_Req_Maintain_Cnt__SHIFT 0x0
+#define L2_L2B_MEMPWR_GATE_9__L2BREG_SD_Req_Maintain_Cnt_MASK 0xFFFFFFFFL
+//L2_L2B_MEMPWR_GATE_10
+#define L2_L2B_MEMPWR_GATE_10__L2BREG_SD_Exit_Maintain_Cnt__SHIFT 0x0
+#define L2_L2B_MEMPWR_GATE_10__L2BREG_SD_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_iohub_iommu_l2bshdw_l2bshdw
+//SHDW_PCIE0_Port0_NBIO_SUB_BUS_NUMBER_LATENCY
+#define SHDW_PCIE0_Port0_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port0_SECONDARY_BUS__SHIFT 0x8
+#define SHDW_PCIE0_Port0_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port0_SUB_BUS_NUM__SHIFT 0x10
+#define SHDW_PCIE0_Port0_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port0_SECONDARY_BUS_MASK 0x0000FF00L
+#define SHDW_PCIE0_Port0_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port0_SUB_BUS_NUM_MASK 0x00FF0000L
+//SHDW_PCIE0_Port1_NBIO_SUB_BUS_NUMBER_LATENCY
+#define SHDW_PCIE0_Port1_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port1_SECONDARY_BUS__SHIFT 0x8
+#define SHDW_PCIE0_Port1_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port1_SUB_BUS_NUM__SHIFT 0x10
+#define SHDW_PCIE0_Port1_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port1_SECONDARY_BUS_MASK 0x0000FF00L
+#define SHDW_PCIE0_Port1_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port1_SUB_BUS_NUM_MASK 0x00FF0000L
+//SHDW_PCIE0_Port2_NBIO_SUB_BUS_NUMBER_LATENCY
+#define SHDW_PCIE0_Port2_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port2_SECONDARY_BUS__SHIFT 0x8
+#define SHDW_PCIE0_Port2_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port2_SUB_BUS_NUM__SHIFT 0x10
+#define SHDW_PCIE0_Port2_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port2_SECONDARY_BUS_MASK 0x0000FF00L
+#define SHDW_PCIE0_Port2_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port2_SUB_BUS_NUM_MASK 0x00FF0000L
+//SHDW_PCIE0_Port3_NBIO_SUB_BUS_NUMBER_LATENCY
+#define SHDW_PCIE0_Port3_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port3_SECONDARY_BUS__SHIFT 0x8
+#define SHDW_PCIE0_Port3_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port3_SUB_BUS_NUM__SHIFT 0x10
+#define SHDW_PCIE0_Port3_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port3_SECONDARY_BUS_MASK 0x0000FF00L
+#define SHDW_PCIE0_Port3_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port3_SUB_BUS_NUM_MASK 0x00FF0000L
+//SHDW_PCIE0_Port4_NBIO_SUB_BUS_NUMBER_LATENCY
+#define SHDW_PCIE0_Port4_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port4_SECONDARY_BUS__SHIFT 0x8
+#define SHDW_PCIE0_Port4_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port4_SUB_BUS_NUM__SHIFT 0x10
+#define SHDW_PCIE0_Port4_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port4_SECONDARY_BUS_MASK 0x0000FF00L
+#define SHDW_PCIE0_Port4_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port4_SUB_BUS_NUM_MASK 0x00FF0000L
+//SHDW_PCIE0_Port5_NBIO_SUB_BUS_NUMBER_LATENCY
+#define SHDW_PCIE0_Port5_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port5_SECONDARY_BUS__SHIFT 0x8
+#define SHDW_PCIE0_Port5_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port5_SUB_BUS_NUM__SHIFT 0x10
+#define SHDW_PCIE0_Port5_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port5_SECONDARY_BUS_MASK 0x0000FF00L
+#define SHDW_PCIE0_Port5_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port5_SUB_BUS_NUM_MASK 0x00FF0000L
+//SHDW_PCIE0_Port6_NBIO_SUB_BUS_NUMBER_LATENCY
+#define SHDW_PCIE0_Port6_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port6_SECONDARY_BUS__SHIFT 0x8
+#define SHDW_PCIE0_Port6_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port6_SUB_BUS_NUM__SHIFT 0x10
+#define SHDW_PCIE0_Port6_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port6_SECONDARY_BUS_MASK 0x0000FF00L
+#define SHDW_PCIE0_Port6_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port6_SUB_BUS_NUM_MASK 0x00FF0000L
+//SHDW_PCIE0_Port7_NBIO_SUB_BUS_NUMBER_LATENCY
+#define SHDW_PCIE0_Port7_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port7_SECONDARY_BUS__SHIFT 0x8
+#define SHDW_PCIE0_Port7_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port7_SUB_BUS_NUM__SHIFT 0x10
+#define SHDW_PCIE0_Port7_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port7_SECONDARY_BUS_MASK 0x0000FF00L
+#define SHDW_PCIE0_Port7_NBIO_SUB_BUS_NUMBER_LATENCY__PCIE0_Port7_SUB_BUS_NUM_MASK 0x00FF0000L
+//SHDW_NBIF1_Port0_NBIO_SUB_BUS_NUMBER_LATENCY
+#define SHDW_NBIF1_Port0_NBIO_SUB_BUS_NUMBER_LATENCY__NBIF1_Port0_SECONDARY_BUS__SHIFT 0x8
+#define SHDW_NBIF1_Port0_NBIO_SUB_BUS_NUMBER_LATENCY__NBIF1_Port0_SUB_BUS_NUM__SHIFT 0x10
+#define SHDW_NBIF1_Port0_NBIO_SUB_BUS_NUMBER_LATENCY__NBIF1_Port0_SECONDARY_BUS_MASK 0x0000FF00L
+#define SHDW_NBIF1_Port0_NBIO_SUB_BUS_NUMBER_LATENCY__NBIF1_Port0_SUB_BUS_NUM_MASK 0x00FF0000L
+//SHDW_NBIF1_Port1_NBIO_SUB_BUS_NUMBER_LATENCY
+#define SHDW_NBIF1_Port1_NBIO_SUB_BUS_NUMBER_LATENCY__NBIF1_Port1_SECONDARY_BUS__SHIFT 0x8
+#define SHDW_NBIF1_Port1_NBIO_SUB_BUS_NUMBER_LATENCY__NBIF1_Port1_SUB_BUS_NUM__SHIFT 0x10
+#define SHDW_NBIF1_Port1_NBIO_SUB_BUS_NUMBER_LATENCY__NBIF1_Port1_SECONDARY_BUS_MASK 0x0000FF00L
+#define SHDW_NBIF1_Port1_NBIO_SUB_BUS_NUMBER_LATENCY__NBIF1_Port1_SUB_BUS_NUM_MASK 0x00FF0000L
+
+
+// addressBlock: nbio_iohub_iommu_l2bpsp_l2bpsp
+//L2BPSP_ERR_REP_ENABLE
+#define L2BPSP_ERR_REP_ENABLE__HE_SUP__SHIFT 0x0
+#define L2BPSP_ERR_REP_ENABLE__Reserved__SHIFT 0x1
+#define L2BPSP_ERR_REP_ENABLE__HE_SUP_MASK 0x00000001L
+#define L2BPSP_ERR_REP_ENABLE__Reserved_MASK 0xFFFFFFFEL
+//L2BPSP_HW_ERR_STATUS_0
+#define L2BPSP_HW_ERR_STATUS_0__HEV__SHIFT 0x0
+#define L2BPSP_HW_ERR_STATUS_0__HEO__SHIFT 0x1
+#define L2BPSP_HW_ERR_STATUS_0__Reserved__SHIFT 0x3
+#define L2BPSP_HW_ERR_STATUS_0__HEV_MASK 0x00000001L
+#define L2BPSP_HW_ERR_STATUS_0__HEO_MASK 0x00000002L
+#define L2BPSP_HW_ERR_STATUS_0__Reserved_MASK 0xFFFFFFF8L
+//L2BPSP_HW_ERR_STATUS_1
+#define L2BPSP_HW_ERR_STATUS_1__Reserved__SHIFT 0x0
+#define L2BPSP_HW_ERR_STATUS_1__Reserved_MASK 0xFFFFFFFFL
+//L2BPSP_HW_ERR_LOWER_0
+#define L2BPSP_HW_ERR_LOWER_0__SECOND_EV_CODE_LO__SHIFT 0x0
+#define L2BPSP_HW_ERR_LOWER_0__SECOND_EV_CODE_LO_MASK 0xFFFFFFFFL
+//L2BPSP_HW_ERR_LOWER_1
+#define L2BPSP_HW_ERR_LOWER_1__SECOND_EV_CODE_HI__SHIFT 0x0
+#define L2BPSP_HW_ERR_LOWER_1__SECOND_EV_CODE_HI_MASK 0xFFFFFFFFL
+//L2BPSP_HW_ERR_UPPER_0
+#define L2BPSP_HW_ERR_UPPER_0__FIRST_EV_CODE_LO__SHIFT 0x0
+#define L2BPSP_HW_ERR_UPPER_0__FIRST_EV_CODE_LO_MASK 0xFFFFFFFFL
+//L2BPSP_HW_ERR_UPPER_1
+#define L2BPSP_HW_ERR_UPPER_1__FIRST_EV_CODE_HI__SHIFT 0x0
+#define L2BPSP_HW_ERR_UPPER_1__EV_CODE__SHIFT 0x1c
+#define L2BPSP_HW_ERR_UPPER_1__FIRST_EV_CODE_HI_MASK 0x0FFFFFFFL
+#define L2BPSP_HW_ERR_UPPER_1__EV_CODE_MASK 0xF0000000L
+
+
+// addressBlock: nbio_iohub_nb_ioapiccfg_ioapic_cfgdec
+//FEATURES_ENABLE
+#define FEATURES_ENABLE__Ioapic_id_ext_en__SHIFT 0x2
+#define FEATURES_ENABLE__Ioapic_sb_feature_en__SHIFT 0x4
+#define FEATURES_ENABLE__Ioapic_secondary_en__SHIFT 0x5
+#define FEATURES_ENABLE__Ioapic_processor_mode__SHIFT 0x8
+#define FEATURES_ENABLE__INTx_LevelOnlyMode__SHIFT 0x9
+#define FEATURES_ENABLE__Ioapic_id_ext_en_MASK 0x00000004L
+#define FEATURES_ENABLE__Ioapic_sb_feature_en_MASK 0x00000010L
+#define FEATURES_ENABLE__Ioapic_secondary_en_MASK 0x00000020L
+#define FEATURES_ENABLE__Ioapic_processor_mode_MASK 0x00000100L
+#define FEATURES_ENABLE__INTx_LevelOnlyMode_MASK 0x00000200L
+//IOAPIC_BR0_INTERRUPT_ROUTING
+#define IOAPIC_BR0_INTERRUPT_ROUTING__Br0_ext_Intr_grp__SHIFT 0x0
+#define IOAPIC_BR0_INTERRUPT_ROUTING__Br0_ext_Intr_swz__SHIFT 0x4
+#define IOAPIC_BR0_INTERRUPT_ROUTING__Br0_int_Intr_map__SHIFT 0x10
+#define IOAPIC_BR0_INTERRUPT_ROUTING__Br0_ext_Intr_grp_MASK 0x00000007L
+#define IOAPIC_BR0_INTERRUPT_ROUTING__Br0_ext_Intr_swz_MASK 0x00000030L
+#define IOAPIC_BR0_INTERRUPT_ROUTING__Br0_int_Intr_map_MASK 0x001F0000L
+//IOAPIC_BR1_INTERRUPT_ROUTING
+#define IOAPIC_BR1_INTERRUPT_ROUTING__Br1_ext_Intr_grp__SHIFT 0x0
+#define IOAPIC_BR1_INTERRUPT_ROUTING__Br1_ext_Intr_swz__SHIFT 0x4
+#define IOAPIC_BR1_INTERRUPT_ROUTING__Br1_int_Intr_map__SHIFT 0x10
+#define IOAPIC_BR1_INTERRUPT_ROUTING__Br1_ext_Intr_grp_MASK 0x00000007L
+#define IOAPIC_BR1_INTERRUPT_ROUTING__Br1_ext_Intr_swz_MASK 0x00000030L
+#define IOAPIC_BR1_INTERRUPT_ROUTING__Br1_int_Intr_map_MASK 0x001F0000L
+//IOAPIC_BR2_INTERRUPT_ROUTING
+#define IOAPIC_BR2_INTERRUPT_ROUTING__Br2_ext_Intr_grp__SHIFT 0x0
+#define IOAPIC_BR2_INTERRUPT_ROUTING__Br2_ext_Intr_swz__SHIFT 0x4
+#define IOAPIC_BR2_INTERRUPT_ROUTING__Br2_int_Intr_map__SHIFT 0x10
+#define IOAPIC_BR2_INTERRUPT_ROUTING__Br2_ext_Intr_grp_MASK 0x00000007L
+#define IOAPIC_BR2_INTERRUPT_ROUTING__Br2_ext_Intr_swz_MASK 0x00000030L
+#define IOAPIC_BR2_INTERRUPT_ROUTING__Br2_int_Intr_map_MASK 0x001F0000L
+//IOAPIC_BR3_INTERRUPT_ROUTING
+#define IOAPIC_BR3_INTERRUPT_ROUTING__Br3_ext_Intr_grp__SHIFT 0x0
+#define IOAPIC_BR3_INTERRUPT_ROUTING__Br3_ext_Intr_swz__SHIFT 0x4
+#define IOAPIC_BR3_INTERRUPT_ROUTING__Br3_int_Intr_map__SHIFT 0x10
+#define IOAPIC_BR3_INTERRUPT_ROUTING__Br3_ext_Intr_grp_MASK 0x00000007L
+#define IOAPIC_BR3_INTERRUPT_ROUTING__Br3_ext_Intr_swz_MASK 0x00000030L
+#define IOAPIC_BR3_INTERRUPT_ROUTING__Br3_int_Intr_map_MASK 0x001F0000L
+//IOAPIC_BR4_INTERRUPT_ROUTING
+#define IOAPIC_BR4_INTERRUPT_ROUTING__Br4_ext_Intr_grp__SHIFT 0x0
+#define IOAPIC_BR4_INTERRUPT_ROUTING__Br4_ext_Intr_swz__SHIFT 0x4
+#define IOAPIC_BR4_INTERRUPT_ROUTING__Br4_int_Intr_map__SHIFT 0x10
+#define IOAPIC_BR4_INTERRUPT_ROUTING__Br4_ext_Intr_grp_MASK 0x00000007L
+#define IOAPIC_BR4_INTERRUPT_ROUTING__Br4_ext_Intr_swz_MASK 0x00000030L
+#define IOAPIC_BR4_INTERRUPT_ROUTING__Br4_int_Intr_map_MASK 0x001F0000L
+//IOAPIC_BR5_INTERRUPT_ROUTING
+#define IOAPIC_BR5_INTERRUPT_ROUTING__Br5_ext_Intr_grp__SHIFT 0x0
+#define IOAPIC_BR5_INTERRUPT_ROUTING__Br5_ext_Intr_swz__SHIFT 0x4
+#define IOAPIC_BR5_INTERRUPT_ROUTING__Br5_int_Intr_map__SHIFT 0x10
+#define IOAPIC_BR5_INTERRUPT_ROUTING__Br5_ext_Intr_grp_MASK 0x00000007L
+#define IOAPIC_BR5_INTERRUPT_ROUTING__Br5_ext_Intr_swz_MASK 0x00000030L
+#define IOAPIC_BR5_INTERRUPT_ROUTING__Br5_int_Intr_map_MASK 0x001F0000L
+//IOAPIC_BR6_INTERRUPT_ROUTING
+#define IOAPIC_BR6_INTERRUPT_ROUTING__Br6_ext_Intr_grp__SHIFT 0x0
+#define IOAPIC_BR6_INTERRUPT_ROUTING__Br6_ext_Intr_swz__SHIFT 0x4
+#define IOAPIC_BR6_INTERRUPT_ROUTING__Br6_int_Intr_map__SHIFT 0x10
+#define IOAPIC_BR6_INTERRUPT_ROUTING__Br6_ext_Intr_grp_MASK 0x00000007L
+#define IOAPIC_BR6_INTERRUPT_ROUTING__Br6_ext_Intr_swz_MASK 0x00000030L
+#define IOAPIC_BR6_INTERRUPT_ROUTING__Br6_int_Intr_map_MASK 0x001F0000L
+//IOAPIC_BR7_INTERRUPT_ROUTING
+#define IOAPIC_BR7_INTERRUPT_ROUTING__Br7_ext_Intr_grp__SHIFT 0x0
+#define IOAPIC_BR7_INTERRUPT_ROUTING__Br7_ext_Intr_swz__SHIFT 0x4
+#define IOAPIC_BR7_INTERRUPT_ROUTING__Br7_int_Intr_map__SHIFT 0x10
+#define IOAPIC_BR7_INTERRUPT_ROUTING__Br7_ext_Intr_grp_MASK 0x00000007L
+#define IOAPIC_BR7_INTERRUPT_ROUTING__Br7_ext_Intr_swz_MASK 0x00000030L
+#define IOAPIC_BR7_INTERRUPT_ROUTING__Br7_int_Intr_map_MASK 0x001F0000L
+//IOAPIC_BR8_INTERRUPT_ROUTING
+#define IOAPIC_BR8_INTERRUPT_ROUTING__Br8_ext_Intr_grp__SHIFT 0x0
+#define IOAPIC_BR8_INTERRUPT_ROUTING__Br8_ext_Intr_swz__SHIFT 0x4
+#define IOAPIC_BR8_INTERRUPT_ROUTING__Br8_int_Intr_map__SHIFT 0x10
+#define IOAPIC_BR8_INTERRUPT_ROUTING__Br8_ext_Intr_grp_MASK 0x00000007L
+#define IOAPIC_BR8_INTERRUPT_ROUTING__Br8_ext_Intr_swz_MASK 0x00000030L
+#define IOAPIC_BR8_INTERRUPT_ROUTING__Br8_int_Intr_map_MASK 0x001F0000L
+//IOAPIC_SERIAL_IRQ_STATUS
+#define IOAPIC_SERIAL_IRQ_STATUS__Internal_irq_sts__SHIFT 0x0
+#define IOAPIC_SERIAL_IRQ_STATUS__Internal_irq_sts_MASK 0xFFFFFFFFL
+//IOAPIC_SCRATCH_0
+#define IOAPIC_SCRATCH_0__Scratch_0__SHIFT 0x0
+#define IOAPIC_SCRATCH_0__Scratch_0_MASK 0xFFFFFFFFL
+//IOAPIC_SCRATCH_1
+#define IOAPIC_SCRATCH_1__Scratch_1__SHIFT 0x0
+#define IOAPIC_SCRATCH_1__Scratch_1_MASK 0xFFFFFFFFL
+//IOAPIC_GLUE_CG_LCLK_CTRL_0
+#define IOAPIC_GLUE_CG_LCLK_CTRL_0__CG_OFF_HYSTERESIS__SHIFT 0x4
+#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK9__SHIFT 0x16
+#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK8__SHIFT 0x17
+#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK7__SHIFT 0x18
+#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK6__SHIFT 0x19
+#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK5__SHIFT 0x1a
+#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK4__SHIFT 0x1b
+#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK3__SHIFT 0x1c
+#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK2__SHIFT 0x1d
+#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK1__SHIFT 0x1e
+#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK0__SHIFT 0x1f
+#define IOAPIC_GLUE_CG_LCLK_CTRL_0__CG_OFF_HYSTERESIS_MASK 0x00000FF0L
+#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK9_MASK 0x00400000L
+#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK8_MASK 0x00800000L
+#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK7_MASK 0x01000000L
+#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK6_MASK 0x02000000L
+#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK5_MASK 0x04000000L
+#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK4_MASK 0x08000000L
+#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK3_MASK 0x10000000L
+#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK2_MASK 0x20000000L
+#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK1_MASK 0x40000000L
+#define IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK0_MASK 0x80000000L
+//IOAPIC_SDP_PORT_CONTROL
+#define IOAPIC_SDP_PORT_CONTROL__Port_Disconnect_Hysteresis__SHIFT 0x0
+#define IOAPIC_SDP_PORT_CONTROL__Port_Disconnect_Hysteresis_MASK 0x0000003FL
+//IOAPIC_PERF_CNTL
+#define IOAPIC_PERF_CNTL__EVENT0_SEL__SHIFT 0x0
+#define IOAPIC_PERF_CNTL__EVENT1_SEL__SHIFT 0x8
+#define IOAPIC_PERF_CNTL__EVENT2_SEL__SHIFT 0x10
+#define IOAPIC_PERF_CNTL__EVENT3_SEL__SHIFT 0x18
+#define IOAPIC_PERF_CNTL__EVENT0_SEL_MASK 0x000000FFL
+#define IOAPIC_PERF_CNTL__EVENT1_SEL_MASK 0x0000FF00L
+#define IOAPIC_PERF_CNTL__EVENT2_SEL_MASK 0x00FF0000L
+#define IOAPIC_PERF_CNTL__EVENT3_SEL_MASK 0xFF000000L
+//IOAPIC_PERF_COUNT0
+#define IOAPIC_PERF_COUNT0__COUNTER0__SHIFT 0x0
+#define IOAPIC_PERF_COUNT0__COUNTER0_MASK 0xFFFFFFFFL
+//IOAPIC_PERF_COUNT0_UPPER
+#define IOAPIC_PERF_COUNT0_UPPER__COUNTER0_UPPER__SHIFT 0x0
+#define IOAPIC_PERF_COUNT0_UPPER__COUNTER0_UPPER_MASK 0x00FFFFFFL
+//IOAPIC_PERF_COUNT1
+#define IOAPIC_PERF_COUNT1__COUNTER1__SHIFT 0x0
+#define IOAPIC_PERF_COUNT1__COUNTER1_MASK 0xFFFFFFFFL
+//IOAPIC_PERF_COUNT1_UPPER
+#define IOAPIC_PERF_COUNT1_UPPER__COUNTER1_UPPER__SHIFT 0x0
+#define IOAPIC_PERF_COUNT1_UPPER__COUNTER1_UPPER_MASK 0x00FFFFFFL
+//IOAPIC_PERF_COUNT2
+#define IOAPIC_PERF_COUNT2__COUNTER2__SHIFT 0x0
+#define IOAPIC_PERF_COUNT2__COUNTER2_MASK 0xFFFFFFFFL
+//IOAPIC_PERF_COUNT2_UPPER
+#define IOAPIC_PERF_COUNT2_UPPER__COUNTER2_UPPER__SHIFT 0x0
+#define IOAPIC_PERF_COUNT2_UPPER__COUNTER2_UPPER_MASK 0x00FFFFFFL
+//IOAPIC_PERF_COUNT3
+#define IOAPIC_PERF_COUNT3__COUNTER3__SHIFT 0x0
+#define IOAPIC_PERF_COUNT3__COUNTER3_MASK 0xFFFFFFFFL
+//IOAPIC_PERF_COUNT3_UPPER
+#define IOAPIC_PERF_COUNT3_UPPER__COUNTER3_UPPER__SHIFT 0x0
+#define IOAPIC_PERF_COUNT3_UPPER__COUNTER3_UPPER_MASK 0x00FFFFFFL
+//IOAPIC_PGSLV_CONTROL
+#define IOAPIC_PGSLV_CONTROL__PGSLV_Hysteresis__SHIFT 0x0
+#define IOAPIC_PGSLV_CONTROL__PGSLV_Hysteresis_MASK 0x0000001FL
+
+
+// addressBlock: nbio_iohub_nb_ioapicshdw_ioapic_shdwdec
+//IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr0
+#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr0__PBr0_DevFnMap__SHIFT 0x0
+#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr0__PBr0_DevFnMap_MASK 0x000000FFL
+//IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr1
+#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr1__PBr1_DevFnMap__SHIFT 0x0
+#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr1__PBr1_DevFnMap_MASK 0x000000FFL
+//IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr2
+#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr2__PBr2_DevFnMap__SHIFT 0x0
+#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr2__PBr2_DevFnMap_MASK 0x000000FFL
+//IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr3
+#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr3__PBr3_DevFnMap__SHIFT 0x0
+#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr3__PBr3_DevFnMap_MASK 0x000000FFL
+//IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr4
+#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr4__PBr4_DevFnMap__SHIFT 0x0
+#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr4__PBr4_DevFnMap_MASK 0x000000FFL
+//IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr5
+#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr5__PBr5_DevFnMap__SHIFT 0x0
+#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr5__PBr5_DevFnMap_MASK 0x000000FFL
+//IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr6
+#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr6__PBr6_DevFnMap__SHIFT 0x0
+#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr6__PBr6_DevFnMap_MASK 0x000000FFL
+//IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr7
+#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr7__PBr7_DevFnMap__SHIFT 0x0
+#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr7__PBr7_DevFnMap_MASK 0x000000FFL
+//IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr8
+#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr8__PBr8_DevFnMap__SHIFT 0x0
+#define IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr8__PBr8_DevFnMap_MASK 0x000000FFL
+
+
+// addressBlock: nbio_iohub_iommu_l1_PCIE0_iommul1cfg
+//IOMMU_L1_PCIE0_L1_PERF_CNTL
+#define IOMMU_L1_PCIE0_L1_PERF_CNTL__L1_PERF_EVENT0__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_PERF_CNTL__L1_PERF_EVENT1__SHIFT 0x8
+#define IOMMU_L1_PCIE0_L1_PERF_CNTL__L1_PERF_COUNT_HI_0__SHIFT 0x10
+#define IOMMU_L1_PCIE0_L1_PERF_CNTL__L1_PERF_COUNT_HI_1__SHIFT 0x18
+#define IOMMU_L1_PCIE0_L1_PERF_CNTL__L1_PERF_EVENT0_MASK 0x000000FFL
+#define IOMMU_L1_PCIE0_L1_PERF_CNTL__L1_PERF_EVENT1_MASK 0x0000FF00L
+#define IOMMU_L1_PCIE0_L1_PERF_CNTL__L1_PERF_COUNT_HI_0_MASK 0x00FF0000L
+#define IOMMU_L1_PCIE0_L1_PERF_CNTL__L1_PERF_COUNT_HI_1_MASK 0xFF000000L
+//IOMMU_L1_PCIE0_L1_PERF_COUNT_0
+#define IOMMU_L1_PCIE0_L1_PERF_COUNT_0__L1_PERF_COUNT_0__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_PERF_COUNT_0__L1_PERF_COUNT_0_MASK 0xFFFFFFFFL
+//IOMMU_L1_PCIE0_L1_PERF_COUNT_1
+#define IOMMU_L1_PCIE0_L1_PERF_COUNT_1__L1_PERF_COUNT_1__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_PERF_COUNT_1__L1_PERF_COUNT_1_MASK 0xFFFFFFFFL
+//IOMMU_L1_PCIE0_L1_PERF_CNTL_B
+#define IOMMU_L1_PCIE0_L1_PERF_CNTL_B__L1_PERF_EVENT2__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_PERF_CNTL_B__L1_PERF_EVENT3__SHIFT 0x8
+#define IOMMU_L1_PCIE0_L1_PERF_CNTL_B__L1_PERF_COUNT_HI_2__SHIFT 0x10
+#define IOMMU_L1_PCIE0_L1_PERF_CNTL_B__L1_PERF_COUNT_HI_3__SHIFT 0x18
+#define IOMMU_L1_PCIE0_L1_PERF_CNTL_B__L1_PERF_EVENT2_MASK 0x000000FFL
+#define IOMMU_L1_PCIE0_L1_PERF_CNTL_B__L1_PERF_EVENT3_MASK 0x0000FF00L
+#define IOMMU_L1_PCIE0_L1_PERF_CNTL_B__L1_PERF_COUNT_HI_2_MASK 0x00FF0000L
+#define IOMMU_L1_PCIE0_L1_PERF_CNTL_B__L1_PERF_COUNT_HI_3_MASK 0xFF000000L
+//IOMMU_L1_PCIE0_L1_PERF_COUNT_B0
+#define IOMMU_L1_PCIE0_L1_PERF_COUNT_B0__L1_PERF_COUNT_2__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_PERF_COUNT_B0__L1_PERF_COUNT_2_MASK 0xFFFFFFFFL
+//IOMMU_L1_PCIE0_L1_PERF_COUNT_B1
+#define IOMMU_L1_PCIE0_L1_PERF_COUNT_B1__L1_PERF_COUNT_3__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_PERF_COUNT_B1__L1_PERF_COUNT_3_MASK 0xFFFFFFFFL
+//IOMMU_L1_PCIE0_L1_SB_LOCATION
+#define IOMMU_L1_PCIE0_L1_SB_LOCATION__SBlocated_Port__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_SB_LOCATION__SBlocated_Core__SHIFT 0x10
+#define IOMMU_L1_PCIE0_L1_SB_LOCATION__SBlocated_Port_MASK 0x0000FFFFL
+#define IOMMU_L1_PCIE0_L1_SB_LOCATION__SBlocated_Core_MASK 0xFFFF0000L
+//IOMMU_L1_PCIE0_L1_CNTRL_0
+#define IOMMU_L1_PCIE0_L1_CNTRL_0__Unfilter_dis__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_CNTRL_0__Fragment_dis__SHIFT 0x1
+#define IOMMU_L1_PCIE0_L1_CNTRL_0__CacheIR_only__SHIFT 0x2
+#define IOMMU_L1_PCIE0_L1_CNTRL_0__CacheIW_only__SHIFT 0x3
+#define IOMMU_L1_PCIE0_L1_CNTRL_0__Reserved0__SHIFT 0x4
+#define IOMMU_L1_PCIE0_L1_CNTRL_0__RESERVED__SHIFT 0x5
+#define IOMMU_L1_PCIE0_L1_CNTRL_0__L2Credits__SHIFT 0x8
+#define IOMMU_L1_PCIE0_L1_CNTRL_0__Reserved1__SHIFT 0xe
+#define IOMMU_L1_PCIE0_L1_CNTRL_0__L1Banks__SHIFT 0x14
+#define IOMMU_L1_PCIE0_L1_CNTRL_0__L1Entries__SHIFT 0x18
+#define IOMMU_L1_PCIE0_L1_CNTRL_0__L1ErrEventDetectDis__SHIFT 0x1c
+#define IOMMU_L1_PCIE0_L1_CNTRL_0__L1ForceHostRspPassPWHigh__SHIFT 0x1d
+#define IOMMU_L1_PCIE0_L1_CNTRL_0__L1InterruptHalfDwDis__SHIFT 0x1f
+#define IOMMU_L1_PCIE0_L1_CNTRL_0__Unfilter_dis_MASK 0x00000001L
+#define IOMMU_L1_PCIE0_L1_CNTRL_0__Fragment_dis_MASK 0x00000002L
+#define IOMMU_L1_PCIE0_L1_CNTRL_0__CacheIR_only_MASK 0x00000004L
+#define IOMMU_L1_PCIE0_L1_CNTRL_0__CacheIW_only_MASK 0x00000008L
+#define IOMMU_L1_PCIE0_L1_CNTRL_0__Reserved0_MASK 0x00000010L
+#define IOMMU_L1_PCIE0_L1_CNTRL_0__RESERVED_MASK 0x00000020L
+#define IOMMU_L1_PCIE0_L1_CNTRL_0__L2Credits_MASK 0x00003F00L
+#define IOMMU_L1_PCIE0_L1_CNTRL_0__Reserved1_MASK 0x000FC000L
+#define IOMMU_L1_PCIE0_L1_CNTRL_0__L1Banks_MASK 0x00300000L
+#define IOMMU_L1_PCIE0_L1_CNTRL_0__L1Entries_MASK 0x0F000000L
+#define IOMMU_L1_PCIE0_L1_CNTRL_0__L1ErrEventDetectDis_MASK 0x10000000L
+#define IOMMU_L1_PCIE0_L1_CNTRL_0__L1ForceHostRspPassPWHigh_MASK 0x60000000L
+#define IOMMU_L1_PCIE0_L1_CNTRL_0__L1InterruptHalfDwDis_MASK 0x80000000L
+//IOMMU_L1_PCIE0_L1_CNTRL_1
+#define IOMMU_L1_PCIE0_L1_CNTRL_1__RESERVED__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_CNTRL_1__CacheByPass__SHIFT 0x9
+#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1CacheParityEn__SHIFT 0xa
+#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1ParityEn__SHIFT 0xb
+#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1DTEDis__SHIFT 0xc
+#define IOMMU_L1_PCIE0_L1_CNTRL_1__WQ_EntryDis__SHIFT 0xd
+#define IOMMU_L1_PCIE0_L1_CNTRL_1__Snd_filter_dis__SHIFT 0x14
+#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1Order_en__SHIFT 0x15
+#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1CacheInvAllEn__SHIFT 0x16
+#define IOMMU_L1_PCIE0_L1_CNTRL_1__Select_timeout_pulse__SHIFT 0x17
+#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1_cache_sel_reqid__SHIFT 0x1a
+#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1_cache_sel_interleave__SHIFT 0x1b
+#define IOMMU_L1_PCIE0_L1_CNTRL_1__Pretrans_noVA_filterEn__SHIFT 0x1c
+#define IOMMU_L1_PCIE0_L1_CNTRL_1__UnTrans_2M_filterEn__SHIFT 0x1d
+#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1StrictVCOrder_En__SHIFT 0x1e
+#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1DmaUseChainAll_En__SHIFT 0x1f
+#define IOMMU_L1_PCIE0_L1_CNTRL_1__RESERVED_MASK 0x000001FFL
+#define IOMMU_L1_PCIE0_L1_CNTRL_1__CacheByPass_MASK 0x00000200L
+#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1CacheParityEn_MASK 0x00000400L
+#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1ParityEn_MASK 0x00000800L
+#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1DTEDis_MASK 0x00001000L
+#define IOMMU_L1_PCIE0_L1_CNTRL_1__WQ_EntryDis_MASK 0x000FE000L
+#define IOMMU_L1_PCIE0_L1_CNTRL_1__Snd_filter_dis_MASK 0x00100000L
+#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1Order_en_MASK 0x00200000L
+#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1CacheInvAllEn_MASK 0x00400000L
+#define IOMMU_L1_PCIE0_L1_CNTRL_1__Select_timeout_pulse_MASK 0x03800000L
+#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1_cache_sel_reqid_MASK 0x04000000L
+#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1_cache_sel_interleave_MASK 0x08000000L
+#define IOMMU_L1_PCIE0_L1_CNTRL_1__Pretrans_noVA_filterEn_MASK 0x10000000L
+#define IOMMU_L1_PCIE0_L1_CNTRL_1__UnTrans_2M_filterEn_MASK 0x20000000L
+#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1StrictVCOrder_En_MASK 0x40000000L
+#define IOMMU_L1_PCIE0_L1_CNTRL_1__L1DmaUseChainAll_En_MASK 0x80000000L
+//IOMMU_L1_PCIE0_L1_CNTRL_2
+#define IOMMU_L1_PCIE0_L1_CNTRL_2__L1Disable__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_CNTRL_2__MSI_to_HT_remap_dis__SHIFT 0x1
+#define IOMMU_L1_PCIE0_L1_CNTRL_2__L1_abrt_ats_dis__SHIFT 0x2
+#define IOMMU_L1_PCIE0_L1_CNTRL_2__L1ATSDataErrorSignalEn__SHIFT 0x3
+#define IOMMU_L1_PCIE0_L1_CNTRL_2__RESERVED__SHIFT 0x4
+#define IOMMU_L1_PCIE0_L1_CNTRL_2__CPD_RESP_MODE__SHIFT 0x18
+#define IOMMU_L1_PCIE0_L1_CNTRL_2__L1NonConsumedDataErrorSignalEn__SHIFT 0x1b
+#define IOMMU_L1_PCIE0_L1_CNTRL_2__L1ConsumedDataErrorSignalEn__SHIFT 0x1c
+#define IOMMU_L1_PCIE0_L1_CNTRL_2__L1SDPParityEn__SHIFT 0x1d
+#define IOMMU_L1_PCIE0_L1_CNTRL_2__FlushVC_HRT1_Inv__SHIFT 0x1e
+#define IOMMU_L1_PCIE0_L1_CNTRL_2__FlushVC_HRT1_IntInv__SHIFT 0x1f
+#define IOMMU_L1_PCIE0_L1_CNTRL_2__L1Disable_MASK 0x00000001L
+#define IOMMU_L1_PCIE0_L1_CNTRL_2__MSI_to_HT_remap_dis_MASK 0x00000002L
+#define IOMMU_L1_PCIE0_L1_CNTRL_2__L1_abrt_ats_dis_MASK 0x00000004L
+#define IOMMU_L1_PCIE0_L1_CNTRL_2__L1ATSDataErrorSignalEn_MASK 0x00000008L
+#define IOMMU_L1_PCIE0_L1_CNTRL_2__RESERVED_MASK 0x00FFFFF0L
+#define IOMMU_L1_PCIE0_L1_CNTRL_2__CPD_RESP_MODE_MASK 0x07000000L
+#define IOMMU_L1_PCIE0_L1_CNTRL_2__L1NonConsumedDataErrorSignalEn_MASK 0x08000000L
+#define IOMMU_L1_PCIE0_L1_CNTRL_2__L1ConsumedDataErrorSignalEn_MASK 0x10000000L
+#define IOMMU_L1_PCIE0_L1_CNTRL_2__L1SDPParityEn_MASK 0x20000000L
+#define IOMMU_L1_PCIE0_L1_CNTRL_2__FlushVC_HRT1_Inv_MASK 0x40000000L
+#define IOMMU_L1_PCIE0_L1_CNTRL_2__FlushVC_HRT1_IntInv_MASK 0x80000000L
+//IOMMU_L1_PCIE0_L1_CNTRL_3
+#define IOMMU_L1_PCIE0_L1_CNTRL_3__ATS_tlbinv_pulse_width__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_CNTRL_3__ATS_tlbinv_pulse_width_MASK 0xFFFFFFFFL
+//IOMMU_L1_PCIE0_L1_BANK_SEL_0
+#define IOMMU_L1_PCIE0_L1_BANK_SEL_0__L1CacheBankSel_0__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_BANK_SEL_0__L1CacheBankSel_0_MASK 0x0000FFFFL
+//IOMMU_L1_PCIE0_L1_BANK_DISABLE_0
+#define IOMMU_L1_PCIE0_L1_BANK_DISABLE_0__L1CacheLineDis_0__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_BANK_DISABLE_0__L1CacheLineDis_1__SHIFT 0x8
+#define IOMMU_L1_PCIE0_L1_BANK_DISABLE_0__L1CacheLineDis_0_MASK 0x0000003FL
+#define IOMMU_L1_PCIE0_L1_BANK_DISABLE_0__L1CacheLineDis_1_MASK 0x00003F00L
+//IOMMU_L1_PCIE0_L1_WQ_STATUS_0
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus0__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus1__SHIFT 0x3
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus2__SHIFT 0x6
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus3__SHIFT 0x9
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus4__SHIFT 0xc
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus5__SHIFT 0xf
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus6__SHIFT 0x12
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus7__SHIFT 0x15
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus8__SHIFT 0x18
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus9__SHIFT 0x1b
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus0_MASK 0x00000007L
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus1_MASK 0x00000038L
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus2_MASK 0x000001C0L
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus3_MASK 0x00000E00L
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus4_MASK 0x00007000L
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus5_MASK 0x00038000L
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus6_MASK 0x001C0000L
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus7_MASK 0x00E00000L
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus8_MASK 0x07000000L
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus9_MASK 0x38000000L
+//IOMMU_L1_PCIE0_L1_WQ_STATUS_1
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus10__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus11__SHIFT 0x3
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus12__SHIFT 0x6
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus13__SHIFT 0x9
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus14__SHIFT 0xc
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus15__SHIFT 0xf
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus16__SHIFT 0x12
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus17__SHIFT 0x15
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus18__SHIFT 0x18
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus19__SHIFT 0x1b
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus10_MASK 0x00000007L
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus11_MASK 0x00000038L
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus12_MASK 0x000001C0L
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus13_MASK 0x00000E00L
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus14_MASK 0x00007000L
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus15_MASK 0x00038000L
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus16_MASK 0x001C0000L
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus17_MASK 0x00E00000L
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus18_MASK 0x07000000L
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus19_MASK 0x38000000L
+//IOMMU_L1_PCIE0_L1_WQ_STATUS_2
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus20__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus21__SHIFT 0x3
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus22__SHIFT 0x6
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus23__SHIFT 0x9
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus24__SHIFT 0xc
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus25__SHIFT 0xf
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus26__SHIFT 0x12
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus27__SHIFT 0x15
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus28__SHIFT 0x18
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus29__SHIFT 0x1b
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus20_MASK 0x00000007L
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus21_MASK 0x00000038L
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus22_MASK 0x000001C0L
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus23_MASK 0x00000E00L
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus24_MASK 0x00007000L
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus25_MASK 0x00038000L
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus26_MASK 0x001C0000L
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus27_MASK 0x00E00000L
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus28_MASK 0x07000000L
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus29_MASK 0x38000000L
+//IOMMU_L1_PCIE0_L1_WQ_STATUS_3
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_3__EntryStatus30__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_3__EntryStatus31__SHIFT 0x3
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_3__Invalidation_status__SHIFT 0x8
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_3__EntryStatus30_MASK 0x00000007L
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_3__EntryStatus31_MASK 0x00000038L
+#define IOMMU_L1_PCIE0_L1_WQ_STATUS_3__Invalidation_status_MASK 0x0000FF00L
+//IOMMU_L1_PCIE0_L1_FEATURE_CNTRL
+#define IOMMU_L1_PCIE0_L1_FEATURE_CNTRL__Debug_sticky_bits__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_FEATURE_CNTRL__Reserved__SHIFT 0x8
+#define IOMMU_L1_PCIE0_L1_FEATURE_CNTRL__Debug_sticky_bits_MASK 0x000000FFL
+#define IOMMU_L1_PCIE0_L1_FEATURE_CNTRL__Reserved_MASK 0xFFFFFF00L
+//IOMMU_L1_PCIE0_L1_PGMEM_CTRL_5
+#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_5__L1_LS_Req_Maintain_Cnt__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_5__L1_LS_Req_Maintain_Cnt_MASK 0xFFFFFFFFL
+//IOMMU_L1_PCIE0_L1_PGMEM_CTRL_6
+#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_6__L1_LS_Exit_Maintain_Cnt__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_6__L1_LS_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL
+//IOMMU_L1_PCIE0_L1_PGMEM_CTRL_7
+#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_7__L1_DS_Req_Maintain_Cnt__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_7__L1_DS_Req_Maintain_Cnt_MASK 0xFFFFFFFFL
+//IOMMU_L1_PCIE0_L1_PGMEM_CTRL_8
+#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_8__L1_DS_Exit_Maintain_Cnt__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_8__L1_DS_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL
+//IOMMU_L1_PCIE0_L1_PGMEM_CTRL_9
+#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_9__L1_SD_Req_Maintain_Cnt__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_9__L1_SD_Req_Maintain_Cnt_MASK 0xFFFFFFFFL
+//IOMMU_L1_PCIE0_L1_PGMEM_CTRL_10
+#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_10__L1_SD_Exit_Maintain_Cnt__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_10__L1_SD_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL
+//IOMMU_L1_PCIE0_L1_CNTRL_4
+#define IOMMU_L1_PCIE0_L1_CNTRL_4__ATS_multiple_resp_en__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_CNTRL_4__Timeout_pulse_ext_En__SHIFT 0x2
+#define IOMMU_L1_PCIE0_L1_CNTRL_4__RESERVED__SHIFT 0x4
+#define IOMMU_L1_PCIE0_L1_CNTRL_4__AtsRsp_send_mem_type_en__SHIFT 0x17
+#define IOMMU_L1_PCIE0_L1_CNTRL_4__IntGfx_UnitID_Val__SHIFT 0x18
+#define IOMMU_L1_PCIE0_L1_CNTRL_4__ATS_multiple_resp_en_MASK 0x00000001L
+#define IOMMU_L1_PCIE0_L1_CNTRL_4__Timeout_pulse_ext_En_MASK 0x00000004L
+#define IOMMU_L1_PCIE0_L1_CNTRL_4__RESERVED_MASK 0x007FFFF0L
+#define IOMMU_L1_PCIE0_L1_CNTRL_4__AtsRsp_send_mem_type_en_MASK 0x00800000L
+#define IOMMU_L1_PCIE0_L1_CNTRL_4__IntGfx_UnitID_Val_MASK 0x7F000000L
+//IOMMU_L1_PCIE0_L1_CLKCNTRL_0
+#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_DMA_CLKGATE_EN__SHIFT 0x4
+#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_CACHE_CLKGATE_EN__SHIFT 0x5
+#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_CPSLV_CLKGATE_EN__SHIFT 0x6
+#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_PERF_CLKGATE_EN__SHIFT 0x8
+#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_MEMORY_CLKGATE_EN__SHIFT 0x9
+#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_REG_CLKGATE_EN__SHIFT 0xa
+#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_HOSTREQ_CLKGATE_EN__SHIFT 0xb
+#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_DMARSP_CLKGATE_EN__SHIFT 0xc
+#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_HOSTRSP_CLKGATE_EN__SHIFT 0xd
+#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_CLKGATE_HYSTERESIS__SHIFT 0xe
+#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__reserved__SHIFT 0x16
+#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_L2_CLKGATE_EN__SHIFT 0x1f
+#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_DMA_CLKGATE_EN_MASK 0x00000010L
+#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_CACHE_CLKGATE_EN_MASK 0x00000020L
+#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_CPSLV_CLKGATE_EN_MASK 0x00000040L
+#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_PERF_CLKGATE_EN_MASK 0x00000100L
+#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_MEMORY_CLKGATE_EN_MASK 0x00000200L
+#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_REG_CLKGATE_EN_MASK 0x00000400L
+#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_HOSTREQ_CLKGATE_EN_MASK 0x00000800L
+#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_DMARSP_CLKGATE_EN_MASK 0x00001000L
+#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_HOSTRSP_CLKGATE_EN_MASK 0x00002000L
+#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_CLKGATE_HYSTERESIS_MASK 0x003FC000L
+#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__reserved_MASK 0x7FC00000L
+#define IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_L2_CLKGATE_EN_MASK 0x80000000L
+//IOMMU_L1_PCIE0_L1_SDP_CLKREQ_CNTRL
+#define IOMMU_L1_PCIE0_L1_SDP_CLKREQ_CNTRL__HW_PG_WAKEUP_EN_DMA__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_SDP_CLKREQ_CNTRL__HW_PG_WAKEUP_EN_HOST__SHIFT 0x1
+#define IOMMU_L1_PCIE0_L1_SDP_CLKREQ_CNTRL__HW_PG_WAKEUP_EN_DMA_MASK 0x00000001L
+#define IOMMU_L1_PCIE0_L1_SDP_CLKREQ_CNTRL__HW_PG_WAKEUP_EN_HOST_MASK 0x00000002L
+//IOMMU_L1_PCIE0_L1_GUEST_ADDR_CNTRL
+#define IOMMU_L1_PCIE0_L1_GUEST_ADDR_CNTRL__L1_CANONICAL_ERR_EN__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_GUEST_ADDR_CNTRL__reserved__SHIFT 0x1
+#define IOMMU_L1_PCIE0_L1_GUEST_ADDR_CNTRL__L1_GUEST_ADDR_MSK__SHIFT 0x8
+#define IOMMU_L1_PCIE0_L1_GUEST_ADDR_CNTRL__L1_CANONICAL_ERR_EN_MASK 0x00000001L
+#define IOMMU_L1_PCIE0_L1_GUEST_ADDR_CNTRL__reserved_MASK 0x000000FEL
+#define IOMMU_L1_PCIE0_L1_GUEST_ADDR_CNTRL__L1_GUEST_ADDR_MSK_MASK 0xFFFFFF00L
+//IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL
+#define IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__L1_EFR_SUP__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__L1_PPR_SUP__SHIFT 0x1
+#define IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__L1_DTE_seg_W__SHIFT 0x2
+#define IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__L1_GT_SUP_W__SHIFT 0x4
+#define IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__reserved__SHIFT 0x5
+#define IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__L1_EFR_SUP_MASK 0x00000001L
+#define IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__L1_PPR_SUP_MASK 0x00000002L
+#define IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__L1_DTE_seg_W_MASK 0x0000000CL
+#define IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__L1_GT_SUP_W_MASK 0x00000010L
+#define IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__reserved_MASK 0xFFFFFFE0L
+//IOMMU_L1_PCIE0_L1_CNTRL_5
+#define IOMMU_L1_PCIE0_L1_CNTRL_5__RESERVED__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_CNTRL_5__RESERVED_MASK 0xFFFFFFFFL
+//IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1
+#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1__L1_LS_EN__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1__L1_DS_EN__SHIFT 0x1
+#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1__L1_SD_EN__SHIFT 0x2
+#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1__L1_IP_PGMEM_SEL__SHIFT 0x3
+#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1__L1_LS_EN_MASK 0x00000001L
+#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1__L1_DS_EN_MASK 0x00000002L
+#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1__L1_SD_EN_MASK 0x00000004L
+#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1__L1_IP_PGMEM_SEL_MASK 0x00000008L
+//IOMMU_L1_PCIE0_L1_PGMEM_CTRL_2
+#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_2__L1_LS_thres__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_2__L1_LS_thres_MASK 0xFFFFFFFFL
+//IOMMU_L1_PCIE0_L1_PGMEM_CTRL_3
+#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_3__L1_DS_thres__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_3__L1_DS_thres_MASK 0xFFFFFFFFL
+//IOMMU_L1_PCIE0_L1_PGMEM_CTRL_4
+#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_4__L1_SD_thres__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_PGMEM_CTRL_4__L1_SD_thres_MASK 0xFFFFFFFFL
+//IOMMU_L1_PCIE0_IOMMU_PGSLV_CONTROL
+#define IOMMU_L1_PCIE0_IOMMU_PGSLV_CONTROL__CFG_IDLE_HYSTERESIS__SHIFT 0x0
+#define IOMMU_L1_PCIE0_IOMMU_PGSLV_CONTROL__L1_PG_STATUS__SHIFT 0x5
+#define IOMMU_L1_PCIE0_IOMMU_PGSLV_CONTROL__CFG_IDLE_HYSTERESIS_MASK 0x0000001FL
+#define IOMMU_L1_PCIE0_IOMMU_PGSLV_CONTROL__L1_PG_STATUS_MASK 0x00000020L
+//IOMMU_L1_PCIE0_L1_ATS_RESP_CTRL_0
+#define IOMMU_L1_PCIE0_L1_ATS_RESP_CTRL_0__L1_ATS_Resp_allow_timer__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_ATS_RESP_CTRL_0__L1_ATS_Resp_delay_timer__SHIFT 0x8
+#define IOMMU_L1_PCIE0_L1_ATS_RESP_CTRL_0__L1_ATSdely_on_PPRAutoResp_en__SHIFT 0x1f
+#define IOMMU_L1_PCIE0_L1_ATS_RESP_CTRL_0__L1_ATS_Resp_allow_timer_MASK 0x000000FFL
+#define IOMMU_L1_PCIE0_L1_ATS_RESP_CTRL_0__L1_ATS_Resp_delay_timer_MASK 0x0000FF00L
+#define IOMMU_L1_PCIE0_L1_ATS_RESP_CTRL_0__L1_ATSdely_on_PPRAutoResp_en_MASK 0x80000000L
+//IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control
+#define IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control__StallNPReqEn__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control__StallPReqEn__SHIFT 0x2
+#define IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control__StallUpWrReqEn__SHIFT 0x6
+#define IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn__SHIFT 0xe
+#define IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control__StallNPReqEn_MASK 0x00000003L
+#define IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control__StallPReqEn_MASK 0x0000000CL
+#define IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control__StallUpWrReqEn_MASK 0x000000C0L
+#define IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn_MASK 0x0000C000L
+//IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control
+#define IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control__StallNPRspEn__SHIFT 0x0
+#define IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control__StallPRspEn__SHIFT 0x2
+#define IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control__StallUpWrRspEn__SHIFT 0x6
+#define IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control__StallHRT1RspEn__SHIFT 0xe
+#define IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control__StallNPRspEn_MASK 0x00000003L
+#define IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control__StallPRspEn_MASK 0x0000000CL
+#define IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control__StallUpWrRspEn_MASK 0x000000C0L
+#define IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control__StallHRT1RspEn_MASK 0x0000C000L
+//IOMMU_L1_PCIE0_L1_CLIENT_HostReq_Stall_Control
+#define IOMMU_L1_PCIE0_L1_CLIENT_HostReq_Stall_Control__StallNPReqEn__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_CLIENT_HostReq_Stall_Control__StallPReqEn__SHIFT 0x2
+#define IOMMU_L1_PCIE0_L1_CLIENT_HostReq_Stall_Control__StallNPReqEn_MASK 0x00000003L
+#define IOMMU_L1_PCIE0_L1_CLIENT_HostReq_Stall_Control__StallPReqEn_MASK 0x0000000CL
+//IOMMU_L1_PCIE0_IOHC_L1_HostRsp_Stall_Control
+#define IOMMU_L1_PCIE0_IOHC_L1_HostRsp_Stall_Control__StallNPRspEn__SHIFT 0x0
+#define IOMMU_L1_PCIE0_IOHC_L1_HostRsp_Stall_Control__StallPRspEn__SHIFT 0x2
+#define IOMMU_L1_PCIE0_IOHC_L1_HostRsp_Stall_Control__StallNPRspEn_MASK 0x00000003L
+#define IOMMU_L1_PCIE0_IOHC_L1_HostRsp_Stall_Control__StallPRspEn_MASK 0x0000000CL
+//IOMMU_L1_PCIE0_L1_SDP_MAXCRED_0
+#define IOMMU_L1_PCIE0_L1_SDP_MAXCRED_0__L1_FLUSHRSP_MAXCRED__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_SDP_MAXCRED_0__L1_HOSTRDRSP_MAXCRED__SHIFT 0x4
+#define IOMMU_L1_PCIE0_L1_SDP_MAXCRED_0__L1_HOSTWRRSP_MAXCRED__SHIFT 0xa
+#define IOMMU_L1_PCIE0_L1_SDP_MAXCRED_0__L1_FLUSHRSP_MAXCRED_MASK 0x0000000FL
+#define IOMMU_L1_PCIE0_L1_SDP_MAXCRED_0__L1_HOSTRDRSP_MAXCRED_MASK 0x000003F0L
+#define IOMMU_L1_PCIE0_L1_SDP_MAXCRED_0__L1_HOSTWRRSP_MAXCRED_MASK 0x0000FC00L
+//IOMMU_L1_PCIE0_L1_ECO_CNTRL
+#define IOMMU_L1_PCIE0_L1_ECO_CNTRL__L1_ECO__SHIFT 0x0
+#define IOMMU_L1_PCIE0_L1_ECO_CNTRL__L1_ECO_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_iohub_iommu_l1shdw_PCIE0_l1shdw
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_BASE_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE_MASK 0x000001FFL
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__IOMMU_EN__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__HT_TUN_EN__SHIFT 0x1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__EVENT_LOG_EN__SHIFT 0x2
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__EVENT_INT_EN__SHIFT 0x3
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__COM_WAIT_INTEN__SHIFT 0x4
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__INV_TIMEOUT__SHIFT 0x5
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__PASS_PW__SHIFT 0x8
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__RES_PASS_PW__SHIFT 0x9
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__COHERENT__SHIFT 0xa
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__ISOC__SHIFT 0xb
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__CMD_BUF_EN__SHIFT 0xc
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__PPR_LOG_EN__SHIFT 0xd
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__PPR_EN__SHIFT 0xf
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__GT_EN__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__GA_EN__SHIFT 0x11
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__TLPT__SHIFT 0x12
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__IOMMU_EN_MASK 0x00000001L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__HT_TUN_EN_MASK 0x00000002L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__EVENT_LOG_EN_MASK 0x00000004L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__EVENT_INT_EN_MASK 0x00000008L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__COM_WAIT_INTEN_MASK 0x00000010L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__INV_TIMEOUT_MASK 0x000000E0L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__PASS_PW_MASK 0x00000100L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__RES_PASS_PW_MASK 0x00000200L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__COHERENT_MASK 0x00000400L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__ISOC_MASK 0x00000800L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__CMD_BUF_EN_MASK 0x00001000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__PPR_LOG_EN_MASK 0x00002000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__PPR_EN_MASK 0x00008000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__GT_EN_MASK 0x00010000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__GA_EN_MASK 0x00020000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__TLPT_MASK 0x003C0000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_1__DTE_SEG_EN__SHIFT 0x2
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_1__DTE_SEG_EN_MASK 0x0000000CL
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EX_EN__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW__SHIFT 0x1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__Reserved0__SHIFT 0x2
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO__SHIFT 0xc
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EX_EN_MASK 0x00000001L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW_MASK 0x00000002L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__Reserved0_MASK 0x00000FFCL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO_MASK 0xFFFFF000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_1__Reserved0__SHIFT 0x14
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI_MASK 0x000FFFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_1__Reserved0_MASK 0xFFF00000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_0__Reserved0__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO__SHIFT 0xc
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_0__Reserved0_MASK 0x00000FFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO_MASK 0xFFFFF000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_1__Reserved0__SHIFT 0x14
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI_MASK 0x000FFFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_1__Reserved0_MASK 0xFFF00000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_1_BASE_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE_MASK 0x000001FFL
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_2_BASE_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE_MASK 0x000001FFL
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_3_BASE_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE_MASK 0x000001FFL
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_4_BASE_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE_MASK 0x000001FFL
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_5_BASE_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE_MASK 0x000001FFL
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_6_BASE_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE_MASK 0x000001FFL
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_7_BASE_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE_MASK 0x000001FFL
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0__PASID_LOCK_LO__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0__PASID_LOCK_LO_MASK 0xFFFFFFFFL
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1__PASID_LOCK_HI__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1__PASID_LOCK_HI_MASK 0xFFFFFFFFL
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0__DOMAIN_LOCK_LO__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0__DOMAIN_LOCK_LO_MASK 0xFFFFFFFFL
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1__DOMAIN_LOCK_HI__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1__DOMAIN_LOCK_HI_MASK 0xFFFFFFFFL
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0__DEVID_LOCK_LO__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0__DEVID_LOCK_LO_MASK 0xFFFFFFFFL
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1__DEVID_LOCK_HI__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1__DEVID_LOCK_HI_MASK 0xFFFFFFFFL
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CSOURCE_0_0__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__Reserved1__SHIFT 0x8
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__COUNT_UNITS_0_0__SHIFT 0x1e
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CAC_0_0__SHIFT 0x1f
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CSOURCE_0_0_MASK 0x000000FFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__Reserved1_MASK 0x3FFFFF00L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__COUNT_UNITS_0_0_MASK 0x40000000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CAC_0_0_MASK 0x80000000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASID_MATCH_0_0__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASMEN_0_0__SHIFT 0x1f
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASID_MATCH_0_0_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASMEN_0_0_MASK 0x80000000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__PASID_MASK_0_0__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__PASID_MASK_0_0_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMAIN_MATCH_0_0__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMMEN_0_0__SHIFT 0x1f
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMAIN_MATCH_0_0_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMMEN_0_0_MASK 0x80000000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__DOMAIN_MASK_0_0__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__DOMAIN_MASK_0_0_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DEVICEID_MATCH_0_0__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DIDMEN_0_0__SHIFT 0x1f
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DEVICEID_MATCH_0_0_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DIDMEN_0_0_MASK 0x80000000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__DEVICEID_MASK_0_0__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__DEVICEID_MASK_0_0_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CSOURCE_0_1__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__Reserved1__SHIFT 0x8
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__COUNT_UNITS_0_1__SHIFT 0x1e
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CAC_0_1__SHIFT 0x1f
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CSOURCE_0_1_MASK 0x000000FFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__Reserved1_MASK 0x3FFFFF00L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__COUNT_UNITS_0_1_MASK 0x40000000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CAC_0_1_MASK 0x80000000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASID_MATCH_0_1__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASMEN_0_1__SHIFT 0x1f
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASID_MATCH_0_1_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASMEN_0_1_MASK 0x80000000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__PASID_MASK_0_1__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__PASID_MASK_0_1_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMAIN_MATCH_0_1__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMMEN_0_1__SHIFT 0x1f
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMAIN_MATCH_0_1_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMMEN_0_1_MASK 0x80000000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__DOMAIN_MASK_0_1__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__DOMAIN_MASK_0_1_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DEVICEID_MATCH_0_1__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DIDMEN_0_1__SHIFT 0x1f
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DEVICEID_MATCH_0_1_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DIDMEN_0_1_MASK 0x80000000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__DEVICEID_MASK_0_1__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__DEVICEID_MASK_0_1_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CSOURCE_0_2__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__Reserved1__SHIFT 0x8
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__COUNT_UNITS_0_2__SHIFT 0x1e
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CAC_0_2__SHIFT 0x1f
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CSOURCE_0_2_MASK 0x000000FFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__Reserved1_MASK 0x3FFFFF00L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__COUNT_UNITS_0_2_MASK 0x40000000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CAC_0_2_MASK 0x80000000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASID_MATCH_0_2__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASMEN_0_2__SHIFT 0x1f
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASID_MATCH_0_2_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASMEN_0_2_MASK 0x80000000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__PASID_MASK_0_2__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__PASID_MASK_0_2_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMAIN_MATCH_0_2__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMMEN_0_2__SHIFT 0x1f
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMAIN_MATCH_0_2_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMMEN_0_2_MASK 0x80000000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__DOMAIN_MASK_0_2__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__DOMAIN_MASK_0_2_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DEVICEID_MATCH_0_2__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DIDMEN_0_2__SHIFT 0x1f
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DEVICEID_MATCH_0_2_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DIDMEN_0_2_MASK 0x80000000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__DEVICEID_MASK_0_2__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__DEVICEID_MASK_0_2_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CSOURCE_0_3__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__Reserved1__SHIFT 0x8
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__COUNT_UNITS_0_3__SHIFT 0x1e
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CAC_0_3__SHIFT 0x1f
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CSOURCE_0_3_MASK 0x000000FFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__Reserved1_MASK 0x3FFFFF00L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__COUNT_UNITS_0_3_MASK 0x40000000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CAC_0_3_MASK 0x80000000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASID_MATCH_0_3__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASMEN_0_3__SHIFT 0x1f
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASID_MATCH_0_3_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASMEN_0_3_MASK 0x80000000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__PASID_MASK_0_3__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__PASID_MASK_0_3_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMAIN_MATCH_0_3__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMMEN_0_3__SHIFT 0x1f
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMAIN_MATCH_0_3_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMMEN_0_3_MASK 0x80000000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__DOMAIN_MASK_0_3__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__DOMAIN_MASK_0_3_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DEVICEID_MATCH_0_3__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DIDMEN_0_3__SHIFT 0x1f
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DEVICEID_MATCH_0_3_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DIDMEN_0_3_MASK 0x80000000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__DEVICEID_MASK_0_3__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__DEVICEID_MASK_0_3_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CSOURCE_1_0__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__Reserved1__SHIFT 0x8
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__COUNT_UNITS_1_0__SHIFT 0x1e
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CAC_1_0__SHIFT 0x1f
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CSOURCE_1_0_MASK 0x000000FFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__Reserved1_MASK 0x3FFFFF00L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__COUNT_UNITS_1_0_MASK 0x40000000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CAC_1_0_MASK 0x80000000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASID_MATCH_1_0__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASMEN_1_0__SHIFT 0x1f
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASID_MATCH_1_0_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASMEN_1_0_MASK 0x80000000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__PASID_MASK_1_0__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__PASID_MASK_1_0_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMAIN_MATCH_1_0__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMMEN_1_0__SHIFT 0x1f
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMAIN_MATCH_1_0_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMMEN_1_0_MASK 0x80000000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__DOMAIN_MASK_1_0__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__DOMAIN_MASK_1_0_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DEVICEID_MATCH_1_0__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DIDMEN_1_0__SHIFT 0x1f
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DEVICEID_MATCH_1_0_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DIDMEN_1_0_MASK 0x80000000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__DEVICEID_MASK_1_0__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__DEVICEID_MASK_1_0_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CSOURCE_1_1__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__Reserved1__SHIFT 0x8
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__COUNT_UNITS_1_1__SHIFT 0x1e
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CAC_1_1__SHIFT 0x1f
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CSOURCE_1_1_MASK 0x000000FFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__Reserved1_MASK 0x3FFFFF00L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__COUNT_UNITS_1_1_MASK 0x40000000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CAC_1_1_MASK 0x80000000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASID_MATCH_1_1__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASMEN_1_1__SHIFT 0x1f
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASID_MATCH_1_1_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASMEN_1_1_MASK 0x80000000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__PASID_MASK_1_1__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__PASID_MASK_1_1_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMAIN_MATCH_1_1__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMMEN_1_1__SHIFT 0x1f
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMAIN_MATCH_1_1_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMMEN_1_1_MASK 0x80000000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__DOMAIN_MASK_1_1__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__DOMAIN_MASK_1_1_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DEVICEID_MATCH_1_1__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DIDMEN_1_1__SHIFT 0x1f
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DEVICEID_MATCH_1_1_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DIDMEN_1_1_MASK 0x80000000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__DEVICEID_MASK_1_1__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__DEVICEID_MASK_1_1_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CSOURCE_1_2__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__Reserved1__SHIFT 0x8
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__COUNT_UNITS_1_2__SHIFT 0x1e
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CAC_1_2__SHIFT 0x1f
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CSOURCE_1_2_MASK 0x000000FFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__Reserved1_MASK 0x3FFFFF00L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__COUNT_UNITS_1_2_MASK 0x40000000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CAC_1_2_MASK 0x80000000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASID_MATCH_1_2__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASMEN_1_2__SHIFT 0x1f
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASID_MATCH_1_2_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASMEN_1_2_MASK 0x80000000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__PASID_MASK_1_2__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__PASID_MASK_1_2_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMAIN_MATCH_1_2__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMMEN_1_2__SHIFT 0x1f
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMAIN_MATCH_1_2_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMMEN_1_2_MASK 0x80000000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__DOMAIN_MASK_1_2__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__DOMAIN_MASK_1_2_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DEVICEID_MATCH_1_2__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DIDMEN_1_2__SHIFT 0x1f
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DEVICEID_MATCH_1_2_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DIDMEN_1_2_MASK 0x80000000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__DEVICEID_MASK_1_2__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__DEVICEID_MASK_1_2_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CSOURCE_1_3__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__Reserved1__SHIFT 0x8
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__COUNT_UNITS_1_3__SHIFT 0x1e
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CAC_1_3__SHIFT 0x1f
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CSOURCE_1_3_MASK 0x000000FFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__Reserved1_MASK 0x3FFFFF00L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__COUNT_UNITS_1_3_MASK 0x40000000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CAC_1_3_MASK 0x80000000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASID_MATCH_1_3__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASMEN_1_3__SHIFT 0x1f
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASID_MATCH_1_3_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASMEN_1_3_MASK 0x80000000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__PASID_MASK_1_3__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__PASID_MASK_1_3_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMAIN_MATCH_1_3__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMMEN_1_3__SHIFT 0x1f
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMAIN_MATCH_1_3_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMMEN_1_3_MASK 0x80000000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__DOMAIN_MASK_1_3__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__DOMAIN_MASK_1_3_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DEVICEID_MATCH_1_3__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DIDMEN_1_3__SHIFT 0x1f
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DEVICEID_MATCH_1_3_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DIDMEN_1_3_MASK 0x80000000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__DEVICEID_MASK_1_3__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__DEVICEID_MASK_1_3_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_BASE_LO
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_BASE_LO__IOMMU_ENABLE__SHIFT 0x0
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_BASE_LO__IOMMU_ENABLE_MASK 0x00000001L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV__SHIFT 0x16
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV_MASK 0x00400000L
+//IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC_1
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE__SHIFT 0x5
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC_1__DVM_MODE__SHIFT 0x6
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE_MASK 0x00000020L
+#define IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC_1__DVM_MODE_MASK 0x000000C0L
+
+
+// addressBlock: nbio_iohub_iommu_l1psp_PCIE0_l1psp
+//IOMMU_L1PSP_PCIE0_L1PSP_ERR_REP_CNTRL
+#define IOMMU_L1PSP_PCIE0_L1PSP_ERR_REP_CNTRL__CPD_SUP__SHIFT 0x0
+#define IOMMU_L1PSP_PCIE0_L1PSP_ERR_REP_CNTRL__Reserved__SHIFT 0x1
+#define IOMMU_L1PSP_PCIE0_L1PSP_ERR_REP_CNTRL__CPD_SUP_MASK 0x00000001L
+#define IOMMU_L1PSP_PCIE0_L1PSP_ERR_REP_CNTRL__Reserved_MASK 0xFFFFFFFEL
+//IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0
+#define IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0__CPDV__SHIFT 0x0
+#define IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0__CPDO__SHIFT 0x1
+#define IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0__Reserved__SHIFT 0x2
+#define IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0__CPD_REQSTREAM_ID__SHIFT 0x10
+#define IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0__CPDV_MASK 0x00000001L
+#define IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0__CPDO_MASK 0x00000002L
+#define IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0__Reserved_MASK 0x0000FFFCL
+#define IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0__CPD_REQSTREAM_ID_MASK 0xFFFF0000L
+//IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_1
+#define IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_1__Reserved__SHIFT 0x0
+#define IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_1__Reserved_MASK 0xFFFFFFFFL
+//IOMMU_L1PSP_PCIE0_L1PSP_CPD_REQADDR_0
+#define IOMMU_L1PSP_PCIE0_L1PSP_CPD_REQADDR_0__CPD_REQADDR_LO__SHIFT 0x0
+#define IOMMU_L1PSP_PCIE0_L1PSP_CPD_REQADDR_0__CPD_REQADDR_LO_MASK 0xFFFFFFFFL
+//IOMMU_L1PSP_PCIE0_L1PSP_CPD_REQADDR_1
+#define IOMMU_L1PSP_PCIE0_L1PSP_CPD_REQADDR_1__CPD_REQADDR_HI__SHIFT 0x0
+#define IOMMU_L1PSP_PCIE0_L1PSP_CPD_REQADDR_1__CPD_REQADDR_HI_MASK 0xFFFFFFFFL
+//IOMMU_L1PSP_PCIE0_L1PSP_REQ_CNTRL
+#define IOMMU_L1PSP_PCIE0_L1PSP_REQ_CNTRL__AbortPreTrans__SHIFT 0x0
+#define IOMMU_L1PSP_PCIE0_L1PSP_REQ_CNTRL__Reserved__SHIFT 0x1
+#define IOMMU_L1PSP_PCIE0_L1PSP_REQ_CNTRL__AbortPreTrans_MASK 0x00000001L
+#define IOMMU_L1PSP_PCIE0_L1PSP_REQ_CNTRL__Reserved_MASK 0xFFFFFFFEL
+
+
+// addressBlock: nbio_iohub_iommu_l1_IOAGR_iommul1cfg
+//IOMMU_L1_IOAGR_L1_PERF_CNTL
+#define IOMMU_L1_IOAGR_L1_PERF_CNTL__L1_PERF_EVENT0__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_PERF_CNTL__L1_PERF_EVENT1__SHIFT 0x8
+#define IOMMU_L1_IOAGR_L1_PERF_CNTL__L1_PERF_COUNT_HI_0__SHIFT 0x10
+#define IOMMU_L1_IOAGR_L1_PERF_CNTL__L1_PERF_COUNT_HI_1__SHIFT 0x18
+#define IOMMU_L1_IOAGR_L1_PERF_CNTL__L1_PERF_EVENT0_MASK 0x000000FFL
+#define IOMMU_L1_IOAGR_L1_PERF_CNTL__L1_PERF_EVENT1_MASK 0x0000FF00L
+#define IOMMU_L1_IOAGR_L1_PERF_CNTL__L1_PERF_COUNT_HI_0_MASK 0x00FF0000L
+#define IOMMU_L1_IOAGR_L1_PERF_CNTL__L1_PERF_COUNT_HI_1_MASK 0xFF000000L
+//IOMMU_L1_IOAGR_L1_PERF_COUNT_0
+#define IOMMU_L1_IOAGR_L1_PERF_COUNT_0__L1_PERF_COUNT_0__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_PERF_COUNT_0__L1_PERF_COUNT_0_MASK 0xFFFFFFFFL
+//IOMMU_L1_IOAGR_L1_PERF_COUNT_1
+#define IOMMU_L1_IOAGR_L1_PERF_COUNT_1__L1_PERF_COUNT_1__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_PERF_COUNT_1__L1_PERF_COUNT_1_MASK 0xFFFFFFFFL
+//IOMMU_L1_IOAGR_L1_PERF_CNTL_B
+#define IOMMU_L1_IOAGR_L1_PERF_CNTL_B__L1_PERF_EVENT2__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_PERF_CNTL_B__L1_PERF_EVENT3__SHIFT 0x8
+#define IOMMU_L1_IOAGR_L1_PERF_CNTL_B__L1_PERF_COUNT_HI_2__SHIFT 0x10
+#define IOMMU_L1_IOAGR_L1_PERF_CNTL_B__L1_PERF_COUNT_HI_3__SHIFT 0x18
+#define IOMMU_L1_IOAGR_L1_PERF_CNTL_B__L1_PERF_EVENT2_MASK 0x000000FFL
+#define IOMMU_L1_IOAGR_L1_PERF_CNTL_B__L1_PERF_EVENT3_MASK 0x0000FF00L
+#define IOMMU_L1_IOAGR_L1_PERF_CNTL_B__L1_PERF_COUNT_HI_2_MASK 0x00FF0000L
+#define IOMMU_L1_IOAGR_L1_PERF_CNTL_B__L1_PERF_COUNT_HI_3_MASK 0xFF000000L
+//IOMMU_L1_IOAGR_L1_PERF_COUNT_B0
+#define IOMMU_L1_IOAGR_L1_PERF_COUNT_B0__L1_PERF_COUNT_2__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_PERF_COUNT_B0__L1_PERF_COUNT_2_MASK 0xFFFFFFFFL
+//IOMMU_L1_IOAGR_L1_PERF_COUNT_B1
+#define IOMMU_L1_IOAGR_L1_PERF_COUNT_B1__L1_PERF_COUNT_3__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_PERF_COUNT_B1__L1_PERF_COUNT_3_MASK 0xFFFFFFFFL
+//IOMMU_L1_IOAGR_L1_SB_LOCATION
+#define IOMMU_L1_IOAGR_L1_SB_LOCATION__SBlocated_Port__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_SB_LOCATION__SBlocated_Core__SHIFT 0x10
+#define IOMMU_L1_IOAGR_L1_SB_LOCATION__SBlocated_Port_MASK 0x0000FFFFL
+#define IOMMU_L1_IOAGR_L1_SB_LOCATION__SBlocated_Core_MASK 0xFFFF0000L
+//IOMMU_L1_IOAGR_L1_CNTRL_0
+#define IOMMU_L1_IOAGR_L1_CNTRL_0__Unfilter_dis__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_CNTRL_0__Fragment_dis__SHIFT 0x1
+#define IOMMU_L1_IOAGR_L1_CNTRL_0__CacheIR_only__SHIFT 0x2
+#define IOMMU_L1_IOAGR_L1_CNTRL_0__CacheIW_only__SHIFT 0x3
+#define IOMMU_L1_IOAGR_L1_CNTRL_0__Reserved0__SHIFT 0x4
+#define IOMMU_L1_IOAGR_L1_CNTRL_0__RESERVED__SHIFT 0x5
+#define IOMMU_L1_IOAGR_L1_CNTRL_0__L2Credits__SHIFT 0x8
+#define IOMMU_L1_IOAGR_L1_CNTRL_0__Reserved1__SHIFT 0xe
+#define IOMMU_L1_IOAGR_L1_CNTRL_0__L1Banks__SHIFT 0x14
+#define IOMMU_L1_IOAGR_L1_CNTRL_0__L1Entries__SHIFT 0x18
+#define IOMMU_L1_IOAGR_L1_CNTRL_0__L1ErrEventDetectDis__SHIFT 0x1c
+#define IOMMU_L1_IOAGR_L1_CNTRL_0__L1ForceHostRspPassPWHigh__SHIFT 0x1d
+#define IOMMU_L1_IOAGR_L1_CNTRL_0__L1InterruptHalfDwDis__SHIFT 0x1f
+#define IOMMU_L1_IOAGR_L1_CNTRL_0__Unfilter_dis_MASK 0x00000001L
+#define IOMMU_L1_IOAGR_L1_CNTRL_0__Fragment_dis_MASK 0x00000002L
+#define IOMMU_L1_IOAGR_L1_CNTRL_0__CacheIR_only_MASK 0x00000004L
+#define IOMMU_L1_IOAGR_L1_CNTRL_0__CacheIW_only_MASK 0x00000008L
+#define IOMMU_L1_IOAGR_L1_CNTRL_0__Reserved0_MASK 0x00000010L
+#define IOMMU_L1_IOAGR_L1_CNTRL_0__RESERVED_MASK 0x00000020L
+#define IOMMU_L1_IOAGR_L1_CNTRL_0__L2Credits_MASK 0x00003F00L
+#define IOMMU_L1_IOAGR_L1_CNTRL_0__Reserved1_MASK 0x000FC000L
+#define IOMMU_L1_IOAGR_L1_CNTRL_0__L1Banks_MASK 0x00300000L
+#define IOMMU_L1_IOAGR_L1_CNTRL_0__L1Entries_MASK 0x0F000000L
+#define IOMMU_L1_IOAGR_L1_CNTRL_0__L1ErrEventDetectDis_MASK 0x10000000L
+#define IOMMU_L1_IOAGR_L1_CNTRL_0__L1ForceHostRspPassPWHigh_MASK 0x60000000L
+#define IOMMU_L1_IOAGR_L1_CNTRL_0__L1InterruptHalfDwDis_MASK 0x80000000L
+//IOMMU_L1_IOAGR_L1_CNTRL_1
+#define IOMMU_L1_IOAGR_L1_CNTRL_1__RESERVED__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_CNTRL_1__CacheByPass__SHIFT 0x9
+#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1CacheParityEn__SHIFT 0xa
+#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1ParityEn__SHIFT 0xb
+#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1DTEDis__SHIFT 0xc
+#define IOMMU_L1_IOAGR_L1_CNTRL_1__WQ_EntryDis__SHIFT 0xd
+#define IOMMU_L1_IOAGR_L1_CNTRL_1__Snd_filter_dis__SHIFT 0x14
+#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1Order_en__SHIFT 0x15
+#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1CacheInvAllEn__SHIFT 0x16
+#define IOMMU_L1_IOAGR_L1_CNTRL_1__Select_timeout_pulse__SHIFT 0x17
+#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1_cache_sel_reqid__SHIFT 0x1a
+#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1_cache_sel_interleave__SHIFT 0x1b
+#define IOMMU_L1_IOAGR_L1_CNTRL_1__Pretrans_noVA_filterEn__SHIFT 0x1c
+#define IOMMU_L1_IOAGR_L1_CNTRL_1__UnTrans_2M_filterEn__SHIFT 0x1d
+#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1StrictVCOrder_En__SHIFT 0x1e
+#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1DmaUseChainAll_En__SHIFT 0x1f
+#define IOMMU_L1_IOAGR_L1_CNTRL_1__RESERVED_MASK 0x000001FFL
+#define IOMMU_L1_IOAGR_L1_CNTRL_1__CacheByPass_MASK 0x00000200L
+#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1CacheParityEn_MASK 0x00000400L
+#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1ParityEn_MASK 0x00000800L
+#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1DTEDis_MASK 0x00001000L
+#define IOMMU_L1_IOAGR_L1_CNTRL_1__WQ_EntryDis_MASK 0x000FE000L
+#define IOMMU_L1_IOAGR_L1_CNTRL_1__Snd_filter_dis_MASK 0x00100000L
+#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1Order_en_MASK 0x00200000L
+#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1CacheInvAllEn_MASK 0x00400000L
+#define IOMMU_L1_IOAGR_L1_CNTRL_1__Select_timeout_pulse_MASK 0x03800000L
+#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1_cache_sel_reqid_MASK 0x04000000L
+#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1_cache_sel_interleave_MASK 0x08000000L
+#define IOMMU_L1_IOAGR_L1_CNTRL_1__Pretrans_noVA_filterEn_MASK 0x10000000L
+#define IOMMU_L1_IOAGR_L1_CNTRL_1__UnTrans_2M_filterEn_MASK 0x20000000L
+#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1StrictVCOrder_En_MASK 0x40000000L
+#define IOMMU_L1_IOAGR_L1_CNTRL_1__L1DmaUseChainAll_En_MASK 0x80000000L
+//IOMMU_L1_IOAGR_L1_CNTRL_2
+#define IOMMU_L1_IOAGR_L1_CNTRL_2__L1Disable__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_CNTRL_2__MSI_to_HT_remap_dis__SHIFT 0x1
+#define IOMMU_L1_IOAGR_L1_CNTRL_2__L1_abrt_ats_dis__SHIFT 0x2
+#define IOMMU_L1_IOAGR_L1_CNTRL_2__L1ATSDataErrorSignalEn__SHIFT 0x3
+#define IOMMU_L1_IOAGR_L1_CNTRL_2__RESERVED__SHIFT 0x4
+#define IOMMU_L1_IOAGR_L1_CNTRL_2__CPD_RESP_MODE__SHIFT 0x18
+#define IOMMU_L1_IOAGR_L1_CNTRL_2__L1NonConsumedDataErrorSignalEn__SHIFT 0x1b
+#define IOMMU_L1_IOAGR_L1_CNTRL_2__L1ConsumedDataErrorSignalEn__SHIFT 0x1c
+#define IOMMU_L1_IOAGR_L1_CNTRL_2__L1SDPParityEn__SHIFT 0x1d
+#define IOMMU_L1_IOAGR_L1_CNTRL_2__FlushVC_HRT1_Inv__SHIFT 0x1e
+#define IOMMU_L1_IOAGR_L1_CNTRL_2__FlushVC_HRT1_IntInv__SHIFT 0x1f
+#define IOMMU_L1_IOAGR_L1_CNTRL_2__L1Disable_MASK 0x00000001L
+#define IOMMU_L1_IOAGR_L1_CNTRL_2__MSI_to_HT_remap_dis_MASK 0x00000002L
+#define IOMMU_L1_IOAGR_L1_CNTRL_2__L1_abrt_ats_dis_MASK 0x00000004L
+#define IOMMU_L1_IOAGR_L1_CNTRL_2__L1ATSDataErrorSignalEn_MASK 0x00000008L
+#define IOMMU_L1_IOAGR_L1_CNTRL_2__RESERVED_MASK 0x00FFFFF0L
+#define IOMMU_L1_IOAGR_L1_CNTRL_2__CPD_RESP_MODE_MASK 0x07000000L
+#define IOMMU_L1_IOAGR_L1_CNTRL_2__L1NonConsumedDataErrorSignalEn_MASK 0x08000000L
+#define IOMMU_L1_IOAGR_L1_CNTRL_2__L1ConsumedDataErrorSignalEn_MASK 0x10000000L
+#define IOMMU_L1_IOAGR_L1_CNTRL_2__L1SDPParityEn_MASK 0x20000000L
+#define IOMMU_L1_IOAGR_L1_CNTRL_2__FlushVC_HRT1_Inv_MASK 0x40000000L
+#define IOMMU_L1_IOAGR_L1_CNTRL_2__FlushVC_HRT1_IntInv_MASK 0x80000000L
+//IOMMU_L1_IOAGR_L1_CNTRL_3
+#define IOMMU_L1_IOAGR_L1_CNTRL_3__ATS_tlbinv_pulse_width__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_CNTRL_3__ATS_tlbinv_pulse_width_MASK 0xFFFFFFFFL
+//IOMMU_L1_IOAGR_L1_BANK_SEL_0
+#define IOMMU_L1_IOAGR_L1_BANK_SEL_0__L1CacheBankSel_0__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_BANK_SEL_0__L1CacheBankSel_0_MASK 0x0000FFFFL
+//IOMMU_L1_IOAGR_L1_BANK_DISABLE_0
+#define IOMMU_L1_IOAGR_L1_BANK_DISABLE_0__L1CacheLineDis_0__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_BANK_DISABLE_0__L1CacheLineDis_1__SHIFT 0x8
+#define IOMMU_L1_IOAGR_L1_BANK_DISABLE_0__L1CacheLineDis_0_MASK 0x0000003FL
+#define IOMMU_L1_IOAGR_L1_BANK_DISABLE_0__L1CacheLineDis_1_MASK 0x00003F00L
+//IOMMU_L1_IOAGR_L1_WQ_STATUS_0
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus0__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus1__SHIFT 0x3
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus2__SHIFT 0x6
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus3__SHIFT 0x9
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus4__SHIFT 0xc
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus5__SHIFT 0xf
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus6__SHIFT 0x12
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus7__SHIFT 0x15
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus8__SHIFT 0x18
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus9__SHIFT 0x1b
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus0_MASK 0x00000007L
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus1_MASK 0x00000038L
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus2_MASK 0x000001C0L
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus3_MASK 0x00000E00L
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus4_MASK 0x00007000L
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus5_MASK 0x00038000L
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus6_MASK 0x001C0000L
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus7_MASK 0x00E00000L
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus8_MASK 0x07000000L
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus9_MASK 0x38000000L
+//IOMMU_L1_IOAGR_L1_WQ_STATUS_1
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus10__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus11__SHIFT 0x3
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus12__SHIFT 0x6
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus13__SHIFT 0x9
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus14__SHIFT 0xc
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus15__SHIFT 0xf
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus16__SHIFT 0x12
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus17__SHIFT 0x15
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus18__SHIFT 0x18
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus19__SHIFT 0x1b
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus10_MASK 0x00000007L
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus11_MASK 0x00000038L
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus12_MASK 0x000001C0L
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus13_MASK 0x00000E00L
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus14_MASK 0x00007000L
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus15_MASK 0x00038000L
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus16_MASK 0x001C0000L
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus17_MASK 0x00E00000L
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus18_MASK 0x07000000L
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus19_MASK 0x38000000L
+//IOMMU_L1_IOAGR_L1_WQ_STATUS_2
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus20__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus21__SHIFT 0x3
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus22__SHIFT 0x6
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus23__SHIFT 0x9
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus24__SHIFT 0xc
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus25__SHIFT 0xf
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus26__SHIFT 0x12
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus27__SHIFT 0x15
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus28__SHIFT 0x18
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus29__SHIFT 0x1b
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus20_MASK 0x00000007L
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus21_MASK 0x00000038L
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus22_MASK 0x000001C0L
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus23_MASK 0x00000E00L
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus24_MASK 0x00007000L
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus25_MASK 0x00038000L
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus26_MASK 0x001C0000L
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus27_MASK 0x00E00000L
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus28_MASK 0x07000000L
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus29_MASK 0x38000000L
+//IOMMU_L1_IOAGR_L1_WQ_STATUS_3
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_3__EntryStatus30__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_3__EntryStatus31__SHIFT 0x3
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_3__Invalidation_status__SHIFT 0x8
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_3__EntryStatus30_MASK 0x00000007L
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_3__EntryStatus31_MASK 0x00000038L
+#define IOMMU_L1_IOAGR_L1_WQ_STATUS_3__Invalidation_status_MASK 0x0000FF00L
+//IOMMU_L1_IOAGR_L1_FEATURE_CNTRL
+#define IOMMU_L1_IOAGR_L1_FEATURE_CNTRL__Debug_sticky_bits__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_FEATURE_CNTRL__Reserved__SHIFT 0x8
+#define IOMMU_L1_IOAGR_L1_FEATURE_CNTRL__Debug_sticky_bits_MASK 0x000000FFL
+#define IOMMU_L1_IOAGR_L1_FEATURE_CNTRL__Reserved_MASK 0xFFFFFF00L
+//IOMMU_L1_IOAGR_L1_PGMEM_CTRL_5
+#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_5__L1_LS_Req_Maintain_Cnt__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_5__L1_LS_Req_Maintain_Cnt_MASK 0xFFFFFFFFL
+//IOMMU_L1_IOAGR_L1_PGMEM_CTRL_6
+#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_6__L1_LS_Exit_Maintain_Cnt__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_6__L1_LS_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL
+//IOMMU_L1_IOAGR_L1_PGMEM_CTRL_7
+#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_7__L1_DS_Req_Maintain_Cnt__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_7__L1_DS_Req_Maintain_Cnt_MASK 0xFFFFFFFFL
+//IOMMU_L1_IOAGR_L1_PGMEM_CTRL_8
+#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_8__L1_DS_Exit_Maintain_Cnt__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_8__L1_DS_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL
+//IOMMU_L1_IOAGR_L1_PGMEM_CTRL_9
+#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_9__L1_SD_Req_Maintain_Cnt__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_9__L1_SD_Req_Maintain_Cnt_MASK 0xFFFFFFFFL
+//IOMMU_L1_IOAGR_L1_PGMEM_CTRL_10
+#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_10__L1_SD_Exit_Maintain_Cnt__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_10__L1_SD_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL
+//IOMMU_L1_IOAGR_L1_CNTRL_4
+#define IOMMU_L1_IOAGR_L1_CNTRL_4__ATS_multiple_resp_en__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_CNTRL_4__Timeout_pulse_ext_En__SHIFT 0x2
+#define IOMMU_L1_IOAGR_L1_CNTRL_4__RESERVED__SHIFT 0x4
+#define IOMMU_L1_IOAGR_L1_CNTRL_4__AtsRsp_send_mem_type_en__SHIFT 0x17
+#define IOMMU_L1_IOAGR_L1_CNTRL_4__IntGfx_UnitID_Val__SHIFT 0x18
+#define IOMMU_L1_IOAGR_L1_CNTRL_4__ATS_multiple_resp_en_MASK 0x00000001L
+#define IOMMU_L1_IOAGR_L1_CNTRL_4__Timeout_pulse_ext_En_MASK 0x00000004L
+#define IOMMU_L1_IOAGR_L1_CNTRL_4__RESERVED_MASK 0x007FFFF0L
+#define IOMMU_L1_IOAGR_L1_CNTRL_4__AtsRsp_send_mem_type_en_MASK 0x00800000L
+#define IOMMU_L1_IOAGR_L1_CNTRL_4__IntGfx_UnitID_Val_MASK 0x7F000000L
+//IOMMU_L1_IOAGR_L1_CLKCNTRL_0
+#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_DMA_CLKGATE_EN__SHIFT 0x4
+#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_CACHE_CLKGATE_EN__SHIFT 0x5
+#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_CPSLV_CLKGATE_EN__SHIFT 0x6
+#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_PERF_CLKGATE_EN__SHIFT 0x8
+#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_MEMORY_CLKGATE_EN__SHIFT 0x9
+#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_REG_CLKGATE_EN__SHIFT 0xa
+#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_HOSTREQ_CLKGATE_EN__SHIFT 0xb
+#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_DMARSP_CLKGATE_EN__SHIFT 0xc
+#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_HOSTRSP_CLKGATE_EN__SHIFT 0xd
+#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_CLKGATE_HYSTERESIS__SHIFT 0xe
+#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__reserved__SHIFT 0x16
+#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_L2_CLKGATE_EN__SHIFT 0x1f
+#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_DMA_CLKGATE_EN_MASK 0x00000010L
+#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_CACHE_CLKGATE_EN_MASK 0x00000020L
+#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_CPSLV_CLKGATE_EN_MASK 0x00000040L
+#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_PERF_CLKGATE_EN_MASK 0x00000100L
+#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_MEMORY_CLKGATE_EN_MASK 0x00000200L
+#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_REG_CLKGATE_EN_MASK 0x00000400L
+#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_HOSTREQ_CLKGATE_EN_MASK 0x00000800L
+#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_DMARSP_CLKGATE_EN_MASK 0x00001000L
+#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_HOSTRSP_CLKGATE_EN_MASK 0x00002000L
+#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_CLKGATE_HYSTERESIS_MASK 0x003FC000L
+#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__reserved_MASK 0x7FC00000L
+#define IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_L2_CLKGATE_EN_MASK 0x80000000L
+//IOMMU_L1_IOAGR_L1_SDP_CLKREQ_CNTRL
+#define IOMMU_L1_IOAGR_L1_SDP_CLKREQ_CNTRL__HW_PG_WAKEUP_EN_DMA__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_SDP_CLKREQ_CNTRL__HW_PG_WAKEUP_EN_HOST__SHIFT 0x1
+#define IOMMU_L1_IOAGR_L1_SDP_CLKREQ_CNTRL__HW_PG_WAKEUP_EN_DMA_MASK 0x00000001L
+#define IOMMU_L1_IOAGR_L1_SDP_CLKREQ_CNTRL__HW_PG_WAKEUP_EN_HOST_MASK 0x00000002L
+//IOMMU_L1_IOAGR_L1_GUEST_ADDR_CNTRL
+#define IOMMU_L1_IOAGR_L1_GUEST_ADDR_CNTRL__L1_CANONICAL_ERR_EN__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_GUEST_ADDR_CNTRL__reserved__SHIFT 0x1
+#define IOMMU_L1_IOAGR_L1_GUEST_ADDR_CNTRL__L1_GUEST_ADDR_MSK__SHIFT 0x8
+#define IOMMU_L1_IOAGR_L1_GUEST_ADDR_CNTRL__L1_CANONICAL_ERR_EN_MASK 0x00000001L
+#define IOMMU_L1_IOAGR_L1_GUEST_ADDR_CNTRL__reserved_MASK 0x000000FEL
+#define IOMMU_L1_IOAGR_L1_GUEST_ADDR_CNTRL__L1_GUEST_ADDR_MSK_MASK 0xFFFFFF00L
+//IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL
+#define IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__L1_EFR_SUP__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__L1_PPR_SUP__SHIFT 0x1
+#define IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__L1_DTE_seg_W__SHIFT 0x2
+#define IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__L1_GT_SUP_W__SHIFT 0x4
+#define IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__reserved__SHIFT 0x5
+#define IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__L1_EFR_SUP_MASK 0x00000001L
+#define IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__L1_PPR_SUP_MASK 0x00000002L
+#define IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__L1_DTE_seg_W_MASK 0x0000000CL
+#define IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__L1_GT_SUP_W_MASK 0x00000010L
+#define IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__reserved_MASK 0xFFFFFFE0L
+//IOMMU_L1_IOAGR_L1_CNTRL_5
+#define IOMMU_L1_IOAGR_L1_CNTRL_5__RESERVED__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_CNTRL_5__RESERVED_MASK 0xFFFFFFFFL
+//IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1
+#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1__L1_LS_EN__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1__L1_DS_EN__SHIFT 0x1
+#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1__L1_SD_EN__SHIFT 0x2
+#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1__L1_IP_PGMEM_SEL__SHIFT 0x3
+#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1__L1_LS_EN_MASK 0x00000001L
+#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1__L1_DS_EN_MASK 0x00000002L
+#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1__L1_SD_EN_MASK 0x00000004L
+#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1__L1_IP_PGMEM_SEL_MASK 0x00000008L
+//IOMMU_L1_IOAGR_L1_PGMEM_CTRL_2
+#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_2__L1_LS_thres__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_2__L1_LS_thres_MASK 0xFFFFFFFFL
+//IOMMU_L1_IOAGR_L1_PGMEM_CTRL_3
+#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_3__L1_DS_thres__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_3__L1_DS_thres_MASK 0xFFFFFFFFL
+//IOMMU_L1_IOAGR_L1_PGMEM_CTRL_4
+#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_4__L1_SD_thres__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_PGMEM_CTRL_4__L1_SD_thres_MASK 0xFFFFFFFFL
+//IOMMU_L1_IOAGR_IOMMU_PGSLV_CONTROL
+#define IOMMU_L1_IOAGR_IOMMU_PGSLV_CONTROL__CFG_IDLE_HYSTERESIS__SHIFT 0x0
+#define IOMMU_L1_IOAGR_IOMMU_PGSLV_CONTROL__L1_PG_STATUS__SHIFT 0x5
+#define IOMMU_L1_IOAGR_IOMMU_PGSLV_CONTROL__CFG_IDLE_HYSTERESIS_MASK 0x0000001FL
+#define IOMMU_L1_IOAGR_IOMMU_PGSLV_CONTROL__L1_PG_STATUS_MASK 0x00000020L
+//IOMMU_L1_IOAGR_L1_ATS_RESP_CTRL_0
+#define IOMMU_L1_IOAGR_L1_ATS_RESP_CTRL_0__L1_ATS_Resp_allow_timer__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_ATS_RESP_CTRL_0__L1_ATS_Resp_delay_timer__SHIFT 0x8
+#define IOMMU_L1_IOAGR_L1_ATS_RESP_CTRL_0__L1_ATSdely_on_PPRAutoResp_en__SHIFT 0x1f
+#define IOMMU_L1_IOAGR_L1_ATS_RESP_CTRL_0__L1_ATS_Resp_allow_timer_MASK 0x000000FFL
+#define IOMMU_L1_IOAGR_L1_ATS_RESP_CTRL_0__L1_ATS_Resp_delay_timer_MASK 0x0000FF00L
+#define IOMMU_L1_IOAGR_L1_ATS_RESP_CTRL_0__L1_ATSdely_on_PPRAutoResp_en_MASK 0x80000000L
+//IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control
+#define IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control__StallNPReqEn__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control__StallPReqEn__SHIFT 0x2
+#define IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control__StallUpWrReqEn__SHIFT 0x6
+#define IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn__SHIFT 0xe
+#define IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control__StallNPReqEn_MASK 0x00000003L
+#define IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control__StallPReqEn_MASK 0x0000000CL
+#define IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control__StallUpWrReqEn_MASK 0x000000C0L
+#define IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn_MASK 0x0000C000L
+//IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control
+#define IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control__StallNPRspEn__SHIFT 0x0
+#define IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control__StallPRspEn__SHIFT 0x2
+#define IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control__StallUpWrRspEn__SHIFT 0x6
+#define IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control__StallHRT1RspEn__SHIFT 0xe
+#define IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control__StallNPRspEn_MASK 0x00000003L
+#define IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control__StallPRspEn_MASK 0x0000000CL
+#define IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control__StallUpWrRspEn_MASK 0x000000C0L
+#define IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control__StallHRT1RspEn_MASK 0x0000C000L
+//IOMMU_L1_IOAGR_L1_CLIENT_HostReq_Stall_Control
+#define IOMMU_L1_IOAGR_L1_CLIENT_HostReq_Stall_Control__StallNPReqEn__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_CLIENT_HostReq_Stall_Control__StallPReqEn__SHIFT 0x2
+#define IOMMU_L1_IOAGR_L1_CLIENT_HostReq_Stall_Control__StallNPReqEn_MASK 0x00000003L
+#define IOMMU_L1_IOAGR_L1_CLIENT_HostReq_Stall_Control__StallPReqEn_MASK 0x0000000CL
+//IOMMU_L1_IOAGR_IOHC_L1_HostRsp_Stall_Control
+#define IOMMU_L1_IOAGR_IOHC_L1_HostRsp_Stall_Control__StallNPRspEn__SHIFT 0x0
+#define IOMMU_L1_IOAGR_IOHC_L1_HostRsp_Stall_Control__StallPRspEn__SHIFT 0x2
+#define IOMMU_L1_IOAGR_IOHC_L1_HostRsp_Stall_Control__StallNPRspEn_MASK 0x00000003L
+#define IOMMU_L1_IOAGR_IOHC_L1_HostRsp_Stall_Control__StallPRspEn_MASK 0x0000000CL
+//IOMMU_L1_IOAGR_L1_SDP_MAXCRED_0
+#define IOMMU_L1_IOAGR_L1_SDP_MAXCRED_0__L1_FLUSHRSP_MAXCRED__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_SDP_MAXCRED_0__L1_HOSTRDRSP_MAXCRED__SHIFT 0x4
+#define IOMMU_L1_IOAGR_L1_SDP_MAXCRED_0__L1_HOSTWRRSP_MAXCRED__SHIFT 0xa
+#define IOMMU_L1_IOAGR_L1_SDP_MAXCRED_0__L1_FLUSHRSP_MAXCRED_MASK 0x0000000FL
+#define IOMMU_L1_IOAGR_L1_SDP_MAXCRED_0__L1_HOSTRDRSP_MAXCRED_MASK 0x000003F0L
+#define IOMMU_L1_IOAGR_L1_SDP_MAXCRED_0__L1_HOSTWRRSP_MAXCRED_MASK 0x0000FC00L
+//IOMMU_L1_IOAGR_L1_ECO_CNTRL
+#define IOMMU_L1_IOAGR_L1_ECO_CNTRL__L1_ECO__SHIFT 0x0
+#define IOMMU_L1_IOAGR_L1_ECO_CNTRL__L1_ECO_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_iohub_iommu_l1shdw_IOAGR_l1shdw
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_BASE_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE_MASK 0x000001FFL
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__IOMMU_EN__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__HT_TUN_EN__SHIFT 0x1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__EVENT_LOG_EN__SHIFT 0x2
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__EVENT_INT_EN__SHIFT 0x3
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__COM_WAIT_INTEN__SHIFT 0x4
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__INV_TIMEOUT__SHIFT 0x5
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__PASS_PW__SHIFT 0x8
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__RES_PASS_PW__SHIFT 0x9
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__COHERENT__SHIFT 0xa
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__ISOC__SHIFT 0xb
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__CMD_BUF_EN__SHIFT 0xc
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__PPR_LOG_EN__SHIFT 0xd
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__PPR_EN__SHIFT 0xf
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__GT_EN__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__GA_EN__SHIFT 0x11
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__TLPT__SHIFT 0x12
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__IOMMU_EN_MASK 0x00000001L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__HT_TUN_EN_MASK 0x00000002L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__EVENT_LOG_EN_MASK 0x00000004L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__EVENT_INT_EN_MASK 0x00000008L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__COM_WAIT_INTEN_MASK 0x00000010L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__INV_TIMEOUT_MASK 0x000000E0L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__PASS_PW_MASK 0x00000100L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__RES_PASS_PW_MASK 0x00000200L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__COHERENT_MASK 0x00000400L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__ISOC_MASK 0x00000800L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__CMD_BUF_EN_MASK 0x00001000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__PPR_LOG_EN_MASK 0x00002000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__PPR_EN_MASK 0x00008000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__GT_EN_MASK 0x00010000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__GA_EN_MASK 0x00020000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__TLPT_MASK 0x003C0000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_1__DTE_SEG_EN__SHIFT 0x2
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_1__DTE_SEG_EN_MASK 0x0000000CL
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EX_EN__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW__SHIFT 0x1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__Reserved0__SHIFT 0x2
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO__SHIFT 0xc
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EX_EN_MASK 0x00000001L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW_MASK 0x00000002L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__Reserved0_MASK 0x00000FFCL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO_MASK 0xFFFFF000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_1__Reserved0__SHIFT 0x14
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI_MASK 0x000FFFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_1__Reserved0_MASK 0xFFF00000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_0__Reserved0__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO__SHIFT 0xc
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_0__Reserved0_MASK 0x00000FFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO_MASK 0xFFFFF000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_1__Reserved0__SHIFT 0x14
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI_MASK 0x000FFFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_1__Reserved0_MASK 0xFFF00000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_1_BASE_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE_MASK 0x000001FFL
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_2_BASE_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE_MASK 0x000001FFL
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_3_BASE_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE_MASK 0x000001FFL
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_4_BASE_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE_MASK 0x000001FFL
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_5_BASE_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE_MASK 0x000001FFL
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_6_BASE_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE_MASK 0x000001FFL
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_7_BASE_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE_MASK 0x000001FFL
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0__PASID_LOCK_LO__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0__PASID_LOCK_LO_MASK 0xFFFFFFFFL
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1__PASID_LOCK_HI__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1__PASID_LOCK_HI_MASK 0xFFFFFFFFL
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0__DOMAIN_LOCK_LO__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0__DOMAIN_LOCK_LO_MASK 0xFFFFFFFFL
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1__DOMAIN_LOCK_HI__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1__DOMAIN_LOCK_HI_MASK 0xFFFFFFFFL
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0__DEVID_LOCK_LO__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0__DEVID_LOCK_LO_MASK 0xFFFFFFFFL
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1__DEVID_LOCK_HI__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1__DEVID_LOCK_HI_MASK 0xFFFFFFFFL
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CSOURCE_0_0__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__Reserved1__SHIFT 0x8
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__COUNT_UNITS_0_0__SHIFT 0x1e
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CAC_0_0__SHIFT 0x1f
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CSOURCE_0_0_MASK 0x000000FFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__Reserved1_MASK 0x3FFFFF00L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__COUNT_UNITS_0_0_MASK 0x40000000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CAC_0_0_MASK 0x80000000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASID_MATCH_0_0__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASMEN_0_0__SHIFT 0x1f
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASID_MATCH_0_0_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASMEN_0_0_MASK 0x80000000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__PASID_MASK_0_0__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__PASID_MASK_0_0_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMAIN_MATCH_0_0__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMMEN_0_0__SHIFT 0x1f
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMAIN_MATCH_0_0_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMMEN_0_0_MASK 0x80000000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__DOMAIN_MASK_0_0__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__DOMAIN_MASK_0_0_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DEVICEID_MATCH_0_0__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DIDMEN_0_0__SHIFT 0x1f
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DEVICEID_MATCH_0_0_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DIDMEN_0_0_MASK 0x80000000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__DEVICEID_MASK_0_0__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__DEVICEID_MASK_0_0_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CSOURCE_0_1__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__Reserved1__SHIFT 0x8
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__COUNT_UNITS_0_1__SHIFT 0x1e
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CAC_0_1__SHIFT 0x1f
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CSOURCE_0_1_MASK 0x000000FFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__Reserved1_MASK 0x3FFFFF00L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__COUNT_UNITS_0_1_MASK 0x40000000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CAC_0_1_MASK 0x80000000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASID_MATCH_0_1__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASMEN_0_1__SHIFT 0x1f
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASID_MATCH_0_1_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASMEN_0_1_MASK 0x80000000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__PASID_MASK_0_1__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__PASID_MASK_0_1_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMAIN_MATCH_0_1__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMMEN_0_1__SHIFT 0x1f
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMAIN_MATCH_0_1_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMMEN_0_1_MASK 0x80000000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__DOMAIN_MASK_0_1__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__DOMAIN_MASK_0_1_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DEVICEID_MATCH_0_1__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DIDMEN_0_1__SHIFT 0x1f
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DEVICEID_MATCH_0_1_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DIDMEN_0_1_MASK 0x80000000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__DEVICEID_MASK_0_1__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__DEVICEID_MASK_0_1_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CSOURCE_0_2__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__Reserved1__SHIFT 0x8
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__COUNT_UNITS_0_2__SHIFT 0x1e
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CAC_0_2__SHIFT 0x1f
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CSOURCE_0_2_MASK 0x000000FFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__Reserved1_MASK 0x3FFFFF00L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__COUNT_UNITS_0_2_MASK 0x40000000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CAC_0_2_MASK 0x80000000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASID_MATCH_0_2__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASMEN_0_2__SHIFT 0x1f
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASID_MATCH_0_2_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASMEN_0_2_MASK 0x80000000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__PASID_MASK_0_2__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__PASID_MASK_0_2_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMAIN_MATCH_0_2__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMMEN_0_2__SHIFT 0x1f
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMAIN_MATCH_0_2_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMMEN_0_2_MASK 0x80000000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__DOMAIN_MASK_0_2__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__DOMAIN_MASK_0_2_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DEVICEID_MATCH_0_2__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DIDMEN_0_2__SHIFT 0x1f
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DEVICEID_MATCH_0_2_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DIDMEN_0_2_MASK 0x80000000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__DEVICEID_MASK_0_2__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__DEVICEID_MASK_0_2_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CSOURCE_0_3__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__Reserved1__SHIFT 0x8
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__COUNT_UNITS_0_3__SHIFT 0x1e
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CAC_0_3__SHIFT 0x1f
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CSOURCE_0_3_MASK 0x000000FFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__Reserved1_MASK 0x3FFFFF00L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__COUNT_UNITS_0_3_MASK 0x40000000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CAC_0_3_MASK 0x80000000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASID_MATCH_0_3__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASMEN_0_3__SHIFT 0x1f
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASID_MATCH_0_3_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASMEN_0_3_MASK 0x80000000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__PASID_MASK_0_3__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__PASID_MASK_0_3_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMAIN_MATCH_0_3__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMMEN_0_3__SHIFT 0x1f
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMAIN_MATCH_0_3_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMMEN_0_3_MASK 0x80000000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__DOMAIN_MASK_0_3__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__DOMAIN_MASK_0_3_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DEVICEID_MATCH_0_3__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DIDMEN_0_3__SHIFT 0x1f
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DEVICEID_MATCH_0_3_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DIDMEN_0_3_MASK 0x80000000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__DEVICEID_MASK_0_3__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__DEVICEID_MASK_0_3_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CSOURCE_1_0__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__Reserved1__SHIFT 0x8
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__COUNT_UNITS_1_0__SHIFT 0x1e
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CAC_1_0__SHIFT 0x1f
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CSOURCE_1_0_MASK 0x000000FFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__Reserved1_MASK 0x3FFFFF00L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__COUNT_UNITS_1_0_MASK 0x40000000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CAC_1_0_MASK 0x80000000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASID_MATCH_1_0__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASMEN_1_0__SHIFT 0x1f
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASID_MATCH_1_0_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASMEN_1_0_MASK 0x80000000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__PASID_MASK_1_0__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__PASID_MASK_1_0_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMAIN_MATCH_1_0__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMMEN_1_0__SHIFT 0x1f
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMAIN_MATCH_1_0_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMMEN_1_0_MASK 0x80000000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__DOMAIN_MASK_1_0__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__DOMAIN_MASK_1_0_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DEVICEID_MATCH_1_0__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DIDMEN_1_0__SHIFT 0x1f
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DEVICEID_MATCH_1_0_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DIDMEN_1_0_MASK 0x80000000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__DEVICEID_MASK_1_0__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__DEVICEID_MASK_1_0_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CSOURCE_1_1__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__Reserved1__SHIFT 0x8
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__COUNT_UNITS_1_1__SHIFT 0x1e
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CAC_1_1__SHIFT 0x1f
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CSOURCE_1_1_MASK 0x000000FFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__Reserved1_MASK 0x3FFFFF00L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__COUNT_UNITS_1_1_MASK 0x40000000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CAC_1_1_MASK 0x80000000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASID_MATCH_1_1__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASMEN_1_1__SHIFT 0x1f
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASID_MATCH_1_1_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASMEN_1_1_MASK 0x80000000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__PASID_MASK_1_1__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__PASID_MASK_1_1_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMAIN_MATCH_1_1__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMMEN_1_1__SHIFT 0x1f
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMAIN_MATCH_1_1_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMMEN_1_1_MASK 0x80000000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__DOMAIN_MASK_1_1__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__DOMAIN_MASK_1_1_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DEVICEID_MATCH_1_1__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DIDMEN_1_1__SHIFT 0x1f
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DEVICEID_MATCH_1_1_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DIDMEN_1_1_MASK 0x80000000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__DEVICEID_MASK_1_1__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__DEVICEID_MASK_1_1_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CSOURCE_1_2__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__Reserved1__SHIFT 0x8
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__COUNT_UNITS_1_2__SHIFT 0x1e
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CAC_1_2__SHIFT 0x1f
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CSOURCE_1_2_MASK 0x000000FFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__Reserved1_MASK 0x3FFFFF00L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__COUNT_UNITS_1_2_MASK 0x40000000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CAC_1_2_MASK 0x80000000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASID_MATCH_1_2__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASMEN_1_2__SHIFT 0x1f
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASID_MATCH_1_2_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASMEN_1_2_MASK 0x80000000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__PASID_MASK_1_2__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__PASID_MASK_1_2_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMAIN_MATCH_1_2__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMMEN_1_2__SHIFT 0x1f
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMAIN_MATCH_1_2_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMMEN_1_2_MASK 0x80000000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__DOMAIN_MASK_1_2__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__DOMAIN_MASK_1_2_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DEVICEID_MATCH_1_2__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DIDMEN_1_2__SHIFT 0x1f
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DEVICEID_MATCH_1_2_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DIDMEN_1_2_MASK 0x80000000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__DEVICEID_MASK_1_2__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__DEVICEID_MASK_1_2_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CSOURCE_1_3__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__Reserved1__SHIFT 0x8
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__COUNT_UNITS_1_3__SHIFT 0x1e
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CAC_1_3__SHIFT 0x1f
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CSOURCE_1_3_MASK 0x000000FFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__Reserved1_MASK 0x3FFFFF00L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__COUNT_UNITS_1_3_MASK 0x40000000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CAC_1_3_MASK 0x80000000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASID_MATCH_1_3__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASMEN_1_3__SHIFT 0x1f
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASID_MATCH_1_3_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASMEN_1_3_MASK 0x80000000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__PASID_MASK_1_3__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__PASID_MASK_1_3_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMAIN_MATCH_1_3__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMMEN_1_3__SHIFT 0x1f
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMAIN_MATCH_1_3_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMMEN_1_3_MASK 0x80000000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__DOMAIN_MASK_1_3__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__DOMAIN_MASK_1_3_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DEVICEID_MATCH_1_3__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DIDMEN_1_3__SHIFT 0x1f
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DEVICEID_MATCH_1_3_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DIDMEN_1_3_MASK 0x80000000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__DEVICEID_MASK_1_3__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__DEVICEID_MASK_1_3_MASK 0x0000FFFFL
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_BASE_LO
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_BASE_LO__IOMMU_ENABLE__SHIFT 0x0
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_BASE_LO__IOMMU_ENABLE_MASK 0x00000001L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV__SHIFT 0x16
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV_MASK 0x00400000L
+//IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC_1
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE__SHIFT 0x5
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC_1__DVM_MODE__SHIFT 0x6
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE_MASK 0x00000020L
+#define IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC_1__DVM_MODE_MASK 0x000000C0L
+
+
+// addressBlock: nbio_iohub_iommu_l1psp_IOAGR_l1psp
+//IOMMU_L1PSP_IOAGR_L1PSP_ERR_REP_CNTRL
+#define IOMMU_L1PSP_IOAGR_L1PSP_ERR_REP_CNTRL__CPD_SUP__SHIFT 0x0
+#define IOMMU_L1PSP_IOAGR_L1PSP_ERR_REP_CNTRL__Reserved__SHIFT 0x1
+#define IOMMU_L1PSP_IOAGR_L1PSP_ERR_REP_CNTRL__CPD_SUP_MASK 0x00000001L
+#define IOMMU_L1PSP_IOAGR_L1PSP_ERR_REP_CNTRL__Reserved_MASK 0xFFFFFFFEL
+//IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0
+#define IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0__CPDV__SHIFT 0x0
+#define IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0__CPDO__SHIFT 0x1
+#define IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0__Reserved__SHIFT 0x2
+#define IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0__CPD_REQSTREAM_ID__SHIFT 0x10
+#define IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0__CPDV_MASK 0x00000001L
+#define IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0__CPDO_MASK 0x00000002L
+#define IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0__Reserved_MASK 0x0000FFFCL
+#define IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0__CPD_REQSTREAM_ID_MASK 0xFFFF0000L
+//IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_1
+#define IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_1__Reserved__SHIFT 0x0
+#define IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_1__Reserved_MASK 0xFFFFFFFFL
+//IOMMU_L1PSP_IOAGR_L1PSP_CPD_REQADDR_0
+#define IOMMU_L1PSP_IOAGR_L1PSP_CPD_REQADDR_0__CPD_REQADDR_LO__SHIFT 0x0
+#define IOMMU_L1PSP_IOAGR_L1PSP_CPD_REQADDR_0__CPD_REQADDR_LO_MASK 0xFFFFFFFFL
+//IOMMU_L1PSP_IOAGR_L1PSP_CPD_REQADDR_1
+#define IOMMU_L1PSP_IOAGR_L1PSP_CPD_REQADDR_1__CPD_REQADDR_HI__SHIFT 0x0
+#define IOMMU_L1PSP_IOAGR_L1PSP_CPD_REQADDR_1__CPD_REQADDR_HI_MASK 0xFFFFFFFFL
+//IOMMU_L1PSP_IOAGR_L1PSP_REQ_CNTRL
+#define IOMMU_L1PSP_IOAGR_L1PSP_REQ_CNTRL__AbortPreTrans__SHIFT 0x0
+#define IOMMU_L1PSP_IOAGR_L1PSP_REQ_CNTRL__Reserved__SHIFT 0x1
+#define IOMMU_L1PSP_IOAGR_L1PSP_REQ_CNTRL__AbortPreTrans_MASK 0x00000001L
+#define IOMMU_L1PSP_IOAGR_L1PSP_REQ_CNTRL__Reserved_MASK 0xFFFFFFFEL
+
+
+// addressBlock: nbio_iohub_iommu_l2a_l2acfg
+//L2_PERF_CNTL_0
+#define L2_PERF_CNTL_0__L2PerfEvent0__SHIFT 0x0
+#define L2_PERF_CNTL_0__L2PerfEvent1__SHIFT 0x8
+#define L2_PERF_CNTL_0__L2PerfCountUpper0__SHIFT 0x10
+#define L2_PERF_CNTL_0__L2PerfCountUpper1__SHIFT 0x18
+#define L2_PERF_CNTL_0__L2PerfEvent0_MASK 0x000000FFL
+#define L2_PERF_CNTL_0__L2PerfEvent1_MASK 0x0000FF00L
+#define L2_PERF_CNTL_0__L2PerfCountUpper0_MASK 0x00FF0000L
+#define L2_PERF_CNTL_0__L2PerfCountUpper1_MASK 0xFF000000L
+//L2_PERF_COUNT_0
+#define L2_PERF_COUNT_0__L2PerfCount0__SHIFT 0x0
+#define L2_PERF_COUNT_0__L2PerfCount0_MASK 0xFFFFFFFFL
+//L2_PERF_COUNT_1
+#define L2_PERF_COUNT_1__L2PerfCount1__SHIFT 0x0
+#define L2_PERF_COUNT_1__L2PerfCount1_MASK 0xFFFFFFFFL
+//L2_PERF_CNTL_1
+#define L2_PERF_CNTL_1__L2PerfEvent2__SHIFT 0x0
+#define L2_PERF_CNTL_1__L2PerfEvent3__SHIFT 0x8
+#define L2_PERF_CNTL_1__L2PerfCountUpper2__SHIFT 0x10
+#define L2_PERF_CNTL_1__L2PerfCountUpper3__SHIFT 0x18
+#define L2_PERF_CNTL_1__L2PerfEvent2_MASK 0x000000FFL
+#define L2_PERF_CNTL_1__L2PerfEvent3_MASK 0x0000FF00L
+#define L2_PERF_CNTL_1__L2PerfCountUpper2_MASK 0x00FF0000L
+#define L2_PERF_CNTL_1__L2PerfCountUpper3_MASK 0xFF000000L
+//L2_PERF_COUNT_2
+#define L2_PERF_COUNT_2__L2PerfCount2__SHIFT 0x0
+#define L2_PERF_COUNT_2__L2PerfCount2_MASK 0xFFFFFFFFL
+//L2_PERF_COUNT_3
+#define L2_PERF_COUNT_3__L2PerfCount3__SHIFT 0x0
+#define L2_PERF_COUNT_3__L2PerfCount3_MASK 0xFFFFFFFFL
+//L2_STATUS_0
+#define L2_STATUS_0__L2STATUS0__SHIFT 0x0
+#define L2_STATUS_0__L2STATUS0_MASK 0xFFFFFFFFL
+//L2_CONTROL_0
+#define L2_CONTROL_0__AllowL1CacheVZero__SHIFT 0x1
+#define L2_CONTROL_0__AllowL1CacheATSRsp__SHIFT 0x2
+#define L2_CONTROL_0__DTCHitVZeroOrIVZero__SHIFT 0x3
+#define L2_CONTROL_0__SIDEPTEOnUntransExcl__SHIFT 0xa
+#define L2_CONTROL_0__SIDEPTEOnAddrTransExcl__SHIFT 0xb
+#define L2_CONTROL_0__RESERVED__SHIFT 0xc
+#define L2_CONTROL_0__FLTCMBPriority__SHIFT 0x12
+#define L2_CONTROL_0__IFifoBurstLength__SHIFT 0x14
+#define L2_CONTROL_0__IFifoClientPriority__SHIFT 0x18
+#define L2_CONTROL_0__AllowL1CacheVZero_MASK 0x00000002L
+#define L2_CONTROL_0__AllowL1CacheATSRsp_MASK 0x00000004L
+#define L2_CONTROL_0__DTCHitVZeroOrIVZero_MASK 0x00000008L
+#define L2_CONTROL_0__SIDEPTEOnUntransExcl_MASK 0x00000400L
+#define L2_CONTROL_0__SIDEPTEOnAddrTransExcl_MASK 0x00000800L
+#define L2_CONTROL_0__RESERVED_MASK 0x0003F000L
+#define L2_CONTROL_0__FLTCMBPriority_MASK 0x00040000L
+#define L2_CONTROL_0__IFifoBurstLength_MASK 0x00F00000L
+#define L2_CONTROL_0__IFifoClientPriority_MASK 0xFF000000L
+//L2_CONTROL_1
+#define L2_CONTROL_1__SeqInvBurstLimitInv__SHIFT 0x0
+#define L2_CONTROL_1__SeqInvBurstLimitL2Req__SHIFT 0x8
+#define L2_CONTROL_1__SeqInvBurstLimitEn__SHIFT 0x10
+#define L2_CONTROL_1__PerfThreshold__SHIFT 0x18
+#define L2_CONTROL_1__SeqInvBurstLimitInv_MASK 0x000000FFL
+#define L2_CONTROL_1__SeqInvBurstLimitL2Req_MASK 0x0000FF00L
+#define L2_CONTROL_1__SeqInvBurstLimitEn_MASK 0x00010000L
+#define L2_CONTROL_1__PerfThreshold_MASK 0xFF000000L
+//L2_DTC_CONTROL
+#define L2_DTC_CONTROL__RESERVED__SHIFT 0x0
+#define L2_DTC_CONTROL__DTCLRUUpdatePri__SHIFT 0x3
+#define L2_DTC_CONTROL__DTCParityEn__SHIFT 0x4
+#define L2_DTC_CONTROL__DTCInvalidationSel__SHIFT 0x8
+#define L2_DTC_CONTROL__DTCSoftInvalidate__SHIFT 0xa
+#define L2_DTC_CONTROL__DTCBypass__SHIFT 0xd
+#define L2_DTC_CONTROL__DTCParitySupport__SHIFT 0xf
+#define L2_DTC_CONTROL__DTCWays__SHIFT 0x10
+#define L2_DTC_CONTROL__DTCEntries__SHIFT 0x1c
+#define L2_DTC_CONTROL__RESERVED_MASK 0x00000003L
+#define L2_DTC_CONTROL__DTCLRUUpdatePri_MASK 0x00000008L
+#define L2_DTC_CONTROL__DTCParityEn_MASK 0x00000010L
+#define L2_DTC_CONTROL__DTCInvalidationSel_MASK 0x00000300L
+#define L2_DTC_CONTROL__DTCSoftInvalidate_MASK 0x00000400L
+#define L2_DTC_CONTROL__DTCBypass_MASK 0x00002000L
+#define L2_DTC_CONTROL__DTCParitySupport_MASK 0x00008000L
+#define L2_DTC_CONTROL__DTCWays_MASK 0x00FF0000L
+#define L2_DTC_CONTROL__DTCEntries_MASK 0xF0000000L
+//L2_DTC_HASH_CONTROL
+#define L2_DTC_HASH_CONTROL__DTCAddressMask__SHIFT 0x10
+#define L2_DTC_HASH_CONTROL__DTCAddressMask_MASK 0xFFFF0000L
+//L2_DTC_WAY_CONTROL
+#define L2_DTC_WAY_CONTROL__DTCWayDisable__SHIFT 0x0
+#define L2_DTC_WAY_CONTROL__DTCWayAccessDisable__SHIFT 0x10
+#define L2_DTC_WAY_CONTROL__DTCWayDisable_MASK 0x0000FFFFL
+#define L2_DTC_WAY_CONTROL__DTCWayAccessDisable_MASK 0xFFFF0000L
+//L2_ITC_CONTROL
+#define L2_ITC_CONTROL__RESERVED__SHIFT 0x0
+#define L2_ITC_CONTROL__ITCLRUUpdatePri__SHIFT 0x3
+#define L2_ITC_CONTROL__ITCParityEn__SHIFT 0x4
+#define L2_ITC_CONTROL__ITCInvalidationSel__SHIFT 0x8
+#define L2_ITC_CONTROL__ITCSoftInvalidate__SHIFT 0xa
+#define L2_ITC_CONTROL__ITCBypass__SHIFT 0xd
+#define L2_ITC_CONTROL__ITCParitySupport__SHIFT 0xf
+#define L2_ITC_CONTROL__ITCWays__SHIFT 0x10
+#define L2_ITC_CONTROL__ITCEntries__SHIFT 0x1c
+#define L2_ITC_CONTROL__RESERVED_MASK 0x00000003L
+#define L2_ITC_CONTROL__ITCLRUUpdatePri_MASK 0x00000008L
+#define L2_ITC_CONTROL__ITCParityEn_MASK 0x00000010L
+#define L2_ITC_CONTROL__ITCInvalidationSel_MASK 0x00000300L
+#define L2_ITC_CONTROL__ITCSoftInvalidate_MASK 0x00000400L
+#define L2_ITC_CONTROL__ITCBypass_MASK 0x00002000L
+#define L2_ITC_CONTROL__ITCParitySupport_MASK 0x00008000L
+#define L2_ITC_CONTROL__ITCWays_MASK 0x00FF0000L
+#define L2_ITC_CONTROL__ITCEntries_MASK 0xF0000000L
+//L2_ITC_HASH_CONTROL
+#define L2_ITC_HASH_CONTROL__ITCAddressMask__SHIFT 0x10
+#define L2_ITC_HASH_CONTROL__ITCAddressMask_MASK 0xFFFF0000L
+//L2_ITC_WAY_CONTROL
+#define L2_ITC_WAY_CONTROL__ITCWayDisable__SHIFT 0x0
+#define L2_ITC_WAY_CONTROL__ITCWayAccessDisable__SHIFT 0x10
+#define L2_ITC_WAY_CONTROL__ITCWayDisable_MASK 0x0000FFFFL
+#define L2_ITC_WAY_CONTROL__ITCWayAccessDisable_MASK 0xFFFF0000L
+//L2_PTC_A_CONTROL
+#define L2_PTC_A_CONTROL__RESERVED__SHIFT 0x0
+#define L2_PTC_A_CONTROL__PTCALRUUpdatePri__SHIFT 0x3
+#define L2_PTC_A_CONTROL__PTCAParityEn__SHIFT 0x4
+#define L2_PTC_A_CONTROL__PTCAInvalidationSel__SHIFT 0x8
+#define L2_PTC_A_CONTROL__PTCASoftInvalidate__SHIFT 0xa
+#define L2_PTC_A_CONTROL__PTCA2MMode__SHIFT 0xb
+#define L2_PTC_A_CONTROL__PTCABypass__SHIFT 0xd
+#define L2_PTC_A_CONTROL__PTCAParitySupport__SHIFT 0xf
+#define L2_PTC_A_CONTROL__PTCAWays__SHIFT 0x10
+#define L2_PTC_A_CONTROL__PTCAEntries__SHIFT 0x1c
+#define L2_PTC_A_CONTROL__RESERVED_MASK 0x00000003L
+#define L2_PTC_A_CONTROL__PTCALRUUpdatePri_MASK 0x00000008L
+#define L2_PTC_A_CONTROL__PTCAParityEn_MASK 0x00000010L
+#define L2_PTC_A_CONTROL__PTCAInvalidationSel_MASK 0x00000300L
+#define L2_PTC_A_CONTROL__PTCASoftInvalidate_MASK 0x00000400L
+#define L2_PTC_A_CONTROL__PTCA2MMode_MASK 0x00000800L
+#define L2_PTC_A_CONTROL__PTCABypass_MASK 0x00002000L
+#define L2_PTC_A_CONTROL__PTCAParitySupport_MASK 0x00008000L
+#define L2_PTC_A_CONTROL__PTCAWays_MASK 0x00FF0000L
+#define L2_PTC_A_CONTROL__PTCAEntries_MASK 0xF0000000L
+//L2_PTC_A_HASH_CONTROL
+#define L2_PTC_A_HASH_CONTROL__PTCAAddressMask__SHIFT 0x10
+#define L2_PTC_A_HASH_CONTROL__PTCAAddressMask_MASK 0xFFFF0000L
+//L2_PTC_A_WAY_CONTROL
+#define L2_PTC_A_WAY_CONTROL__PTCAWayDisable__SHIFT 0x0
+#define L2_PTC_A_WAY_CONTROL__PTCAWayAccessDisable__SHIFT 0x10
+#define L2_PTC_A_WAY_CONTROL__PTCAWayDisable_MASK 0x0000FFFFL
+#define L2_PTC_A_WAY_CONTROL__PTCAWayAccessDisable_MASK 0xFFFF0000L
+//L2_CREDIT_CONTROL_2
+#define L2_CREDIT_CONTROL_2__QUEUECredits__SHIFT 0x0
+#define L2_CREDIT_CONTROL_2__QUEUEOverride__SHIFT 0x7
+#define L2_CREDIT_CONTROL_2__FLTCMBCredits__SHIFT 0x8
+#define L2_CREDIT_CONTROL_2__FLTCMBOverride__SHIFT 0xf
+#define L2_CREDIT_CONTROL_2__FCELCredits__SHIFT 0x10
+#define L2_CREDIT_CONTROL_2__FCELOverride__SHIFT 0x17
+#define L2_CREDIT_CONTROL_2__PPR_logger_credits__SHIFT 0x18
+#define L2_CREDIT_CONTROL_2__QUEUECredits_MASK 0x0000003FL
+#define L2_CREDIT_CONTROL_2__QUEUEOverride_MASK 0x00000080L
+#define L2_CREDIT_CONTROL_2__FLTCMBCredits_MASK 0x00003F00L
+#define L2_CREDIT_CONTROL_2__FLTCMBOverride_MASK 0x00008000L
+#define L2_CREDIT_CONTROL_2__FCELCredits_MASK 0x003F0000L
+#define L2_CREDIT_CONTROL_2__FCELOverride_MASK 0x00800000L
+#define L2_CREDIT_CONTROL_2__PPR_logger_credits_MASK 0x0F000000L
+//L2A_UPDATE_FILTER_CNTL
+#define L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_Bypass__SHIFT 0x0
+#define L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_RdLatency__SHIFT 0x1
+#define L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_Bypass_MASK 0x00000001L
+#define L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_RdLatency_MASK 0x0000001EL
+//L2_ERR_RULE_CONTROL_3
+#define L2_ERR_RULE_CONTROL_3__ERRRuleLock1__SHIFT 0x0
+#define L2_ERR_RULE_CONTROL_3__ERRRuleDisable3__SHIFT 0x4
+#define L2_ERR_RULE_CONTROL_3__ERRRuleLock1_MASK 0x00000001L
+#define L2_ERR_RULE_CONTROL_3__ERRRuleDisable3_MASK 0xFFFFFFF0L
+//L2_ERR_RULE_CONTROL_4
+#define L2_ERR_RULE_CONTROL_4__ERRRuleDisable4__SHIFT 0x0
+#define L2_ERR_RULE_CONTROL_4__ERRRuleDisable4_MASK 0xFFFFFFFFL
+//L2_ERR_RULE_CONTROL_5
+#define L2_ERR_RULE_CONTROL_5__ERRRuleDisable5__SHIFT 0x0
+#define L2_ERR_RULE_CONTROL_5__ERRRuleDisable5_MASK 0xFFFFFFFFL
+//L2_L2A_CK_GATE_CONTROL
+#define L2_L2A_CK_GATE_CONTROL__CKGateL2ARegsDisable__SHIFT 0x0
+#define L2_L2A_CK_GATE_CONTROL__CKGateL2ADynamicDisable__SHIFT 0x1
+#define L2_L2A_CK_GATE_CONTROL__CKGateL2ACacheDisable__SHIFT 0x2
+#define L2_L2A_CK_GATE_CONTROL__CKGateL2ASpare__SHIFT 0x3
+#define L2_L2A_CK_GATE_CONTROL__CKGateL2ALength__SHIFT 0x4
+#define L2_L2A_CK_GATE_CONTROL__CKGateL2AStop__SHIFT 0x6
+#define L2_L2A_CK_GATE_CONTROL__Reserved__SHIFT 0x8
+#define L2_L2A_CK_GATE_CONTROL__CKGateL2ARegsDisable_MASK 0x00000001L
+#define L2_L2A_CK_GATE_CONTROL__CKGateL2ADynamicDisable_MASK 0x00000002L
+#define L2_L2A_CK_GATE_CONTROL__CKGateL2ACacheDisable_MASK 0x00000004L
+#define L2_L2A_CK_GATE_CONTROL__CKGateL2ASpare_MASK 0x00000008L
+#define L2_L2A_CK_GATE_CONTROL__CKGateL2ALength_MASK 0x00000030L
+#define L2_L2A_CK_GATE_CONTROL__CKGateL2AStop_MASK 0x000000C0L
+#define L2_L2A_CK_GATE_CONTROL__Reserved_MASK 0xFFFFFF00L
+//L2_L2A_PGSIZE_CONTROL
+#define L2_L2A_PGSIZE_CONTROL__L2AREG_GST_PGSIZE__SHIFT 0x0
+#define L2_L2A_PGSIZE_CONTROL__L2AREG_HOST_PGSIZE__SHIFT 0x8
+#define L2_L2A_PGSIZE_CONTROL__L2AREG_GST_PGSIZE_MASK 0x0000007FL
+#define L2_L2A_PGSIZE_CONTROL__L2AREG_HOST_PGSIZE_MASK 0x00007F00L
+//L2_L2A_MEMPWR_GATE_1
+#define L2_L2A_MEMPWR_GATE_1__L2AREG_LS_EN__SHIFT 0x0
+#define L2_L2A_MEMPWR_GATE_1__L2AREG_DS_EN__SHIFT 0x1
+#define L2_L2A_MEMPWR_GATE_1__L2AREG_SD_EN__SHIFT 0x2
+#define L2_L2A_MEMPWR_GATE_1__L2AREG_CACHE_PGMEM_SEL__SHIFT 0x4
+#define L2_L2A_MEMPWR_GATE_1__L2AREG_LS_EN_MASK 0x00000001L
+#define L2_L2A_MEMPWR_GATE_1__L2AREG_DS_EN_MASK 0x00000002L
+#define L2_L2A_MEMPWR_GATE_1__L2AREG_SD_EN_MASK 0x00000004L
+#define L2_L2A_MEMPWR_GATE_1__L2AREG_CACHE_PGMEM_SEL_MASK 0x00000010L
+//L2_L2A_MEMPWR_GATE_2
+#define L2_L2A_MEMPWR_GATE_2__L2AREG_LS_thres__SHIFT 0x0
+#define L2_L2A_MEMPWR_GATE_2__L2AREG_LS_thres_MASK 0xFFFFFFFFL
+//L2_L2A_MEMPWR_GATE_3
+#define L2_L2A_MEMPWR_GATE_3__L2AREG_DS_thres__SHIFT 0x0
+#define L2_L2A_MEMPWR_GATE_3__L2AREG_DS_thres_MASK 0xFFFFFFFFL
+//L2_L2A_MEMPWR_GATE_4
+#define L2_L2A_MEMPWR_GATE_4__L2AREG_SD_thres__SHIFT 0x0
+#define L2_L2A_MEMPWR_GATE_4__L2AREG_SD_thres_MASK 0xFFFFFFFFL
+//L2_L2A_MEMPWR_GATE_5
+#define L2_L2A_MEMPWR_GATE_5__L2AREG_LS_Req_Maintain_Cnt__SHIFT 0x0
+#define L2_L2A_MEMPWR_GATE_5__L2AREG_LS_Req_Maintain_Cnt_MASK 0xFFFFFFFFL
+//L2_L2A_MEMPWR_GATE_6
+#define L2_L2A_MEMPWR_GATE_6__L2AREG_LS_Exit_Maintain_Cnt__SHIFT 0x0
+#define L2_L2A_MEMPWR_GATE_6__L2AREG_LS_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL
+//L2_L2A_MEMPWR_GATE_7
+#define L2_L2A_MEMPWR_GATE_7__L2AREG_DS_Req_Maintain_Cnt__SHIFT 0x0
+#define L2_L2A_MEMPWR_GATE_7__L2AREG_DS_Req_Maintain_Cnt_MASK 0xFFFFFFFFL
+//L2_L2A_MEMPWR_GATE_8
+#define L2_L2A_MEMPWR_GATE_8__L2AREG_DS_Exit_Maintain_Cnt__SHIFT 0x0
+#define L2_L2A_MEMPWR_GATE_8__L2AREG_DS_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL
+//L2_L2A_MEMPWR_GATE_9
+#define L2_L2A_MEMPWR_GATE_9__L2AREG_SD_Req_Maintain_Cnt__SHIFT 0x0
+#define L2_L2A_MEMPWR_GATE_9__L2AREG_SD_Req_Maintain_Cnt_MASK 0xFFFFFFFFL
+//L2_PWRGATE_CNTRL_REG_0
+#define L2_PWRGATE_CNTRL_REG_0__IP_PG_thres__SHIFT 0x0
+#define L2_PWRGATE_CNTRL_REG_0__IP_PG_thres_MASK 0xFFFFFFFFL
+//L2_L2A_MEMPWR_GATE_10
+#define L2_L2A_MEMPWR_GATE_10__L2AREG_SD_Exit_Maintain_Cnt__SHIFT 0x0
+#define L2_L2A_MEMPWR_GATE_10__L2AREG_SD_Exit_Maintain_Cnt_MASK 0xFFFFFFFFL
+//L2_PWRGATE_CNTRL_REG_3
+#define L2_PWRGATE_CNTRL_REG_3__IP_PG_en__SHIFT 0x0
+#define L2_PWRGATE_CNTRL_REG_3__IP_PG_busy__SHIFT 0x1
+#define L2_PWRGATE_CNTRL_REG_3__L2_PG_STATUS__SHIFT 0x2
+#define L2_PWRGATE_CNTRL_REG_3__CFG_FW_PG_EXIT_EN__SHIFT 0x3
+#define L2_PWRGATE_CNTRL_REG_3__IP_PG_en_MASK 0x00000001L
+#define L2_PWRGATE_CNTRL_REG_3__IP_PG_busy_MASK 0x00000002L
+#define L2_PWRGATE_CNTRL_REG_3__L2_PG_STATUS_MASK 0x00000004L
+#define L2_PWRGATE_CNTRL_REG_3__CFG_FW_PG_EXIT_EN_MASK 0x00000018L
+//L2_ECO_CNTRL_0
+#define L2_ECO_CNTRL_0__L2_ECO_0__SHIFT 0x0
+#define L2_ECO_CNTRL_0__L2_ECO_0_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_iohub_iommu_l2ashdw_l2ashdw
+//SHDWL2A_IOMMU_MMIO_DEVTBL_BASE_0
+#define SHDWL2A_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE__SHIFT 0x0
+#define SHDWL2A_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE_MASK 0x000001FFL
+//SHDWL2A_IOMMU_MMIO_CNTRL_0
+#define SHDWL2A_IOMMU_MMIO_CNTRL_0__IOMMU_EN__SHIFT 0x0
+#define SHDWL2A_IOMMU_MMIO_CNTRL_0__GT_EN__SHIFT 0x10
+#define SHDWL2A_IOMMU_MMIO_CNTRL_0__GA_EN__SHIFT 0x11
+#define SHDWL2A_IOMMU_MMIO_CNTRL_0__SMIF_EN__SHIFT 0x16
+#define SHDWL2A_IOMMU_MMIO_CNTRL_0__SMIF_LOG_EN__SHIFT 0x18
+#define SHDWL2A_IOMMU_MMIO_CNTRL_0__GAM_EN__SHIFT 0x19
+#define SHDWL2A_IOMMU_MMIO_CNTRL_0__IOMMU_EN_MASK 0x00000001L
+#define SHDWL2A_IOMMU_MMIO_CNTRL_0__GT_EN_MASK 0x00010000L
+#define SHDWL2A_IOMMU_MMIO_CNTRL_0__GA_EN_MASK 0x00020000L
+#define SHDWL2A_IOMMU_MMIO_CNTRL_0__SMIF_EN_MASK 0x00400000L
+#define SHDWL2A_IOMMU_MMIO_CNTRL_0__SMIF_LOG_EN_MASK 0x01000000L
+#define SHDWL2A_IOMMU_MMIO_CNTRL_0__GAM_EN_MASK 0x0E000000L
+//SHDWL2A_IOMMU_MMIO_CNTRL_1
+#define SHDWL2A_IOMMU_MMIO_CNTRL_1__DTE_SEG_EN__SHIFT 0x2
+#define SHDWL2A_IOMMU_MMIO_CNTRL_1__PRIV_ABORT_EN__SHIFT 0x5
+#define SHDWL2A_IOMMU_MMIO_CNTRL_1__EPH_EN__SHIFT 0xd
+#define SHDWL2A_IOMMU_MMIO_CNTRL_1__DTE_SEG_EN_MASK 0x0000000CL
+#define SHDWL2A_IOMMU_MMIO_CNTRL_1__PRIV_ABORT_EN_MASK 0x00000060L
+#define SHDWL2A_IOMMU_MMIO_CNTRL_1__EPH_EN_MASK 0x00002000L
+//SHDWL2A_IOMMU_MMIO_EXCL_BASE_0
+#define SHDWL2A_IOMMU_MMIO_EXCL_BASE_0__EX_EN__SHIFT 0x0
+#define SHDWL2A_IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW__SHIFT 0x1
+#define SHDWL2A_IOMMU_MMIO_EXCL_BASE_0__Reserved0__SHIFT 0x2
+#define SHDWL2A_IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO__SHIFT 0xc
+#define SHDWL2A_IOMMU_MMIO_EXCL_BASE_0__EX_EN_MASK 0x00000001L
+#define SHDWL2A_IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW_MASK 0x00000002L
+#define SHDWL2A_IOMMU_MMIO_EXCL_BASE_0__Reserved0_MASK 0x00000FFCL
+#define SHDWL2A_IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO_MASK 0xFFFFF000L
+//SHDWL2A_IOMMU_MMIO_EXCL_BASE_1
+#define SHDWL2A_IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI__SHIFT 0x0
+#define SHDWL2A_IOMMU_MMIO_EXCL_BASE_1__Reserved0__SHIFT 0x14
+#define SHDWL2A_IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI_MASK 0x000FFFFFL
+#define SHDWL2A_IOMMU_MMIO_EXCL_BASE_1__Reserved0_MASK 0xFFF00000L
+//SHDWL2A_IOMMU_MMIO_EXCL_LIM_0
+#define SHDWL2A_IOMMU_MMIO_EXCL_LIM_0__Reserved0__SHIFT 0x0
+#define SHDWL2A_IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO__SHIFT 0xc
+#define SHDWL2A_IOMMU_MMIO_EXCL_LIM_0__Reserved0_MASK 0x00000FFFL
+#define SHDWL2A_IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO_MASK 0xFFFFF000L
+//SHDWL2A_IOMMU_MMIO_EXCL_LIM_1
+#define SHDWL2A_IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI__SHIFT 0x0
+#define SHDWL2A_IOMMU_MMIO_EXCL_LIM_1__Reserved0__SHIFT 0x14
+#define SHDWL2A_IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI_MASK 0x000FFFFFL
+#define SHDWL2A_IOMMU_MMIO_EXCL_LIM_1__Reserved0_MASK 0xFFF00000L
+//SHDWL2A_SMI_FILTER_REGISTER_0_0
+#define SHDWL2A_SMI_FILTER_REGISTER_0_0__SmiDID_0__SHIFT 0x0
+#define SHDWL2A_SMI_FILTER_REGISTER_0_0__SmiDV_0__SHIFT 0x10
+#define SHDWL2A_SMI_FILTER_REGISTER_0_0__SmiFLock_0__SHIFT 0x11
+#define SHDWL2A_SMI_FILTER_REGISTER_0_0__Reserved__SHIFT 0x12
+#define SHDWL2A_SMI_FILTER_REGISTER_0_0__SmiDID_0_MASK 0x0000FFFFL
+#define SHDWL2A_SMI_FILTER_REGISTER_0_0__SmiDV_0_MASK 0x00010000L
+#define SHDWL2A_SMI_FILTER_REGISTER_0_0__SmiFLock_0_MASK 0x00020000L
+#define SHDWL2A_SMI_FILTER_REGISTER_0_0__Reserved_MASK 0xFFFC0000L
+//SHDWL2A_SMI_FILTER_REGISTER_1_0
+#define SHDWL2A_SMI_FILTER_REGISTER_1_0__SmiDID_1__SHIFT 0x0
+#define SHDWL2A_SMI_FILTER_REGISTER_1_0__SmiDV_1__SHIFT 0x10
+#define SHDWL2A_SMI_FILTER_REGISTER_1_0__SmiFLock_1__SHIFT 0x11
+#define SHDWL2A_SMI_FILTER_REGISTER_1_0__Reserved__SHIFT 0x12
+#define SHDWL2A_SMI_FILTER_REGISTER_1_0__SmiDID_1_MASK 0x0000FFFFL
+#define SHDWL2A_SMI_FILTER_REGISTER_1_0__SmiDV_1_MASK 0x00010000L
+#define SHDWL2A_SMI_FILTER_REGISTER_1_0__SmiFLock_1_MASK 0x00020000L
+#define SHDWL2A_SMI_FILTER_REGISTER_1_0__Reserved_MASK 0xFFFC0000L
+//SHDWL2A_SMI_FILTER_REGISTER_2_0
+#define SHDWL2A_SMI_FILTER_REGISTER_2_0__SmiDID_2__SHIFT 0x0
+#define SHDWL2A_SMI_FILTER_REGISTER_2_0__SmiDV_2__SHIFT 0x10
+#define SHDWL2A_SMI_FILTER_REGISTER_2_0__SmiFLock_2__SHIFT 0x11
+#define SHDWL2A_SMI_FILTER_REGISTER_2_0__Reserved__SHIFT 0x12
+#define SHDWL2A_SMI_FILTER_REGISTER_2_0__SmiDID_2_MASK 0x0000FFFFL
+#define SHDWL2A_SMI_FILTER_REGISTER_2_0__SmiDV_2_MASK 0x00010000L
+#define SHDWL2A_SMI_FILTER_REGISTER_2_0__SmiFLock_2_MASK 0x00020000L
+#define SHDWL2A_SMI_FILTER_REGISTER_2_0__Reserved_MASK 0xFFFC0000L
+//SHDWL2A_SMI_FILTER_REGISTER_3_0
+#define SHDWL2A_SMI_FILTER_REGISTER_3_0__SmiDID_3__SHIFT 0x0
+#define SHDWL2A_SMI_FILTER_REGISTER_3_0__SmiDV_3__SHIFT 0x10
+#define SHDWL2A_SMI_FILTER_REGISTER_3_0__SmiFLock_3__SHIFT 0x11
+#define SHDWL2A_SMI_FILTER_REGISTER_3_0__Reserved__SHIFT 0x12
+#define SHDWL2A_SMI_FILTER_REGISTER_3_0__SmiDID_3_MASK 0x0000FFFFL
+#define SHDWL2A_SMI_FILTER_REGISTER_3_0__SmiDV_3_MASK 0x00010000L
+#define SHDWL2A_SMI_FILTER_REGISTER_3_0__SmiFLock_3_MASK 0x00020000L
+#define SHDWL2A_SMI_FILTER_REGISTER_3_0__Reserved_MASK 0xFFFC0000L
+//SHDWL2A_IOMMU_MMIO_DEVTBL_1_BASE_0
+#define SHDWL2A_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE__SHIFT 0x0
+#define SHDWL2A_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE_MASK 0x000001FFL
+//SHDWL2A_IOMMU_MMIO_DEVTBL_2_BASE_0
+#define SHDWL2A_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE__SHIFT 0x0
+#define SHDWL2A_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE_MASK 0x000001FFL
+//SHDWL2A_IOMMU_MMIO_DEVTBL_3_BASE_0
+#define SHDWL2A_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE__SHIFT 0x0
+#define SHDWL2A_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE_MASK 0x000001FFL
+//SHDWL2A_IOMMU_MMIO_DEVTBL_4_BASE_0
+#define SHDWL2A_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE__SHIFT 0x0
+#define SHDWL2A_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE_MASK 0x000001FFL
+//SHDWL2A_IOMMU_MMIO_DEVTBL_5_BASE_0
+#define SHDWL2A_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE__SHIFT 0x0
+#define SHDWL2A_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE_MASK 0x000001FFL
+//SHDWL2A_IOMMU_MMIO_DEVTBL_6_BASE_0
+#define SHDWL2A_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE__SHIFT 0x0
+#define SHDWL2A_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE_MASK 0x000001FFL
+//SHDWL2A_IOMMU_MMIO_DEVTBL_7_BASE_0
+#define SHDWL2A_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE__SHIFT 0x0
+#define SHDWL2A_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE_MASK 0x000001FFL
+//SHDWL2A_IOMMU_CAP_BASE_LO
+#define SHDWL2A_IOMMU_CAP_BASE_LO__IOMMU_ENABLE__SHIFT 0x0
+#define SHDWL2A_IOMMU_CAP_BASE_LO__IOMMU_ENABLE_MASK 0x00000001L
+//SHDWL2A_IOMMU_CAP_MISC
+#define SHDWL2A_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV__SHIFT 0x16
+#define SHDWL2A_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV_MASK 0x00400000L
+//SHDWL2A_IOMMU_CAP_MISC_1
+#define SHDWL2A_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE__SHIFT 0x5
+#define SHDWL2A_IOMMU_CAP_MISC_1__DVM_MODE__SHIFT 0x6
+#define SHDWL2A_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE_MASK 0x00000020L
+#define SHDWL2A_IOMMU_CAP_MISC_1__DVM_MODE_MASK 0x000000C0L
+//SHDWL2A_IOMMU_CONTROL_W
+#define SHDWL2A_IOMMU_CONTROL_W__IO_TLBSUP_W__SHIFT 0x8
+#define SHDWL2A_IOMMU_CONTROL_W__EFR_SUP_W__SHIFT 0x9
+#define SHDWL2A_IOMMU_CONTROL_W__IO_TLBSUP_W_MASK 0x00000100L
+#define SHDWL2A_IOMMU_CONTROL_W__EFR_SUP_W_MASK 0x00000200L
+//SHDWL2A_IOMMU_MMIO_CONTROL0_W
+#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__PREF_SUP_W__SHIFT 0x0
+#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__PPR_SUP_W__SHIFT 0x1
+#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__NX_SUP_W__SHIFT 0x3
+#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__GT_SUP_W__SHIFT 0x4
+#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__GA_SUP_W__SHIFT 0x7
+#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__PC_SUP_W__SHIFT 0x9
+#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__HATS_W__SHIFT 0xa
+#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__US_SUP_W__SHIFT 0xc
+#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__GAM_SUP_W__SHIFT 0x15
+#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__PREF_SUP_W_MASK 0x00000001L
+#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__PPR_SUP_W_MASK 0x00000002L
+#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__NX_SUP_W_MASK 0x00000008L
+#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__GT_SUP_W_MASK 0x00000010L
+#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__GA_SUP_W_MASK 0x00000080L
+#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__PC_SUP_W_MASK 0x00000200L
+#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__HATS_W_MASK 0x00000C00L
+#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__US_SUP_W_MASK 0x00001000L
+#define SHDWL2A_IOMMU_MMIO_CONTROL0_W__GAM_SUP_W_MASK 0x00E00000L
+//SHDWL2A_IOMMU_MMIO_CONTROL1_W
+#define SHDWL2A_IOMMU_MMIO_CONTROL1_W__PAS_MAX_W__SHIFT 0x0
+#define SHDWL2A_IOMMU_MMIO_CONTROL1_W__DTE_seg_W__SHIFT 0x6
+#define SHDWL2A_IOMMU_MMIO_CONTROL1_W__EPH_SUP_W__SHIFT 0x10
+#define SHDWL2A_IOMMU_MMIO_CONTROL1_W__PAS_MAX_W_MASK 0x0000000FL
+#define SHDWL2A_IOMMU_MMIO_CONTROL1_W__DTE_seg_W_MASK 0x000000C0L
+#define SHDWL2A_IOMMU_MMIO_CONTROL1_W__EPH_SUP_W_MASK 0x00010000L
+
+
+// addressBlock: nbio_iohub_smmu_mmio_smmummiocfg
+//SMMU_IDR0
+#define SMMU_IDR0__S2P__SHIFT 0x0
+#define SMMU_IDR0__S1P__SHIFT 0x1
+#define SMMU_IDR0__TTF__SHIFT 0x2
+#define SMMU_IDR0__COHACC__SHIFT 0x4
+#define SMMU_IDR0__BTM__SHIFT 0x5
+#define SMMU_IDR0__HTTU__SHIFT 0x6
+#define SMMU_IDR0__DORMHINT__SHIFT 0x8
+#define SMMU_IDR0__Hyp__SHIFT 0x9
+#define SMMU_IDR0__ATS__SHIFT 0xa
+#define SMMU_IDR0__PERFCTRS__SHIFT 0xb
+#define SMMU_IDR0__ASID16__SHIFT 0xc
+#define SMMU_IDR0__MSI__SHIFT 0xd
+#define SMMU_IDR0__SEV__SHIFT 0xe
+#define SMMU_IDR0__ATOS__SHIFT 0xf
+#define SMMU_IDR0__PRI__SHIFT 0x10
+#define SMMU_IDR0__VMW__SHIFT 0x11
+#define SMMU_IDR0__VMID16__SHIFT 0x12
+#define SMMU_IDR0__CD2L__SHIFT 0x13
+#define SMMU_IDR0__VATOS__SHIFT 0x14
+#define SMMU_IDR0__TTENDIAN__SHIFT 0x15
+#define SMMU_IDR0__STALL_MODEL__SHIFT 0x18
+#define SMMU_IDR0__TERM_MODEL__SHIFT 0x1a
+#define SMMU_IDR0__ST_LEVEL__SHIFT 0x1b
+#define SMMU_IDR0__RAS__SHIFT 0x1d
+#define SMMU_IDR0__S2P_MASK 0x00000001L
+#define SMMU_IDR0__S1P_MASK 0x00000002L
+#define SMMU_IDR0__TTF_MASK 0x0000000CL
+#define SMMU_IDR0__COHACC_MASK 0x00000010L
+#define SMMU_IDR0__BTM_MASK 0x00000020L
+#define SMMU_IDR0__HTTU_MASK 0x000000C0L
+#define SMMU_IDR0__DORMHINT_MASK 0x00000100L
+#define SMMU_IDR0__Hyp_MASK 0x00000200L
+#define SMMU_IDR0__ATS_MASK 0x00000400L
+#define SMMU_IDR0__PERFCTRS_MASK 0x00000800L
+#define SMMU_IDR0__ASID16_MASK 0x00001000L
+#define SMMU_IDR0__MSI_MASK 0x00002000L
+#define SMMU_IDR0__SEV_MASK 0x00004000L
+#define SMMU_IDR0__ATOS_MASK 0x00008000L
+#define SMMU_IDR0__PRI_MASK 0x00010000L
+#define SMMU_IDR0__VMW_MASK 0x00020000L
+#define SMMU_IDR0__VMID16_MASK 0x00040000L
+#define SMMU_IDR0__CD2L_MASK 0x00080000L
+#define SMMU_IDR0__VATOS_MASK 0x00100000L
+#define SMMU_IDR0__TTENDIAN_MASK 0x00600000L
+#define SMMU_IDR0__STALL_MODEL_MASK 0x03000000L
+#define SMMU_IDR0__TERM_MODEL_MASK 0x04000000L
+#define SMMU_IDR0__ST_LEVEL_MASK 0x18000000L
+#define SMMU_IDR0__RAS_MASK 0x20000000L
+//SMMU_IDR1
+#define SMMU_IDR1__SIDSIZE__SHIFT 0x0
+#define SMMU_IDR1__SSIDSIZE__SHIFT 0x6
+#define SMMU_IDR1__PRIQS__SHIFT 0xb
+#define SMMU_IDR1__EVENTQS__SHIFT 0x10
+#define SMMU_IDR1__CMDQS__SHIFT 0x15
+#define SMMU_IDR1__ATTR_PERMS_OVR__SHIFT 0x1a
+#define SMMU_IDR1__ATTR_TYPES_OVR__SHIFT 0x1b
+#define SMMU_IDR1__REL__SHIFT 0x1c
+#define SMMU_IDR1__QUEUES_PRESET__SHIFT 0x1d
+#define SMMU_IDR1__TABLES_PRESET__SHIFT 0x1e
+#define SMMU_IDR1__SIDSIZE_MASK 0x0000003FL
+#define SMMU_IDR1__SSIDSIZE_MASK 0x000007C0L
+#define SMMU_IDR1__PRIQS_MASK 0x0000F800L
+#define SMMU_IDR1__EVENTQS_MASK 0x001F0000L
+#define SMMU_IDR1__CMDQS_MASK 0x03E00000L
+#define SMMU_IDR1__ATTR_PERMS_OVR_MASK 0x04000000L
+#define SMMU_IDR1__ATTR_TYPES_OVR_MASK 0x08000000L
+#define SMMU_IDR1__REL_MASK 0x10000000L
+#define SMMU_IDR1__QUEUES_PRESET_MASK 0x20000000L
+#define SMMU_IDR1__TABLES_PRESET_MASK 0x40000000L
+//SMMU_IDR2
+#define SMMU_IDR2__BA_VATOS__SHIFT 0x0
+#define SMMU_IDR2__BA_RAS__SHIFT 0xa
+#define SMMU_IDR2__BA_VATOS_MASK 0x000003FFL
+#define SMMU_IDR2__BA_RAS_MASK 0x000FFC00L
+//SMMU_IDR3
+#define SMMU_IDR3__RESERVED__SHIFT 0x0
+#define SMMU_IDR3__HAD__SHIFT 0x2
+#define SMMU_IDR3__RESERVED_MASK 0x00000003L
+#define SMMU_IDR3__HAD_MASK 0x00000004L
+//SMMU_IDR4
+#define SMMU_IDR4__IMPDEF__SHIFT 0x0
+#define SMMU_IDR4__IMPDEF_MASK 0xFFFFFFFFL
+//SMMU_IDR5
+#define SMMU_IDR5__OAS__SHIFT 0x0
+#define SMMU_IDR5__GRAN4K__SHIFT 0x4
+#define SMMU_IDR5__GRAN16K__SHIFT 0x5
+#define SMMU_IDR5__GRAN64K__SHIFT 0x6
+#define SMMU_IDR5__STALL_MAX__SHIFT 0x10
+#define SMMU_IDR5__OAS_MASK 0x00000007L
+#define SMMU_IDR5__GRAN4K_MASK 0x00000010L
+#define SMMU_IDR5__GRAN16K_MASK 0x00000020L
+#define SMMU_IDR5__GRAN64K_MASK 0x00000040L
+#define SMMU_IDR5__STALL_MAX_MASK 0xFFFF0000L
+//SMMU_IIDR
+#define SMMU_IIDR__Implementer__SHIFT 0x0
+#define SMMU_IIDR__Revision__SHIFT 0xc
+#define SMMU_IIDR__Variant__SHIFT 0x10
+#define SMMU_IIDR__ProductID__SHIFT 0x14
+#define SMMU_IIDR__Implementer_MASK 0x00000FFFL
+#define SMMU_IIDR__Revision_MASK 0x0000F000L
+#define SMMU_IIDR__Variant_MASK 0x000F0000L
+#define SMMU_IIDR__ProductID_MASK 0xFFF00000L
+//SMMU_AIDR
+#define SMMU_AIDR__ArchMinorRev__SHIFT 0x0
+#define SMMU_AIDR__ArchMajorRev__SHIFT 0x4
+#define SMMU_AIDR__ArchMinorRev_MASK 0x0000000FL
+#define SMMU_AIDR__ArchMajorRev_MASK 0x000000F0L
+//SMMU_CR0
+#define SMMU_CR0__SMMUEN__SHIFT 0x0
+#define SMMU_CR0__PRIQEN__SHIFT 0x1
+#define SMMU_CR0__EVQEN__SHIFT 0x2
+#define SMMU_CR0__CMDEN__SHIFT 0x3
+#define SMMU_CR0__ATSCHK__SHIFT 0x4
+#define SMMU_CR0__VMW__SHIFT 0x6
+#define SMMU_CR0__SMMUEN_MASK 0x00000001L
+#define SMMU_CR0__PRIQEN_MASK 0x00000002L
+#define SMMU_CR0__EVQEN_MASK 0x00000004L
+#define SMMU_CR0__CMDEN_MASK 0x00000008L
+#define SMMU_CR0__ATSCHK_MASK 0x00000010L
+#define SMMU_CR0__VMW_MASK 0x000001C0L
+//SMMU_CR0ACK
+#define SMMU_CR0ACK__SMMUEN__SHIFT 0x0
+#define SMMU_CR0ACK__PRIQEN__SHIFT 0x1
+#define SMMU_CR0ACK__EVQEN__SHIFT 0x2
+#define SMMU_CR0ACK__CMDEN__SHIFT 0x3
+#define SMMU_CR0ACK__ATSCHK__SHIFT 0x4
+#define SMMU_CR0ACK__VMW__SHIFT 0x6
+#define SMMU_CR0ACK__SMMUEN_MASK 0x00000001L
+#define SMMU_CR0ACK__PRIQEN_MASK 0x00000002L
+#define SMMU_CR0ACK__EVQEN_MASK 0x00000004L
+#define SMMU_CR0ACK__CMDEN_MASK 0x00000008L
+#define SMMU_CR0ACK__ATSCHK_MASK 0x00000010L
+#define SMMU_CR0ACK__VMW_MASK 0x000001C0L
+//SMMU_CR2
+#define SMMU_CR2__E2H__SHIFT 0x0
+#define SMMU_CR2__RECINVSID__SHIFT 0x1
+#define SMMU_CR2__PTM__SHIFT 0x2
+#define SMMU_CR2__E2H_MASK 0x00000001L
+#define SMMU_CR2__RECINVSID_MASK 0x00000002L
+#define SMMU_CR2__PTM_MASK 0x00000004L
+//SMMU_GBPA
+#define SMMU_GBPA__ABORT__SHIFT 0x14
+#define SMMU_GBPA__Update__SHIFT 0x1f
+#define SMMU_GBPA__ABORT_MASK 0x00100000L
+#define SMMU_GBPA__Update_MASK 0x80000000L
+//SMMU_STRTAB_BASE_HI
+#define SMMU_STRTAB_BASE_HI__STRTAB_BASE_ADDR_HI__SHIFT 0x0
+#define SMMU_STRTAB_BASE_HI__STRTAB_RA__SHIFT 0x1e
+#define SMMU_STRTAB_BASE_HI__STRTAB_BASE_ADDR_HI_MASK 0x0000FFFFL
+#define SMMU_STRTAB_BASE_HI__STRTAB_RA_MASK 0x40000000L
+//SMMU_STRTAB_BASE_LO
+#define SMMU_STRTAB_BASE_LO__STRTAB_BASE_ADDR_LO__SHIFT 0x6
+#define SMMU_STRTAB_BASE_LO__STRTAB_BASE_ADDR_LO_MASK 0xFFFFFFC0L
+//SMMU_STRTAB_BASE_CFG
+#define SMMU_STRTAB_BASE_CFG__STRTAB_LOG2SIZE__SHIFT 0x0
+#define SMMU_STRTAB_BASE_CFG__STRTAB_SPLIT__SHIFT 0x6
+#define SMMU_STRTAB_BASE_CFG__STRTAB_FMT__SHIFT 0x10
+#define SMMU_STRTAB_BASE_CFG__STRTAB_LOG2SIZE_MASK 0x0000003FL
+#define SMMU_STRTAB_BASE_CFG__STRTAB_SPLIT_MASK 0x000007C0L
+#define SMMU_STRTAB_BASE_CFG__STRTAB_FMT_MASK 0x00030000L
+
+
+// addressBlock: nbio_iohub_nb_ioagrcfg_ioagr_cfgdec
+//IOAGR_GLUE_CG_LCLK_CTRL_0
+#define IOAGR_GLUE_CG_LCLK_CTRL_0__CG_OFF_HYSTERESIS__SHIFT 0x4
+#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK9__SHIFT 0x16
+#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK8__SHIFT 0x17
+#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK7__SHIFT 0x18
+#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK6__SHIFT 0x19
+#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK5__SHIFT 0x1a
+#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK4__SHIFT 0x1b
+#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK3__SHIFT 0x1c
+#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK2__SHIFT 0x1d
+#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK1__SHIFT 0x1e
+#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK0__SHIFT 0x1f
+#define IOAGR_GLUE_CG_LCLK_CTRL_0__CG_OFF_HYSTERESIS_MASK 0x00000FF0L
+#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK9_MASK 0x00400000L
+#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK8_MASK 0x00800000L
+#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK7_MASK 0x01000000L
+#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK6_MASK 0x02000000L
+#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK5_MASK 0x04000000L
+#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK4_MASK 0x08000000L
+#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK3_MASK 0x10000000L
+#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK2_MASK 0x20000000L
+#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK1_MASK 0x40000000L
+#define IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK0_MASK 0x80000000L
+//IOAGR_GLUE_CG_LCLK_CTRL_1
+#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK9__SHIFT 0x16
+#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK8__SHIFT 0x17
+#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK7__SHIFT 0x18
+#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK6__SHIFT 0x19
+#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK5__SHIFT 0x1a
+#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK4__SHIFT 0x1b
+#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK3__SHIFT 0x1c
+#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK2__SHIFT 0x1d
+#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK1__SHIFT 0x1e
+#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK0__SHIFT 0x1f
+#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK9_MASK 0x00400000L
+#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK8_MASK 0x00800000L
+#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK7_MASK 0x01000000L
+#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK6_MASK 0x02000000L
+#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK5_MASK 0x04000000L
+#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK4_MASK 0x08000000L
+#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK3_MASK 0x10000000L
+#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK2_MASK 0x20000000L
+#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK1_MASK 0x40000000L
+#define IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK0_MASK 0x80000000L
+//IOAGR_REQDECODE_OVERRIDE
+#define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client0__SHIFT 0x0
+#define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client1__SHIFT 0x4
+#define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client2__SHIFT 0x8
+#define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client3__SHIFT 0xc
+#define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client4__SHIFT 0x10
+#define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client5__SHIFT 0x14
+#define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client6__SHIFT 0x18
+#define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client7__SHIFT 0x1c
+#define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client0_MASK 0x0000000FL
+#define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client1_MASK 0x000000F0L
+#define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client2_MASK 0x00000F00L
+#define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client3_MASK 0x0000F000L
+#define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client4_MASK 0x000F0000L
+#define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client5_MASK 0x00F00000L
+#define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client6_MASK 0x0F000000L
+#define IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client7_MASK 0xF0000000L
+//IOAGR_RSPDECODE_OVERRIDE
+#define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client0__SHIFT 0x0
+#define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client1__SHIFT 0x4
+#define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client2__SHIFT 0x8
+#define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client3__SHIFT 0xc
+#define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client4__SHIFT 0x10
+#define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client5__SHIFT 0x14
+#define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client6__SHIFT 0x18
+#define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client7__SHIFT 0x1c
+#define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client0_MASK 0x0000000FL
+#define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client1_MASK 0x000000F0L
+#define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client2_MASK 0x00000F00L
+#define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client3_MASK 0x0000F000L
+#define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client4_MASK 0x000F0000L
+#define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client5_MASK 0x00F00000L
+#define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client6_MASK 0x0F000000L
+#define IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client7_MASK 0xF0000000L
+//IOAGR_USERBIT_BYPASS
+#define IOAGR_USERBIT_BYPASS__Userbit_Bypass__SHIFT 0x0
+#define IOAGR_USERBIT_BYPASS__Userbit_Bypass_MASK 0x00000001L
+//IOAGR_SDP_PORT_CONTROL
+#define IOAGR_SDP_PORT_CONTROL__Port_Disconnect_Hysteresis__SHIFT 0x0
+#define IOAGR_SDP_PORT_CONTROL__DMAEnableEarlyClkReq__SHIFT 0xf
+#define IOAGR_SDP_PORT_CONTROL__HostEnableEarlyClkReq__SHIFT 0x10
+#define IOAGR_SDP_PORT_CONTROL__Port_Disconnect_Hysteresis_MASK 0x0000003FL
+#define IOAGR_SDP_PORT_CONTROL__DMAEnableEarlyClkReq_MASK 0x00008000L
+#define IOAGR_SDP_PORT_CONTROL__HostEnableEarlyClkReq_MASK 0xFFFF0000L
+//IOAGR_PERF_CNTL
+#define IOAGR_PERF_CNTL__EVENT0_SEL__SHIFT 0x0
+#define IOAGR_PERF_CNTL__EVENT1_SEL__SHIFT 0x8
+#define IOAGR_PERF_CNTL__EVENT2_SEL__SHIFT 0x10
+#define IOAGR_PERF_CNTL__EVENT3_SEL__SHIFT 0x18
+#define IOAGR_PERF_CNTL__EVENT0_SEL_MASK 0x000000FFL
+#define IOAGR_PERF_CNTL__EVENT1_SEL_MASK 0x0000FF00L
+#define IOAGR_PERF_CNTL__EVENT2_SEL_MASK 0x00FF0000L
+#define IOAGR_PERF_CNTL__EVENT3_SEL_MASK 0xFF000000L
+//IOAGR_PERF_COUNT0
+#define IOAGR_PERF_COUNT0__COUNTER0__SHIFT 0x0
+#define IOAGR_PERF_COUNT0__COUNTER0_MASK 0xFFFFFFFFL
+//IOAGR_PERF_COUNT0_UPPER
+#define IOAGR_PERF_COUNT0_UPPER__COUNTER0_UPPER__SHIFT 0x0
+#define IOAGR_PERF_COUNT0_UPPER__COUNTER0_UPPER_MASK 0x00FFFFFFL
+//IOAGR_PERF_COUNT1
+#define IOAGR_PERF_COUNT1__COUNTER1__SHIFT 0x0
+#define IOAGR_PERF_COUNT1__COUNTER1_MASK 0xFFFFFFFFL
+//IOAGR_PERF_COUNT1_UPPER
+#define IOAGR_PERF_COUNT1_UPPER__COUNTER1_UPPER__SHIFT 0x0
+#define IOAGR_PERF_COUNT1_UPPER__COUNTER1_UPPER_MASK 0x00FFFFFFL
+//IOAGR_PERF_COUNT2
+#define IOAGR_PERF_COUNT2__COUNTER2__SHIFT 0x0
+#define IOAGR_PERF_COUNT2__COUNTER2_MASK 0xFFFFFFFFL
+//IOAGR_PERF_COUNT2_UPPER
+#define IOAGR_PERF_COUNT2_UPPER__COUNTER2_UPPER__SHIFT 0x0
+#define IOAGR_PERF_COUNT2_UPPER__COUNTER2_UPPER_MASK 0x00FFFFFFL
+//IOAGR_PERF_COUNT3
+#define IOAGR_PERF_COUNT3__COUNTER3__SHIFT 0x0
+#define IOAGR_PERF_COUNT3__COUNTER3_MASK 0xFFFFFFFFL
+//IOAGR_PERF_COUNT3_UPPER
+#define IOAGR_PERF_COUNT3_UPPER__COUNTER3_UPPER__SHIFT 0x0
+#define IOAGR_PERF_COUNT3_UPPER__COUNTER3_UPPER_MASK 0x00FFFFFFL
+//IOAGR_PGMST_CNTL
+#define IOAGR_PGMST_CNTL__CFG_PG_HYSTERESIS__SHIFT 0x0
+#define IOAGR_PGMST_CNTL__CFG_PG_EN__SHIFT 0x8
+#define IOAGR_PGMST_CNTL__CFG_IDLENESS_COUNT_EN__SHIFT 0xa
+#define IOAGR_PGMST_CNTL__CFG_FW_PG_EXIT_EN__SHIFT 0xe
+#define IOAGR_PGMST_CNTL__CFG_PG_HYSTERESIS_MASK 0x000000FFL
+#define IOAGR_PGMST_CNTL__CFG_PG_EN_MASK 0x00000100L
+#define IOAGR_PGMST_CNTL__CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L
+#define IOAGR_PGMST_CNTL__CFG_FW_PG_EXIT_EN_MASK 0x0000C000L
+//IOAGR_PGSLV_CNTL
+#define IOAGR_PGSLV_CNTL__CFG_IDLE_HYSTERESIS__SHIFT 0x0
+#define IOAGR_PGSLV_CNTL__CFG_IDLE_HYSTERESIS_MASK 0x0000001FL
+//IOAGR_SION_S0_Client0_Req_BurstTarget_Lower
+#define IOAGR_SION_S0_Client0_Req_BurstTarget_Lower__IOAGR_SION_S0_Client0_Req_BurstTarget_Lower__SHIFT 0x0
+#define IOAGR_SION_S0_Client0_Req_BurstTarget_Lower__IOAGR_SION_S0_Client0_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client0_Req_BurstTarget_Upper
+#define IOAGR_SION_S0_Client0_Req_BurstTarget_Upper__IOAGR_SION_S0_Client0_Req_BurstTarget_Upper__SHIFT 0x0
+#define IOAGR_SION_S0_Client0_Req_BurstTarget_Upper__IOAGR_SION_S0_Client0_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client0_Req_TimeSlot_Lower
+#define IOAGR_SION_S0_Client0_Req_TimeSlot_Lower__IOAGR_SION_S0_Client0_Req_TimeSlot_Lower__SHIFT 0x0
+#define IOAGR_SION_S0_Client0_Req_TimeSlot_Lower__IOAGR_SION_S0_Client0_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client0_Req_TimeSlot_Upper
+#define IOAGR_SION_S0_Client0_Req_TimeSlot_Upper__IOAGR_SION_S0_Client0_Req_TimeSlot_Upper__SHIFT 0x0
+#define IOAGR_SION_S0_Client0_Req_TimeSlot_Upper__IOAGR_SION_S0_Client0_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Lower
+#define IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Lower__IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Lower__IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Upper
+#define IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Upper__IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Upper__IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Lower
+#define IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Lower__IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Lower__IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Upper
+#define IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Upper__IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Upper__IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Lower
+#define IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Lower__IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Lower__IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Upper
+#define IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Upper__IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Upper__IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Lower
+#define IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Lower__IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Lower__IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Upper
+#define IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Upper__IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Upper__IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client0_Req_BurstTarget_Lower
+#define IOAGR_SION_S1_Client0_Req_BurstTarget_Lower__IOAGR_SION_S1_Client0_Req_BurstTarget_Lower__SHIFT 0x0
+#define IOAGR_SION_S1_Client0_Req_BurstTarget_Lower__IOAGR_SION_S1_Client0_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client0_Req_BurstTarget_Upper
+#define IOAGR_SION_S1_Client0_Req_BurstTarget_Upper__IOAGR_SION_S1_Client0_Req_BurstTarget_Upper__SHIFT 0x0
+#define IOAGR_SION_S1_Client0_Req_BurstTarget_Upper__IOAGR_SION_S1_Client0_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client0_Req_TimeSlot_Lower
+#define IOAGR_SION_S1_Client0_Req_TimeSlot_Lower__IOAGR_SION_S1_Client0_Req_TimeSlot_Lower__SHIFT 0x0
+#define IOAGR_SION_S1_Client0_Req_TimeSlot_Lower__IOAGR_SION_S1_Client0_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client0_Req_TimeSlot_Upper
+#define IOAGR_SION_S1_Client0_Req_TimeSlot_Upper__IOAGR_SION_S1_Client0_Req_TimeSlot_Upper__SHIFT 0x0
+#define IOAGR_SION_S1_Client0_Req_TimeSlot_Upper__IOAGR_SION_S1_Client0_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Lower
+#define IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Lower__IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Lower__IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Upper
+#define IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Upper__IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Upper__IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Lower
+#define IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Lower__IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Lower__IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Upper
+#define IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Upper__IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Upper__IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Lower
+#define IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Lower__IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Lower__IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Upper
+#define IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Upper__IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Upper__IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Lower
+#define IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Lower__IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Lower__IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Upper
+#define IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Upper__IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Upper__IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_Client0_ReqPoolCredit_Alloc_Lower
+#define IOAGR_SION_Client0_ReqPoolCredit_Alloc_Lower__IOAGR_SION_Client0_ReqPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOAGR_SION_Client0_ReqPoolCredit_Alloc_Lower__IOAGR_SION_Client0_ReqPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_Client0_ReqPoolCredit_Alloc_Upper
+#define IOAGR_SION_Client0_ReqPoolCredit_Alloc_Upper__IOAGR_SION_Client0_ReqPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOAGR_SION_Client0_ReqPoolCredit_Alloc_Upper__IOAGR_SION_Client0_ReqPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_Client0_DataPoolCredit_Alloc_Lower
+#define IOAGR_SION_Client0_DataPoolCredit_Alloc_Lower__IOAGR_SION_Client0_DataPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOAGR_SION_Client0_DataPoolCredit_Alloc_Lower__IOAGR_SION_Client0_DataPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_Client0_DataPoolCredit_Alloc_Upper
+#define IOAGR_SION_Client0_DataPoolCredit_Alloc_Upper__IOAGR_SION_Client0_DataPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOAGR_SION_Client0_DataPoolCredit_Alloc_Upper__IOAGR_SION_Client0_DataPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Lower
+#define IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Lower__IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Lower__IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Upper
+#define IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Upper__IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Upper__IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Lower
+#define IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Lower__IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Lower__IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Upper
+#define IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Upper__IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Upper__IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client1_Req_BurstTarget_Lower
+#define IOAGR_SION_S0_Client1_Req_BurstTarget_Lower__IOAGR_SION_S0_Client1_Req_BurstTarget_Lower__SHIFT 0x0
+#define IOAGR_SION_S0_Client1_Req_BurstTarget_Lower__IOAGR_SION_S0_Client1_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client1_Req_BurstTarget_Upper
+#define IOAGR_SION_S0_Client1_Req_BurstTarget_Upper__IOAGR_SION_S0_Client1_Req_BurstTarget_Upper__SHIFT 0x0
+#define IOAGR_SION_S0_Client1_Req_BurstTarget_Upper__IOAGR_SION_S0_Client1_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client1_Req_TimeSlot_Lower
+#define IOAGR_SION_S0_Client1_Req_TimeSlot_Lower__IOAGR_SION_S0_Client1_Req_TimeSlot_Lower__SHIFT 0x0
+#define IOAGR_SION_S0_Client1_Req_TimeSlot_Lower__IOAGR_SION_S0_Client1_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client1_Req_TimeSlot_Upper
+#define IOAGR_SION_S0_Client1_Req_TimeSlot_Upper__IOAGR_SION_S0_Client1_Req_TimeSlot_Upper__SHIFT 0x0
+#define IOAGR_SION_S0_Client1_Req_TimeSlot_Upper__IOAGR_SION_S0_Client1_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Lower
+#define IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Lower__IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Lower__IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Upper
+#define IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Upper__IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Upper__IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Lower
+#define IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Lower__IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Lower__IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Upper
+#define IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Upper__IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Upper__IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Lower
+#define IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Lower__IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Lower__IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Upper
+#define IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Upper__IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Upper__IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Lower
+#define IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Lower__IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Lower__IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Upper
+#define IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Upper__IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Upper__IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client1_Req_BurstTarget_Lower
+#define IOAGR_SION_S1_Client1_Req_BurstTarget_Lower__IOAGR_SION_S1_Client1_Req_BurstTarget_Lower__SHIFT 0x0
+#define IOAGR_SION_S1_Client1_Req_BurstTarget_Lower__IOAGR_SION_S1_Client1_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client1_Req_BurstTarget_Upper
+#define IOAGR_SION_S1_Client1_Req_BurstTarget_Upper__IOAGR_SION_S1_Client1_Req_BurstTarget_Upper__SHIFT 0x0
+#define IOAGR_SION_S1_Client1_Req_BurstTarget_Upper__IOAGR_SION_S1_Client1_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client1_Req_TimeSlot_Lower
+#define IOAGR_SION_S1_Client1_Req_TimeSlot_Lower__IOAGR_SION_S1_Client1_Req_TimeSlot_Lower__SHIFT 0x0
+#define IOAGR_SION_S1_Client1_Req_TimeSlot_Lower__IOAGR_SION_S1_Client1_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client1_Req_TimeSlot_Upper
+#define IOAGR_SION_S1_Client1_Req_TimeSlot_Upper__IOAGR_SION_S1_Client1_Req_TimeSlot_Upper__SHIFT 0x0
+#define IOAGR_SION_S1_Client1_Req_TimeSlot_Upper__IOAGR_SION_S1_Client1_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Lower
+#define IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Lower__IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Lower__IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Upper
+#define IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Upper__IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Upper__IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Lower
+#define IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Lower__IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Lower__IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Upper
+#define IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Upper__IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Upper__IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Lower
+#define IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Lower__IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Lower__IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Upper
+#define IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Upper__IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Upper__IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Lower
+#define IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Lower__IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Lower__IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Upper
+#define IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Upper__IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Upper__IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_Client1_ReqPoolCredit_Alloc_Lower
+#define IOAGR_SION_Client1_ReqPoolCredit_Alloc_Lower__IOAGR_SION_Client1_ReqPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOAGR_SION_Client1_ReqPoolCredit_Alloc_Lower__IOAGR_SION_Client1_ReqPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_Client1_ReqPoolCredit_Alloc_Upper
+#define IOAGR_SION_Client1_ReqPoolCredit_Alloc_Upper__IOAGR_SION_Client1_ReqPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOAGR_SION_Client1_ReqPoolCredit_Alloc_Upper__IOAGR_SION_Client1_ReqPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_Client1_DataPoolCredit_Alloc_Lower
+#define IOAGR_SION_Client1_DataPoolCredit_Alloc_Lower__IOAGR_SION_Client1_DataPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOAGR_SION_Client1_DataPoolCredit_Alloc_Lower__IOAGR_SION_Client1_DataPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_Client1_DataPoolCredit_Alloc_Upper
+#define IOAGR_SION_Client1_DataPoolCredit_Alloc_Upper__IOAGR_SION_Client1_DataPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOAGR_SION_Client1_DataPoolCredit_Alloc_Upper__IOAGR_SION_Client1_DataPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Lower
+#define IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Lower__IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Lower__IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Upper
+#define IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Upper__IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Upper__IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Lower
+#define IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Lower__IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Lower__IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Upper
+#define IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Upper__IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Upper__IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client2_Req_BurstTarget_Lower
+#define IOAGR_SION_S0_Client2_Req_BurstTarget_Lower__IOAGR_SION_S0_Client2_Req_BurstTarget_Lower__SHIFT 0x0
+#define IOAGR_SION_S0_Client2_Req_BurstTarget_Lower__IOAGR_SION_S0_Client2_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client2_Req_BurstTarget_Upper
+#define IOAGR_SION_S0_Client2_Req_BurstTarget_Upper__IOAGR_SION_S0_Client2_Req_BurstTarget_Upper__SHIFT 0x0
+#define IOAGR_SION_S0_Client2_Req_BurstTarget_Upper__IOAGR_SION_S0_Client2_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client2_Req_TimeSlot_Lower
+#define IOAGR_SION_S0_Client2_Req_TimeSlot_Lower__IOAGR_SION_S0_Client2_Req_TimeSlot_Lower__SHIFT 0x0
+#define IOAGR_SION_S0_Client2_Req_TimeSlot_Lower__IOAGR_SION_S0_Client2_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client2_Req_TimeSlot_Upper
+#define IOAGR_SION_S0_Client2_Req_TimeSlot_Upper__IOAGR_SION_S0_Client2_Req_TimeSlot_Upper__SHIFT 0x0
+#define IOAGR_SION_S0_Client2_Req_TimeSlot_Upper__IOAGR_SION_S0_Client2_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Lower
+#define IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Lower__IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Lower__IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Upper
+#define IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Upper__IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Upper__IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Lower
+#define IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Lower__IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Lower__IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Upper
+#define IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Upper__IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Upper__IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Lower
+#define IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Lower__IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Lower__IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Upper
+#define IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Upper__IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Upper__IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Lower
+#define IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Lower__IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Lower__IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Upper
+#define IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Upper__IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Upper__IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client2_Req_BurstTarget_Lower
+#define IOAGR_SION_S1_Client2_Req_BurstTarget_Lower__IOAGR_SION_S1_Client2_Req_BurstTarget_Lower__SHIFT 0x0
+#define IOAGR_SION_S1_Client2_Req_BurstTarget_Lower__IOAGR_SION_S1_Client2_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client2_Req_BurstTarget_Upper
+#define IOAGR_SION_S1_Client2_Req_BurstTarget_Upper__IOAGR_SION_S1_Client2_Req_BurstTarget_Upper__SHIFT 0x0
+#define IOAGR_SION_S1_Client2_Req_BurstTarget_Upper__IOAGR_SION_S1_Client2_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client2_Req_TimeSlot_Lower
+#define IOAGR_SION_S1_Client2_Req_TimeSlot_Lower__IOAGR_SION_S1_Client2_Req_TimeSlot_Lower__SHIFT 0x0
+#define IOAGR_SION_S1_Client2_Req_TimeSlot_Lower__IOAGR_SION_S1_Client2_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client2_Req_TimeSlot_Upper
+#define IOAGR_SION_S1_Client2_Req_TimeSlot_Upper__IOAGR_SION_S1_Client2_Req_TimeSlot_Upper__SHIFT 0x0
+#define IOAGR_SION_S1_Client2_Req_TimeSlot_Upper__IOAGR_SION_S1_Client2_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Lower
+#define IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Lower__IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Lower__IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Upper
+#define IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Upper__IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Upper__IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Lower
+#define IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Lower__IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Lower__IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Upper
+#define IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Upper__IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Upper__IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Lower
+#define IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Lower__IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Lower__IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Upper
+#define IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Upper__IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Upper__IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Lower
+#define IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Lower__IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Lower__IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Upper
+#define IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Upper__IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Upper__IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_Client2_ReqPoolCredit_Alloc_Lower
+#define IOAGR_SION_Client2_ReqPoolCredit_Alloc_Lower__IOAGR_SION_Client2_ReqPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOAGR_SION_Client2_ReqPoolCredit_Alloc_Lower__IOAGR_SION_Client2_ReqPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_Client2_ReqPoolCredit_Alloc_Upper
+#define IOAGR_SION_Client2_ReqPoolCredit_Alloc_Upper__IOAGR_SION_Client2_ReqPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOAGR_SION_Client2_ReqPoolCredit_Alloc_Upper__IOAGR_SION_Client2_ReqPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_Client2_DataPoolCredit_Alloc_Lower
+#define IOAGR_SION_Client2_DataPoolCredit_Alloc_Lower__IOAGR_SION_Client2_DataPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOAGR_SION_Client2_DataPoolCredit_Alloc_Lower__IOAGR_SION_Client2_DataPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_Client2_DataPoolCredit_Alloc_Upper
+#define IOAGR_SION_Client2_DataPoolCredit_Alloc_Upper__IOAGR_SION_Client2_DataPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOAGR_SION_Client2_DataPoolCredit_Alloc_Upper__IOAGR_SION_Client2_DataPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Lower
+#define IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Lower__IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Lower__IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Upper
+#define IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Upper__IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Upper__IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Lower
+#define IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Lower__IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Lower__IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Upper
+#define IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Upper__IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Upper__IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client3_Req_BurstTarget_Lower
+#define IOAGR_SION_S0_Client3_Req_BurstTarget_Lower__IOAGR_SION_S0_Client3_Req_BurstTarget_Lower__SHIFT 0x0
+#define IOAGR_SION_S0_Client3_Req_BurstTarget_Lower__IOAGR_SION_S0_Client3_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client3_Req_BurstTarget_Upper
+#define IOAGR_SION_S0_Client3_Req_BurstTarget_Upper__IOAGR_SION_S0_Client3_Req_BurstTarget_Upper__SHIFT 0x0
+#define IOAGR_SION_S0_Client3_Req_BurstTarget_Upper__IOAGR_SION_S0_Client3_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client3_Req_TimeSlot_Lower
+#define IOAGR_SION_S0_Client3_Req_TimeSlot_Lower__IOAGR_SION_S0_Client3_Req_TimeSlot_Lower__SHIFT 0x0
+#define IOAGR_SION_S0_Client3_Req_TimeSlot_Lower__IOAGR_SION_S0_Client3_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client3_Req_TimeSlot_Upper
+#define IOAGR_SION_S0_Client3_Req_TimeSlot_Upper__IOAGR_SION_S0_Client3_Req_TimeSlot_Upper__SHIFT 0x0
+#define IOAGR_SION_S0_Client3_Req_TimeSlot_Upper__IOAGR_SION_S0_Client3_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Lower
+#define IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Lower__IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Lower__IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Upper
+#define IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Upper__IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Upper__IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Lower
+#define IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Lower__IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Lower__IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Upper
+#define IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Upper__IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Upper__IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Lower
+#define IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Lower__IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Lower__IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Upper
+#define IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Upper__IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Upper__IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Lower
+#define IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Lower__IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Lower__IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Upper
+#define IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Upper__IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Upper__IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client3_Req_BurstTarget_Lower
+#define IOAGR_SION_S1_Client3_Req_BurstTarget_Lower__IOAGR_SION_S1_Client3_Req_BurstTarget_Lower__SHIFT 0x0
+#define IOAGR_SION_S1_Client3_Req_BurstTarget_Lower__IOAGR_SION_S1_Client3_Req_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client3_Req_BurstTarget_Upper
+#define IOAGR_SION_S1_Client3_Req_BurstTarget_Upper__IOAGR_SION_S1_Client3_Req_BurstTarget_Upper__SHIFT 0x0
+#define IOAGR_SION_S1_Client3_Req_BurstTarget_Upper__IOAGR_SION_S1_Client3_Req_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client3_Req_TimeSlot_Lower
+#define IOAGR_SION_S1_Client3_Req_TimeSlot_Lower__IOAGR_SION_S1_Client3_Req_TimeSlot_Lower__SHIFT 0x0
+#define IOAGR_SION_S1_Client3_Req_TimeSlot_Lower__IOAGR_SION_S1_Client3_Req_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client3_Req_TimeSlot_Upper
+#define IOAGR_SION_S1_Client3_Req_TimeSlot_Upper__IOAGR_SION_S1_Client3_Req_TimeSlot_Upper__SHIFT 0x0
+#define IOAGR_SION_S1_Client3_Req_TimeSlot_Upper__IOAGR_SION_S1_Client3_Req_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Lower
+#define IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Lower__IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Lower__IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Upper
+#define IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Upper__IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Upper__IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Lower
+#define IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Lower__IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Lower__IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Upper
+#define IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Upper__IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Upper__IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Lower
+#define IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Lower__IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Lower__SHIFT 0x0
+#define IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Lower__IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Upper
+#define IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Upper__IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Upper__SHIFT 0x0
+#define IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Upper__IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Lower
+#define IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Lower__IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Lower__SHIFT 0x0
+#define IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Lower__IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Upper
+#define IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Upper__IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Upper__SHIFT 0x0
+#define IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Upper__IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_Client3_ReqPoolCredit_Alloc_Lower
+#define IOAGR_SION_Client3_ReqPoolCredit_Alloc_Lower__IOAGR_SION_Client3_ReqPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOAGR_SION_Client3_ReqPoolCredit_Alloc_Lower__IOAGR_SION_Client3_ReqPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_Client3_ReqPoolCredit_Alloc_Upper
+#define IOAGR_SION_Client3_ReqPoolCredit_Alloc_Upper__IOAGR_SION_Client3_ReqPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOAGR_SION_Client3_ReqPoolCredit_Alloc_Upper__IOAGR_SION_Client3_ReqPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_Client3_DataPoolCredit_Alloc_Lower
+#define IOAGR_SION_Client3_DataPoolCredit_Alloc_Lower__IOAGR_SION_Client3_DataPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOAGR_SION_Client3_DataPoolCredit_Alloc_Lower__IOAGR_SION_Client3_DataPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_Client3_DataPoolCredit_Alloc_Upper
+#define IOAGR_SION_Client3_DataPoolCredit_Alloc_Upper__IOAGR_SION_Client3_DataPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOAGR_SION_Client3_DataPoolCredit_Alloc_Upper__IOAGR_SION_Client3_DataPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Lower
+#define IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Lower__IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Lower__IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Upper
+#define IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Upper__IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Upper__IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Lower
+#define IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Lower__IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Lower__SHIFT 0x0
+#define IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Lower__IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Lower_MASK 0xFFFFFFFFL
+//IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Upper
+#define IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Upper__IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Upper__SHIFT 0x0
+#define IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Upper__IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Upper_MASK 0xFFFFFFFFL
+//IOAGR_SION_LiveLock_WatchDog_Threshold
+#define IOAGR_SION_LiveLock_WatchDog_Threshold__IOAGR_SION_LiveLock_WatchDog_Threshold__SHIFT 0x0
+#define IOAGR_SION_LiveLock_WatchDog_Threshold__IOAGR_SION_LiveLock_WatchDog_Threshold_MASK 0x000000FFL
+
+
+// addressBlock: nbio_sst0_sst_core_sstcorecfg
+//SST_CORE0_SST_CLOCK_CTRL
+#define SST_CORE0_SST_CLOCK_CTRL__TXCLKGATEEn__SHIFT 0x0
+#define SST_CORE0_SST_CLOCK_CTRL__Reserved1__SHIFT 0x1
+#define SST_CORE0_SST_CLOCK_CTRL__PCTRL_IDLE_TIME__SHIFT 0x8
+#define SST_CORE0_SST_CLOCK_CTRL__RXCLKGATEEn__SHIFT 0x10
+#define SST_CORE0_SST_CLOCK_CTRL__Reserved0__SHIFT 0x11
+#define SST_CORE0_SST_CLOCK_CTRL__TXCLKGATEEn_MASK 0x00000001L
+#define SST_CORE0_SST_CLOCK_CTRL__Reserved1_MASK 0x000000FEL
+#define SST_CORE0_SST_CLOCK_CTRL__PCTRL_IDLE_TIME_MASK 0x0000FF00L
+#define SST_CORE0_SST_CLOCK_CTRL__RXCLKGATEEn_MASK 0x00010000L
+#define SST_CORE0_SST_CLOCK_CTRL__Reserved0_MASK 0xFFFE0000L
+//SST_CORE0_SST_ENABLE_CTRL
+#define SST_CORE0_SST_ENABLE_CTRL__SST_ENABLE__SHIFT 0x0
+#define SST_CORE0_SST_ENABLE_CTRL__Reserved0__SHIFT 0x1
+#define SST_CORE0_SST_ENABLE_CTRL__SST_RST_DONE__SHIFT 0x8
+#define SST_CORE0_SST_ENABLE_CTRL__Reserved1__SHIFT 0x9
+#define SST_CORE0_SST_ENABLE_CTRL__SST_ENABLE_MASK 0x00000001L
+#define SST_CORE0_SST_ENABLE_CTRL__Reserved0_MASK 0x000000FEL
+#define SST_CORE0_SST_ENABLE_CTRL__SST_RST_DONE_MASK 0x00000100L
+#define SST_CORE0_SST_ENABLE_CTRL__Reserved1_MASK 0xFFFFFE00L
+//SST_CORE0_SST_RSMU_HCID
+#define SST_CORE0_SST_RSMU_HCID__RSMU_HCID_HwRev__SHIFT 0x0
+#define SST_CORE0_SST_RSMU_HCID__RSMU_HCID_HwMinVer__SHIFT 0x6
+#define SST_CORE0_SST_RSMU_HCID__RSMU_HCID_HwMajVer__SHIFT 0xd
+#define SST_CORE0_SST_RSMU_HCID__RESERVED__SHIFT 0x14
+#define SST_CORE0_SST_RSMU_HCID__RSMU_HCID_HwRev_MASK 0x0000003FL
+#define SST_CORE0_SST_RSMU_HCID__RSMU_HCID_HwMinVer_MASK 0x00001FC0L
+#define SST_CORE0_SST_RSMU_HCID__RSMU_HCID_HwMajVer_MASK 0x000FE000L
+#define SST_CORE0_SST_RSMU_HCID__RESERVED_MASK 0xFFF00000L
+//SST_CORE0_SST_RSMU_SIID
+#define SST_CORE0_SST_RSMU_SIID__RSMU_SIID_SwIfRev__SHIFT 0x0
+#define SST_CORE0_SST_RSMU_SIID__RSMU_SIID_SwIfMinVer__SHIFT 0x6
+#define SST_CORE0_SST_RSMU_SIID__RSMU_SIID_SwIfMajVer__SHIFT 0xd
+#define SST_CORE0_SST_RSMU_SIID__RESERVED__SHIFT 0x14
+#define SST_CORE0_SST_RSMU_SIID__RSMU_SIID_SwIfRev_MASK 0x0000003FL
+#define SST_CORE0_SST_RSMU_SIID__RSMU_SIID_SwIfMinVer_MASK 0x00001FC0L
+#define SST_CORE0_SST_RSMU_SIID__RSMU_SIID_SwIfMajVer_MASK 0x000FE000L
+#define SST_CORE0_SST_RSMU_SIID__RESERVED_MASK 0xFFF00000L
+//SST_CORE0_SST_STATISTIC_0
+#define SST_CORE0_SST_STATISTIC_0__RdRspCnt__SHIFT 0x0
+#define SST_CORE0_SST_STATISTIC_0__WrRspCnt__SHIFT 0x10
+#define SST_CORE0_SST_STATISTIC_0__RdRspCnt_MASK 0x0000FFFFL
+#define SST_CORE0_SST_STATISTIC_0__WrRspCnt_MASK 0xFFFF0000L
+//SST_CORE0_SION_CFG_S0_REQ_BURSTTARGET_LO
+#define SST_CORE0_SION_CFG_S0_REQ_BURSTTARGET_LO__cfg_s0_src_Req_BurstTarget_lo__SHIFT 0x0
+#define SST_CORE0_SION_CFG_S0_REQ_BURSTTARGET_LO__cfg_s0_src_Req_BurstTarget_lo_MASK 0xFFFFFFFFL
+//SST_CORE0_SION_CFG_S0_REQ_BURSTTARGET_HI
+#define SST_CORE0_SION_CFG_S0_REQ_BURSTTARGET_HI__cfg_s0_src_Req_BurstTarget_hi__SHIFT 0x0
+#define SST_CORE0_SION_CFG_S0_REQ_BURSTTARGET_HI__cfg_s0_src_Req_BurstTarget_hi_MASK 0xFFFFFFFFL
+//SST_CORE0_SION_CFG_S0_RDRSP_BURSTTARGET_LO
+#define SST_CORE0_SION_CFG_S0_RDRSP_BURSTTARGET_LO__cfg_s0_src_RdRsp_BurstTarget_lo__SHIFT 0x0
+#define SST_CORE0_SION_CFG_S0_RDRSP_BURSTTARGET_LO__cfg_s0_src_RdRsp_BurstTarget_lo_MASK 0xFFFFFFFFL
+//SST_CORE0_SION_CFG_S0_RDRSP_BURSTTARGET_HI
+#define SST_CORE0_SION_CFG_S0_RDRSP_BURSTTARGET_HI__cfg_s0_src_RdRsp_BurstTarget_hi__SHIFT 0x0
+#define SST_CORE0_SION_CFG_S0_RDRSP_BURSTTARGET_HI__cfg_s0_src_RdRsp_BurstTarget_hi_MASK 0xFFFFFFFFL
+//SST_CORE0_SION_CFG_S0_WRRSP_BURSTTARGET_LO
+#define SST_CORE0_SION_CFG_S0_WRRSP_BURSTTARGET_LO__cfg_s0_src_WrRsp_BurstTarget_lo__SHIFT 0x0
+#define SST_CORE0_SION_CFG_S0_WRRSP_BURSTTARGET_LO__cfg_s0_src_WrRsp_BurstTarget_lo_MASK 0xFFFFFFFFL
+//SST_CORE0_SION_CFG_S0_WRRSP_BURSTTARGET_HI
+#define SST_CORE0_SION_CFG_S0_WRRSP_BURSTTARGET_HI__cfg_s0_src_WrRsp_BurstTarget_hi__SHIFT 0x0
+#define SST_CORE0_SION_CFG_S0_WRRSP_BURSTTARGET_HI__cfg_s0_src_WrRsp_BurstTarget_hi_MASK 0xFFFFFFFFL
+//SST_CORE0_SION_CFG_S0_REQ_TIMESLOT_LO
+#define SST_CORE0_SION_CFG_S0_REQ_TIMESLOT_LO__cfg_s0_src_Req_TimeSlot_lo__SHIFT 0x0
+#define SST_CORE0_SION_CFG_S0_REQ_TIMESLOT_LO__cfg_s0_src_Req_TimeSlot_lo_MASK 0xFFFFFFFFL
+//SST_CORE0_SION_CFG_S0_REQ_TIMESLOT_HI
+#define SST_CORE0_SION_CFG_S0_REQ_TIMESLOT_HI__cfg_s0_src_Req_TimeSlot_hi__SHIFT 0x0
+#define SST_CORE0_SION_CFG_S0_REQ_TIMESLOT_HI__cfg_s0_src_Req_TimeSlot_hi_MASK 0xFFFFFFFFL
+//SST_CORE0_SION_CFG_S0_RDRSP_TIMESLOT_LO
+#define SST_CORE0_SION_CFG_S0_RDRSP_TIMESLOT_LO__cfg_s0_src_RdRsp_TimeSlot_lo__SHIFT 0x0
+#define SST_CORE0_SION_CFG_S0_RDRSP_TIMESLOT_LO__cfg_s0_src_RdRsp_TimeSlot_lo_MASK 0xFFFFFFFFL
+//SST_CORE0_SION_CFG_S0_RDRSP_TIMESLOT_HI
+#define SST_CORE0_SION_CFG_S0_RDRSP_TIMESLOT_HI__cfg_s0_src_RdRsp_TimeSlot_hi__SHIFT 0x0
+#define SST_CORE0_SION_CFG_S0_RDRSP_TIMESLOT_HI__cfg_s0_src_RdRsp_TimeSlot_hi_MASK 0xFFFFFFFFL
+//SST_CORE0_SION_CFG_S0_WRRSP_TIMESLOT_LO
+#define SST_CORE0_SION_CFG_S0_WRRSP_TIMESLOT_LO__cfg_s0_src_WrRsp_TimeSlot_lo__SHIFT 0x0
+#define SST_CORE0_SION_CFG_S0_WRRSP_TIMESLOT_LO__cfg_s0_src_WrRsp_TimeSlot_lo_MASK 0xFFFFFFFFL
+//SST_CORE0_SION_CFG_S0_WRRSP_TIMESLOT_HI
+#define SST_CORE0_SION_CFG_S0_WRRSP_TIMESLOT_HI__cfg_s0_src_WrRsp_TimeSlot_hi__SHIFT 0x0
+#define SST_CORE0_SION_CFG_S0_WRRSP_TIMESLOT_HI__cfg_s0_src_WrRsp_TimeSlot_hi_MASK 0xFFFFFFFFL
+//SST_CORE0_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS
+#define SST_CORE0_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS__CFG_CG_OFF_HYSTERESIS__SHIFT 0x0
+#define SST_CORE0_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS__Reserved__SHIFT 0x8
+#define SST_CORE0_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS__CFG_CG_OFF_HYSTERESIS_MASK 0x000000FFL
+#define SST_CORE0_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS__Reserved_MASK 0xFFFFFF00L
+//SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK
+#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT 0x0
+#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT 0x1
+#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT 0x2
+#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT 0x3
+#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT 0x4
+#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT 0x5
+#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT 0x6
+#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT 0x7
+#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT 0x8
+#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT 0x9
+#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__Reserved1__SHIFT 0xa
+#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__Reserved0__SHIFT 0x1a
+#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_MASK 0x00000001L
+#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_MASK 0x00000002L
+#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_MASK 0x00000004L
+#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_MASK 0x00000008L
+#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_MASK 0x00000010L
+#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_MASK 0x00000020L
+#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_MASK 0x00000040L
+#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_MASK 0x00000080L
+#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_MASK 0x00000100L
+#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_MASK 0x00000200L
+#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__Reserved1_MASK 0x0000FC00L
+#define SST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__Reserved0_MASK 0xFC000000L
+//SST_CORE0_CFG_SST_ReqPoolCredit_Alloc_LO
+#define SST_CORE0_CFG_SST_ReqPoolCredit_Alloc_LO__CFG_SST_ReqPoolCredit_Alloc_LO__SHIFT 0x0
+#define SST_CORE0_CFG_SST_ReqPoolCredit_Alloc_LO__CFG_SST_ReqPoolCredit_Alloc_LO_MASK 0xFFFFFFFFL
+//SST_CORE0_CFG_SST_ReqPoolCredit_Alloc_HI
+#define SST_CORE0_CFG_SST_ReqPoolCredit_Alloc_HI__CFG_SST_ReqPoolCredit_Alloc_HI__SHIFT 0x0
+#define SST_CORE0_CFG_SST_ReqPoolCredit_Alloc_HI__CFG_SST_ReqPoolCredit_Alloc_HI_MASK 0xFFFFFFFFL
+//SST_CORE0_CFG_SST_DataPoolCredit_Alloc_LO
+#define SST_CORE0_CFG_SST_DataPoolCredit_Alloc_LO__CFG_SST_DataPoolCredit_Alloc_LO__SHIFT 0x0
+#define SST_CORE0_CFG_SST_DataPoolCredit_Alloc_LO__CFG_SST_DataPoolCredit_Alloc_LO_MASK 0xFFFFFFFFL
+//SST_CORE0_CFG_SST_DataPoolCredit_Alloc_HI
+#define SST_CORE0_CFG_SST_DataPoolCredit_Alloc_HI__CFG_SST_DataPoolCredit_Alloc_HI__SHIFT 0x0
+#define SST_CORE0_CFG_SST_DataPoolCredit_Alloc_HI__CFG_SST_DataPoolCredit_Alloc_HI_MASK 0xFFFFFFFFL
+//SST_CORE0_CFG_SST_RdRspPoolCredit_Alloc_LO
+#define SST_CORE0_CFG_SST_RdRspPoolCredit_Alloc_LO__CFG_SST_RdRspPoolCredit_Alloc_LO__SHIFT 0x0
+#define SST_CORE0_CFG_SST_RdRspPoolCredit_Alloc_LO__CFG_SST_RdRspPoolCredit_Alloc_LO_MASK 0xFFFFFFFFL
+//SST_CORE0_CFG_SST_RdRspPoolCredit_Alloc_HI
+#define SST_CORE0_CFG_SST_RdRspPoolCredit_Alloc_HI__CFG_SST_RdRspPoolCredit_Alloc_HI__SHIFT 0x0
+#define SST_CORE0_CFG_SST_RdRspPoolCredit_Alloc_HI__CFG_SST_RdRspPoolCredit_Alloc_HI_MASK 0xFFFFFFFFL
+//SST_CORE0_CFG_SST_WrRspPoolCredit_Alloc_LO
+#define SST_CORE0_CFG_SST_WrRspPoolCredit_Alloc_LO__CFG_SST_WrRspPoolCredit_Alloc_LO__SHIFT 0x0
+#define SST_CORE0_CFG_SST_WrRspPoolCredit_Alloc_LO__CFG_SST_WrRspPoolCredit_Alloc_LO_MASK 0xFFFFFFFFL
+//SST_CORE0_CFG_SST_WrRspPoolCredit_Alloc_HI
+#define SST_CORE0_CFG_SST_WrRspPoolCredit_Alloc_HI__CFG_SST_WrRspPoolCredit_Alloc_HI__SHIFT 0x0
+#define SST_CORE0_CFG_SST_WrRspPoolCredit_Alloc_HI__CFG_SST_WrRspPoolCredit_Alloc_HI_MASK 0xFFFFFFFFL
+//SST_CORE0_SST_BACKDOOR0
+#define SST_CORE0_SST_BACKDOOR0__BACKDOOR_CODE__SHIFT 0x0
+#define SST_CORE0_SST_BACKDOOR0__BACKDOOR_CODE_MASK 0xFFFFFFFFL
+//SST_CORE0_SST_BACKDOOR1
+#define SST_CORE0_SST_BACKDOOR1__BACKDOOR_CFG0__SHIFT 0x0
+#define SST_CORE0_SST_BACKDOOR1__BACKDOOR_CFG0_MASK 0xFFFFFFFFL
+//SST_CORE0_SST_BACKDOOR2
+#define SST_CORE0_SST_BACKDOOR2__BACKDOOR_CHK0__SHIFT 0x0
+#define SST_CORE0_SST_BACKDOOR2__BACKDOOR_CHK0_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_sst1_sst_core_sstcorecfg
+//SST_CORE1_SST_CLOCK_CTRL
+#define SST_CORE1_SST_CLOCK_CTRL__TXCLKGATEEn__SHIFT 0x0
+#define SST_CORE1_SST_CLOCK_CTRL__Reserved1__SHIFT 0x1
+#define SST_CORE1_SST_CLOCK_CTRL__PCTRL_IDLE_TIME__SHIFT 0x8
+#define SST_CORE1_SST_CLOCK_CTRL__RXCLKGATEEn__SHIFT 0x10
+#define SST_CORE1_SST_CLOCK_CTRL__Reserved0__SHIFT 0x11
+#define SST_CORE1_SST_CLOCK_CTRL__TXCLKGATEEn_MASK 0x00000001L
+#define SST_CORE1_SST_CLOCK_CTRL__Reserved1_MASK 0x000000FEL
+#define SST_CORE1_SST_CLOCK_CTRL__PCTRL_IDLE_TIME_MASK 0x0000FF00L
+#define SST_CORE1_SST_CLOCK_CTRL__RXCLKGATEEn_MASK 0x00010000L
+#define SST_CORE1_SST_CLOCK_CTRL__Reserved0_MASK 0xFFFE0000L
+//SST_CORE1_SST_ENABLE_CTRL
+#define SST_CORE1_SST_ENABLE_CTRL__SST_ENABLE__SHIFT 0x0
+#define SST_CORE1_SST_ENABLE_CTRL__Reserved0__SHIFT 0x1
+#define SST_CORE1_SST_ENABLE_CTRL__SST_RST_DONE__SHIFT 0x8
+#define SST_CORE1_SST_ENABLE_CTRL__Reserved1__SHIFT 0x9
+#define SST_CORE1_SST_ENABLE_CTRL__SST_ENABLE_MASK 0x00000001L
+#define SST_CORE1_SST_ENABLE_CTRL__Reserved0_MASK 0x000000FEL
+#define SST_CORE1_SST_ENABLE_CTRL__SST_RST_DONE_MASK 0x00000100L
+#define SST_CORE1_SST_ENABLE_CTRL__Reserved1_MASK 0xFFFFFE00L
+//SST_CORE1_SST_RSMU_HCID
+#define SST_CORE1_SST_RSMU_HCID__RSMU_HCID_HwRev__SHIFT 0x0
+#define SST_CORE1_SST_RSMU_HCID__RSMU_HCID_HwMinVer__SHIFT 0x6
+#define SST_CORE1_SST_RSMU_HCID__RSMU_HCID_HwMajVer__SHIFT 0xd
+#define SST_CORE1_SST_RSMU_HCID__RESERVED__SHIFT 0x14
+#define SST_CORE1_SST_RSMU_HCID__RSMU_HCID_HwRev_MASK 0x0000003FL
+#define SST_CORE1_SST_RSMU_HCID__RSMU_HCID_HwMinVer_MASK 0x00001FC0L
+#define SST_CORE1_SST_RSMU_HCID__RSMU_HCID_HwMajVer_MASK 0x000FE000L
+#define SST_CORE1_SST_RSMU_HCID__RESERVED_MASK 0xFFF00000L
+//SST_CORE1_SST_RSMU_SIID
+#define SST_CORE1_SST_RSMU_SIID__RSMU_SIID_SwIfRev__SHIFT 0x0
+#define SST_CORE1_SST_RSMU_SIID__RSMU_SIID_SwIfMinVer__SHIFT 0x6
+#define SST_CORE1_SST_RSMU_SIID__RSMU_SIID_SwIfMajVer__SHIFT 0xd
+#define SST_CORE1_SST_RSMU_SIID__RESERVED__SHIFT 0x14
+#define SST_CORE1_SST_RSMU_SIID__RSMU_SIID_SwIfRev_MASK 0x0000003FL
+#define SST_CORE1_SST_RSMU_SIID__RSMU_SIID_SwIfMinVer_MASK 0x00001FC0L
+#define SST_CORE1_SST_RSMU_SIID__RSMU_SIID_SwIfMajVer_MASK 0x000FE000L
+#define SST_CORE1_SST_RSMU_SIID__RESERVED_MASK 0xFFF00000L
+//SST_CORE1_SST_STATISTIC_0
+#define SST_CORE1_SST_STATISTIC_0__RdRspCnt__SHIFT 0x0
+#define SST_CORE1_SST_STATISTIC_0__WrRspCnt__SHIFT 0x10
+#define SST_CORE1_SST_STATISTIC_0__RdRspCnt_MASK 0x0000FFFFL
+#define SST_CORE1_SST_STATISTIC_0__WrRspCnt_MASK 0xFFFF0000L
+//SST_CORE1_SION_CFG_S0_REQ_BURSTTARGET_LO
+#define SST_CORE1_SION_CFG_S0_REQ_BURSTTARGET_LO__cfg_s0_src_Req_BurstTarget_lo__SHIFT 0x0
+#define SST_CORE1_SION_CFG_S0_REQ_BURSTTARGET_LO__cfg_s0_src_Req_BurstTarget_lo_MASK 0xFFFFFFFFL
+//SST_CORE1_SION_CFG_S0_REQ_BURSTTARGET_HI
+#define SST_CORE1_SION_CFG_S0_REQ_BURSTTARGET_HI__cfg_s0_src_Req_BurstTarget_hi__SHIFT 0x0
+#define SST_CORE1_SION_CFG_S0_REQ_BURSTTARGET_HI__cfg_s0_src_Req_BurstTarget_hi_MASK 0xFFFFFFFFL
+//SST_CORE1_SION_CFG_S0_RDRSP_BURSTTARGET_LO
+#define SST_CORE1_SION_CFG_S0_RDRSP_BURSTTARGET_LO__cfg_s0_src_RdRsp_BurstTarget_lo__SHIFT 0x0
+#define SST_CORE1_SION_CFG_S0_RDRSP_BURSTTARGET_LO__cfg_s0_src_RdRsp_BurstTarget_lo_MASK 0xFFFFFFFFL
+//SST_CORE1_SION_CFG_S0_RDRSP_BURSTTARGET_HI
+#define SST_CORE1_SION_CFG_S0_RDRSP_BURSTTARGET_HI__cfg_s0_src_RdRsp_BurstTarget_hi__SHIFT 0x0
+#define SST_CORE1_SION_CFG_S0_RDRSP_BURSTTARGET_HI__cfg_s0_src_RdRsp_BurstTarget_hi_MASK 0xFFFFFFFFL
+//SST_CORE1_SION_CFG_S0_WRRSP_BURSTTARGET_LO
+#define SST_CORE1_SION_CFG_S0_WRRSP_BURSTTARGET_LO__cfg_s0_src_WrRsp_BurstTarget_lo__SHIFT 0x0
+#define SST_CORE1_SION_CFG_S0_WRRSP_BURSTTARGET_LO__cfg_s0_src_WrRsp_BurstTarget_lo_MASK 0xFFFFFFFFL
+//SST_CORE1_SION_CFG_S0_WRRSP_BURSTTARGET_HI
+#define SST_CORE1_SION_CFG_S0_WRRSP_BURSTTARGET_HI__cfg_s0_src_WrRsp_BurstTarget_hi__SHIFT 0x0
+#define SST_CORE1_SION_CFG_S0_WRRSP_BURSTTARGET_HI__cfg_s0_src_WrRsp_BurstTarget_hi_MASK 0xFFFFFFFFL
+//SST_CORE1_SION_CFG_S0_REQ_TIMESLOT_LO
+#define SST_CORE1_SION_CFG_S0_REQ_TIMESLOT_LO__cfg_s0_src_Req_TimeSlot_lo__SHIFT 0x0
+#define SST_CORE1_SION_CFG_S0_REQ_TIMESLOT_LO__cfg_s0_src_Req_TimeSlot_lo_MASK 0xFFFFFFFFL
+//SST_CORE1_SION_CFG_S0_REQ_TIMESLOT_HI
+#define SST_CORE1_SION_CFG_S0_REQ_TIMESLOT_HI__cfg_s0_src_Req_TimeSlot_hi__SHIFT 0x0
+#define SST_CORE1_SION_CFG_S0_REQ_TIMESLOT_HI__cfg_s0_src_Req_TimeSlot_hi_MASK 0xFFFFFFFFL
+//SST_CORE1_SION_CFG_S0_RDRSP_TIMESLOT_LO
+#define SST_CORE1_SION_CFG_S0_RDRSP_TIMESLOT_LO__cfg_s0_src_RdRsp_TimeSlot_lo__SHIFT 0x0
+#define SST_CORE1_SION_CFG_S0_RDRSP_TIMESLOT_LO__cfg_s0_src_RdRsp_TimeSlot_lo_MASK 0xFFFFFFFFL
+//SST_CORE1_SION_CFG_S0_RDRSP_TIMESLOT_HI
+#define SST_CORE1_SION_CFG_S0_RDRSP_TIMESLOT_HI__cfg_s0_src_RdRsp_TimeSlot_hi__SHIFT 0x0
+#define SST_CORE1_SION_CFG_S0_RDRSP_TIMESLOT_HI__cfg_s0_src_RdRsp_TimeSlot_hi_MASK 0xFFFFFFFFL
+//SST_CORE1_SION_CFG_S0_WRRSP_TIMESLOT_LO
+#define SST_CORE1_SION_CFG_S0_WRRSP_TIMESLOT_LO__cfg_s0_src_WrRsp_TimeSlot_lo__SHIFT 0x0
+#define SST_CORE1_SION_CFG_S0_WRRSP_TIMESLOT_LO__cfg_s0_src_WrRsp_TimeSlot_lo_MASK 0xFFFFFFFFL
+//SST_CORE1_SION_CFG_S0_WRRSP_TIMESLOT_HI
+#define SST_CORE1_SION_CFG_S0_WRRSP_TIMESLOT_HI__cfg_s0_src_WrRsp_TimeSlot_hi__SHIFT 0x0
+#define SST_CORE1_SION_CFG_S0_WRRSP_TIMESLOT_HI__cfg_s0_src_WrRsp_TimeSlot_hi_MASK 0xFFFFFFFFL
+//SST_CORE1_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS
+#define SST_CORE1_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS__CFG_CG_OFF_HYSTERESIS__SHIFT 0x0
+#define SST_CORE1_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS__Reserved__SHIFT 0x8
+#define SST_CORE1_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS__CFG_CG_OFF_HYSTERESIS_MASK 0x000000FFL
+#define SST_CORE1_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS__Reserved_MASK 0xFFFFFF00L
+//SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK
+#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT 0x0
+#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT 0x1
+#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT 0x2
+#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT 0x3
+#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT 0x4
+#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT 0x5
+#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT 0x6
+#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT 0x7
+#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT 0x8
+#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT 0x9
+#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__Reserved1__SHIFT 0xa
+#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__Reserved0__SHIFT 0x1a
+#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_MASK 0x00000001L
+#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_MASK 0x00000002L
+#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_MASK 0x00000004L
+#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_MASK 0x00000008L
+#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_MASK 0x00000010L
+#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_MASK 0x00000020L
+#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_MASK 0x00000040L
+#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_MASK 0x00000080L
+#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_MASK 0x00000100L
+#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__CFG_SSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_MASK 0x00000200L
+#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__Reserved1_MASK 0x0000FC00L
+#define SST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK__Reserved0_MASK 0xFC000000L
+//SST_CORE1_CFG_SST_ReqPoolCredit_Alloc_LO
+#define SST_CORE1_CFG_SST_ReqPoolCredit_Alloc_LO__CFG_SST_ReqPoolCredit_Alloc_LO__SHIFT 0x0
+#define SST_CORE1_CFG_SST_ReqPoolCredit_Alloc_LO__CFG_SST_ReqPoolCredit_Alloc_LO_MASK 0xFFFFFFFFL
+//SST_CORE1_CFG_SST_ReqPoolCredit_Alloc_HI
+#define SST_CORE1_CFG_SST_ReqPoolCredit_Alloc_HI__CFG_SST_ReqPoolCredit_Alloc_HI__SHIFT 0x0
+#define SST_CORE1_CFG_SST_ReqPoolCredit_Alloc_HI__CFG_SST_ReqPoolCredit_Alloc_HI_MASK 0xFFFFFFFFL
+//SST_CORE1_CFG_SST_DataPoolCredit_Alloc_LO
+#define SST_CORE1_CFG_SST_DataPoolCredit_Alloc_LO__CFG_SST_DataPoolCredit_Alloc_LO__SHIFT 0x0
+#define SST_CORE1_CFG_SST_DataPoolCredit_Alloc_LO__CFG_SST_DataPoolCredit_Alloc_LO_MASK 0xFFFFFFFFL
+//SST_CORE1_CFG_SST_DataPoolCredit_Alloc_HI
+#define SST_CORE1_CFG_SST_DataPoolCredit_Alloc_HI__CFG_SST_DataPoolCredit_Alloc_HI__SHIFT 0x0
+#define SST_CORE1_CFG_SST_DataPoolCredit_Alloc_HI__CFG_SST_DataPoolCredit_Alloc_HI_MASK 0xFFFFFFFFL
+//SST_CORE1_CFG_SST_RdRspPoolCredit_Alloc_LO
+#define SST_CORE1_CFG_SST_RdRspPoolCredit_Alloc_LO__CFG_SST_RdRspPoolCredit_Alloc_LO__SHIFT 0x0
+#define SST_CORE1_CFG_SST_RdRspPoolCredit_Alloc_LO__CFG_SST_RdRspPoolCredit_Alloc_LO_MASK 0xFFFFFFFFL
+//SST_CORE1_CFG_SST_RdRspPoolCredit_Alloc_HI
+#define SST_CORE1_CFG_SST_RdRspPoolCredit_Alloc_HI__CFG_SST_RdRspPoolCredit_Alloc_HI__SHIFT 0x0
+#define SST_CORE1_CFG_SST_RdRspPoolCredit_Alloc_HI__CFG_SST_RdRspPoolCredit_Alloc_HI_MASK 0xFFFFFFFFL
+//SST_CORE1_CFG_SST_WrRspPoolCredit_Alloc_LO
+#define SST_CORE1_CFG_SST_WrRspPoolCredit_Alloc_LO__CFG_SST_WrRspPoolCredit_Alloc_LO__SHIFT 0x0
+#define SST_CORE1_CFG_SST_WrRspPoolCredit_Alloc_LO__CFG_SST_WrRspPoolCredit_Alloc_LO_MASK 0xFFFFFFFFL
+//SST_CORE1_CFG_SST_WrRspPoolCredit_Alloc_HI
+#define SST_CORE1_CFG_SST_WrRspPoolCredit_Alloc_HI__CFG_SST_WrRspPoolCredit_Alloc_HI__SHIFT 0x0
+#define SST_CORE1_CFG_SST_WrRspPoolCredit_Alloc_HI__CFG_SST_WrRspPoolCredit_Alloc_HI_MASK 0xFFFFFFFFL
+//SST_CORE1_SST_BACKDOOR0
+#define SST_CORE1_SST_BACKDOOR0__BACKDOOR_CODE__SHIFT 0x0
+#define SST_CORE1_SST_BACKDOOR0__BACKDOOR_CODE_MASK 0xFFFFFFFFL
+//SST_CORE1_SST_BACKDOOR1
+#define SST_CORE1_SST_BACKDOOR1__BACKDOOR_CFG0__SHIFT 0x0
+#define SST_CORE1_SST_BACKDOOR1__BACKDOOR_CFG0_MASK 0xFFFFFFFFL
+//SST_CORE1_SST_BACKDOOR2
+#define SST_CORE1_SST_BACKDOOR2__BACKDOOR_CHK0__SHIFT 0x0
+#define SST_CORE1_SST_BACKDOOR2__BACKDOOR_CHK0_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_iohub_iommu_l2mmio_l2mmiocfg
+//IOMMU_MMIO_DEVTBL_BASE_0
+#define IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE__SHIFT 0x0
+#define IOMMU_MMIO_DEVTBL_BASE_0__Reserved1__SHIFT 0x9
+#define IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_BASE_LO__SHIFT 0xc
+#define IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE_MASK 0x000001FFL
+#define IOMMU_MMIO_DEVTBL_BASE_0__Reserved1_MASK 0x00000E00L
+#define IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_BASE_LO_MASK 0xFFFFF000L
+//IOMMU_MMIO_DEVTBL_BASE_1
+#define IOMMU_MMIO_DEVTBL_BASE_1__DEV_TBL_BASE_HI__SHIFT 0x0
+#define IOMMU_MMIO_DEVTBL_BASE_1__Reserved0__SHIFT 0x14
+#define IOMMU_MMIO_DEVTBL_BASE_1__DEV_TBL_BASE_HI_MASK 0x000FFFFFL
+#define IOMMU_MMIO_DEVTBL_BASE_1__Reserved0_MASK 0xFFF00000L
+//IOMMU_MMIO_CMD_BASE_0
+#define IOMMU_MMIO_CMD_BASE_0__Reserved1__SHIFT 0x0
+#define IOMMU_MMIO_CMD_BASE_0__COM_BASE_LO__SHIFT 0xc
+#define IOMMU_MMIO_CMD_BASE_0__Reserved1_MASK 0x00000FFFL
+#define IOMMU_MMIO_CMD_BASE_0__COM_BASE_LO_MASK 0xFFFFF000L
+//IOMMU_MMIO_CMD_BASE_1
+#define IOMMU_MMIO_CMD_BASE_1__COM_BASE_HI__SHIFT 0x0
+#define IOMMU_MMIO_CMD_BASE_1__Reserved1__SHIFT 0x14
+#define IOMMU_MMIO_CMD_BASE_1__COM_LEN__SHIFT 0x18
+#define IOMMU_MMIO_CMD_BASE_1__Reserved0__SHIFT 0x1c
+#define IOMMU_MMIO_CMD_BASE_1__COM_BASE_HI_MASK 0x000FFFFFL
+#define IOMMU_MMIO_CMD_BASE_1__Reserved1_MASK 0x00F00000L
+#define IOMMU_MMIO_CMD_BASE_1__COM_LEN_MASK 0x0F000000L
+#define IOMMU_MMIO_CMD_BASE_1__Reserved0_MASK 0xF0000000L
+//IOMMU_MMIO_EVENT_BASE_0
+#define IOMMU_MMIO_EVENT_BASE_0__Reserved1__SHIFT 0x0
+#define IOMMU_MMIO_EVENT_BASE_0__EVENT_BASE_LO__SHIFT 0xc
+#define IOMMU_MMIO_EVENT_BASE_0__Reserved1_MASK 0x00000FFFL
+#define IOMMU_MMIO_EVENT_BASE_0__EVENT_BASE_LO_MASK 0xFFFFF000L
+//IOMMU_MMIO_EVENT_BASE_1
+#define IOMMU_MMIO_EVENT_BASE_1__EVENT_BASE_HI__SHIFT 0x0
+#define IOMMU_MMIO_EVENT_BASE_1__Reserved1__SHIFT 0x14
+#define IOMMU_MMIO_EVENT_BASE_1__EVENT_LEN__SHIFT 0x18
+#define IOMMU_MMIO_EVENT_BASE_1__Reserved0__SHIFT 0x1c
+#define IOMMU_MMIO_EVENT_BASE_1__EVENT_BASE_HI_MASK 0x000FFFFFL
+#define IOMMU_MMIO_EVENT_BASE_1__Reserved1_MASK 0x00F00000L
+#define IOMMU_MMIO_EVENT_BASE_1__EVENT_LEN_MASK 0x0F000000L
+#define IOMMU_MMIO_EVENT_BASE_1__Reserved0_MASK 0xF0000000L
+//IOMMU_MMIO_CNTRL_0
+#define IOMMU_MMIO_CNTRL_0__IOMMU_EN__SHIFT 0x0
+#define IOMMU_MMIO_CNTRL_0__HT_TUN_EN__SHIFT 0x1
+#define IOMMU_MMIO_CNTRL_0__EVENT_LOG_EN__SHIFT 0x2
+#define IOMMU_MMIO_CNTRL_0__EVENT_INT_EN__SHIFT 0x3
+#define IOMMU_MMIO_CNTRL_0__COM_WAIT_INTEN__SHIFT 0x4
+#define IOMMU_MMIO_CNTRL_0__INV_TIMEOUT__SHIFT 0x5
+#define IOMMU_MMIO_CNTRL_0__PASS_PW__SHIFT 0x8
+#define IOMMU_MMIO_CNTRL_0__RES_PASS_PW__SHIFT 0x9
+#define IOMMU_MMIO_CNTRL_0__COHERENT__SHIFT 0xa
+#define IOMMU_MMIO_CNTRL_0__ISOC__SHIFT 0xb
+#define IOMMU_MMIO_CNTRL_0__CMD_BUF_EN__SHIFT 0xc
+#define IOMMU_MMIO_CNTRL_0__PPR_LOG_EN__SHIFT 0xd
+#define IOMMU_MMIO_CNTRL_0__PPR_INT_EN__SHIFT 0xe
+#define IOMMU_MMIO_CNTRL_0__PPR_EN__SHIFT 0xf
+#define IOMMU_MMIO_CNTRL_0__GT_EN__SHIFT 0x10
+#define IOMMU_MMIO_CNTRL_0__GA_EN__SHIFT 0x11
+#define IOMMU_MMIO_CNTRL_0__TLPT__SHIFT 0x12
+#define IOMMU_MMIO_CNTRL_0__SMIF_EN__SHIFT 0x16
+#define IOMMU_MMIO_CNTRL_0__SMIF_LOG_EN__SHIFT 0x18
+#define IOMMU_MMIO_CNTRL_0__GAM_EN__SHIFT 0x19
+#define IOMMU_MMIO_CNTRL_0__GA_LOG_EN__SHIFT 0x1c
+#define IOMMU_MMIO_CNTRL_0__GA_INT_EN__SHIFT 0x1d
+#define IOMMU_MMIO_CNTRL_0__PPRQ__SHIFT 0x1e
+#define IOMMU_MMIO_CNTRL_0__IOMMU_EN_MASK 0x00000001L
+#define IOMMU_MMIO_CNTRL_0__HT_TUN_EN_MASK 0x00000002L
+#define IOMMU_MMIO_CNTRL_0__EVENT_LOG_EN_MASK 0x00000004L
+#define IOMMU_MMIO_CNTRL_0__EVENT_INT_EN_MASK 0x00000008L
+#define IOMMU_MMIO_CNTRL_0__COM_WAIT_INTEN_MASK 0x00000010L
+#define IOMMU_MMIO_CNTRL_0__INV_TIMEOUT_MASK 0x000000E0L
+#define IOMMU_MMIO_CNTRL_0__PASS_PW_MASK 0x00000100L
+#define IOMMU_MMIO_CNTRL_0__RES_PASS_PW_MASK 0x00000200L
+#define IOMMU_MMIO_CNTRL_0__COHERENT_MASK 0x00000400L
+#define IOMMU_MMIO_CNTRL_0__ISOC_MASK 0x00000800L
+#define IOMMU_MMIO_CNTRL_0__CMD_BUF_EN_MASK 0x00001000L
+#define IOMMU_MMIO_CNTRL_0__PPR_LOG_EN_MASK 0x00002000L
+#define IOMMU_MMIO_CNTRL_0__PPR_INT_EN_MASK 0x00004000L
+#define IOMMU_MMIO_CNTRL_0__PPR_EN_MASK 0x00008000L
+#define IOMMU_MMIO_CNTRL_0__GT_EN_MASK 0x00010000L
+#define IOMMU_MMIO_CNTRL_0__GA_EN_MASK 0x00020000L
+#define IOMMU_MMIO_CNTRL_0__TLPT_MASK 0x003C0000L
+#define IOMMU_MMIO_CNTRL_0__SMIF_EN_MASK 0x00400000L
+#define IOMMU_MMIO_CNTRL_0__SMIF_LOG_EN_MASK 0x01000000L
+#define IOMMU_MMIO_CNTRL_0__GAM_EN_MASK 0x0E000000L
+#define IOMMU_MMIO_CNTRL_0__GA_LOG_EN_MASK 0x10000000L
+#define IOMMU_MMIO_CNTRL_0__GA_INT_EN_MASK 0x20000000L
+#define IOMMU_MMIO_CNTRL_0__PPRQ_MASK 0xC0000000L
+//IOMMU_MMIO_CNTRL_1
+#define IOMMU_MMIO_CNTRL_1__EVENTQ__SHIFT 0x0
+#define IOMMU_MMIO_CNTRL_1__DTE_SEG_EN__SHIFT 0x2
+#define IOMMU_MMIO_CNTRL_1__Reserved1__SHIFT 0x4
+#define IOMMU_MMIO_CNTRL_1__PRIV_ABORT_EN__SHIFT 0x5
+#define IOMMU_MMIO_CNTRL_1__PPR_Auto_resp_en__SHIFT 0x7
+#define IOMMU_MMIO_CNTRL_1__MARC_en__SHIFT 0x8
+#define IOMMU_MMIO_CNTRL_1__Block_StopMark_En__SHIFT 0x9
+#define IOMMU_MMIO_CNTRL_1__PPR_Auto_resp_AON__SHIFT 0xa
+#define IOMMU_MMIO_CNTRL_1__DVM_DOMAIN_PNE__SHIFT 0xb
+#define IOMMU_MMIO_CNTRL_1__DVM_ERR_EN__SHIFT 0xc
+#define IOMMU_MMIO_CNTRL_1__EPH_EN__SHIFT 0xd
+#define IOMMU_MMIO_CNTRL_1__HW_Prefetch_AD__SHIFT 0xe
+#define IOMMU_MMIO_CNTRL_1__V2_HD_Dis__SHIFT 0x10
+#define IOMMU_MMIO_CNTRL_1__Reserved0__SHIFT 0x11
+#define IOMMU_MMIO_CNTRL_1__EVENTQ_MASK 0x00000003L
+#define IOMMU_MMIO_CNTRL_1__DTE_SEG_EN_MASK 0x0000000CL
+#define IOMMU_MMIO_CNTRL_1__Reserved1_MASK 0x00000010L
+#define IOMMU_MMIO_CNTRL_1__PRIV_ABORT_EN_MASK 0x00000060L
+#define IOMMU_MMIO_CNTRL_1__PPR_Auto_resp_en_MASK 0x00000080L
+#define IOMMU_MMIO_CNTRL_1__MARC_en_MASK 0x00000100L
+#define IOMMU_MMIO_CNTRL_1__Block_StopMark_En_MASK 0x00000200L
+#define IOMMU_MMIO_CNTRL_1__PPR_Auto_resp_AON_MASK 0x00000400L
+#define IOMMU_MMIO_CNTRL_1__DVM_DOMAIN_PNE_MASK 0x00000800L
+#define IOMMU_MMIO_CNTRL_1__DVM_ERR_EN_MASK 0x00001000L
+#define IOMMU_MMIO_CNTRL_1__EPH_EN_MASK 0x00002000L
+#define IOMMU_MMIO_CNTRL_1__HW_Prefetch_AD_MASK 0x0000C000L
+#define IOMMU_MMIO_CNTRL_1__V2_HD_Dis_MASK 0x00010000L
+#define IOMMU_MMIO_CNTRL_1__Reserved0_MASK 0xFFFE0000L
+//IOMMU_MMIO_EXCL_BASE_0
+#define IOMMU_MMIO_EXCL_BASE_0__EX_EN__SHIFT 0x0
+#define IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW__SHIFT 0x1
+#define IOMMU_MMIO_EXCL_BASE_0__Reserved0__SHIFT 0x2
+#define IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO__SHIFT 0xc
+#define IOMMU_MMIO_EXCL_BASE_0__EX_EN_MASK 0x00000001L
+#define IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW_MASK 0x00000002L
+#define IOMMU_MMIO_EXCL_BASE_0__Reserved0_MASK 0x00000FFCL
+#define IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO_MASK 0xFFFFF000L
+//IOMMU_MMIO_EXCL_BASE_1
+#define IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI__SHIFT 0x0
+#define IOMMU_MMIO_EXCL_BASE_1__Reserved0__SHIFT 0x14
+#define IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI_MASK 0x000FFFFFL
+#define IOMMU_MMIO_EXCL_BASE_1__Reserved0_MASK 0xFFF00000L
+//IOMMU_MMIO_EXCL_LIM_0
+#define IOMMU_MMIO_EXCL_LIM_0__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO__SHIFT 0xc
+#define IOMMU_MMIO_EXCL_LIM_0__Reserved0_MASK 0x00000FFFL
+#define IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO_MASK 0xFFFFF000L
+//IOMMU_MMIO_EXCL_LIM_1
+#define IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI__SHIFT 0x0
+#define IOMMU_MMIO_EXCL_LIM_1__Reserved0__SHIFT 0x14
+#define IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI_MASK 0x000FFFFFL
+#define IOMMU_MMIO_EXCL_LIM_1__Reserved0_MASK 0xFFF00000L
+//IOMMU_MMIO_EFR_0
+#define IOMMU_MMIO_EFR_0__PREF_SUP__SHIFT 0x0
+#define IOMMU_MMIO_EFR_0__PPR_SUP__SHIFT 0x1
+#define IOMMU_MMIO_EFR_0__XT_SUP__SHIFT 0x2
+#define IOMMU_MMIO_EFR_0__NX_SUP__SHIFT 0x3
+#define IOMMU_MMIO_EFR_0__GT_SUP__SHIFT 0x4
+#define IOMMU_MMIO_EFR_0__Reserved__SHIFT 0x5
+#define IOMMU_MMIO_EFR_0__IA_SUP__SHIFT 0x6
+#define IOMMU_MMIO_EFR_0__GA_SUP__SHIFT 0x7
+#define IOMMU_MMIO_EFR_0__HE_SUP__SHIFT 0x8
+#define IOMMU_MMIO_EFR_0__PC_SUP__SHIFT 0x9
+#define IOMMU_MMIO_EFR_0__HATS__SHIFT 0xa
+#define IOMMU_MMIO_EFR_0__GATS__SHIFT 0xc
+#define IOMMU_MMIO_EFR_0__GLX_SUP__SHIFT 0xe
+#define IOMMU_MMIO_EFR_0__SMIF_SUP__SHIFT 0x10
+#define IOMMU_MMIO_EFR_0__SMIF_RC__SHIFT 0x12
+#define IOMMU_MMIO_EFR_0__GAM_SUP__SHIFT 0x15
+#define IOMMU_MMIO_EFR_0__PPRF__SHIFT 0x18
+#define IOMMU_MMIO_EFR_0__GAF__SHIFT 0x1a
+#define IOMMU_MMIO_EFR_0__EVENTF__SHIFT 0x1c
+#define IOMMU_MMIO_EFR_0__DVM_ERR_SUP__SHIFT 0x1e
+#define IOMMU_MMIO_EFR_0__Reserved1__SHIFT 0x1f
+#define IOMMU_MMIO_EFR_0__PREF_SUP_MASK 0x00000001L
+#define IOMMU_MMIO_EFR_0__PPR_SUP_MASK 0x00000002L
+#define IOMMU_MMIO_EFR_0__XT_SUP_MASK 0x00000004L
+#define IOMMU_MMIO_EFR_0__NX_SUP_MASK 0x00000008L
+#define IOMMU_MMIO_EFR_0__GT_SUP_MASK 0x00000010L
+#define IOMMU_MMIO_EFR_0__Reserved_MASK 0x00000020L
+#define IOMMU_MMIO_EFR_0__IA_SUP_MASK 0x00000040L
+#define IOMMU_MMIO_EFR_0__GA_SUP_MASK 0x00000080L
+#define IOMMU_MMIO_EFR_0__HE_SUP_MASK 0x00000100L
+#define IOMMU_MMIO_EFR_0__PC_SUP_MASK 0x00000200L
+#define IOMMU_MMIO_EFR_0__HATS_MASK 0x00000C00L
+#define IOMMU_MMIO_EFR_0__GATS_MASK 0x00003000L
+#define IOMMU_MMIO_EFR_0__GLX_SUP_MASK 0x0000C000L
+#define IOMMU_MMIO_EFR_0__SMIF_SUP_MASK 0x00030000L
+#define IOMMU_MMIO_EFR_0__SMIF_RC_MASK 0x001C0000L
+#define IOMMU_MMIO_EFR_0__GAM_SUP_MASK 0x00E00000L
+#define IOMMU_MMIO_EFR_0__PPRF_MASK 0x03000000L
+#define IOMMU_MMIO_EFR_0__GAF_MASK 0x0C000000L
+#define IOMMU_MMIO_EFR_0__EVENTF_MASK 0x30000000L
+#define IOMMU_MMIO_EFR_0__DVM_ERR_SUP_MASK 0x40000000L
+#define IOMMU_MMIO_EFR_0__Reserved1_MASK 0x80000000L
+//IOMMU_MMIO_EFR_1
+#define IOMMU_MMIO_EFR_1__PAS_MAX__SHIFT 0x0
+#define IOMMU_MMIO_EFR_1__Reserved1__SHIFT 0x4
+#define IOMMU_MMIO_EFR_1__US_SUP__SHIFT 0x5
+#define IOMMU_MMIO_EFR_1__DTE_seg__SHIFT 0x6
+#define IOMMU_MMIO_EFR_1__PPR_OVERFLOW_EARLY_SUP__SHIFT 0x8
+#define IOMMU_MMIO_EFR_1__PPR_AUTORESP_SUP__SHIFT 0x9
+#define IOMMU_MMIO_EFR_1__MARCnum__SHIFT 0xa
+#define IOMMU_MMIO_EFR_1__BLOCK_STOPMARK_SUP__SHIFT 0xc
+#define IOMMU_MMIO_EFR_1__GMC_IOMMU_BYPASS_SUP__SHIFT 0xd
+#define IOMMU_MMIO_EFR_1__MMIO_MSI_CAP_SUP__SHIFT 0xe
+#define IOMMU_MMIO_EFR_1__SNOOP_ATTRS_SUP__SHIFT 0xf
+#define IOMMU_MMIO_EFR_1__GIo_SUP__SHIFT 0x10
+#define IOMMU_MMIO_EFR_1__HA_SUP__SHIFT 0x11
+#define IOMMU_MMIO_EFR_1__EPH_SUP__SHIFT 0x12
+#define IOMMU_MMIO_EFR_1__ATTRFW_SUP__SHIFT 0x13
+#define IOMMU_MMIO_EFR_1__HD_SUP__SHIFT 0x14
+#define IOMMU_MMIO_EFR_1__V2_HD_DIS_SUP__SHIFT 0x15
+#define IOMMU_MMIO_EFR_1__InvIotlbTypeSup__SHIFT 0x16
+#define IOMMU_MMIO_EFR_1__Reserved0__SHIFT 0x17
+#define IOMMU_MMIO_EFR_1__PAS_MAX_MASK 0x0000000FL
+#define IOMMU_MMIO_EFR_1__Reserved1_MASK 0x00000010L
+#define IOMMU_MMIO_EFR_1__US_SUP_MASK 0x00000020L
+#define IOMMU_MMIO_EFR_1__DTE_seg_MASK 0x000000C0L
+#define IOMMU_MMIO_EFR_1__PPR_OVERFLOW_EARLY_SUP_MASK 0x00000100L
+#define IOMMU_MMIO_EFR_1__PPR_AUTORESP_SUP_MASK 0x00000200L
+#define IOMMU_MMIO_EFR_1__MARCnum_MASK 0x00000C00L
+#define IOMMU_MMIO_EFR_1__BLOCK_STOPMARK_SUP_MASK 0x00001000L
+#define IOMMU_MMIO_EFR_1__GMC_IOMMU_BYPASS_SUP_MASK 0x00002000L
+#define IOMMU_MMIO_EFR_1__MMIO_MSI_CAP_SUP_MASK 0x00004000L
+#define IOMMU_MMIO_EFR_1__SNOOP_ATTRS_SUP_MASK 0x00008000L
+#define IOMMU_MMIO_EFR_1__GIo_SUP_MASK 0x00010000L
+#define IOMMU_MMIO_EFR_1__HA_SUP_MASK 0x00020000L
+#define IOMMU_MMIO_EFR_1__EPH_SUP_MASK 0x00040000L
+#define IOMMU_MMIO_EFR_1__ATTRFW_SUP_MASK 0x00080000L
+#define IOMMU_MMIO_EFR_1__HD_SUP_MASK 0x00100000L
+#define IOMMU_MMIO_EFR_1__V2_HD_DIS_SUP_MASK 0x00200000L
+#define IOMMU_MMIO_EFR_1__InvIotlbTypeSup_MASK 0x00400000L
+#define IOMMU_MMIO_EFR_1__Reserved0_MASK 0xFF800000L
+//IOMMU_MMIO_PPR_BASE_0
+#define IOMMU_MMIO_PPR_BASE_0__Reserved1__SHIFT 0x0
+#define IOMMU_MMIO_PPR_BASE_0__PPR_BASE_LO__SHIFT 0xc
+#define IOMMU_MMIO_PPR_BASE_0__Reserved1_MASK 0x00000FFFL
+#define IOMMU_MMIO_PPR_BASE_0__PPR_BASE_LO_MASK 0xFFFFF000L
+//IOMMU_MMIO_PPR_BASE_1
+#define IOMMU_MMIO_PPR_BASE_1__PPR_BASE_HI__SHIFT 0x0
+#define IOMMU_MMIO_PPR_BASE_1__Reserved1__SHIFT 0x14
+#define IOMMU_MMIO_PPR_BASE_1__PPR_LEN__SHIFT 0x18
+#define IOMMU_MMIO_PPR_BASE_1__Reserved0__SHIFT 0x1c
+#define IOMMU_MMIO_PPR_BASE_1__PPR_BASE_HI_MASK 0x000FFFFFL
+#define IOMMU_MMIO_PPR_BASE_1__Reserved1_MASK 0x00F00000L
+#define IOMMU_MMIO_PPR_BASE_1__PPR_LEN_MASK 0x0F000000L
+#define IOMMU_MMIO_PPR_BASE_1__Reserved0_MASK 0xF0000000L
+//IOMMU_MMIO_HW_ERR_UPPER_0
+#define IOMMU_MMIO_HW_ERR_UPPER_0__FIRST_EV_CODE_LO__SHIFT 0x0
+#define IOMMU_MMIO_HW_ERR_UPPER_0__FIRST_EV_CODE_LO_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_HW_ERR_UPPER_1
+#define IOMMU_MMIO_HW_ERR_UPPER_1__FIRST_EV_CODE_HI__SHIFT 0x0
+#define IOMMU_MMIO_HW_ERR_UPPER_1__EV_CODE__SHIFT 0x1c
+#define IOMMU_MMIO_HW_ERR_UPPER_1__FIRST_EV_CODE_HI_MASK 0x0FFFFFFFL
+#define IOMMU_MMIO_HW_ERR_UPPER_1__EV_CODE_MASK 0xF0000000L
+//IOMMU_MMIO_HW_ERR_LOWER_0
+#define IOMMU_MMIO_HW_ERR_LOWER_0__SECOND_EV_CODE_LO__SHIFT 0x0
+#define IOMMU_MMIO_HW_ERR_LOWER_0__SECOND_EV_CODE_LO_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_HW_ERR_LOWER_1
+#define IOMMU_MMIO_HW_ERR_LOWER_1__SECOND_EV_CODE_HI__SHIFT 0x0
+#define IOMMU_MMIO_HW_ERR_LOWER_1__SECOND_EV_CODE_HI_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_HW_ERR_STATUS_0
+#define IOMMU_MMIO_HW_ERR_STATUS_0__HEV__SHIFT 0x0
+#define IOMMU_MMIO_HW_ERR_STATUS_0__HEO__SHIFT 0x1
+#define IOMMU_MMIO_HW_ERR_STATUS_0__Reserved__SHIFT 0x2
+#define IOMMU_MMIO_HW_ERR_STATUS_0__HEV_MASK 0x00000001L
+#define IOMMU_MMIO_HW_ERR_STATUS_0__HEO_MASK 0x00000002L
+#define IOMMU_MMIO_HW_ERR_STATUS_0__Reserved_MASK 0xFFFFFFFCL
+//IOMMU_MMIO_HW_ERR_STATUS_1
+#define IOMMU_MMIO_HW_ERR_STATUS_1__Reserved__SHIFT 0x0
+#define IOMMU_MMIO_HW_ERR_STATUS_1__Reserved_MASK 0xFFFFFFFFL
+//SMI_FILTER_REGISTER_0_0
+#define SMI_FILTER_REGISTER_0_0__SmiDID_0__SHIFT 0x0
+#define SMI_FILTER_REGISTER_0_0__SmiDV_0__SHIFT 0x10
+#define SMI_FILTER_REGISTER_0_0__SmiFLock_0__SHIFT 0x11
+#define SMI_FILTER_REGISTER_0_0__Reserved__SHIFT 0x12
+#define SMI_FILTER_REGISTER_0_0__SmiDID_0_MASK 0x0000FFFFL
+#define SMI_FILTER_REGISTER_0_0__SmiDV_0_MASK 0x00010000L
+#define SMI_FILTER_REGISTER_0_0__SmiFLock_0_MASK 0x00020000L
+#define SMI_FILTER_REGISTER_0_0__Reserved_MASK 0xFFFC0000L
+//SMI_FILTER_REGISTER_0_1
+#define SMI_FILTER_REGISTER_0_1__Reserved__SHIFT 0x0
+#define SMI_FILTER_REGISTER_0_1__Reserved_MASK 0xFFFFFFFFL
+//SMI_FILTER_REGISTER_1_0
+#define SMI_FILTER_REGISTER_1_0__SmiDID_1__SHIFT 0x0
+#define SMI_FILTER_REGISTER_1_0__SmiDV_1__SHIFT 0x10
+#define SMI_FILTER_REGISTER_1_0__SmiFLock_1__SHIFT 0x11
+#define SMI_FILTER_REGISTER_1_0__Reserved__SHIFT 0x12
+#define SMI_FILTER_REGISTER_1_0__SmiDID_1_MASK 0x0000FFFFL
+#define SMI_FILTER_REGISTER_1_0__SmiDV_1_MASK 0x00010000L
+#define SMI_FILTER_REGISTER_1_0__SmiFLock_1_MASK 0x00020000L
+#define SMI_FILTER_REGISTER_1_0__Reserved_MASK 0xFFFC0000L
+//SMI_FILTER_REGISTER_1_1
+#define SMI_FILTER_REGISTER_1_1__Reserved__SHIFT 0x0
+#define SMI_FILTER_REGISTER_1_1__Reserved_MASK 0xFFFFFFFFL
+//SMI_FILTER_REGISTER_2_0
+#define SMI_FILTER_REGISTER_2_0__SmiDID_2__SHIFT 0x0
+#define SMI_FILTER_REGISTER_2_0__SmiDV_2__SHIFT 0x10
+#define SMI_FILTER_REGISTER_2_0__SmiFLock_2__SHIFT 0x11
+#define SMI_FILTER_REGISTER_2_0__Reserved__SHIFT 0x12
+#define SMI_FILTER_REGISTER_2_0__SmiDID_2_MASK 0x0000FFFFL
+#define SMI_FILTER_REGISTER_2_0__SmiDV_2_MASK 0x00010000L
+#define SMI_FILTER_REGISTER_2_0__SmiFLock_2_MASK 0x00020000L
+#define SMI_FILTER_REGISTER_2_0__Reserved_MASK 0xFFFC0000L
+//SMI_FILTER_REGISTER_2_1
+#define SMI_FILTER_REGISTER_2_1__Reserved__SHIFT 0x0
+#define SMI_FILTER_REGISTER_2_1__Reserved_MASK 0xFFFFFFFFL
+//SMI_FILTER_REGISTER_3_0
+#define SMI_FILTER_REGISTER_3_0__SmiDID_3__SHIFT 0x0
+#define SMI_FILTER_REGISTER_3_0__SmiDV_3__SHIFT 0x10
+#define SMI_FILTER_REGISTER_3_0__SmiFLock_3__SHIFT 0x11
+#define SMI_FILTER_REGISTER_3_0__Reserved__SHIFT 0x12
+#define SMI_FILTER_REGISTER_3_0__SmiDID_3_MASK 0x0000FFFFL
+#define SMI_FILTER_REGISTER_3_0__SmiDV_3_MASK 0x00010000L
+#define SMI_FILTER_REGISTER_3_0__SmiFLock_3_MASK 0x00020000L
+#define SMI_FILTER_REGISTER_3_0__Reserved_MASK 0xFFFC0000L
+//SMI_FILTER_REGISTER_3_1
+#define SMI_FILTER_REGISTER_3_1__Reserved__SHIFT 0x0
+#define SMI_FILTER_REGISTER_3_1__Reserved_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_GA_LOG_BASE_0
+#define IOMMU_MMIO_GA_LOG_BASE_0__GA_LOG_BASE_LO__SHIFT 0xc
+#define IOMMU_MMIO_GA_LOG_BASE_0__GA_LOG_BASE_LO_MASK 0xFFFFF000L
+//IOMMU_MMIO_GA_LOG_BASE_1
+#define IOMMU_MMIO_GA_LOG_BASE_1__GA_LOG_BASE_HI__SHIFT 0x0
+#define IOMMU_MMIO_GA_LOG_BASE_1__GA_LOG_LEN__SHIFT 0x18
+#define IOMMU_MMIO_GA_LOG_BASE_1__GA_LOG_BASE_HI_MASK 0x000FFFFFL
+#define IOMMU_MMIO_GA_LOG_BASE_1__GA_LOG_LEN_MASK 0x0F000000L
+//IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0
+#define IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0__GA_LOG_TAILPTR_ADDR_LO__SHIFT 0x3
+#define IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0__GA_LOG_TAILPTR_ADDR_LO_MASK 0xFFFFFFF8L
+//IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1
+#define IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1__GA_LOG_TAILPTR_ADDR_HI__SHIFT 0x0
+#define IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1__GA_LOG_TAILPTR_ADDR_HI_MASK 0x000FFFFFL
+//IOMMU_MMIO_PPR_B_BASE_0
+#define IOMMU_MMIO_PPR_B_BASE_0__Reserved1__SHIFT 0x0
+#define IOMMU_MMIO_PPR_B_BASE_0__PPR_B_BASE_LO__SHIFT 0xc
+#define IOMMU_MMIO_PPR_B_BASE_0__Reserved1_MASK 0x00000FFFL
+#define IOMMU_MMIO_PPR_B_BASE_0__PPR_B_BASE_LO_MASK 0xFFFFF000L
+//IOMMU_MMIO_PPR_B_BASE_1
+#define IOMMU_MMIO_PPR_B_BASE_1__PPR_B_BASE_HI__SHIFT 0x0
+#define IOMMU_MMIO_PPR_B_BASE_1__Reserved1__SHIFT 0x14
+#define IOMMU_MMIO_PPR_B_BASE_1__PPR_B_LEN__SHIFT 0x18
+#define IOMMU_MMIO_PPR_B_BASE_1__Reserved0__SHIFT 0x1c
+#define IOMMU_MMIO_PPR_B_BASE_1__PPR_B_BASE_HI_MASK 0x000FFFFFL
+#define IOMMU_MMIO_PPR_B_BASE_1__Reserved1_MASK 0x00F00000L
+#define IOMMU_MMIO_PPR_B_BASE_1__PPR_B_LEN_MASK 0x0F000000L
+#define IOMMU_MMIO_PPR_B_BASE_1__Reserved0_MASK 0xF0000000L
+//IOMMU_MMIO_EVENT_B_BASE_0
+#define IOMMU_MMIO_EVENT_B_BASE_0__Reserved1__SHIFT 0x0
+#define IOMMU_MMIO_EVENT_B_BASE_0__EVENT_B_BASE_LO__SHIFT 0xc
+#define IOMMU_MMIO_EVENT_B_BASE_0__Reserved1_MASK 0x00000FFFL
+#define IOMMU_MMIO_EVENT_B_BASE_0__EVENT_B_BASE_LO_MASK 0xFFFFF000L
+//IOMMU_MMIO_EVENT_B_BASE_1
+#define IOMMU_MMIO_EVENT_B_BASE_1__EVENT_B_BASE_HI__SHIFT 0x0
+#define IOMMU_MMIO_EVENT_B_BASE_1__Reserved1__SHIFT 0x14
+#define IOMMU_MMIO_EVENT_B_BASE_1__EVENT_B_LEN__SHIFT 0x18
+#define IOMMU_MMIO_EVENT_B_BASE_1__Reserved0__SHIFT 0x1c
+#define IOMMU_MMIO_EVENT_B_BASE_1__EVENT_B_BASE_HI_MASK 0x000FFFFFL
+#define IOMMU_MMIO_EVENT_B_BASE_1__Reserved1_MASK 0x00F00000L
+#define IOMMU_MMIO_EVENT_B_BASE_1__EVENT_B_LEN_MASK 0x0F000000L
+#define IOMMU_MMIO_EVENT_B_BASE_1__Reserved0_MASK 0xF0000000L
+//IOMMU_MMIO_DEVTBL_1_BASE_0
+#define IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE__SHIFT 0x0
+#define IOMMU_MMIO_DEVTBL_1_BASE_0__Reserved1__SHIFT 0x9
+#define IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_BASE_LO__SHIFT 0xc
+#define IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE_MASK 0x000001FFL
+#define IOMMU_MMIO_DEVTBL_1_BASE_0__Reserved1_MASK 0x00000E00L
+#define IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_BASE_LO_MASK 0xFFFFF000L
+//IOMMU_MMIO_DEVTBL_1_BASE_1
+#define IOMMU_MMIO_DEVTBL_1_BASE_1__DEV_TBL_1_BASE_HI__SHIFT 0x0
+#define IOMMU_MMIO_DEVTBL_1_BASE_1__Reserved0__SHIFT 0x14
+#define IOMMU_MMIO_DEVTBL_1_BASE_1__DEV_TBL_1_BASE_HI_MASK 0x000FFFFFL
+#define IOMMU_MMIO_DEVTBL_1_BASE_1__Reserved0_MASK 0xFFF00000L
+//IOMMU_MMIO_DEVTBL_2_BASE_0
+#define IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE__SHIFT 0x0
+#define IOMMU_MMIO_DEVTBL_2_BASE_0__Reserved1__SHIFT 0x9
+#define IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_BASE_LO__SHIFT 0xc
+#define IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE_MASK 0x000001FFL
+#define IOMMU_MMIO_DEVTBL_2_BASE_0__Reserved1_MASK 0x00000E00L
+#define IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_BASE_LO_MASK 0xFFFFF000L
+//IOMMU_MMIO_DEVTBL_2_BASE_1
+#define IOMMU_MMIO_DEVTBL_2_BASE_1__DEV_TBL_2_BASE_HI__SHIFT 0x0
+#define IOMMU_MMIO_DEVTBL_2_BASE_1__Reserved0__SHIFT 0x14
+#define IOMMU_MMIO_DEVTBL_2_BASE_1__DEV_TBL_2_BASE_HI_MASK 0x000FFFFFL
+#define IOMMU_MMIO_DEVTBL_2_BASE_1__Reserved0_MASK 0xFFF00000L
+//IOMMU_MMIO_DEVTBL_3_BASE_0
+#define IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE__SHIFT 0x0
+#define IOMMU_MMIO_DEVTBL_3_BASE_0__Reserved1__SHIFT 0x9
+#define IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_BASE_LO__SHIFT 0xc
+#define IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE_MASK 0x000001FFL
+#define IOMMU_MMIO_DEVTBL_3_BASE_0__Reserved1_MASK 0x00000E00L
+#define IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_BASE_LO_MASK 0xFFFFF000L
+//IOMMU_MMIO_DEVTBL_3_BASE_1
+#define IOMMU_MMIO_DEVTBL_3_BASE_1__DEV_TBL_3_BASE_HI__SHIFT 0x0
+#define IOMMU_MMIO_DEVTBL_3_BASE_1__Reserved0__SHIFT 0x14
+#define IOMMU_MMIO_DEVTBL_3_BASE_1__DEV_TBL_3_BASE_HI_MASK 0x000FFFFFL
+#define IOMMU_MMIO_DEVTBL_3_BASE_1__Reserved0_MASK 0xFFF00000L
+//IOMMU_MMIO_DEVTBL_4_BASE_0
+#define IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE__SHIFT 0x0
+#define IOMMU_MMIO_DEVTBL_4_BASE_0__Reserved1__SHIFT 0x9
+#define IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_BASE_LO__SHIFT 0xc
+#define IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE_MASK 0x000001FFL
+#define IOMMU_MMIO_DEVTBL_4_BASE_0__Reserved1_MASK 0x00000E00L
+#define IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_BASE_LO_MASK 0xFFFFF000L
+//IOMMU_MMIO_DEVTBL_4_BASE_1
+#define IOMMU_MMIO_DEVTBL_4_BASE_1__DEV_TBL_4_BASE_HI__SHIFT 0x0
+#define IOMMU_MMIO_DEVTBL_4_BASE_1__Reserved0__SHIFT 0x14
+#define IOMMU_MMIO_DEVTBL_4_BASE_1__DEV_TBL_4_BASE_HI_MASK 0x000FFFFFL
+#define IOMMU_MMIO_DEVTBL_4_BASE_1__Reserved0_MASK 0xFFF00000L
+//IOMMU_MMIO_DEVTBL_5_BASE_0
+#define IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE__SHIFT 0x0
+#define IOMMU_MMIO_DEVTBL_5_BASE_0__Reserved1__SHIFT 0x9
+#define IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_BASE_LO__SHIFT 0xc
+#define IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE_MASK 0x000001FFL
+#define IOMMU_MMIO_DEVTBL_5_BASE_0__Reserved1_MASK 0x00000E00L
+#define IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_BASE_LO_MASK 0xFFFFF000L
+//IOMMU_MMIO_DEVTBL_5_BASE_1
+#define IOMMU_MMIO_DEVTBL_5_BASE_1__DEV_TBL_5_BASE_HI__SHIFT 0x0
+#define IOMMU_MMIO_DEVTBL_5_BASE_1__Reserved0__SHIFT 0x14
+#define IOMMU_MMIO_DEVTBL_5_BASE_1__DEV_TBL_5_BASE_HI_MASK 0x000FFFFFL
+#define IOMMU_MMIO_DEVTBL_5_BASE_1__Reserved0_MASK 0xFFF00000L
+//IOMMU_MMIO_DEVTBL_6_BASE_0
+#define IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE__SHIFT 0x0
+#define IOMMU_MMIO_DEVTBL_6_BASE_0__Reserved1__SHIFT 0x9
+#define IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_BASE_LO__SHIFT 0xc
+#define IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE_MASK 0x000001FFL
+#define IOMMU_MMIO_DEVTBL_6_BASE_0__Reserved1_MASK 0x00000E00L
+#define IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_BASE_LO_MASK 0xFFFFF000L
+//IOMMU_MMIO_DEVTBL_6_BASE_1
+#define IOMMU_MMIO_DEVTBL_6_BASE_1__DEV_TBL_6_BASE_HI__SHIFT 0x0
+#define IOMMU_MMIO_DEVTBL_6_BASE_1__Reserved0__SHIFT 0x14
+#define IOMMU_MMIO_DEVTBL_6_BASE_1__DEV_TBL_6_BASE_HI_MASK 0x000FFFFFL
+#define IOMMU_MMIO_DEVTBL_6_BASE_1__Reserved0_MASK 0xFFF00000L
+//IOMMU_MMIO_DEVTBL_7_BASE_0
+#define IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE__SHIFT 0x0
+#define IOMMU_MMIO_DEVTBL_7_BASE_0__Reserved1__SHIFT 0x9
+#define IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_BASE_LO__SHIFT 0xc
+#define IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE_MASK 0x000001FFL
+#define IOMMU_MMIO_DEVTBL_7_BASE_0__Reserved1_MASK 0x00000E00L
+#define IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_BASE_LO_MASK 0xFFFFF000L
+//IOMMU_MMIO_DEVTBL_7_BASE_1
+#define IOMMU_MMIO_DEVTBL_7_BASE_1__DEV_TBL_7_BASE_HI__SHIFT 0x0
+#define IOMMU_MMIO_DEVTBL_7_BASE_1__Reserved0__SHIFT 0x14
+#define IOMMU_MMIO_DEVTBL_7_BASE_1__DEV_TBL_7_BASE_HI_MASK 0x000FFFFFL
+#define IOMMU_MMIO_DEVTBL_7_BASE_1__Reserved0_MASK 0xFFF00000L
+//IOMMU_MMIO_DSFX
+#define IOMMU_MMIO_DSFX__DSFXSup__SHIFT 0x0
+#define IOMMU_MMIO_DSFX__REVISION_MINOR__SHIFT 0x18
+#define IOMMU_MMIO_DSFX__REVISION_MAJOR__SHIFT 0x1c
+#define IOMMU_MMIO_DSFX__DSFXSup_MASK 0x00FFFFFFL
+#define IOMMU_MMIO_DSFX__REVISION_MINOR_MASK 0x0F000000L
+#define IOMMU_MMIO_DSFX__REVISION_MAJOR_MASK 0xF0000000L
+//IOMMU_MMIO_DSCX
+#define IOMMU_MMIO_DSCX__DSCX_CNTRL__SHIFT 0x0
+#define IOMMU_MMIO_DSCX__REVISION_MINOR__SHIFT 0x18
+#define IOMMU_MMIO_DSCX__REVISION_MAJOR__SHIFT 0x1c
+#define IOMMU_MMIO_DSCX__DSCX_CNTRL_MASK 0x00FFFFFFL
+#define IOMMU_MMIO_DSCX__REVISION_MINOR_MASK 0x0F000000L
+#define IOMMU_MMIO_DSCX__REVISION_MAJOR_MASK 0xF0000000L
+//IOMMU_MMIO_DSSX
+#define IOMMU_MMIO_DSSX__DSSX_status__SHIFT 0x0
+#define IOMMU_MMIO_DSSX__REVISION_MINOR__SHIFT 0x18
+#define IOMMU_MMIO_DSSX__REVISION_MAJOR__SHIFT 0x1c
+#define IOMMU_MMIO_DSSX__DSSX_status_MASK 0x00FFFFFFL
+#define IOMMU_MMIO_DSSX__REVISION_MINOR_MASK 0x0F000000L
+#define IOMMU_MMIO_DSSX__REVISION_MAJOR_MASK 0xF0000000L
+//IOMMU_MMIO_CAP_MISC
+#define IOMMU_MMIO_CAP_MISC__IOMMU_MSI_NUM__SHIFT 0x0
+#define IOMMU_MMIO_CAP_MISC__Reserved1__SHIFT 0x5
+#define IOMMU_MMIO_CAP_MISC__IOMMU_MSI_NUM_PPR__SHIFT 0x1b
+#define IOMMU_MMIO_CAP_MISC__IOMMU_MSI_NUM_MASK 0x0000001FL
+#define IOMMU_MMIO_CAP_MISC__Reserved1_MASK 0x07FFFFE0L
+#define IOMMU_MMIO_CAP_MISC__IOMMU_MSI_NUM_PPR_MASK 0xF8000000L
+//IOMMU_MMIO_CAP_MISC_1
+#define IOMMU_MMIO_CAP_MISC_1__IOMMU_MSI_NUM_GA__SHIFT 0x0
+#define IOMMU_MMIO_CAP_MISC_1__Reserved__SHIFT 0x5
+#define IOMMU_MMIO_CAP_MISC_1__IOMMU_MSI_NUM_GA_MASK 0x0000001FL
+#define IOMMU_MMIO_CAP_MISC_1__Reserved_MASK 0xFFFFFFE0L
+//IOMMU_MMIO_MSI_CAP
+#define IOMMU_MMIO_MSI_CAP__MSI_CAP_ID__SHIFT 0x0
+#define IOMMU_MMIO_MSI_CAP__MSI_CAP_PTR__SHIFT 0x8
+#define IOMMU_MMIO_MSI_CAP__MSI_EN__SHIFT 0x10
+#define IOMMU_MMIO_MSI_CAP__MSI_MULT_MESS_CAP__SHIFT 0x11
+#define IOMMU_MMIO_MSI_CAP__MSI_MULT_MESS_EN__SHIFT 0x14
+#define IOMMU_MMIO_MSI_CAP__MSI_64_EN__SHIFT 0x17
+#define IOMMU_MMIO_MSI_CAP__Reserved__SHIFT 0x18
+#define IOMMU_MMIO_MSI_CAP__MSI_CAP_ID_MASK 0x000000FFL
+#define IOMMU_MMIO_MSI_CAP__MSI_CAP_PTR_MASK 0x0000FF00L
+#define IOMMU_MMIO_MSI_CAP__MSI_EN_MASK 0x00010000L
+#define IOMMU_MMIO_MSI_CAP__MSI_MULT_MESS_CAP_MASK 0x000E0000L
+#define IOMMU_MMIO_MSI_CAP__MSI_MULT_MESS_EN_MASK 0x00700000L
+#define IOMMU_MMIO_MSI_CAP__MSI_64_EN_MASK 0x00800000L
+#define IOMMU_MMIO_MSI_CAP__Reserved_MASK 0xFF000000L
+//IOMMU_MMIO_MSI_ADDR_LO
+#define IOMMU_MMIO_MSI_ADDR_LO__Reserved__SHIFT 0x0
+#define IOMMU_MMIO_MSI_ADDR_LO__MSI_ADDR_LO__SHIFT 0x2
+#define IOMMU_MMIO_MSI_ADDR_LO__Reserved_MASK 0x00000003L
+#define IOMMU_MMIO_MSI_ADDR_LO__MSI_ADDR_LO_MASK 0xFFFFFFFCL
+//IOMMU_MMIO_MSI_ADDR_HI
+#define IOMMU_MMIO_MSI_ADDR_HI__MSI_ADDR_HI__SHIFT 0x0
+#define IOMMU_MMIO_MSI_ADDR_HI__MSI_ADDR_HI_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_MSI_DATA
+#define IOMMU_MMIO_MSI_DATA__MSI_DATA__SHIFT 0x0
+#define IOMMU_MMIO_MSI_DATA__Reserved__SHIFT 0x10
+#define IOMMU_MMIO_MSI_DATA__MSI_DATA_MASK 0x0000FFFFL
+#define IOMMU_MMIO_MSI_DATA__Reserved_MASK 0xFFFF0000L
+//IOMMU_MMIO_MSI_MAPPING_CAP
+#define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_ID__SHIFT 0x0
+#define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR__SHIFT 0x8
+#define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_EN__SHIFT 0x10
+#define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_FIXD__SHIFT 0x11
+#define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_RSV__SHIFT 0x12
+#define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE__SHIFT 0x1b
+#define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_ID_MASK 0x000000FFL
+#define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR_MASK 0x0000FF00L
+#define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_EN_MASK 0x00010000L
+#define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_FIXD_MASK 0x00020000L
+#define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_RSV_MASK 0x07FC0000L
+#define IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE_MASK 0xF8000000L
+//IOMMU_MMIO_CONTROL_W
+#define IOMMU_MMIO_CONTROL_W__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_CONTROL_W__GMC_IOMMU_BYPASS__SHIFT 0xd
+#define IOMMU_MMIO_CONTROL_W__Reserved1__SHIFT 0xe
+#define IOMMU_MMIO_CONTROL_W__Reserved0_MASK 0x00001FFFL
+#define IOMMU_MMIO_CONTROL_W__GMC_IOMMU_BYPASS_MASK 0x00002000L
+#define IOMMU_MMIO_CONTROL_W__Reserved1_MASK 0xFFFFC000L
+//IOMMU_MARC_BASE_LO_0
+#define IOMMU_MARC_BASE_LO_0__Reserved__SHIFT 0x0
+#define IOMMU_MARC_BASE_LO_0__MARCBaseAddr_L_0__SHIFT 0xc
+#define IOMMU_MARC_BASE_LO_0__Reserved_MASK 0x00000FFFL
+#define IOMMU_MARC_BASE_LO_0__MARCBaseAddr_L_0_MASK 0xFFFFF000L
+//IOMMU_MARC_BASE_HI_0
+#define IOMMU_MARC_BASE_HI_0__MARCBaseAddr_H_0__SHIFT 0x0
+#define IOMMU_MARC_BASE_HI_0__Reserved__SHIFT 0x14
+#define IOMMU_MARC_BASE_HI_0__MARCBaseAddr_H_0_MASK 0x000FFFFFL
+#define IOMMU_MARC_BASE_HI_0__Reserved_MASK 0xFFF00000L
+//IOMMU_MARC_RELOC_LO_0
+#define IOMMU_MARC_RELOC_LO_0__MARCEnable_0__SHIFT 0x0
+#define IOMMU_MARC_RELOC_LO_0__MARCReadOnly_0__SHIFT 0x1
+#define IOMMU_MARC_RELOC_LO_0__Reserved__SHIFT 0x2
+#define IOMMU_MARC_RELOC_LO_0__MARCRelocAddr_L_0__SHIFT 0xc
+#define IOMMU_MARC_RELOC_LO_0__MARCEnable_0_MASK 0x00000001L
+#define IOMMU_MARC_RELOC_LO_0__MARCReadOnly_0_MASK 0x00000002L
+#define IOMMU_MARC_RELOC_LO_0__Reserved_MASK 0x00000FFCL
+#define IOMMU_MARC_RELOC_LO_0__MARCRelocAddr_L_0_MASK 0xFFFFF000L
+//IOMMU_MARC_RELOC_HI_0
+#define IOMMU_MARC_RELOC_HI_0__MARCRelocAddr_H_0__SHIFT 0x0
+#define IOMMU_MARC_RELOC_HI_0__Reserved__SHIFT 0x14
+#define IOMMU_MARC_RELOC_HI_0__MARCRelocAddr_H_0_MASK 0x000FFFFFL
+#define IOMMU_MARC_RELOC_HI_0__Reserved_MASK 0xFFF00000L
+//IOMMU_MARC_LEN_LO_0
+#define IOMMU_MARC_LEN_LO_0__Reserved__SHIFT 0x0
+#define IOMMU_MARC_LEN_LO_0__MARCLen_L_0__SHIFT 0xc
+#define IOMMU_MARC_LEN_LO_0__Reserved_MASK 0x00000FFFL
+#define IOMMU_MARC_LEN_LO_0__MARCLen_L_0_MASK 0xFFFFF000L
+//IOMMU_MARC_LEN_HI_0
+#define IOMMU_MARC_LEN_HI_0__MARCLen_H_0__SHIFT 0x0
+#define IOMMU_MARC_LEN_HI_0__Reserved__SHIFT 0x14
+#define IOMMU_MARC_LEN_HI_0__MARCLen_H_0_MASK 0x000FFFFFL
+#define IOMMU_MARC_LEN_HI_0__Reserved_MASK 0xFFF00000L
+//IOMMU_MARC_BASE_LO_1
+#define IOMMU_MARC_BASE_LO_1__Reserved__SHIFT 0x0
+#define IOMMU_MARC_BASE_LO_1__MARCBaseAddr_L_1__SHIFT 0xc
+#define IOMMU_MARC_BASE_LO_1__Reserved_MASK 0x00000FFFL
+#define IOMMU_MARC_BASE_LO_1__MARCBaseAddr_L_1_MASK 0xFFFFF000L
+//IOMMU_MARC_BASE_HI_1
+#define IOMMU_MARC_BASE_HI_1__MARCBaseAddr_H_1__SHIFT 0x0
+#define IOMMU_MARC_BASE_HI_1__Reserved__SHIFT 0x14
+#define IOMMU_MARC_BASE_HI_1__MARCBaseAddr_H_1_MASK 0x000FFFFFL
+#define IOMMU_MARC_BASE_HI_1__Reserved_MASK 0xFFF00000L
+//IOMMU_MARC_RELOC_LO_1
+#define IOMMU_MARC_RELOC_LO_1__MARCEnable_1__SHIFT 0x0
+#define IOMMU_MARC_RELOC_LO_1__MARCReadOnly_1__SHIFT 0x1
+#define IOMMU_MARC_RELOC_LO_1__Reserved__SHIFT 0x2
+#define IOMMU_MARC_RELOC_LO_1__MARCRelocAddr_L_1__SHIFT 0xc
+#define IOMMU_MARC_RELOC_LO_1__MARCEnable_1_MASK 0x00000001L
+#define IOMMU_MARC_RELOC_LO_1__MARCReadOnly_1_MASK 0x00000002L
+#define IOMMU_MARC_RELOC_LO_1__Reserved_MASK 0x00000FFCL
+#define IOMMU_MARC_RELOC_LO_1__MARCRelocAddr_L_1_MASK 0xFFFFF000L
+//IOMMU_MARC_RELOC_HI_1
+#define IOMMU_MARC_RELOC_HI_1__MARCRelocAddr_H_1__SHIFT 0x0
+#define IOMMU_MARC_RELOC_HI_1__Reserved__SHIFT 0x14
+#define IOMMU_MARC_RELOC_HI_1__MARCRelocAddr_H_1_MASK 0x000FFFFFL
+#define IOMMU_MARC_RELOC_HI_1__Reserved_MASK 0xFFF00000L
+//IOMMU_MARC_LEN_LO_1
+#define IOMMU_MARC_LEN_LO_1__Reserved__SHIFT 0x0
+#define IOMMU_MARC_LEN_LO_1__MARCLen_L_1__SHIFT 0xc
+#define IOMMU_MARC_LEN_LO_1__Reserved_MASK 0x00000FFFL
+#define IOMMU_MARC_LEN_LO_1__MARCLen_L_1_MASK 0xFFFFF000L
+//IOMMU_MARC_LEN_HI_1
+#define IOMMU_MARC_LEN_HI_1__MARCLen_H_1__SHIFT 0x0
+#define IOMMU_MARC_LEN_HI_1__Reserved__SHIFT 0x14
+#define IOMMU_MARC_LEN_HI_1__MARCLen_H_1_MASK 0x000FFFFFL
+#define IOMMU_MARC_LEN_HI_1__Reserved_MASK 0xFFF00000L
+//IOMMU_MARC_BASE_LO_2
+#define IOMMU_MARC_BASE_LO_2__Reserved__SHIFT 0x0
+#define IOMMU_MARC_BASE_LO_2__MARCBaseAddr_L_2__SHIFT 0xc
+#define IOMMU_MARC_BASE_LO_2__Reserved_MASK 0x00000FFFL
+#define IOMMU_MARC_BASE_LO_2__MARCBaseAddr_L_2_MASK 0xFFFFF000L
+//IOMMU_MARC_BASE_HI_2
+#define IOMMU_MARC_BASE_HI_2__MARCBaseAddr_H_2__SHIFT 0x0
+#define IOMMU_MARC_BASE_HI_2__Reserved__SHIFT 0x14
+#define IOMMU_MARC_BASE_HI_2__MARCBaseAddr_H_2_MASK 0x000FFFFFL
+#define IOMMU_MARC_BASE_HI_2__Reserved_MASK 0xFFF00000L
+//IOMMU_MARC_RELOC_LO_2
+#define IOMMU_MARC_RELOC_LO_2__MARCEnable_2__SHIFT 0x0
+#define IOMMU_MARC_RELOC_LO_2__MARCReadOnly_2__SHIFT 0x1
+#define IOMMU_MARC_RELOC_LO_2__Reserved__SHIFT 0x2
+#define IOMMU_MARC_RELOC_LO_2__MARCRelocAddr_L_2__SHIFT 0xc
+#define IOMMU_MARC_RELOC_LO_2__MARCEnable_2_MASK 0x00000001L
+#define IOMMU_MARC_RELOC_LO_2__MARCReadOnly_2_MASK 0x00000002L
+#define IOMMU_MARC_RELOC_LO_2__Reserved_MASK 0x00000FFCL
+#define IOMMU_MARC_RELOC_LO_2__MARCRelocAddr_L_2_MASK 0xFFFFF000L
+//IOMMU_MARC_RELOC_HI_2
+#define IOMMU_MARC_RELOC_HI_2__MARCRelocAddr_H_2__SHIFT 0x0
+#define IOMMU_MARC_RELOC_HI_2__Reserved__SHIFT 0x14
+#define IOMMU_MARC_RELOC_HI_2__MARCRelocAddr_H_2_MASK 0x000FFFFFL
+#define IOMMU_MARC_RELOC_HI_2__Reserved_MASK 0xFFF00000L
+//IOMMU_MARC_LEN_LO_2
+#define IOMMU_MARC_LEN_LO_2__Reserved__SHIFT 0x0
+#define IOMMU_MARC_LEN_LO_2__MARCLen_L_2__SHIFT 0xc
+#define IOMMU_MARC_LEN_LO_2__Reserved_MASK 0x00000FFFL
+#define IOMMU_MARC_LEN_LO_2__MARCLen_L_2_MASK 0xFFFFF000L
+//IOMMU_MARC_LEN_HI_2
+#define IOMMU_MARC_LEN_HI_2__MARCLen_H_2__SHIFT 0x0
+#define IOMMU_MARC_LEN_HI_2__Reserved__SHIFT 0x14
+#define IOMMU_MARC_LEN_HI_2__MARCLen_H_2_MASK 0x000FFFFFL
+#define IOMMU_MARC_LEN_HI_2__Reserved_MASK 0xFFF00000L
+//IOMMU_MARC_BASE_LO_3
+#define IOMMU_MARC_BASE_LO_3__Reserved__SHIFT 0x0
+#define IOMMU_MARC_BASE_LO_3__MARCBaseAddr_L_3__SHIFT 0xc
+#define IOMMU_MARC_BASE_LO_3__Reserved_MASK 0x00000FFFL
+#define IOMMU_MARC_BASE_LO_3__MARCBaseAddr_L_3_MASK 0xFFFFF000L
+//IOMMU_MARC_BASE_HI_3
+#define IOMMU_MARC_BASE_HI_3__MARCBaseAddr_H_3__SHIFT 0x0
+#define IOMMU_MARC_BASE_HI_3__Reserved__SHIFT 0x14
+#define IOMMU_MARC_BASE_HI_3__MARCBaseAddr_H_3_MASK 0x000FFFFFL
+#define IOMMU_MARC_BASE_HI_3__Reserved_MASK 0xFFF00000L
+//IOMMU_MARC_RELOC_LO_3
+#define IOMMU_MARC_RELOC_LO_3__MARCEnable_3__SHIFT 0x0
+#define IOMMU_MARC_RELOC_LO_3__MARCReadOnly_3__SHIFT 0x1
+#define IOMMU_MARC_RELOC_LO_3__Reserved__SHIFT 0x2
+#define IOMMU_MARC_RELOC_LO_3__MARCRelocAddr_L_3__SHIFT 0xc
+#define IOMMU_MARC_RELOC_LO_3__MARCEnable_3_MASK 0x00000001L
+#define IOMMU_MARC_RELOC_LO_3__MARCReadOnly_3_MASK 0x00000002L
+#define IOMMU_MARC_RELOC_LO_3__Reserved_MASK 0x00000FFCL
+#define IOMMU_MARC_RELOC_LO_3__MARCRelocAddr_L_3_MASK 0xFFFFF000L
+//IOMMU_MARC_RELOC_HI_3
+#define IOMMU_MARC_RELOC_HI_3__MARCRelocAddr_H_3__SHIFT 0x0
+#define IOMMU_MARC_RELOC_HI_3__Reserved__SHIFT 0x14
+#define IOMMU_MARC_RELOC_HI_3__MARCRelocAddr_H_3_MASK 0x000FFFFFL
+#define IOMMU_MARC_RELOC_HI_3__Reserved_MASK 0xFFF00000L
+//IOMMU_MARC_LEN_LO_3
+#define IOMMU_MARC_LEN_LO_3__Reserved__SHIFT 0x0
+#define IOMMU_MARC_LEN_LO_3__MARCLen_L_3__SHIFT 0xc
+#define IOMMU_MARC_LEN_LO_3__Reserved_MASK 0x00000FFFL
+#define IOMMU_MARC_LEN_LO_3__MARCLen_L_3_MASK 0xFFFFF000L
+//IOMMU_MARC_LEN_HI_3
+#define IOMMU_MARC_LEN_HI_3__MARCLen_H_3__SHIFT 0x0
+#define IOMMU_MARC_LEN_HI_3__Reserved__SHIFT 0x14
+#define IOMMU_MARC_LEN_HI_3__MARCLen_H_3_MASK 0x000FFFFFL
+#define IOMMU_MARC_LEN_HI_3__Reserved_MASK 0xFFF00000L
+//IOMMU_MMIO_CMD_BUF_HDPTR_0
+#define IOMMU_MMIO_CMD_BUF_HDPTR_0__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_CMD_BUF_HDPTR_0__CMD_HDPTR__SHIFT 0x4
+#define IOMMU_MMIO_CMD_BUF_HDPTR_0__Reserved1__SHIFT 0x13
+#define IOMMU_MMIO_CMD_BUF_HDPTR_0__Reserved0_MASK 0x0000000FL
+#define IOMMU_MMIO_CMD_BUF_HDPTR_0__CMD_HDPTR_MASK 0x0007FFF0L
+#define IOMMU_MMIO_CMD_BUF_HDPTR_0__Reserved1_MASK 0xFFF80000L
+//IOMMU_MMIO_CMD_BUF_HDPTR_1
+#define IOMMU_MMIO_CMD_BUF_HDPTR_1__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_CMD_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_CMD_BUF_TAILPTR_0
+#define IOMMU_MMIO_CMD_BUF_TAILPTR_0__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_CMD_BUF_TAILPTR_0__CMD_TAILPTR__SHIFT 0x4
+#define IOMMU_MMIO_CMD_BUF_TAILPTR_0__Reserved1__SHIFT 0x13
+#define IOMMU_MMIO_CMD_BUF_TAILPTR_0__Reserved0_MASK 0x0000000FL
+#define IOMMU_MMIO_CMD_BUF_TAILPTR_0__CMD_TAILPTR_MASK 0x0007FFF0L
+#define IOMMU_MMIO_CMD_BUF_TAILPTR_0__Reserved1_MASK 0xFFF80000L
+//IOMMU_MMIO_CMD_BUF_TAILPTR_1
+#define IOMMU_MMIO_CMD_BUF_TAILPTR_1__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_CMD_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_EVENT_BUF_HDPTR_0
+#define IOMMU_MMIO_EVENT_BUF_HDPTR_0__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_EVENT_BUF_HDPTR_0__EVENT_HDPTR__SHIFT 0x4
+#define IOMMU_MMIO_EVENT_BUF_HDPTR_0__Reserved1__SHIFT 0x13
+#define IOMMU_MMIO_EVENT_BUF_HDPTR_0__Reserved0_MASK 0x0000000FL
+#define IOMMU_MMIO_EVENT_BUF_HDPTR_0__EVENT_HDPTR_MASK 0x0007FFF0L
+#define IOMMU_MMIO_EVENT_BUF_HDPTR_0__Reserved1_MASK 0xFFF80000L
+//IOMMU_MMIO_EVENT_BUF_HDPTR_1
+#define IOMMU_MMIO_EVENT_BUF_HDPTR_1__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_EVENT_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_EVENT_BUF_TAILPTR_0
+#define IOMMU_MMIO_EVENT_BUF_TAILPTR_0__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_EVENT_BUF_TAILPTR_0__EVENT_TAILPTR__SHIFT 0x4
+#define IOMMU_MMIO_EVENT_BUF_TAILPTR_0__Reserved1__SHIFT 0x13
+#define IOMMU_MMIO_EVENT_BUF_TAILPTR_0__Reserved0_MASK 0x0000000FL
+#define IOMMU_MMIO_EVENT_BUF_TAILPTR_0__EVENT_TAILPTR_MASK 0x0007FFF0L
+#define IOMMU_MMIO_EVENT_BUF_TAILPTR_0__Reserved1_MASK 0xFFF80000L
+//IOMMU_MMIO_EVENT_BUF_TAILPTR_1
+#define IOMMU_MMIO_EVENT_BUF_TAILPTR_1__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_EVENT_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_STATUS_0
+#define IOMMU_MMIO_STATUS_0__EVENT_OVERFLOW__SHIFT 0x0
+#define IOMMU_MMIO_STATUS_0__EVENT_LOGINT__SHIFT 0x1
+#define IOMMU_MMIO_STATUS_0__COMWAIT_INT__SHIFT 0x2
+#define IOMMU_MMIO_STATUS_0__EVENT_LOGRUN__SHIFT 0x3
+#define IOMMU_MMIO_STATUS_0__CMD_BUFRUN__SHIFT 0x4
+#define IOMMU_MMIO_STATUS_0__PPR_OVERFLOW__SHIFT 0x5
+#define IOMMU_MMIO_STATUS_0__PPR_INT__SHIFT 0x6
+#define IOMMU_MMIO_STATUS_0__PPR_RUN__SHIFT 0x7
+#define IOMMU_MMIO_STATUS_0__GA_RUN__SHIFT 0x8
+#define IOMMU_MMIO_STATUS_0__GA_OVERFLOW__SHIFT 0x9
+#define IOMMU_MMIO_STATUS_0__GA_INT__SHIFT 0xa
+#define IOMMU_MMIO_STATUS_0__PPR_B_OVERFLOW__SHIFT 0xb
+#define IOMMU_MMIO_STATUS_0__PPR_BUF_ACTIVE__SHIFT 0xc
+#define IOMMU_MMIO_STATUS_0__Reserved0__SHIFT 0xd
+#define IOMMU_MMIO_STATUS_0__EVENT_B_OVERFLOW__SHIFT 0xf
+#define IOMMU_MMIO_STATUS_0__EVENT_BUF_ACTIVE__SHIFT 0x10
+#define IOMMU_MMIO_STATUS_0__PPR_B_OVERFLOW_EARLY__SHIFT 0x11
+#define IOMMU_MMIO_STATUS_0__PPR_OVERFLOW_EARLY__SHIFT 0x12
+#define IOMMU_MMIO_STATUS_0__Reserved1__SHIFT 0x13
+#define IOMMU_MMIO_STATUS_0__EVENT_OVERFLOW_MASK 0x00000001L
+#define IOMMU_MMIO_STATUS_0__EVENT_LOGINT_MASK 0x00000002L
+#define IOMMU_MMIO_STATUS_0__COMWAIT_INT_MASK 0x00000004L
+#define IOMMU_MMIO_STATUS_0__EVENT_LOGRUN_MASK 0x00000008L
+#define IOMMU_MMIO_STATUS_0__CMD_BUFRUN_MASK 0x00000010L
+#define IOMMU_MMIO_STATUS_0__PPR_OVERFLOW_MASK 0x00000020L
+#define IOMMU_MMIO_STATUS_0__PPR_INT_MASK 0x00000040L
+#define IOMMU_MMIO_STATUS_0__PPR_RUN_MASK 0x00000080L
+#define IOMMU_MMIO_STATUS_0__GA_RUN_MASK 0x00000100L
+#define IOMMU_MMIO_STATUS_0__GA_OVERFLOW_MASK 0x00000200L
+#define IOMMU_MMIO_STATUS_0__GA_INT_MASK 0x00000400L
+#define IOMMU_MMIO_STATUS_0__PPR_B_OVERFLOW_MASK 0x00000800L
+#define IOMMU_MMIO_STATUS_0__PPR_BUF_ACTIVE_MASK 0x00001000L
+#define IOMMU_MMIO_STATUS_0__Reserved0_MASK 0x00006000L
+#define IOMMU_MMIO_STATUS_0__EVENT_B_OVERFLOW_MASK 0x00008000L
+#define IOMMU_MMIO_STATUS_0__EVENT_BUF_ACTIVE_MASK 0x00010000L
+#define IOMMU_MMIO_STATUS_0__PPR_B_OVERFLOW_EARLY_MASK 0x00020000L
+#define IOMMU_MMIO_STATUS_0__PPR_OVERFLOW_EARLY_MASK 0x00040000L
+#define IOMMU_MMIO_STATUS_0__Reserved1_MASK 0xFFF80000L
+//IOMMU_MMIO_STATUS_1
+#define IOMMU_MMIO_STATUS_1__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_STATUS_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_PPR_BUF_HDPTR_0
+#define IOMMU_MMIO_PPR_BUF_HDPTR_0__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_PPR_BUF_HDPTR_0__PPR_HDPTR__SHIFT 0x4
+#define IOMMU_MMIO_PPR_BUF_HDPTR_0__Reserved1__SHIFT 0x13
+#define IOMMU_MMIO_PPR_BUF_HDPTR_0__Reserved0_MASK 0x0000000FL
+#define IOMMU_MMIO_PPR_BUF_HDPTR_0__PPR_HDPTR_MASK 0x0007FFF0L
+#define IOMMU_MMIO_PPR_BUF_HDPTR_0__Reserved1_MASK 0xFFF80000L
+//IOMMU_MMIO_PPR_BUF_HDPTR_1
+#define IOMMU_MMIO_PPR_BUF_HDPTR_1__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_PPR_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_PPR_BUF_TAILPTR_0
+#define IOMMU_MMIO_PPR_BUF_TAILPTR_0__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_PPR_BUF_TAILPTR_0__PPR_TAILPTR__SHIFT 0x4
+#define IOMMU_MMIO_PPR_BUF_TAILPTR_0__Reserved1__SHIFT 0x13
+#define IOMMU_MMIO_PPR_BUF_TAILPTR_0__Reserved0_MASK 0x0000000FL
+#define IOMMU_MMIO_PPR_BUF_TAILPTR_0__PPR_TAILPTR_MASK 0x0007FFF0L
+#define IOMMU_MMIO_PPR_BUF_TAILPTR_0__Reserved1_MASK 0xFFF80000L
+//IOMMU_MMIO_PPR_BUF_TAILPTR_1
+#define IOMMU_MMIO_PPR_BUF_TAILPTR_1__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_PPR_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_GA_BUF_HDPTR_0
+#define IOMMU_MMIO_GA_BUF_HDPTR_0__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_GA_BUF_HDPTR_0__GA_HDPTR__SHIFT 0x3
+#define IOMMU_MMIO_GA_BUF_HDPTR_0__Reserved1__SHIFT 0x10
+#define IOMMU_MMIO_GA_BUF_HDPTR_0__Reserved0_MASK 0x00000007L
+#define IOMMU_MMIO_GA_BUF_HDPTR_0__GA_HDPTR_MASK 0x0000FFF8L
+#define IOMMU_MMIO_GA_BUF_HDPTR_0__Reserved1_MASK 0xFFFF0000L
+//IOMMU_MMIO_GA_BUF_HDPTR_1
+#define IOMMU_MMIO_GA_BUF_HDPTR_1__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_GA_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_GA_BUF_TAILPTR_0
+#define IOMMU_MMIO_GA_BUF_TAILPTR_0__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_GA_BUF_TAILPTR_0__GA_TAILPTR__SHIFT 0x3
+#define IOMMU_MMIO_GA_BUF_TAILPTR_0__Reserved1__SHIFT 0x10
+#define IOMMU_MMIO_GA_BUF_TAILPTR_0__Reserved0_MASK 0x00000007L
+#define IOMMU_MMIO_GA_BUF_TAILPTR_0__GA_TAILPTR_MASK 0x0000FFF8L
+#define IOMMU_MMIO_GA_BUF_TAILPTR_0__Reserved1_MASK 0xFFFF0000L
+//IOMMU_MMIO_GA_BUF_TAILPTR_1
+#define IOMMU_MMIO_GA_BUF_TAILPTR_1__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_GA_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_PPR_B_BUF_HDPTR_0
+#define IOMMU_MMIO_PPR_B_BUF_HDPTR_0__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_PPR_B_BUF_HDPTR_0__PPR_B_HDPTR__SHIFT 0x4
+#define IOMMU_MMIO_PPR_B_BUF_HDPTR_0__Reserved1__SHIFT 0x13
+#define IOMMU_MMIO_PPR_B_BUF_HDPTR_0__Reserved0_MASK 0x0000000FL
+#define IOMMU_MMIO_PPR_B_BUF_HDPTR_0__PPR_B_HDPTR_MASK 0x0007FFF0L
+#define IOMMU_MMIO_PPR_B_BUF_HDPTR_0__Reserved1_MASK 0xFFF80000L
+//IOMMU_MMIO_PPR_B_BUF_HDPTR_1
+#define IOMMU_MMIO_PPR_B_BUF_HDPTR_1__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_PPR_B_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_PPR_B_BUF_TAILPTR_0
+#define IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__PPR_B_TAILPTR__SHIFT 0x4
+#define IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__Reserved1__SHIFT 0x13
+#define IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__Reserved0_MASK 0x0000000FL
+#define IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__PPR_B_TAILPTR_MASK 0x0007FFF0L
+#define IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__Reserved1_MASK 0xFFF80000L
+//IOMMU_MMIO_PPR_B_BUF_TAILPTR_1
+#define IOMMU_MMIO_PPR_B_BUF_TAILPTR_1__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_PPR_B_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_EVENT_B_BUF_HDPTR_0
+#define IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__EVENT_B_HDPTR__SHIFT 0x4
+#define IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__Reserved1__SHIFT 0x13
+#define IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__Reserved0_MASK 0x0000000FL
+#define IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__EVENT_B_HDPTR_MASK 0x0007FFF0L
+#define IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__Reserved1_MASK 0xFFF80000L
+//IOMMU_MMIO_EVENT_B_BUF_HDPTR_1
+#define IOMMU_MMIO_EVENT_B_BUF_HDPTR_1__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_EVENT_B_BUF_HDPTR_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0
+#define IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__EVENT_B_TAILPTR__SHIFT 0x4
+#define IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__Reserved1__SHIFT 0x13
+#define IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__Reserved0_MASK 0x0000000FL
+#define IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__EVENT_B_TAILPTR_MASK 0x0007FFF0L
+#define IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__Reserved1_MASK 0xFFF80000L
+//IOMMU_MMIO_EVENT_B_BUF_TAILPTR_1
+#define IOMMU_MMIO_EVENT_B_BUF_TAILPTR_1__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_EVENT_B_BUF_TAILPTR_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_PPR_AUTORESP_0
+#define IOMMU_MMIO_PPR_AUTORESP_0__PPR_Auto_resp_code__SHIFT 0x0
+#define IOMMU_MMIO_PPR_AUTORESP_0__PPR_Auto_resp_mask_gn__SHIFT 0x4
+#define IOMMU_MMIO_PPR_AUTORESP_0__Reserved0__SHIFT 0x5
+#define IOMMU_MMIO_PPR_AUTORESP_0__PPR_Auto_resp_code_MASK 0x0000000FL
+#define IOMMU_MMIO_PPR_AUTORESP_0__PPR_Auto_resp_mask_gn_MASK 0x00000010L
+#define IOMMU_MMIO_PPR_AUTORESP_0__Reserved0_MASK 0xFFFFFFE0L
+//IOMMU_MMIO_PPR_OVERFLOW_EARLY_0
+#define IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_threshold__SHIFT 0x0
+#define IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__Reserved0__SHIFT 0xf
+#define IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_int_en__SHIFT 0x1e
+#define IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_en__SHIFT 0x1f
+#define IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_threshold_MASK 0x00007FFFL
+#define IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__Reserved0_MASK 0x3FFF8000L
+#define IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_int_en_MASK 0x40000000L
+#define IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_en_MASK 0x80000000L
+//IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0
+#define IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_threshold__SHIFT 0x0
+#define IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__Reserved0__SHIFT 0xf
+#define IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_int_en__SHIFT 0x1e
+#define IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_en__SHIFT 0x1f
+#define IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_threshold_MASK 0x00007FFFL
+#define IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__Reserved0_MASK 0x3FFF8000L
+#define IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_int_en_MASK 0x40000000L
+#define IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_en_MASK 0x80000000L
+//IOMMU_MMIO_COUNTER_CONFIG_0
+#define IOMMU_MMIO_COUNTER_CONFIG_0__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_CONFIG_0__N_COUNTER__SHIFT 0x7
+#define IOMMU_MMIO_COUNTER_CONFIG_0__Reserved1__SHIFT 0xb
+#define IOMMU_MMIO_COUNTER_CONFIG_0__N_COUNTER_BANKS__SHIFT 0xc
+#define IOMMU_MMIO_COUNTER_CONFIG_0__Reserved2__SHIFT 0x12
+#define IOMMU_MMIO_COUNTER_CONFIG_0__Reserved0_MASK 0x0000007FL
+#define IOMMU_MMIO_COUNTER_CONFIG_0__N_COUNTER_MASK 0x00000780L
+#define IOMMU_MMIO_COUNTER_CONFIG_0__Reserved1_MASK 0x00000800L
+#define IOMMU_MMIO_COUNTER_CONFIG_0__N_COUNTER_BANKS_MASK 0x0003F000L
+#define IOMMU_MMIO_COUNTER_CONFIG_0__Reserved2_MASK 0xFFFC0000L
+//IOMMU_MMIO_COUNTER_CONFIG_1
+#define IOMMU_MMIO_COUNTER_CONFIG_1__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_CONFIG_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0
+#define IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0__PASID_LOCK_LO__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0__PASID_LOCK_LO_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1
+#define IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1__PASID_LOCK_HI__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1__PASID_LOCK_HI_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0
+#define IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0__DOMAIN_LOCK_LO__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0__DOMAIN_LOCK_LO_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1
+#define IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1__DOMAIN_LOCK_HI__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1__DOMAIN_LOCK_HI_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0
+#define IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0__DEVID_LOCK_LO__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0__DEVID_LOCK_LO_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1
+#define IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1__DEVID_LOCK_HI__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1__DEVID_LOCK_HI_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_COUNTER_BANK_0_CNT_0_0
+#define IOMMU_MMIO_COUNTER_BANK_0_CNT_0_0__ICOUNTER_0_0_LO__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_BANK_0_CNT_0_0__ICOUNTER_0_0_LO_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1
+#define IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1__ICOUNTER_0_0_HI__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1__Reserved__SHIFT 0x10
+#define IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1__ICOUNTER_0_0_HI_MASK 0x0000FFFFL
+#define IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1__Reserved_MASK 0xFFFF0000L
+//IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CSOURCE_0_0__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__Reserved1__SHIFT 0x8
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__COUNT_UNITS_0_0__SHIFT 0x1e
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CAC_0_0__SHIFT 0x1f
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CSOURCE_0_0_MASK 0x000000FFL
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__Reserved1_MASK 0x3FFFFF00L
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__COUNT_UNITS_0_0_MASK 0x40000000L
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CAC_0_0_MASK 0x80000000L
+//IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASID_MATCH_0_0__SHIFT 0x0
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASMEN_0_0__SHIFT 0x1f
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASID_MATCH_0_0_MASK 0x0000FFFFL
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASMEN_0_0_MASK 0x80000000L
+//IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__PASID_MASK_0_0__SHIFT 0x0
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__PASID_MASK_0_0_MASK 0x0000FFFFL
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMAIN_MATCH_0_0__SHIFT 0x0
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMMEN_0_0__SHIFT 0x1f
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMAIN_MATCH_0_0_MASK 0x0000FFFFL
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMMEN_0_0_MASK 0x80000000L
+//IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__DOMAIN_MASK_0_0__SHIFT 0x0
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__DOMAIN_MASK_0_0_MASK 0x0000FFFFL
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DEVICEID_MATCH_0_0__SHIFT 0x0
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT 0x10
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DIDMEN_0_0__SHIFT 0x1f
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DEVICEID_MATCH_0_0_MASK 0x0000FFFFL
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DIDMEN_0_0_MASK 0x80000000L
+//IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__DEVICEID_MASK_0_0__SHIFT 0x0
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT 0x10
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__DEVICEID_MASK_0_0_MASK 0x0000FFFFL
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0
+#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0__EVENT_NOTE_0_0_LO__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0__EVENT_NOTE_0_0_LO_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1
+#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__EVENT_NOTE_0_0_HI__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__Reserved0__SHIFT 0x14
+#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__CERE_0_0__SHIFT 0x1f
+#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__EVENT_NOTE_0_0_HI_MASK 0x000FFFFFL
+#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__Reserved0_MASK 0x7FF00000L
+#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__CERE_0_0_MASK 0x80000000L
+//IOMMU_MMIO_COUNTER_BANK_0_CNT_1_0
+#define IOMMU_MMIO_COUNTER_BANK_0_CNT_1_0__ICOUNTER_0_1_LO__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_BANK_0_CNT_1_0__ICOUNTER_0_1_LO_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1
+#define IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1__ICOUNTER_0_1_HI__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1__Reserved__SHIFT 0x10
+#define IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1__ICOUNTER_0_1_HI_MASK 0x0000FFFFL
+#define IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1__Reserved_MASK 0xFFFF0000L
+//IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CSOURCE_0_1__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__Reserved1__SHIFT 0x8
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__COUNT_UNITS_0_1__SHIFT 0x1e
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CAC_0_1__SHIFT 0x1f
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CSOURCE_0_1_MASK 0x000000FFL
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__Reserved1_MASK 0x3FFFFF00L
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__COUNT_UNITS_0_1_MASK 0x40000000L
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CAC_0_1_MASK 0x80000000L
+//IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASID_MATCH_0_1__SHIFT 0x0
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASMEN_0_1__SHIFT 0x1f
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASID_MATCH_0_1_MASK 0x0000FFFFL
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASMEN_0_1_MASK 0x80000000L
+//IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__PASID_MASK_0_1__SHIFT 0x0
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__PASID_MASK_0_1_MASK 0x0000FFFFL
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMAIN_MATCH_0_1__SHIFT 0x0
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMMEN_0_1__SHIFT 0x1f
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMAIN_MATCH_0_1_MASK 0x0000FFFFL
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMMEN_0_1_MASK 0x80000000L
+//IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__DOMAIN_MASK_0_1__SHIFT 0x0
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__DOMAIN_MASK_0_1_MASK 0x0000FFFFL
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DEVICEID_MATCH_0_1__SHIFT 0x0
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT 0x10
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DIDMEN_0_1__SHIFT 0x1f
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DEVICEID_MATCH_0_1_MASK 0x0000FFFFL
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DIDMEN_0_1_MASK 0x80000000L
+//IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__DEVICEID_MASK_0_1__SHIFT 0x0
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT 0x10
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__DEVICEID_MASK_0_1_MASK 0x0000FFFFL
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0
+#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0__EVENT_NOTE_0_1_LO__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0__EVENT_NOTE_0_1_LO_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1
+#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__EVENT_NOTE_0_1_HI__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__Reserved0__SHIFT 0x14
+#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__CERE_0_1__SHIFT 0x1f
+#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__EVENT_NOTE_0_1_HI_MASK 0x000FFFFFL
+#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__Reserved0_MASK 0x7FF00000L
+#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__CERE_0_1_MASK 0x80000000L
+//IOMMU_MMIO_COUNTER_BANK_0_CNT_2_0
+#define IOMMU_MMIO_COUNTER_BANK_0_CNT_2_0__ICOUNTER_0_2_LO__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_BANK_0_CNT_2_0__ICOUNTER_0_2_LO_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1
+#define IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1__ICOUNTER_0_2_HI__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1__Reserved__SHIFT 0x10
+#define IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1__ICOUNTER_0_2_HI_MASK 0x0000FFFFL
+#define IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1__Reserved_MASK 0xFFFF0000L
+//IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CSOURCE_0_2__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__Reserved1__SHIFT 0x8
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__COUNT_UNITS_0_2__SHIFT 0x1e
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CAC_0_2__SHIFT 0x1f
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CSOURCE_0_2_MASK 0x000000FFL
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__Reserved1_MASK 0x3FFFFF00L
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__COUNT_UNITS_0_2_MASK 0x40000000L
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CAC_0_2_MASK 0x80000000L
+//IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASID_MATCH_0_2__SHIFT 0x0
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASMEN_0_2__SHIFT 0x1f
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASID_MATCH_0_2_MASK 0x0000FFFFL
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASMEN_0_2_MASK 0x80000000L
+//IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__PASID_MASK_0_2__SHIFT 0x0
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__PASID_MASK_0_2_MASK 0x0000FFFFL
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMAIN_MATCH_0_2__SHIFT 0x0
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMMEN_0_2__SHIFT 0x1f
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMAIN_MATCH_0_2_MASK 0x0000FFFFL
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMMEN_0_2_MASK 0x80000000L
+//IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__DOMAIN_MASK_0_2__SHIFT 0x0
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__DOMAIN_MASK_0_2_MASK 0x0000FFFFL
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DEVICEID_MATCH_0_2__SHIFT 0x0
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT 0x10
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DIDMEN_0_2__SHIFT 0x1f
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DEVICEID_MATCH_0_2_MASK 0x0000FFFFL
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DIDMEN_0_2_MASK 0x80000000L
+//IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__DEVICEID_MASK_0_2__SHIFT 0x0
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT 0x10
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__DEVICEID_MASK_0_2_MASK 0x0000FFFFL
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0
+#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0__EVENT_NOTE_0_2_LO__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0__EVENT_NOTE_0_2_LO_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1
+#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__EVENT_NOTE_0_2_HI__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__Reserved0__SHIFT 0x14
+#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__CERE_0_2__SHIFT 0x1f
+#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__EVENT_NOTE_0_2_HI_MASK 0x000FFFFFL
+#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__Reserved0_MASK 0x7FF00000L
+#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__CERE_0_2_MASK 0x80000000L
+//IOMMU_MMIO_COUNTER_BANK_0_CNT_3_0
+#define IOMMU_MMIO_COUNTER_BANK_0_CNT_3_0__ICOUNTER_0_3_LO__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_BANK_0_CNT_3_0__ICOUNTER_0_3_LO_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1
+#define IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1__ICOUNTER_0_3_HI__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1__Reserved__SHIFT 0x10
+#define IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1__ICOUNTER_0_3_HI_MASK 0x0000FFFFL
+#define IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1__Reserved_MASK 0xFFFF0000L
+//IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CSOURCE_0_3__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__Reserved1__SHIFT 0x8
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__COUNT_UNITS_0_3__SHIFT 0x1e
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CAC_0_3__SHIFT 0x1f
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CSOURCE_0_3_MASK 0x000000FFL
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__Reserved1_MASK 0x3FFFFF00L
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__COUNT_UNITS_0_3_MASK 0x40000000L
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CAC_0_3_MASK 0x80000000L
+//IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASID_MATCH_0_3__SHIFT 0x0
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASMEN_0_3__SHIFT 0x1f
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASID_MATCH_0_3_MASK 0x0000FFFFL
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASMEN_0_3_MASK 0x80000000L
+//IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__PASID_MASK_0_3__SHIFT 0x0
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__PASID_MASK_0_3_MASK 0x0000FFFFL
+#define IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMAIN_MATCH_0_3__SHIFT 0x0
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMMEN_0_3__SHIFT 0x1f
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMAIN_MATCH_0_3_MASK 0x0000FFFFL
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMMEN_0_3_MASK 0x80000000L
+//IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__DOMAIN_MASK_0_3__SHIFT 0x0
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__DOMAIN_MASK_0_3_MASK 0x0000FFFFL
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DEVICEID_MATCH_0_3__SHIFT 0x0
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT 0x10
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DIDMEN_0_3__SHIFT 0x1f
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DEVICEID_MATCH_0_3_MASK 0x0000FFFFL
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DIDMEN_0_3_MASK 0x80000000L
+//IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__DEVICEID_MASK_0_3__SHIFT 0x0
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT 0x10
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__DEVICEID_MASK_0_3_MASK 0x0000FFFFL
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0
+#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0__EVENT_NOTE_0_3_LO__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0__EVENT_NOTE_0_3_LO_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1
+#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__EVENT_NOTE_0_3_HI__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__Reserved0__SHIFT 0x14
+#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__CERE_0_3__SHIFT 0x1f
+#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__EVENT_NOTE_0_3_HI_MASK 0x000FFFFFL
+#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__Reserved0_MASK 0x7FF00000L
+#define IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__CERE_0_3_MASK 0x80000000L
+//IOMMU_MMIO_COUNTER_BANK_1_CNT_0_0
+#define IOMMU_MMIO_COUNTER_BANK_1_CNT_0_0__ICOUNTER_1_0_LO__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_BANK_1_CNT_0_0__ICOUNTER_1_0_LO_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1
+#define IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1__ICOUNTER_1_0_HI__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1__Reserved__SHIFT 0x10
+#define IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1__ICOUNTER_1_0_HI_MASK 0x0000FFFFL
+#define IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1__Reserved_MASK 0xFFFF0000L
+//IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CSOURCE_1_0__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__Reserved1__SHIFT 0x8
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__COUNT_UNITS_1_0__SHIFT 0x1e
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CAC_1_0__SHIFT 0x1f
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CSOURCE_1_0_MASK 0x000000FFL
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__Reserved1_MASK 0x3FFFFF00L
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__COUNT_UNITS_1_0_MASK 0x40000000L
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CAC_1_0_MASK 0x80000000L
+//IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASID_MATCH_1_0__SHIFT 0x0
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASMEN_1_0__SHIFT 0x1f
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASID_MATCH_1_0_MASK 0x0000FFFFL
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASMEN_1_0_MASK 0x80000000L
+//IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__PASID_MASK_1_0__SHIFT 0x0
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__PASID_MASK_1_0_MASK 0x0000FFFFL
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMAIN_MATCH_1_0__SHIFT 0x0
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMMEN_1_0__SHIFT 0x1f
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMAIN_MATCH_1_0_MASK 0x0000FFFFL
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMMEN_1_0_MASK 0x80000000L
+//IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__DOMAIN_MASK_1_0__SHIFT 0x0
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__DOMAIN_MASK_1_0_MASK 0x0000FFFFL
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DEVICEID_MATCH_1_0__SHIFT 0x0
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT 0x10
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DIDMEN_1_0__SHIFT 0x1f
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DEVICEID_MATCH_1_0_MASK 0x0000FFFFL
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DIDMEN_1_0_MASK 0x80000000L
+//IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__DEVICEID_MASK_1_0__SHIFT 0x0
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT 0x10
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__DEVICEID_MASK_1_0_MASK 0x0000FFFFL
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0
+#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0__EVENT_NOTE_1_0_LO__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0__EVENT_NOTE_1_0_LO_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1
+#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__EVENT_NOTE_1_0_HI__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__Reserved0__SHIFT 0x14
+#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__CERE_1_0__SHIFT 0x1f
+#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__EVENT_NOTE_1_0_HI_MASK 0x000FFFFFL
+#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__Reserved0_MASK 0x7FF00000L
+#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__CERE_1_0_MASK 0x80000000L
+//IOMMU_MMIO_COUNTER_BANK_1_CNT_1_0
+#define IOMMU_MMIO_COUNTER_BANK_1_CNT_1_0__ICOUNTER_1_1_LO__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_BANK_1_CNT_1_0__ICOUNTER_1_1_LO_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1
+#define IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1__ICOUNTER_1_1_HI__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1__Reserved__SHIFT 0x10
+#define IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1__ICOUNTER_1_1_HI_MASK 0x0000FFFFL
+#define IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1__Reserved_MASK 0xFFFF0000L
+//IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CSOURCE_1_1__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__Reserved1__SHIFT 0x8
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__COUNT_UNITS_1_1__SHIFT 0x1e
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CAC_1_1__SHIFT 0x1f
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CSOURCE_1_1_MASK 0x000000FFL
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__Reserved1_MASK 0x3FFFFF00L
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__COUNT_UNITS_1_1_MASK 0x40000000L
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CAC_1_1_MASK 0x80000000L
+//IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASID_MATCH_1_1__SHIFT 0x0
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASMEN_1_1__SHIFT 0x1f
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASID_MATCH_1_1_MASK 0x0000FFFFL
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASMEN_1_1_MASK 0x80000000L
+//IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__PASID_MASK_1_1__SHIFT 0x0
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__PASID_MASK_1_1_MASK 0x0000FFFFL
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMAIN_MATCH_1_1__SHIFT 0x0
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMMEN_1_1__SHIFT 0x1f
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMAIN_MATCH_1_1_MASK 0x0000FFFFL
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMMEN_1_1_MASK 0x80000000L
+//IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__DOMAIN_MASK_1_1__SHIFT 0x0
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__DOMAIN_MASK_1_1_MASK 0x0000FFFFL
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DEVICEID_MATCH_1_1__SHIFT 0x0
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT 0x10
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DIDMEN_1_1__SHIFT 0x1f
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DEVICEID_MATCH_1_1_MASK 0x0000FFFFL
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DIDMEN_1_1_MASK 0x80000000L
+//IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__DEVICEID_MASK_1_1__SHIFT 0x0
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT 0x10
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__DEVICEID_MASK_1_1_MASK 0x0000FFFFL
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0
+#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0__EVENT_NOTE_1_1_LO__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0__EVENT_NOTE_1_1_LO_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1
+#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__EVENT_NOTE_1_1_HI__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__Reserved0__SHIFT 0x14
+#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__CERE_1_1__SHIFT 0x1f
+#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__EVENT_NOTE_1_1_HI_MASK 0x000FFFFFL
+#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__Reserved0_MASK 0x7FF00000L
+#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__CERE_1_1_MASK 0x80000000L
+//IOMMU_MMIO_COUNTER_BANK_1_CNT_2_0
+#define IOMMU_MMIO_COUNTER_BANK_1_CNT_2_0__ICOUNTER_1_2_LO__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_BANK_1_CNT_2_0__ICOUNTER_1_2_LO_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1
+#define IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1__ICOUNTER_1_2_HI__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1__Reserved__SHIFT 0x10
+#define IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1__ICOUNTER_1_2_HI_MASK 0x0000FFFFL
+#define IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1__Reserved_MASK 0xFFFF0000L
+//IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CSOURCE_1_2__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__Reserved1__SHIFT 0x8
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__COUNT_UNITS_1_2__SHIFT 0x1e
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CAC_1_2__SHIFT 0x1f
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CSOURCE_1_2_MASK 0x000000FFL
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__Reserved1_MASK 0x3FFFFF00L
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__COUNT_UNITS_1_2_MASK 0x40000000L
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CAC_1_2_MASK 0x80000000L
+//IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASID_MATCH_1_2__SHIFT 0x0
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASMEN_1_2__SHIFT 0x1f
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASID_MATCH_1_2_MASK 0x0000FFFFL
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASMEN_1_2_MASK 0x80000000L
+//IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__PASID_MASK_1_2__SHIFT 0x0
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__PASID_MASK_1_2_MASK 0x0000FFFFL
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMAIN_MATCH_1_2__SHIFT 0x0
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMMEN_1_2__SHIFT 0x1f
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMAIN_MATCH_1_2_MASK 0x0000FFFFL
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMMEN_1_2_MASK 0x80000000L
+//IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__DOMAIN_MASK_1_2__SHIFT 0x0
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__DOMAIN_MASK_1_2_MASK 0x0000FFFFL
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DEVICEID_MATCH_1_2__SHIFT 0x0
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT 0x10
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DIDMEN_1_2__SHIFT 0x1f
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DEVICEID_MATCH_1_2_MASK 0x0000FFFFL
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DIDMEN_1_2_MASK 0x80000000L
+//IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__DEVICEID_MASK_1_2__SHIFT 0x0
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT 0x10
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__DEVICEID_MASK_1_2_MASK 0x0000FFFFL
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0
+#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0__EVENT_NOTE_1_2_LO__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0__EVENT_NOTE_1_2_LO_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1
+#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__EVENT_NOTE_1_2_HI__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__Reserved0__SHIFT 0x14
+#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__CERE_1_2__SHIFT 0x1f
+#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__EVENT_NOTE_1_2_HI_MASK 0x000FFFFFL
+#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__Reserved0_MASK 0x7FF00000L
+#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__CERE_1_2_MASK 0x80000000L
+//IOMMU_MMIO_COUNTER_BANK_1_CNT_3_0
+#define IOMMU_MMIO_COUNTER_BANK_1_CNT_3_0__ICOUNTER_1_3_LO__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_BANK_1_CNT_3_0__ICOUNTER_1_3_LO_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1
+#define IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1__ICOUNTER_1_3_HI__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1__Reserved__SHIFT 0x10
+#define IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1__ICOUNTER_1_3_HI_MASK 0x0000FFFFL
+#define IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1__Reserved_MASK 0xFFFF0000L
+//IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CSOURCE_1_3__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__Reserved1__SHIFT 0x8
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__COUNT_UNITS_1_3__SHIFT 0x1e
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CAC_1_3__SHIFT 0x1f
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CSOURCE_1_3_MASK 0x000000FFL
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__Reserved1_MASK 0x3FFFFF00L
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__COUNT_UNITS_1_3_MASK 0x40000000L
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CAC_1_3_MASK 0x80000000L
+//IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1__Reserved0__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASID_MATCH_1_3__SHIFT 0x0
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASMEN_1_3__SHIFT 0x1f
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASID_MATCH_1_3_MASK 0x0000FFFFL
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASMEN_1_3_MASK 0x80000000L
+//IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__PASID_MASK_1_3__SHIFT 0x0
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__PASID_MASK_1_3_MASK 0x0000FFFFL
+#define IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMAIN_MATCH_1_3__SHIFT 0x0
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMMEN_1_3__SHIFT 0x1f
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMAIN_MATCH_1_3_MASK 0x0000FFFFL
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMMEN_1_3_MASK 0x80000000L
+//IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__DOMAIN_MASK_1_3__SHIFT 0x0
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__DOMAIN_MASK_1_3_MASK 0x0000FFFFL
+#define IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DEVICEID_MATCH_1_3__SHIFT 0x0
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT 0x10
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DIDMEN_1_3__SHIFT 0x1f
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DEVICEID_MATCH_1_3_MASK 0x0000FFFFL
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__Reserved1_MASK 0x7FFF0000L
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DIDMEN_1_3_MASK 0x80000000L
+//IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__DEVICEID_MASK_1_3__SHIFT 0x0
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT 0x10
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__DEVICEID_MASK_1_3_MASK 0x0000FFFFL
+#define IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__Reserved0_MASK 0xFFFF0000L
+//IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0
+#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0__EVENT_NOTE_1_3_LO__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0__EVENT_NOTE_1_3_LO_MASK 0xFFFFFFFFL
+//IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1
+#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__EVENT_NOTE_1_3_HI__SHIFT 0x0
+#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__Reserved0__SHIFT 0x14
+#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__CERE_1_3__SHIFT 0x1f
+#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__EVENT_NOTE_1_3_HI_MASK 0x000FFFFFL
+#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__Reserved0_MASK 0x7FF00000L
+#define IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__CERE_1_3_MASK 0x80000000L
+
+
+// addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec
+//NB_NBCFG2_NB_VENDOR_ID
+#define NB_NBCFG2_NB_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define NB_NBCFG2_NB_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//NB_NBCFG2_NB_DEVICE_ID
+#define NB_NBCFG2_NB_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define NB_NBCFG2_NB_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//NB_NBCFG2_NB_COMMAND
+#define NB_NBCFG2_NB_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define NB_NBCFG2_NB_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define NB_NBCFG2_NB_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define NB_NBCFG2_NB_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define NB_NBCFG2_NB_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define NB_NBCFG2_NB_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+//NB_NBCFG2_NB_STATUS
+#define NB_NBCFG2_NB_STATUS__CAP_LIST__SHIFT 0x4
+#define NB_NBCFG2_NB_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define NB_NBCFG2_NB_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define NB_NBCFG2_NB_STATUS__CAP_LIST_MASK 0x0010L
+#define NB_NBCFG2_NB_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define NB_NBCFG2_NB_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+//NB_NBCFG2_NB_REVISION_ID
+#define NB_NBCFG2_NB_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define NB_NBCFG2_NB_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define NB_NBCFG2_NB_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define NB_NBCFG2_NB_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//NB_NBCFG2_NB_REGPROG_INF
+#define NB_NBCFG2_NB_REGPROG_INF__REG_LEVEL_PROG_INF__SHIFT 0x0
+#define NB_NBCFG2_NB_REGPROG_INF__REG_LEVEL_PROG_INF_MASK 0xFFL
+//NB_NBCFG2_NB_SUB_CLASS
+#define NB_NBCFG2_NB_SUB_CLASS__SUB_CLASS_INF__SHIFT 0x0
+#define NB_NBCFG2_NB_SUB_CLASS__SUB_CLASS_INF_MASK 0xFFL
+//NB_NBCFG2_NB_BASE_CODE
+#define NB_NBCFG2_NB_BASE_CODE__BASE_CLASS_CODE__SHIFT 0x0
+#define NB_NBCFG2_NB_BASE_CODE__BASE_CLASS_CODE_MASK 0xFFL
+//NB_NBCFG2_NB_CACHE_LINE
+#define NB_NBCFG2_NB_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define NB_NBCFG2_NB_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//NB_NBCFG2_NB_LATENCY
+#define NB_NBCFG2_NB_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define NB_NBCFG2_NB_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//NB_NBCFG2_NB_HEADER
+#define NB_NBCFG2_NB_HEADER__HEADER_TYPE__SHIFT 0x0
+#define NB_NBCFG2_NB_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define NB_NBCFG2_NB_HEADER__HEADER_TYPE_MASK 0x7FL
+#define NB_NBCFG2_NB_HEADER__DEVICE_TYPE_MASK 0x80L
+//NB_NBCFG2_NB_ADAPTER_ID
+#define NB_NBCFG2_NB_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define NB_NBCFG2_NB_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define NB_NBCFG2_NB_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define NB_NBCFG2_NB_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//NB_NBCFG2_NB_CAPABILITIES_PTR
+#define NB_NBCFG2_NB_CAPABILITIES_PTR__CAP_PTR__SHIFT 0x0
+#define NB_NBCFG2_NB_CAPABILITIES_PTR__CAP_PTR_MASK 0x000000FFL
+//NB_NBCFG2_NB_HEADER_W
+#define NB_NBCFG2_NB_HEADER_W__DEVICE_TYPE__SHIFT 0x7
+#define NB_NBCFG2_NB_HEADER_W__DEVICE_TYPE_MASK 0x00000080L
+//NB_NBCFG2_NB_PCI_CTRL
+#define NB_NBCFG2_NB_PCI_CTRL__PMEDis__SHIFT 0x4
+#define NB_NBCFG2_NB_PCI_CTRL__SErrDis__SHIFT 0x5
+#define NB_NBCFG2_NB_PCI_CTRL__MMIOEnable__SHIFT 0x17
+#define NB_NBCFG2_NB_PCI_CTRL__HPDis__SHIFT 0x1a
+#define NB_NBCFG2_NB_PCI_CTRL__PMEDis_MASK 0x00000010L
+#define NB_NBCFG2_NB_PCI_CTRL__SErrDis_MASK 0x00000020L
+#define NB_NBCFG2_NB_PCI_CTRL__MMIOEnable_MASK 0x00800000L
+#define NB_NBCFG2_NB_PCI_CTRL__HPDis_MASK 0x04000000L
+//NB_NBCFG2_NB_ADAPTER_ID_W
+#define NB_NBCFG2_NB_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define NB_NBCFG2_NB_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define NB_NBCFG2_NB_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define NB_NBCFG2_NB_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//NB_NBCFG2_NB_SMN_INDEX_EXTENSION_0
+#define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_0__NB_SMN_INDEX_EXTENSION_0__SHIFT 0x0
+#define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_0__NB_SMN_INDEX_EXTENSION_0_MASK 0x0000000FL
+//NB_NBCFG2_NB_SMN_INDEX_0
+#define NB_NBCFG2_NB_SMN_INDEX_0__NB_SMN_INDEX_0__SHIFT 0x0
+#define NB_NBCFG2_NB_SMN_INDEX_0__NB_SMN_INDEX_0_MASK 0xFFFFFFFFL
+//NB_NBCFG2_NB_SMN_DATA_0
+#define NB_NBCFG2_NB_SMN_DATA_0__NB_SMN_DATA_0__SHIFT 0x0
+#define NB_NBCFG2_NB_SMN_DATA_0__NB_SMN_DATA_0_MASK 0xFFFFFFFFL
+//NB_NBCFG2_NBCFG_SCRATCH_0
+#define NB_NBCFG2_NBCFG_SCRATCH_0__NBCFG_SCRATCH_0__SHIFT 0x0
+#define NB_NBCFG2_NBCFG_SCRATCH_0__NBCFG_SCRATCH_0_MASK 0xFFFFFFFFL
+//NB_NBCFG2_NBCFG_SCRATCH_1
+#define NB_NBCFG2_NBCFG_SCRATCH_1__NBCFG_SCRATCH_1__SHIFT 0x0
+#define NB_NBCFG2_NBCFG_SCRATCH_1__NBCFG_SCRATCH_1_MASK 0xFFFFFFFFL
+//NB_NBCFG2_NBCFG_SCRATCH_2
+#define NB_NBCFG2_NBCFG_SCRATCH_2__NBCFG_SCRATCH_2__SHIFT 0x0
+#define NB_NBCFG2_NBCFG_SCRATCH_2__NBCFG_SCRATCH_2_MASK 0xFFFFFFFFL
+//NB_NBCFG2_NBCFG_SCRATCH_3
+#define NB_NBCFG2_NBCFG_SCRATCH_3__NBCFG_SCRATCH_3__SHIFT 0x0
+#define NB_NBCFG2_NBCFG_SCRATCH_3__NBCFG_SCRATCH_3_MASK 0xFFFFFFFFL
+//NB_NBCFG2_NBCFG_SCRATCH_4
+#define NB_NBCFG2_NBCFG_SCRATCH_4__NBCFG_SCRATCH_4__SHIFT 0x0
+#define NB_NBCFG2_NBCFG_SCRATCH_4__NBCFG_SCRATCH_4_MASK 0xFFFFFFFFL
+//NB_NBCFG2_NB_PCI_ARB
+#define NB_NBCFG2_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3
+#define NB_NBCFG2_NB_PCI_ARB__PMEMode__SHIFT 0x8
+#define NB_NBCFG2_NB_PCI_ARB__PMETurnOff__SHIFT 0x9
+#define NB_NBCFG2_NB_PCI_ARB__PMETOAckStatus__SHIFT 0xa
+#define NB_NBCFG2_NB_PCI_ARB__PMETarget__SHIFT 0x10
+#define NB_NBCFG2_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L
+#define NB_NBCFG2_NB_PCI_ARB__PMEMode_MASK 0x00000100L
+#define NB_NBCFG2_NB_PCI_ARB__PMETurnOff_MASK 0x00000200L
+#define NB_NBCFG2_NB_PCI_ARB__PMETOAckStatus_MASK 0x00000400L
+#define NB_NBCFG2_NB_PCI_ARB__PMETarget_MASK 0x00FF0000L
+//NB_NBCFG2_NB_DRAM_SLOT1_BASE
+#define NB_NBCFG2_NB_DRAM_SLOT1_BASE__DRAM_BASE__SHIFT 0x17
+#define NB_NBCFG2_NB_DRAM_SLOT1_BASE__DRAM_BASE_MASK 0xFF800000L
+//NB_NBCFG2_NB_TOP_OF_DRAM_SLOT1
+#define NB_NBCFG2_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_BIT_32__SHIFT 0x0
+#define NB_NBCFG2_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17
+#define NB_NBCFG2_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_BIT_32_MASK 0x00000001L
+#define NB_NBCFG2_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L
+//NB_NBCFG2_NB_SMN_INDEX_EXTENSION_1
+#define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_1__NB_SMN_INDEX_EXTENSION_1__SHIFT 0x0
+#define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_1__NB_SMN_INDEX_EXTENSION_1_MASK 0x0000000FL
+//NB_NBCFG2_NB_SMN_INDEX_1
+#define NB_NBCFG2_NB_SMN_INDEX_1__NB_SMN_INDEX_1__SHIFT 0x0
+#define NB_NBCFG2_NB_SMN_INDEX_1__NB_SMN_INDEX_1_MASK 0xFFFFFFFFL
+//NB_NBCFG2_NB_SMN_DATA_1
+#define NB_NBCFG2_NB_SMN_DATA_1__NB_SMN_DATA_1__SHIFT 0x0
+#define NB_NBCFG2_NB_SMN_DATA_1__NB_SMN_DATA_1_MASK 0xFFFFFFFFL
+//NB_NBCFG2_NB_INDEX_DATA_MUTEX0
+#define NB_NBCFG2_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0__SHIFT 0x0
+#define NB_NBCFG2_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_UNLOCK__SHIFT 0x1f
+#define NB_NBCFG2_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_MASK 0x7FFFFFFFL
+#define NB_NBCFG2_NB_INDEX_DATA_MUTEX0__NB_INDEX_DATA_MUTEX0_UNLOCK_MASK 0x80000000L
+//NB_NBCFG2_NB_INDEX_DATA_MUTEX1
+#define NB_NBCFG2_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1__SHIFT 0x0
+#define NB_NBCFG2_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_UNLOCK__SHIFT 0x1f
+#define NB_NBCFG2_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_MASK 0x7FFFFFFFL
+#define NB_NBCFG2_NB_INDEX_DATA_MUTEX1__NB_INDEX_DATA_MUTEX1_UNLOCK_MASK 0x80000000L
+//NB_NBCFG2_NB_SMN_INDEX_EXTENSION_2
+#define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_2__NB_SMN_INDEX_EXTENSION_2__SHIFT 0x0
+#define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_2__NB_SMN_INDEX_EXTENSION_2_MASK 0x0000000FL
+//NB_NBCFG2_NB_SMN_INDEX_2
+#define NB_NBCFG2_NB_SMN_INDEX_2__NB_SMN_INDEX_2__SHIFT 0x0
+#define NB_NBCFG2_NB_SMN_INDEX_2__NB_SMN_INDEX_2_MASK 0xFFFFFFFFL
+//NB_NBCFG2_NB_SMN_DATA_2
+#define NB_NBCFG2_NB_SMN_DATA_2__NB_SMN_DATA_2__SHIFT 0x0
+#define NB_NBCFG2_NB_SMN_DATA_2__NB_SMN_DATA_2_MASK 0xFFFFFFFFL
+//NB_NBCFG2_NB_SMN_INDEX_EXTENSION_3
+#define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_3__NB_SMN_INDEX_EXTENSION_3__SHIFT 0x0
+#define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_3__NB_SMN_INDEX_EXTENSION_3_MASK 0x0000000FL
+//NB_NBCFG2_NB_SMN_INDEX_3
+#define NB_NBCFG2_NB_SMN_INDEX_3__NB_SMN_INDEX_3__SHIFT 0x0
+#define NB_NBCFG2_NB_SMN_INDEX_3__NB_SMN_INDEX_3_MASK 0xFFFFFFFFL
+//NB_NBCFG2_NB_SMN_DATA_3
+#define NB_NBCFG2_NB_SMN_DATA_3__NB_SMN_DATA_3__SHIFT 0x0
+#define NB_NBCFG2_NB_SMN_DATA_3__NB_SMN_DATA_3_MASK 0xFFFFFFFFL
+//NB_NBCFG2_NB_SMN_INDEX_EXTENSION_4
+#define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_4__NB_SMN_INDEX_EXTENSION_4__SHIFT 0x0
+#define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_4__NB_SMN_INDEX_EXTENSION_4_MASK 0x0000000FL
+//NB_NBCFG2_NB_SMN_INDEX_4
+#define NB_NBCFG2_NB_SMN_INDEX_4__NB_SMN_INDEX_4__SHIFT 0x0
+#define NB_NBCFG2_NB_SMN_INDEX_4__NB_SMN_INDEX_4_MASK 0xFFFFFFFFL
+//NB_NBCFG2_NB_SMN_DATA_4
+#define NB_NBCFG2_NB_SMN_DATA_4__NB_SMN_DATA_4__SHIFT 0x0
+#define NB_NBCFG2_NB_SMN_DATA_4__NB_SMN_DATA_4_MASK 0xFFFFFFFFL
+//NB_NBCFG2_NB_SMN_INDEX_EXTENSION_5
+#define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_5__NB_SMN_INDEX_EXTENSION_5__SHIFT 0x0
+#define NB_NBCFG2_NB_SMN_INDEX_EXTENSION_5__NB_SMN_INDEX_EXTENSION_5_MASK 0x0000000FL
+//NB_NBCFG2_NB_SMN_INDEX_5
+#define NB_NBCFG2_NB_SMN_INDEX_5__NB_SMN_INDEX_5__SHIFT 0x0
+#define NB_NBCFG2_NB_SMN_INDEX_5__NB_SMN_INDEX_5_MASK 0xFFFFFFFFL
+//NB_NBCFG2_NB_SMN_DATA_5
+#define NB_NBCFG2_NB_SMN_DATA_5__NB_SMN_DATA_5__SHIFT 0x0
+#define NB_NBCFG2_NB_SMN_DATA_5__NB_SMN_DATA_5_MASK 0xFFFFFFFFL
+//NB_NBCFG2_NB_PERF_CNT_CTRL
+#define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_CNT_EN__SHIFT 0x0
+#define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_SHADOW_WR__SHIFT 0x1
+#define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET__SHIFT 0x2
+#define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY__SHIFT 0x8
+#define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY_EN__SHIFT 0xf
+#define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY__SHIFT 0x10
+#define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY_EN__SHIFT 0x17
+#define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_CNT_EN_MASK 0x00000001L
+#define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_SHADOW_WR_MASK 0x00000002L
+#define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_MASK 0x00000004L
+#define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY_MASK 0x00000F00L
+#define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_SHADOW_DELAY_EN_MASK 0x00008000L
+#define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY_MASK 0x000F0000L
+#define NB_NBCFG2_NB_PERF_CNT_CTRL__GLOBE_PERF_RESET_DELAY_EN_MASK 0x00800000L
+//NB_NBCFG2_NB_SMN_INDEX_6
+#define NB_NBCFG2_NB_SMN_INDEX_6__NB_SMN_INDEX_6__SHIFT 0x0
+#define NB_NBCFG2_NB_SMN_INDEX_6__NB_SMN_INDEX_6_MASK 0xFFFFFFFFL
+//NB_NBCFG2_NB_SMN_DATA_6
+#define NB_NBCFG2_NB_SMN_DATA_6__NB_SMN_DATA_6__SHIFT 0x0
+#define NB_NBCFG2_NB_SMN_DATA_6__NB_SMN_DATA_6_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_iohub_iommu_l2_iommul2cfg
+//IOMMU_L2_2_IOMMU_VENDOR_ID
+#define IOMMU_L2_2_IOMMU_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//IOMMU_L2_2_IOMMU_DEVICE_ID
+#define IOMMU_L2_2_IOMMU_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//IOMMU_L2_2_IOMMU_COMMAND
+#define IOMMU_L2_2_IOMMU_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define IOMMU_L2_2_IOMMU_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define IOMMU_L2_2_IOMMU_COMMAND__Reserved1__SHIFT 0x3
+#define IOMMU_L2_2_IOMMU_COMMAND__PARITY_ERROR_EN__SHIFT 0x6
+#define IOMMU_L2_2_IOMMU_COMMAND__Reserved0__SHIFT 0x7
+#define IOMMU_L2_2_IOMMU_COMMAND__SERR_EN__SHIFT 0x8
+#define IOMMU_L2_2_IOMMU_COMMAND__Reserved2__SHIFT 0x9
+#define IOMMU_L2_2_IOMMU_COMMAND__INTERRUPT_DIS__SHIFT 0xa
+#define IOMMU_L2_2_IOMMU_COMMAND__Reserved__SHIFT 0xb
+#define IOMMU_L2_2_IOMMU_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define IOMMU_L2_2_IOMMU_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define IOMMU_L2_2_IOMMU_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define IOMMU_L2_2_IOMMU_COMMAND__Reserved1_MASK 0x0038L
+#define IOMMU_L2_2_IOMMU_COMMAND__PARITY_ERROR_EN_MASK 0x0040L
+#define IOMMU_L2_2_IOMMU_COMMAND__Reserved0_MASK 0x0080L
+#define IOMMU_L2_2_IOMMU_COMMAND__SERR_EN_MASK 0x0100L
+#define IOMMU_L2_2_IOMMU_COMMAND__Reserved2_MASK 0x0200L
+#define IOMMU_L2_2_IOMMU_COMMAND__INTERRUPT_DIS_MASK 0x0400L
+#define IOMMU_L2_2_IOMMU_COMMAND__Reserved_MASK 0xF800L
+//IOMMU_L2_2_IOMMU_STATUS
+#define IOMMU_L2_2_IOMMU_STATUS__Reserved__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_STATUS__INT_Status__SHIFT 0x3
+#define IOMMU_L2_2_IOMMU_STATUS__CAP_LIST__SHIFT 0x4
+#define IOMMU_L2_2_IOMMU_STATUS__Reserved1__SHIFT 0x5
+#define IOMMU_L2_2_IOMMU_STATUS__MASTER_DATA_ERROR__SHIFT 0x8
+#define IOMMU_L2_2_IOMMU_STATUS__Reserved2__SHIFT 0x9
+#define IOMMU_L2_2_IOMMU_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define IOMMU_L2_2_IOMMU_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define IOMMU_L2_2_IOMMU_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define IOMMU_L2_2_IOMMU_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define IOMMU_L2_2_IOMMU_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define IOMMU_L2_2_IOMMU_STATUS__Reserved_MASK 0x0007L
+#define IOMMU_L2_2_IOMMU_STATUS__INT_Status_MASK 0x0008L
+#define IOMMU_L2_2_IOMMU_STATUS__CAP_LIST_MASK 0x0010L
+#define IOMMU_L2_2_IOMMU_STATUS__Reserved1_MASK 0x00E0L
+#define IOMMU_L2_2_IOMMU_STATUS__MASTER_DATA_ERROR_MASK 0x0100L
+#define IOMMU_L2_2_IOMMU_STATUS__Reserved2_MASK 0x0600L
+#define IOMMU_L2_2_IOMMU_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define IOMMU_L2_2_IOMMU_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define IOMMU_L2_2_IOMMU_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define IOMMU_L2_2_IOMMU_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define IOMMU_L2_2_IOMMU_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//IOMMU_L2_2_IOMMU_REVISION_ID
+#define IOMMU_L2_2_IOMMU_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define IOMMU_L2_2_IOMMU_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define IOMMU_L2_2_IOMMU_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//IOMMU_L2_2_IOMMU_REGPROG_INF
+#define IOMMU_L2_2_IOMMU_REGPROG_INF__REG_LEVEL_PROG_INF__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_REGPROG_INF__REG_LEVEL_PROG_INF_MASK 0xFFL
+//IOMMU_L2_2_IOMMU_SUB_CLASS
+#define IOMMU_L2_2_IOMMU_SUB_CLASS__SUB_CLASS_INF__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_SUB_CLASS__SUB_CLASS_INF_MASK 0xFFL
+//IOMMU_L2_2_IOMMU_BASE_CODE
+#define IOMMU_L2_2_IOMMU_BASE_CODE__BASE_CLASS_CODE__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_BASE_CODE__BASE_CLASS_CODE_MASK 0xFFL
+//IOMMU_L2_2_IOMMU_CACHE_LINE
+#define IOMMU_L2_2_IOMMU_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//IOMMU_L2_2_IOMMU_LATENCY
+#define IOMMU_L2_2_IOMMU_LATENCY__LATENCY__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_LATENCY__LATENCY_MASK 0xFFL
+//IOMMU_L2_2_IOMMU_HEADER
+#define IOMMU_L2_2_IOMMU_HEADER__HEADER_TYPE__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_HEADER__HEADER_TYPE_MASK 0xFFL
+//IOMMU_L2_2_IOMMU_BIST
+#define IOMMU_L2_2_IOMMU_BIST__BIST_COMP__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_BIST__BIST_STRT__SHIFT 0x6
+#define IOMMU_L2_2_IOMMU_BIST__BIST_CAP__SHIFT 0x7
+#define IOMMU_L2_2_IOMMU_BIST__BIST_COMP_MASK 0x0FL
+#define IOMMU_L2_2_IOMMU_BIST__BIST_STRT_MASK 0x40L
+#define IOMMU_L2_2_IOMMU_BIST__BIST_CAP_MASK 0x80L
+//IOMMU_L2_2_IOMMU_ADAPTER_ID
+#define IOMMU_L2_2_IOMMU_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define IOMMU_L2_2_IOMMU_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define IOMMU_L2_2_IOMMU_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//IOMMU_L2_2_IOMMU_CAPABILITIES_PTR
+#define IOMMU_L2_2_IOMMU_CAPABILITIES_PTR__CAP_PTR__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_CAPABILITIES_PTR__CAP_PTR_MASK 0x000000FFL
+//IOMMU_L2_2_IOMMU_INTERRUPT_LINE
+#define IOMMU_L2_2_IOMMU_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//IOMMU_L2_2_IOMMU_INTERRUPT_PIN
+#define IOMMU_L2_2_IOMMU_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//IOMMU_L2_2_IOMMU_CAP_HEADER
+#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_ID__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_PTR__SHIFT 0x8
+#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_TYPE__SHIFT 0x10
+#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_REV__SHIFT 0x13
+#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_IO_TLBSUP__SHIFT 0x18
+#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_HT_TUNNEL_SUP__SHIFT 0x19
+#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_NP_CACHE__SHIFT 0x1a
+#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_EFR_SUP__SHIFT 0x1b
+#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_EXT__SHIFT 0x1c
+#define IOMMU_L2_2_IOMMU_CAP_HEADER__Reserved__SHIFT 0x1d
+#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_ID_MASK 0x000000FFL
+#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_PTR_MASK 0x0000FF00L
+#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_TYPE_MASK 0x00070000L
+#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_REV_MASK 0x00F80000L
+#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_IO_TLBSUP_MASK 0x01000000L
+#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_HT_TUNNEL_SUP_MASK 0x02000000L
+#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_NP_CACHE_MASK 0x04000000L
+#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_EFR_SUP_MASK 0x08000000L
+#define IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_EXT_MASK 0x10000000L
+#define IOMMU_L2_2_IOMMU_CAP_HEADER__Reserved_MASK 0xE0000000L
+//IOMMU_L2_2_IOMMU_CAP_BASE_LO
+#define IOMMU_L2_2_IOMMU_CAP_BASE_LO__IOMMU_ENABLE__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_CAP_BASE_LO__Reserved__SHIFT 0x1
+#define IOMMU_L2_2_IOMMU_CAP_BASE_LO__IOMMU_BASE_ADDR_LO__SHIFT 0x13
+#define IOMMU_L2_2_IOMMU_CAP_BASE_LO__IOMMU_ENABLE_MASK 0x00000001L
+#define IOMMU_L2_2_IOMMU_CAP_BASE_LO__Reserved_MASK 0x00003FFEL
+#define IOMMU_L2_2_IOMMU_CAP_BASE_LO__IOMMU_BASE_ADDR_LO_MASK 0xFFF80000L
+//IOMMU_L2_2_IOMMU_CAP_BASE_HI
+#define IOMMU_L2_2_IOMMU_CAP_BASE_HI__IOMMU_BASE_ADDR_HI__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_CAP_BASE_HI__IOMMU_BASE_ADDR_HI_MASK 0xFFFFFFFFL
+//IOMMU_L2_2_IOMMU_CAP_RANGE
+#define IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_UNIT_ID__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_CAP_RANGE__Reserved__SHIFT 0x5
+#define IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_RNG_VALID__SHIFT 0x7
+#define IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_BUS_NUMBER__SHIFT 0x8
+#define IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_FIRST_DEVICE__SHIFT 0x10
+#define IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_LAST_DEVICE__SHIFT 0x18
+#define IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_UNIT_ID_MASK 0x0000001FL
+#define IOMMU_L2_2_IOMMU_CAP_RANGE__Reserved_MASK 0x00000060L
+#define IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_RNG_VALID_MASK 0x00000080L
+#define IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_BUS_NUMBER_MASK 0x0000FF00L
+#define IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_FIRST_DEVICE_MASK 0x00FF0000L
+#define IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_LAST_DEVICE_MASK 0xFF000000L
+//IOMMU_L2_2_IOMMU_CAP_MISC
+#define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_MSI_NUM__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_GVA_SIZE__SHIFT 0x5
+#define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_PA_SIZE__SHIFT 0x8
+#define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_VA_SIZE__SHIFT 0xf
+#define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV__SHIFT 0x16
+#define IOMMU_L2_2_IOMMU_CAP_MISC__Reserved1__SHIFT 0x17
+#define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_MSI_NUM_PPR__SHIFT 0x1b
+#define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_MSI_NUM_MASK 0x0000001FL
+#define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_GVA_SIZE_MASK 0x000000E0L
+#define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_PA_SIZE_MASK 0x00007F00L
+#define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_VA_SIZE_MASK 0x003F8000L
+#define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV_MASK 0x00400000L
+#define IOMMU_L2_2_IOMMU_CAP_MISC__Reserved1_MASK 0x07800000L
+#define IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_MSI_NUM_PPR_MASK 0xF8000000L
+//IOMMU_L2_2_IOMMU_CAP_MISC_1
+#define IOMMU_L2_2_IOMMU_CAP_MISC_1__IOMMU_MSI_NUM_GA__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE__SHIFT 0x5
+#define IOMMU_L2_2_IOMMU_CAP_MISC_1__DVM_MODE__SHIFT 0x6
+#define IOMMU_L2_2_IOMMU_CAP_MISC_1__SMMUMMIO_EN__SHIFT 0xf
+#define IOMMU_L2_2_IOMMU_CAP_MISC_1__SMMUMMIO_LOCK__SHIFT 0x1f
+#define IOMMU_L2_2_IOMMU_CAP_MISC_1__IOMMU_MSI_NUM_GA_MASK 0x0000001FL
+#define IOMMU_L2_2_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE_MASK 0x00000020L
+#define IOMMU_L2_2_IOMMU_CAP_MISC_1__DVM_MODE_MASK 0x000000C0L
+#define IOMMU_L2_2_IOMMU_CAP_MISC_1__SMMUMMIO_EN_MASK 0x00008000L
+#define IOMMU_L2_2_IOMMU_CAP_MISC_1__SMMUMMIO_LOCK_MASK 0x80000000L
+//IOMMU_L2_2_IOMMU_MSI_CAP
+#define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_CAP_ID__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_CAP_PTR__SHIFT 0x8
+#define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_EN__SHIFT 0x10
+#define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_MULT_MESS_CAP__SHIFT 0x11
+#define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_MULT_MESS_EN__SHIFT 0x14
+#define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_64_EN__SHIFT 0x17
+#define IOMMU_L2_2_IOMMU_MSI_CAP__Reserved__SHIFT 0x18
+#define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_CAP_ID_MASK 0x000000FFL
+#define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_CAP_PTR_MASK 0x0000FF00L
+#define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_EN_MASK 0x00010000L
+#define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_MULT_MESS_CAP_MASK 0x000E0000L
+#define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_MULT_MESS_EN_MASK 0x00700000L
+#define IOMMU_L2_2_IOMMU_MSI_CAP__MSI_64_EN_MASK 0x00800000L
+#define IOMMU_L2_2_IOMMU_MSI_CAP__Reserved_MASK 0xFF000000L
+//IOMMU_L2_2_IOMMU_MSI_ADDR_LO
+#define IOMMU_L2_2_IOMMU_MSI_ADDR_LO__Reserved__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_MSI_ADDR_LO__MSI_ADDR_LO__SHIFT 0x2
+#define IOMMU_L2_2_IOMMU_MSI_ADDR_LO__Reserved_MASK 0x00000003L
+#define IOMMU_L2_2_IOMMU_MSI_ADDR_LO__MSI_ADDR_LO_MASK 0xFFFFFFFCL
+//IOMMU_L2_2_IOMMU_MSI_ADDR_HI
+#define IOMMU_L2_2_IOMMU_MSI_ADDR_HI__MSI_ADDR_HI__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_MSI_ADDR_HI__MSI_ADDR_HI_MASK 0xFFFFFFFFL
+//IOMMU_L2_2_IOMMU_MSI_DATA
+#define IOMMU_L2_2_IOMMU_MSI_DATA__MSI_DATA__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_MSI_DATA__Reserved__SHIFT 0x10
+#define IOMMU_L2_2_IOMMU_MSI_DATA__MSI_DATA_MASK 0x0000FFFFL
+#define IOMMU_L2_2_IOMMU_MSI_DATA__Reserved_MASK 0xFFFF0000L
+//IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP
+#define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_ID__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR__SHIFT 0x8
+#define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_EN__SHIFT 0x10
+#define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_FIXD__SHIFT 0x11
+#define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_RSV__SHIFT 0x12
+#define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE__SHIFT 0x1b
+#define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_ID_MASK 0x000000FFL
+#define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR_MASK 0x0000FF00L
+#define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_EN_MASK 0x00010000L
+#define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_FIXD_MASK 0x00020000L
+#define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_RSV_MASK 0x07FC0000L
+#define IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE_MASK 0xF8000000L
+//IOMMU_L2_2_IOMMU_ADAPTER_ID_W
+#define IOMMU_L2_2_IOMMU_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_W__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_ADAPTER_ID_W__SUBSYSTEM_ID_W__SHIFT 0x10
+#define IOMMU_L2_2_IOMMU_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_W_MASK 0x0000FFFFL
+#define IOMMU_L2_2_IOMMU_ADAPTER_ID_W__SUBSYSTEM_ID_W_MASK 0xFFFF0000L
+//IOMMU_L2_2_IOMMU_CONTROL_W
+#define IOMMU_L2_2_IOMMU_CONTROL_W__INTERRUPT_PIN_W__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_CONTROL_W__MINOR_REV_ID_W__SHIFT 0x4
+#define IOMMU_L2_2_IOMMU_CONTROL_W__IO_TLBSUP_W__SHIFT 0x8
+#define IOMMU_L2_2_IOMMU_CONTROL_W__EFR_SUP_W__SHIFT 0x9
+#define IOMMU_L2_2_IOMMU_CONTROL_W__MSI_MULT_MESS_CAP_W__SHIFT 0xa
+#define IOMMU_L2_2_IOMMU_CONTROL_W__IOMMU_CAP_EXT_W__SHIFT 0xd
+#define IOMMU_L2_2_IOMMU_CONTROL_W__INTERRUPT_PIN_W_MASK 0x00000007L
+#define IOMMU_L2_2_IOMMU_CONTROL_W__MINOR_REV_ID_W_MASK 0x000000F0L
+#define IOMMU_L2_2_IOMMU_CONTROL_W__IO_TLBSUP_W_MASK 0x00000100L
+#define IOMMU_L2_2_IOMMU_CONTROL_W__EFR_SUP_W_MASK 0x00000200L
+#define IOMMU_L2_2_IOMMU_CONTROL_W__MSI_MULT_MESS_CAP_W_MASK 0x00001C00L
+#define IOMMU_L2_2_IOMMU_CONTROL_W__IOMMU_CAP_EXT_W_MASK 0x00002000L
+//IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__PREF_SUP_W__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__PPR_SUP_W__SHIFT 0x1
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__Reserved3__SHIFT 0x2
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__NX_SUP_W__SHIFT 0x3
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__GT_SUP_W__SHIFT 0x4
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__Reserved2__SHIFT 0x5
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__IA_SUP_W__SHIFT 0x6
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__GA_SUP_W__SHIFT 0x7
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__HE_SUP_W__SHIFT 0x8
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__PC_SUP_W__SHIFT 0x9
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__HATS_W__SHIFT 0xa
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__US_SUP_W__SHIFT 0xc
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__Reserved5__SHIFT 0xd
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__GAM_SUP_W__SHIFT 0x15
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__PPRF_W__SHIFT 0x18
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__Reserved6__SHIFT 0x1a
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__EVENTF_W__SHIFT 0x1c
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__GLX_SUP_W__SHIFT 0x1e
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__PREF_SUP_W_MASK 0x00000001L
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__PPR_SUP_W_MASK 0x00000002L
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__Reserved3_MASK 0x00000004L
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__NX_SUP_W_MASK 0x00000008L
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__GT_SUP_W_MASK 0x00000010L
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__Reserved2_MASK 0x00000020L
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__IA_SUP_W_MASK 0x00000040L
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__GA_SUP_W_MASK 0x00000080L
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__HE_SUP_W_MASK 0x00000100L
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__PC_SUP_W_MASK 0x00000200L
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__HATS_W_MASK 0x00000C00L
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__US_SUP_W_MASK 0x00001000L
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__Reserved5_MASK 0x001FE000L
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__GAM_SUP_W_MASK 0x00E00000L
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__PPRF_W_MASK 0x03000000L
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__Reserved6_MASK 0x0C000000L
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__EVENTF_W_MASK 0x30000000L
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__GLX_SUP_W_MASK 0xC0000000L
+//IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__PAS_MAX_W__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__Reserved1__SHIFT 0x4
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__DTE_seg_W__SHIFT 0x6
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__PPR_OVERFLOW_EARLY_SUP_W__SHIFT 0x8
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__PPR_AUTORESP_SUP_W__SHIFT 0x9
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__BLOCK_STOPMARK_SUP_W__SHIFT 0xa
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__MARCnum_SUP_W__SHIFT 0xb
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__SNOOP_ATTRS_SUP_W__SHIFT 0xd
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__GIo_SUP_W__SHIFT 0xe
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__HA_SUP_W__SHIFT 0xf
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__EPH_SUP_W__SHIFT 0x10
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__ATTRFW_SUP_W__SHIFT 0x11
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__V2_HD_DIS_SUP_W__SHIFT 0x12
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__InvIotlbTypeSup_W__SHIFT 0x13
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__HD_SUP_W__SHIFT 0x14
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__Reserved__SHIFT 0x15
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__PAS_MAX_W_MASK 0x0000000FL
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__Reserved1_MASK 0x00000030L
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__DTE_seg_W_MASK 0x000000C0L
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__PPR_OVERFLOW_EARLY_SUP_W_MASK 0x00000100L
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__PPR_AUTORESP_SUP_W_MASK 0x00000200L
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__BLOCK_STOPMARK_SUP_W_MASK 0x00000400L
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__MARCnum_SUP_W_MASK 0x00001800L
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__SNOOP_ATTRS_SUP_W_MASK 0x00002000L
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__GIo_SUP_W_MASK 0x00004000L
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__HA_SUP_W_MASK 0x00008000L
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__EPH_SUP_W_MASK 0x00010000L
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__ATTRFW_SUP_W_MASK 0x00020000L
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__V2_HD_DIS_SUP_W_MASK 0x00040000L
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__InvIotlbTypeSup_W_MASK 0x00080000L
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__HD_SUP_W_MASK 0x00100000L
+#define IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__Reserved_MASK 0xFFE00000L
+//IOMMU_L2_2_IOMMU_RANGE_W
+#define IOMMU_L2_2_IOMMU_RANGE_W__Reserved__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_RANGE_W__RNG_VALID_W__SHIFT 0x7
+#define IOMMU_L2_2_IOMMU_RANGE_W__BUS_NUMBER_W__SHIFT 0x8
+#define IOMMU_L2_2_IOMMU_RANGE_W__FIRST_DEVICE_W__SHIFT 0x10
+#define IOMMU_L2_2_IOMMU_RANGE_W__LAST_DEVICE_W__SHIFT 0x18
+#define IOMMU_L2_2_IOMMU_RANGE_W__Reserved_MASK 0x0000007FL
+#define IOMMU_L2_2_IOMMU_RANGE_W__RNG_VALID_W_MASK 0x00000080L
+#define IOMMU_L2_2_IOMMU_RANGE_W__BUS_NUMBER_W_MASK 0x0000FF00L
+#define IOMMU_L2_2_IOMMU_RANGE_W__FIRST_DEVICE_W_MASK 0x00FF0000L
+#define IOMMU_L2_2_IOMMU_RANGE_W__LAST_DEVICE_W_MASK 0xFF000000L
+//IOMMU_L2_2_IOMMU_DSFX_CONTROL
+#define IOMMU_L2_2_IOMMU_DSFX_CONTROL__DSFXSup__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_DSFX_CONTROL__REVISION_MINOR__SHIFT 0x18
+#define IOMMU_L2_2_IOMMU_DSFX_CONTROL__REVISION_MAJOR__SHIFT 0x1c
+#define IOMMU_L2_2_IOMMU_DSFX_CONTROL__DSFXSup_MASK 0x00FFFFFFL
+#define IOMMU_L2_2_IOMMU_DSFX_CONTROL__REVISION_MINOR_MASK 0x0F000000L
+#define IOMMU_L2_2_IOMMU_DSFX_CONTROL__REVISION_MAJOR_MASK 0xF0000000L
+//IOMMU_L2_2_IOMMU_DSSX_DUMMY_0
+#define IOMMU_L2_2_IOMMU_DSSX_DUMMY_0__DSSX_status_set__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_DSSX_DUMMY_0__Reserved__SHIFT 0x18
+#define IOMMU_L2_2_IOMMU_DSSX_DUMMY_0__DSSX_status_set_MASK 0x00FFFFFFL
+#define IOMMU_L2_2_IOMMU_DSSX_DUMMY_0__Reserved_MASK 0xFF000000L
+//IOMMU_L2_2_IOMMU_DSCX_DUMMY_0
+#define IOMMU_L2_2_IOMMU_DSCX_DUMMY_0__DSCX_CNTRL_set__SHIFT 0x0
+#define IOMMU_L2_2_IOMMU_DSCX_DUMMY_0__Reserved__SHIFT 0x18
+#define IOMMU_L2_2_IOMMU_DSCX_DUMMY_0__DSCX_CNTRL_set_MASK 0x00FFFFFFL
+#define IOMMU_L2_2_IOMMU_DSCX_DUMMY_0__Reserved_MASK 0xFF000000L
+//IOMMU_L2_2_L2B_POISON_DVM_CNTRL
+#define IOMMU_L2_2_L2B_POISON_DVM_CNTRL__DVM_POISON_RESP_MODE__SHIFT 0x0
+#define IOMMU_L2_2_L2B_POISON_DVM_CNTRL__DVM_POISON_RESP_MODE_MASK 0x00000003L
+//IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control
+#define IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control__StallNPReqEn__SHIFT 0x0
+#define IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control__StallPReqEn__SHIFT 0x2
+#define IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control__StallMemReqEn__SHIFT 0x8
+#define IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn__SHIFT 0xe
+#define IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control__StallNPReqEn_MASK 0x00000003L
+#define IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control__StallPReqEn_MASK 0x0000000CL
+#define IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control__StallMemReqEn_MASK 0x00000300L
+#define IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn_MASK 0x0000C000L
+//IOMMU_L2_2_IOHC_L2_HostRsp_Stall_Control
+#define IOMMU_L2_2_IOHC_L2_HostRsp_Stall_Control__StallUpRdRspEn__SHIFT 0x4
+#define IOMMU_L2_2_IOHC_L2_HostRsp_Stall_Control__StallUpRdRspEn_MASK 0x00000030L
+//IOMMU_L2_2_SMMU_MMIO_IDR0_W
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__S2P_W__SHIFT 0x0
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__S1P_W__SHIFT 0x1
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__TTF_W__SHIFT 0x2
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__COHACC_W__SHIFT 0x4
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__BTM_W__SHIFT 0x5
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__HTTU_W__SHIFT 0x6
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__DORMHINT_W__SHIFT 0x8
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__Hyp_W__SHIFT 0x9
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__ATS_W__SHIFT 0xa
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__PERFCTRS_W__SHIFT 0xb
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__ASID16_W__SHIFT 0xc
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__MSI_W__SHIFT 0xd
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__SEV_W__SHIFT 0xe
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__ATOS_W__SHIFT 0xf
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__PRI_W__SHIFT 0x10
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__VMW_W__SHIFT 0x11
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__VMID16_W__SHIFT 0x12
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__CD2L_W__SHIFT 0x13
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__VATOS_W__SHIFT 0x14
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__TTENDIAN_W__SHIFT 0x15
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__STALL_MODEL_W__SHIFT 0x18
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__TERM_MODEL_W__SHIFT 0x1a
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__ST_LEVEL_W__SHIFT 0x1b
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__RAS_W__SHIFT 0x1d
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__S2P_W_MASK 0x00000001L
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__S1P_W_MASK 0x00000002L
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__TTF_W_MASK 0x0000000CL
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__COHACC_W_MASK 0x00000010L
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__BTM_W_MASK 0x00000020L
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__HTTU_W_MASK 0x000000C0L
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__DORMHINT_W_MASK 0x00000100L
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__Hyp_W_MASK 0x00000200L
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__ATS_W_MASK 0x00000400L
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__PERFCTRS_W_MASK 0x00000800L
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__ASID16_W_MASK 0x00001000L
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__MSI_W_MASK 0x00002000L
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__SEV_W_MASK 0x00004000L
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__ATOS_W_MASK 0x00008000L
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__PRI_W_MASK 0x00010000L
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__VMW_W_MASK 0x00020000L
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__VMID16_W_MASK 0x00040000L
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__CD2L_W_MASK 0x00080000L
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__VATOS_W_MASK 0x00100000L
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__TTENDIAN_W_MASK 0x00600000L
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__STALL_MODEL_W_MASK 0x03000000L
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__TERM_MODEL_W_MASK 0x04000000L
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__ST_LEVEL_W_MASK 0x18000000L
+#define IOMMU_L2_2_SMMU_MMIO_IDR0_W__RAS_W_MASK 0x20000000L
+//IOMMU_L2_2_SMMU_MMIO_IDR1_W
+#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__SIDSIZE_W__SHIFT 0x0
+#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__SSIDSIZE_W__SHIFT 0x6
+#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__PRIQS_W__SHIFT 0xb
+#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__EVENTQS_W__SHIFT 0x10
+#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__CMDQS_W__SHIFT 0x15
+#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__ATTR_PERMS_OVR_W__SHIFT 0x1a
+#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__ATTR_TYPES_OVR_W__SHIFT 0x1b
+#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__REL_W__SHIFT 0x1c
+#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__QUEUES_PRESET_W__SHIFT 0x1d
+#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__TABLES_PRESET_W__SHIFT 0x1e
+#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__SIDSIZE_W_MASK 0x0000003FL
+#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__SSIDSIZE_W_MASK 0x000007C0L
+#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__PRIQS_W_MASK 0x0000F800L
+#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__EVENTQS_W_MASK 0x001F0000L
+#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__CMDQS_W_MASK 0x03E00000L
+#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__ATTR_PERMS_OVR_W_MASK 0x04000000L
+#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__ATTR_TYPES_OVR_W_MASK 0x08000000L
+#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__REL_W_MASK 0x10000000L
+#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__QUEUES_PRESET_W_MASK 0x20000000L
+#define IOMMU_L2_2_SMMU_MMIO_IDR1_W__TABLES_PRESET_W_MASK 0x40000000L
+//IOMMU_L2_2_SMMU_MMIO_IDR2_W
+#define IOMMU_L2_2_SMMU_MMIO_IDR2_W__BA_VATOS_W__SHIFT 0x0
+#define IOMMU_L2_2_SMMU_MMIO_IDR2_W__BA_RAS_W__SHIFT 0xa
+#define IOMMU_L2_2_SMMU_MMIO_IDR2_W__BA_VATOS_W_MASK 0x000003FFL
+#define IOMMU_L2_2_SMMU_MMIO_IDR2_W__BA_RAS_W_MASK 0x000FFC00L
+//IOMMU_L2_2_SMMU_MMIO_IDR3_W
+#define IOMMU_L2_2_SMMU_MMIO_IDR3_W__HAD_W__SHIFT 0x2
+#define IOMMU_L2_2_SMMU_MMIO_IDR3_W__HAD_W_MASK 0x00000004L
+//IOMMU_L2_2_SMMU_MMIO_IDR5_W
+#define IOMMU_L2_2_SMMU_MMIO_IDR5_W__OAS_W__SHIFT 0x0
+#define IOMMU_L2_2_SMMU_MMIO_IDR5_W__GRAN4K_W__SHIFT 0x4
+#define IOMMU_L2_2_SMMU_MMIO_IDR5_W__GRAN16K_W__SHIFT 0x5
+#define IOMMU_L2_2_SMMU_MMIO_IDR5_W__GRAN64K_W__SHIFT 0x6
+#define IOMMU_L2_2_SMMU_MMIO_IDR5_W__STALL_MAX_W__SHIFT 0x10
+#define IOMMU_L2_2_SMMU_MMIO_IDR5_W__OAS_W_MASK 0x00000007L
+#define IOMMU_L2_2_SMMU_MMIO_IDR5_W__GRAN4K_W_MASK 0x00000010L
+#define IOMMU_L2_2_SMMU_MMIO_IDR5_W__GRAN16K_W_MASK 0x00000020L
+#define IOMMU_L2_2_SMMU_MMIO_IDR5_W__GRAN64K_W_MASK 0x00000040L
+#define IOMMU_L2_2_SMMU_MMIO_IDR5_W__STALL_MAX_W_MASK 0xFFFF0000L
+//IOMMU_L2_2_SMMU_MMIO_IIDR_W
+#define IOMMU_L2_2_SMMU_MMIO_IIDR_W__Implementer_W__SHIFT 0x0
+#define IOMMU_L2_2_SMMU_MMIO_IIDR_W__Revision_W__SHIFT 0xc
+#define IOMMU_L2_2_SMMU_MMIO_IIDR_W__Variant_W__SHIFT 0x10
+#define IOMMU_L2_2_SMMU_MMIO_IIDR_W__ProductID_W__SHIFT 0x14
+#define IOMMU_L2_2_SMMU_MMIO_IIDR_W__Implementer_W_MASK 0x00000FFFL
+#define IOMMU_L2_2_SMMU_MMIO_IIDR_W__Revision_W_MASK 0x0000F000L
+#define IOMMU_L2_2_SMMU_MMIO_IIDR_W__Variant_W_MASK 0x000F0000L
+#define IOMMU_L2_2_SMMU_MMIO_IIDR_W__ProductID_W_MASK 0xFFF00000L
+//IOMMU_L2_2_SMMU_AIDR_W
+#define IOMMU_L2_2_SMMU_AIDR_W__ArchMinorRev_W__SHIFT 0x0
+#define IOMMU_L2_2_SMMU_AIDR_W__ArchMajorRev_W__SHIFT 0x4
+#define IOMMU_L2_2_SMMU_AIDR_W__ArchMinorRev_W_MASK 0x0000000FL
+#define IOMMU_L2_2_SMMU_AIDR_W__ArchMajorRev_W_MASK 0x000000F0L
+
+
+// addressBlock: nbio_iohub_nb_pciedummy0_pciedummy_cfgdec
+//NB_PCIEDUMMY0_2_DEVICE_VENDOR_ID
+#define NB_PCIEDUMMY0_2_DEVICE_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define NB_PCIEDUMMY0_2_DEVICE_VENDOR_ID__DEVICE_ID__SHIFT 0x10
+#define NB_PCIEDUMMY0_2_DEVICE_VENDOR_ID__VENDOR_ID_MASK 0x0000FFFFL
+#define NB_PCIEDUMMY0_2_DEVICE_VENDOR_ID__DEVICE_ID_MASK 0xFFFF0000L
+//NB_PCIEDUMMY0_2_STATUS_COMMAND
+#define NB_PCIEDUMMY0_2_STATUS_COMMAND__COMMAND__SHIFT 0x0
+#define NB_PCIEDUMMY0_2_STATUS_COMMAND__STATUS__SHIFT 0x10
+#define NB_PCIEDUMMY0_2_STATUS_COMMAND__COMMAND_MASK 0x0000FFFFL
+#define NB_PCIEDUMMY0_2_STATUS_COMMAND__STATUS_MASK 0xFFFF0000L
+//NB_PCIEDUMMY0_2_CLASS_CODE_REVID
+#define NB_PCIEDUMMY0_2_CLASS_CODE_REVID__REVID__SHIFT 0x0
+#define NB_PCIEDUMMY0_2_CLASS_CODE_REVID__CLASS_CODE__SHIFT 0x8
+#define NB_PCIEDUMMY0_2_CLASS_CODE_REVID__REVID_MASK 0x000000FFL
+#define NB_PCIEDUMMY0_2_CLASS_CODE_REVID__CLASS_CODE_MASK 0xFFFFFF00L
+//NB_PCIEDUMMY0_2_HEADER_TYPE
+#define NB_PCIEDUMMY0_2_HEADER_TYPE__HEADER_TYPE__SHIFT 0x10
+#define NB_PCIEDUMMY0_2_HEADER_TYPE__DEVICE_TYPE__SHIFT 0x17
+#define NB_PCIEDUMMY0_2_HEADER_TYPE__HEADER_TYPE_MASK 0x007F0000L
+#define NB_PCIEDUMMY0_2_HEADER_TYPE__DEVICE_TYPE_MASK 0x00800000L
+//NB_PCIEDUMMY0_2_HEADER_TYPE_W
+#define NB_PCIEDUMMY0_2_HEADER_TYPE_W__DEVICE_TYPE__SHIFT 0x7
+#define NB_PCIEDUMMY0_2_HEADER_TYPE_W__DEVICE_TYPE_MASK 0x00000080L
+
+
+// addressBlock: nbio_pcie0_bifplr0_cfgdecp
+//BIFPLR0_2_VENDOR_ID
+#define BIFPLR0_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR0_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR0_2_DEVICE_ID
+#define BIFPLR0_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR0_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR0_2_COMMAND
+#define BIFPLR0_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR0_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR0_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR0_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR0_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR0_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR0_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR0_2_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR0_2_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR0_2_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR0_2_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR0_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR0_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR0_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR0_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR0_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR0_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR0_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR0_2_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR0_2_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR0_2_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR0_2_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR0_2_STATUS
+#define BIFPLR0_2_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR0_2_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR0_2_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR0_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR0_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR0_2_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR0_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR0_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR0_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR0_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR0_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR0_2_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR0_2_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR0_2_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR0_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR0_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR0_2_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR0_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR0_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR0_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR0_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR0_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR0_2_REVISION_ID
+#define BIFPLR0_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR0_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR0_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR0_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR0_2_PROG_INTERFACE
+#define BIFPLR0_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR0_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR0_2_SUB_CLASS
+#define BIFPLR0_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR0_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR0_2_BASE_CLASS
+#define BIFPLR0_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR0_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR0_2_CACHE_LINE
+#define BIFPLR0_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR0_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR0_2_LATENCY
+#define BIFPLR0_2_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR0_2_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR0_2_HEADER
+#define BIFPLR0_2_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR0_2_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR0_2_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR0_2_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR0_2_BIST
+#define BIFPLR0_2_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR0_2_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR0_2_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR0_2_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR0_2_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR0_2_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR0_2_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR0_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR0_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR0_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR0_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR0_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR0_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR0_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR0_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR0_2_IO_BASE_LIMIT
+#define BIFPLR0_2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR0_2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR0_2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR0_2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR0_2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR0_2_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR0_2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR0_2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR0_2_SECONDARY_STATUS
+#define BIFPLR0_2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR0_2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR0_2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR0_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR0_2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR0_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR0_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR0_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR0_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR0_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR0_2_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR0_2_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR0_2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR0_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR0_2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR0_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR0_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR0_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR0_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR0_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR0_2_MEM_BASE_LIMIT
+#define BIFPLR0_2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR0_2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR0_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR0_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR0_2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR0_2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR0_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR0_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR0_2_PREF_BASE_LIMIT
+#define BIFPLR0_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR0_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR0_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR0_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR0_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR0_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR0_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR0_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR0_2_PREF_BASE_UPPER
+#define BIFPLR0_2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR0_2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR0_2_PREF_LIMIT_UPPER
+#define BIFPLR0_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR0_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR0_2_IO_BASE_LIMIT_HI
+#define BIFPLR0_2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR0_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR0_2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR0_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR0_2_CAP_PTR
+#define BIFPLR0_2_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR0_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIFPLR0_2_INTERRUPT_LINE
+#define BIFPLR0_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR0_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR0_2_INTERRUPT_PIN
+#define BIFPLR0_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR0_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR0_2_IRQ_BRIDGE_CNTL
+#define BIFPLR0_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR0_2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR0_2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR0_2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR0_2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR0_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR0_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR0_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR0_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR0_2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR0_2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR0_2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR0_2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR0_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR0_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR0_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+//BIFPLR0_2_EXT_BRIDGE_CNTL
+#define BIFPLR0_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR0_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR0_2_PMI_CAP_LIST
+#define BIFPLR0_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR0_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR0_2_PMI_CAP
+#define BIFPLR0_2_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR0_2_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR0_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR0_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR0_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR0_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR0_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR0_2_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR0_2_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR0_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR0_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR0_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR0_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR0_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR0_2_PMI_STATUS_CNTL
+#define BIFPLR0_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR0_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR0_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR0_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR0_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR0_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR0_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR0_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR0_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR0_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR0_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR0_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR0_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR0_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR0_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR0_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR0_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR0_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR0_2_PCIE_CAP_LIST
+#define BIFPLR0_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR0_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR0_2_PCIE_CAP
+#define BIFPLR0_2_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR0_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR0_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR0_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR0_2_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR0_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR0_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR0_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR0_2_DEVICE_CAP
+#define BIFPLR0_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR0_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR0_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR0_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR0_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR0_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR0_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR0_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR0_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR0_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR0_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR0_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR0_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR0_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR0_2_DEVICE_CNTL
+#define BIFPLR0_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR0_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR0_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR0_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR0_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR0_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR0_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR0_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR0_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR0_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR0_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR0_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR0_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR0_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR0_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR0_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR0_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR0_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR0_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR0_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR0_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR0_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR0_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR0_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR0_2_DEVICE_STATUS
+#define BIFPLR0_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR0_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR0_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR0_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR0_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR0_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR0_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR0_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR0_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR0_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR0_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR0_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIFPLR0_2_LINK_CAP
+#define BIFPLR0_2_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR0_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR0_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR0_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR0_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR0_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR0_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR0_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR0_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR0_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR0_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR0_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR0_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR0_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR0_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR0_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR0_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR0_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR0_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR0_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR0_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR0_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR0_2_LINK_CNTL
+#define BIFPLR0_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR0_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR0_2_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR0_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR0_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR0_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR0_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR0_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR0_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR0_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR0_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR0_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR0_2_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR0_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR0_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR0_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR0_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR0_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR0_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR0_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIFPLR0_2_LINK_STATUS
+#define BIFPLR0_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR0_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR0_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR0_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR0_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR0_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR0_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR0_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR0_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR0_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR0_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR0_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR0_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR0_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR0_2_SLOT_CAP
+#define BIFPLR0_2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR0_2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR0_2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR0_2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR0_2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR0_2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR0_2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR0_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR0_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR0_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR0_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR0_2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR0_2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR0_2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR0_2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR0_2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR0_2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR0_2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR0_2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR0_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR0_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR0_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR0_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR0_2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR0_2_SLOT_CNTL
+#define BIFPLR0_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR0_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR0_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR0_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR0_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR0_2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR0_2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR0_2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR0_2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR0_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR0_2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR0_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR0_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR0_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR0_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR0_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR0_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR0_2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR0_2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR0_2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR0_2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR0_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR0_2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR0_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR0_2_SLOT_STATUS
+#define BIFPLR0_2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR0_2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR0_2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR0_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR0_2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR0_2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR0_2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR0_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR0_2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR0_2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR0_2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR0_2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR0_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR0_2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR0_2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR0_2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR0_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR0_2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR0_2_ROOT_CNTL
+#define BIFPLR0_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR0_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR0_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR0_2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR0_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR0_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR0_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR0_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR0_2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR0_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR0_2_ROOT_CAP
+#define BIFPLR0_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR0_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR0_2_ROOT_STATUS
+#define BIFPLR0_2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR0_2_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR0_2_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR0_2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR0_2_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR0_2_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR0_2_DEVICE_CAP2
+#define BIFPLR0_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR0_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR0_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR0_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR0_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR0_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR0_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR0_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR0_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR0_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR0_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR0_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR0_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR0_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR0_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR0_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR0_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR0_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR0_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR0_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR0_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR0_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR0_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR0_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR0_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR0_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR0_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR0_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIFPLR0_2_DEVICE_CNTL2
+#define BIFPLR0_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR0_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR0_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR0_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR0_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR0_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR0_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR0_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR0_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR0_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR0_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR0_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR0_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR0_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR0_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR0_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR0_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR0_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR0_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR0_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR0_2_DEVICE_STATUS2
+#define BIFPLR0_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR0_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR0_2_LINK_CAP2
+#define BIFPLR0_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR0_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR0_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIFPLR0_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR0_2_LINK_CAP2__RESERVED__SHIFT 0x13
+#define BIFPLR0_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR0_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR0_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L
+#define BIFPLR0_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L
+#define BIFPLR0_2_LINK_CAP2__RESERVED_MASK 0xFFF80000L
+//BIFPLR0_2_LINK_CNTL2
+#define BIFPLR0_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR0_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR0_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR0_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR0_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR0_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR0_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR0_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR0_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR0_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR0_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR0_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR0_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR0_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR0_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR0_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR0_2_LINK_STATUS2
+#define BIFPLR0_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR0_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIFPLR0_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIFPLR0_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIFPLR0_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIFPLR0_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIFPLR0_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR0_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIFPLR0_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIFPLR0_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIFPLR0_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIFPLR0_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIFPLR0_2_SLOT_CAP2
+#define BIFPLR0_2_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR0_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR0_2_SLOT_CNTL2
+#define BIFPLR0_2_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR0_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR0_2_SLOT_STATUS2
+#define BIFPLR0_2_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR0_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR0_2_MSI_CAP_LIST
+#define BIFPLR0_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR0_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR0_2_MSI_MSG_CNTL
+#define BIFPLR0_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR0_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR0_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR0_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR0_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR0_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR0_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR0_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR0_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR0_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR0_2_MSI_MSG_ADDR_LO
+#define BIFPLR0_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR0_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR0_2_MSI_MSG_ADDR_HI
+#define BIFPLR0_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR0_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR0_2_MSI_MSG_DATA
+#define BIFPLR0_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR0_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIFPLR0_2_MSI_MSG_DATA_64
+#define BIFPLR0_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR0_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR0_2_SSID_CAP_LIST
+#define BIFPLR0_2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_2_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR0_2_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR0_2_SSID_CAP
+#define BIFPLR0_2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR0_2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR0_2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR0_2_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR0_2_MSI_MAP_CAP_LIST
+#define BIFPLR0_2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR0_2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR0_2_MSI_MAP_CAP
+#define BIFPLR0_2_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR0_2_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR0_2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR0_2_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR0_2_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR0_2_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR0_2_MSI_MAP_ADDR_LO
+#define BIFPLR0_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define BIFPLR0_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L
+//BIFPLR0_2_MSI_MAP_ADDR_HI
+#define BIFPLR0_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define BIFPLR0_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_2_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR0_2_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR0_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR0_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR0_2_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR0_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR0_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR0_2_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR0_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_2_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR0_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR0_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR0_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR0_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR0_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR0_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR0_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR0_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR0_2_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR0_2_PCIE_PORT_VC_CNTL
+#define BIFPLR0_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR0_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR0_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR0_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR0_2_PCIE_PORT_VC_STATUS
+#define BIFPLR0_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR0_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR0_2_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR0_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR0_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR0_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR0_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR0_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR0_2_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR0_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR0_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR0_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR0_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR0_2_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR0_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR0_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR0_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR0_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR0_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR0_2_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR0_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR0_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR0_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR0_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_2_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR0_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR0_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR0_2_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR0_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR0_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_2_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR0_2_PCIE_UNCORR_ERR_MASK
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR0_2_PCIE_CORR_ERR_STATUS
+#define BIFPLR0_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR0_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR0_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR0_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR0_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR0_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR0_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR0_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR0_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR0_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR0_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR0_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR0_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR0_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR0_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR0_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR0_2_PCIE_CORR_ERR_MASK
+#define BIFPLR0_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR0_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR0_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR0_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR0_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR0_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR0_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR0_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR0_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR0_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR0_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR0_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR0_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR0_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR0_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR0_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIFPLR0_2_PCIE_HDR_LOG0
+#define BIFPLR0_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_2_PCIE_HDR_LOG1
+#define BIFPLR0_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_2_PCIE_HDR_LOG2
+#define BIFPLR0_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_2_PCIE_HDR_LOG3
+#define BIFPLR0_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_2_PCIE_ROOT_ERR_CMD
+#define BIFPLR0_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR0_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR0_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR0_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR0_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR0_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR0_2_PCIE_ROOT_ERR_STATUS
+#define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR0_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR0_2_PCIE_ERR_SRC_ID
+#define BIFPLR0_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR0_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR0_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR0_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR0_2_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR0_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_2_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR0_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_2_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR0_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_2_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR0_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_2_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_2_PCIE_LINK_CNTL3
+#define BIFPLR0_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR0_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR0_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define BIFPLR0_2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10
+#define BIFPLR0_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR0_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIFPLR0_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+#define BIFPLR0_2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L
+//BIFPLR0_2_PCIE_LANE_ERROR_STATUS
+#define BIFPLR0_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR0_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIFPLR0_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIFPLR0_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_2_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR0_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_2_PCIE_ACS_CAP
+#define BIFPLR0_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR0_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR0_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR0_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR0_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR0_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR0_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR0_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR0_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR0_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR0_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR0_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR0_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR0_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR0_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR0_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR0_2_PCIE_ACS_CNTL
+#define BIFPLR0_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR0_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR0_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR0_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR0_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR0_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR0_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR0_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR0_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR0_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR0_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR0_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR0_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR0_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR0_2_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR0_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_2_PCIE_MC_CAP
+#define BIFPLR0_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR0_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR0_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR0_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR0_2_PCIE_MC_CNTL
+#define BIFPLR0_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR0_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR0_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR0_2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR0_2_PCIE_MC_ADDR0
+#define BIFPLR0_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR0_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR0_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR0_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR0_2_PCIE_MC_ADDR1
+#define BIFPLR0_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR0_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR0_2_PCIE_MC_RCV0
+#define BIFPLR0_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR0_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR0_2_PCIE_MC_RCV1
+#define BIFPLR0_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR0_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR0_2_PCIE_MC_BLOCK_ALL0
+#define BIFPLR0_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR0_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR0_2_PCIE_MC_BLOCK_ALL1
+#define BIFPLR0_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR0_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR0_2_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR0_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR0_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR0_2_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR0_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR0_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR0_2_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR0_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR0_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR0_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR0_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR0_2_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR0_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR0_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR0_2_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_2_PCIE_L1_PM_SUB_CAP
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR0_2_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR0_2_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR0_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR0_2_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR0_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_2_PCIE_DPC_CAP_LIST
+#define BIFPLR0_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR0_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR0_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR0_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR0_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR0_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR0_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR0_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR0_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR0_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR0_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR0_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR0_2_PCIE_DPC_CNTL
+#define BIFPLR0_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR0_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR0_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR0_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR0_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR0_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR0_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR0_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR0_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR0_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR0_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR0_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR0_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR0_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR0_2_PCIE_DPC_STATUS
+#define BIFPLR0_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR0_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR0_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR0_2_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR0_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR0_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR0_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR0_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR0_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR0_2_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR0_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR0_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR0_2_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR0_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR0_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR0_2_PCIE_RP_PIO_STATUS
+#define BIFPLR0_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR0_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR0_2_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR0_2_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR0_2_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR0_2_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR0_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR0_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR0_2_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR0_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR0_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR0_2_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR0_2_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR0_2_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR0_2_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR0_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR0_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR0_2_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR0_2_PCIE_RP_PIO_MASK
+#define BIFPLR0_2_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR0_2_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR0_2_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR0_2_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR0_2_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR0_2_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR0_2_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR0_2_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR0_2_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR0_2_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR0_2_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR0_2_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR0_2_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR0_2_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR0_2_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR0_2_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR0_2_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR0_2_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR0_2_PCIE_RP_PIO_SEVERITY
+#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR0_2_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR0_2_PCIE_RP_PIO_SYSERROR
+#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR0_2_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR0_2_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR0_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR0_2_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR0_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_2_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR0_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_2_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR0_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_2_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR0_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_2_PCIE_RP_PIO_IMPSPEC_LOG
+#define BIFPLR0_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_2_PCIE_ESM_CAP_LIST
+#define BIFPLR0_2_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_2_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_2_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_2_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_2_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_2_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_2_PCIE_ESM_HEADER_1
+#define BIFPLR0_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR0_2_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR0_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR0_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR0_2_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR0_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR0_2_PCIE_ESM_HEADER_2
+#define BIFPLR0_2_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR0_2_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR0_2_PCIE_ESM_STATUS
+#define BIFPLR0_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR0_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR0_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR0_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR0_2_PCIE_ESM_CTRL
+#define BIFPLR0_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0
+#define BIFPLR0_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8
+#define BIFPLR0_2_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR0_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL
+#define BIFPLR0_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L
+#define BIFPLR0_2_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR0_2_PCIE_ESM_CAP_1
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR0_2_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR0_2_PCIE_ESM_CAP_2
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR0_2_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR0_2_PCIE_ESM_CAP_3
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR0_2_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR0_2_PCIE_ESM_CAP_4
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR0_2_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR0_2_PCIE_ESM_CAP_5
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR0_2_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR0_2_PCIE_ESM_CAP_6
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR0_2_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR0_2_PCIE_ESM_CAP_7
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR0_2_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+
+
+// addressBlock: nbio_pcie0_bifplr1_cfgdecp
+//BIFPLR1_2_VENDOR_ID
+#define BIFPLR1_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR1_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR1_2_DEVICE_ID
+#define BIFPLR1_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR1_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR1_2_COMMAND
+#define BIFPLR1_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR1_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR1_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR1_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR1_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR1_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR1_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR1_2_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR1_2_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR1_2_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR1_2_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR1_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR1_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR1_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR1_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR1_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR1_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR1_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR1_2_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR1_2_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR1_2_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR1_2_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR1_2_STATUS
+#define BIFPLR1_2_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR1_2_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR1_2_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR1_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR1_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR1_2_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR1_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR1_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR1_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR1_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR1_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR1_2_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR1_2_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR1_2_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR1_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR1_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR1_2_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR1_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR1_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR1_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR1_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR1_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR1_2_REVISION_ID
+#define BIFPLR1_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR1_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR1_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR1_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR1_2_PROG_INTERFACE
+#define BIFPLR1_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR1_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR1_2_SUB_CLASS
+#define BIFPLR1_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR1_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR1_2_BASE_CLASS
+#define BIFPLR1_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR1_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR1_2_CACHE_LINE
+#define BIFPLR1_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR1_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR1_2_LATENCY
+#define BIFPLR1_2_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR1_2_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR1_2_HEADER
+#define BIFPLR1_2_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR1_2_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR1_2_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR1_2_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR1_2_BIST
+#define BIFPLR1_2_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR1_2_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR1_2_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR1_2_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR1_2_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR1_2_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR1_2_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR1_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR1_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR1_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR1_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR1_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR1_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR1_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR1_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR1_2_IO_BASE_LIMIT
+#define BIFPLR1_2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR1_2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR1_2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR1_2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR1_2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR1_2_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR1_2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR1_2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR1_2_SECONDARY_STATUS
+#define BIFPLR1_2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR1_2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR1_2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR1_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR1_2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR1_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR1_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR1_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR1_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR1_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR1_2_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR1_2_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR1_2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR1_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR1_2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR1_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR1_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR1_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR1_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR1_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR1_2_MEM_BASE_LIMIT
+#define BIFPLR1_2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR1_2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR1_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR1_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR1_2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR1_2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR1_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR1_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR1_2_PREF_BASE_LIMIT
+#define BIFPLR1_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR1_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR1_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR1_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR1_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR1_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR1_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR1_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR1_2_PREF_BASE_UPPER
+#define BIFPLR1_2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR1_2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR1_2_PREF_LIMIT_UPPER
+#define BIFPLR1_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR1_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR1_2_IO_BASE_LIMIT_HI
+#define BIFPLR1_2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR1_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR1_2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR1_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR1_2_CAP_PTR
+#define BIFPLR1_2_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR1_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIFPLR1_2_INTERRUPT_LINE
+#define BIFPLR1_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR1_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR1_2_INTERRUPT_PIN
+#define BIFPLR1_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR1_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR1_2_IRQ_BRIDGE_CNTL
+#define BIFPLR1_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR1_2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR1_2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR1_2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR1_2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR1_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR1_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR1_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR1_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR1_2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR1_2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR1_2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR1_2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR1_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR1_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR1_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+//BIFPLR1_2_EXT_BRIDGE_CNTL
+#define BIFPLR1_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR1_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR1_2_PMI_CAP_LIST
+#define BIFPLR1_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR1_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR1_2_PMI_CAP
+#define BIFPLR1_2_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR1_2_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR1_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR1_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR1_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR1_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR1_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR1_2_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR1_2_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR1_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR1_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR1_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR1_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR1_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR1_2_PMI_STATUS_CNTL
+#define BIFPLR1_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR1_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR1_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR1_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR1_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR1_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR1_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR1_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR1_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR1_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR1_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR1_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR1_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR1_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR1_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR1_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR1_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR1_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR1_2_PCIE_CAP_LIST
+#define BIFPLR1_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR1_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR1_2_PCIE_CAP
+#define BIFPLR1_2_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR1_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR1_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR1_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR1_2_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR1_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR1_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR1_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR1_2_DEVICE_CAP
+#define BIFPLR1_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR1_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR1_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR1_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR1_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR1_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR1_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR1_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR1_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR1_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR1_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR1_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR1_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR1_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR1_2_DEVICE_CNTL
+#define BIFPLR1_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR1_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR1_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR1_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR1_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR1_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR1_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR1_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR1_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR1_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR1_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR1_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR1_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR1_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR1_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR1_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR1_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR1_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR1_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR1_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR1_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR1_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR1_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR1_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR1_2_DEVICE_STATUS
+#define BIFPLR1_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR1_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR1_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR1_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR1_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR1_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR1_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR1_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR1_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR1_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR1_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR1_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIFPLR1_2_LINK_CAP
+#define BIFPLR1_2_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR1_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR1_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR1_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR1_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR1_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR1_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR1_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR1_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR1_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR1_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR1_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR1_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR1_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR1_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR1_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR1_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR1_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR1_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR1_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR1_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR1_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR1_2_LINK_CNTL
+#define BIFPLR1_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR1_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR1_2_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR1_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR1_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR1_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR1_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR1_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR1_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR1_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR1_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR1_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR1_2_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR1_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR1_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR1_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR1_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR1_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR1_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR1_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIFPLR1_2_LINK_STATUS
+#define BIFPLR1_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR1_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR1_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR1_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR1_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR1_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR1_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR1_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR1_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR1_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR1_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR1_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR1_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR1_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR1_2_SLOT_CAP
+#define BIFPLR1_2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR1_2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR1_2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR1_2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR1_2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR1_2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR1_2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR1_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR1_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR1_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR1_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR1_2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR1_2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR1_2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR1_2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR1_2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR1_2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR1_2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR1_2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR1_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR1_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR1_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR1_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR1_2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR1_2_SLOT_CNTL
+#define BIFPLR1_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR1_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR1_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR1_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR1_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR1_2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR1_2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR1_2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR1_2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR1_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR1_2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR1_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR1_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR1_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR1_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR1_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR1_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR1_2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR1_2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR1_2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR1_2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR1_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR1_2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR1_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR1_2_SLOT_STATUS
+#define BIFPLR1_2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR1_2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR1_2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR1_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR1_2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR1_2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR1_2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR1_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR1_2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR1_2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR1_2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR1_2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR1_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR1_2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR1_2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR1_2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR1_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR1_2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR1_2_ROOT_CNTL
+#define BIFPLR1_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR1_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR1_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR1_2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR1_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR1_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR1_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR1_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR1_2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR1_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR1_2_ROOT_CAP
+#define BIFPLR1_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR1_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR1_2_ROOT_STATUS
+#define BIFPLR1_2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR1_2_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR1_2_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR1_2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR1_2_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR1_2_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR1_2_DEVICE_CAP2
+#define BIFPLR1_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR1_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR1_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR1_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR1_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR1_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR1_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR1_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR1_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR1_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR1_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR1_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR1_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR1_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR1_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR1_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR1_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR1_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR1_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR1_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR1_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR1_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR1_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR1_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR1_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR1_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR1_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR1_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIFPLR1_2_DEVICE_CNTL2
+#define BIFPLR1_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR1_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR1_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR1_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR1_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR1_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR1_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR1_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR1_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR1_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR1_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR1_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR1_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR1_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR1_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR1_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR1_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR1_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR1_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR1_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR1_2_DEVICE_STATUS2
+#define BIFPLR1_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR1_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR1_2_LINK_CAP2
+#define BIFPLR1_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR1_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR1_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIFPLR1_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR1_2_LINK_CAP2__RESERVED__SHIFT 0x13
+#define BIFPLR1_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR1_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR1_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L
+#define BIFPLR1_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L
+#define BIFPLR1_2_LINK_CAP2__RESERVED_MASK 0xFFF80000L
+//BIFPLR1_2_LINK_CNTL2
+#define BIFPLR1_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR1_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR1_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR1_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR1_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR1_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR1_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR1_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR1_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR1_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR1_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR1_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR1_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR1_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR1_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR1_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR1_2_LINK_STATUS2
+#define BIFPLR1_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR1_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIFPLR1_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIFPLR1_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIFPLR1_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIFPLR1_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIFPLR1_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR1_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIFPLR1_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIFPLR1_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIFPLR1_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIFPLR1_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIFPLR1_2_SLOT_CAP2
+#define BIFPLR1_2_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR1_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR1_2_SLOT_CNTL2
+#define BIFPLR1_2_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR1_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR1_2_SLOT_STATUS2
+#define BIFPLR1_2_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR1_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR1_2_MSI_CAP_LIST
+#define BIFPLR1_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR1_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR1_2_MSI_MSG_CNTL
+#define BIFPLR1_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR1_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR1_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR1_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR1_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR1_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR1_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR1_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR1_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR1_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR1_2_MSI_MSG_ADDR_LO
+#define BIFPLR1_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR1_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR1_2_MSI_MSG_ADDR_HI
+#define BIFPLR1_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR1_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR1_2_MSI_MSG_DATA
+#define BIFPLR1_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR1_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIFPLR1_2_MSI_MSG_DATA_64
+#define BIFPLR1_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR1_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR1_2_SSID_CAP_LIST
+#define BIFPLR1_2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_2_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR1_2_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR1_2_SSID_CAP
+#define BIFPLR1_2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR1_2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR1_2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR1_2_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR1_2_MSI_MAP_CAP_LIST
+#define BIFPLR1_2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR1_2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR1_2_MSI_MAP_CAP
+#define BIFPLR1_2_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR1_2_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR1_2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR1_2_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR1_2_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR1_2_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR1_2_MSI_MAP_ADDR_LO
+#define BIFPLR1_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define BIFPLR1_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L
+//BIFPLR1_2_MSI_MAP_ADDR_HI
+#define BIFPLR1_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define BIFPLR1_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_2_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR1_2_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR1_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR1_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR1_2_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR1_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR1_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR1_2_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR1_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_2_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR1_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR1_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR1_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR1_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR1_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR1_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR1_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR1_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR1_2_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR1_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR1_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR1_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR1_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR1_2_PCIE_PORT_VC_CNTL
+#define BIFPLR1_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR1_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR1_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR1_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR1_2_PCIE_PORT_VC_STATUS
+#define BIFPLR1_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR1_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR1_2_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR1_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR1_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR1_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR1_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR1_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR1_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR1_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR1_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR1_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR1_2_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR1_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR1_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR1_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR1_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR1_2_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR1_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR1_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR1_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR1_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR1_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR1_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR1_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR1_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR1_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR1_2_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR1_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR1_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR1_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR1_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_2_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR1_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR1_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR1_2_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR1_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR1_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_2_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR1_2_PCIE_UNCORR_ERR_MASK
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR1_2_PCIE_CORR_ERR_STATUS
+#define BIFPLR1_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR1_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR1_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR1_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR1_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR1_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR1_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR1_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR1_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR1_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR1_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR1_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR1_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR1_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR1_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR1_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR1_2_PCIE_CORR_ERR_MASK
+#define BIFPLR1_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR1_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR1_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR1_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR1_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR1_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR1_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR1_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR1_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR1_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR1_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR1_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR1_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR1_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR1_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR1_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIFPLR1_2_PCIE_HDR_LOG0
+#define BIFPLR1_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_2_PCIE_HDR_LOG1
+#define BIFPLR1_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_2_PCIE_HDR_LOG2
+#define BIFPLR1_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_2_PCIE_HDR_LOG3
+#define BIFPLR1_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_2_PCIE_ROOT_ERR_CMD
+#define BIFPLR1_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR1_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR1_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR1_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR1_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR1_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR1_2_PCIE_ROOT_ERR_STATUS
+#define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR1_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR1_2_PCIE_ERR_SRC_ID
+#define BIFPLR1_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR1_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR1_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR1_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR1_2_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR1_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_2_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR1_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_2_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR1_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_2_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR1_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_2_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR1_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_2_PCIE_LINK_CNTL3
+#define BIFPLR1_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR1_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR1_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define BIFPLR1_2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10
+#define BIFPLR1_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR1_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIFPLR1_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+#define BIFPLR1_2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L
+//BIFPLR1_2_PCIE_LANE_ERROR_STATUS
+#define BIFPLR1_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR1_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIFPLR1_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIFPLR1_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_2_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR1_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_2_PCIE_ACS_CAP
+#define BIFPLR1_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR1_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR1_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR1_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR1_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR1_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR1_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR1_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR1_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR1_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR1_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR1_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR1_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR1_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR1_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR1_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR1_2_PCIE_ACS_CNTL
+#define BIFPLR1_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR1_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR1_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR1_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR1_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR1_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR1_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR1_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR1_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR1_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR1_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR1_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR1_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR1_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR1_2_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR1_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_2_PCIE_MC_CAP
+#define BIFPLR1_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR1_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR1_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR1_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR1_2_PCIE_MC_CNTL
+#define BIFPLR1_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR1_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR1_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR1_2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR1_2_PCIE_MC_ADDR0
+#define BIFPLR1_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR1_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR1_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR1_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR1_2_PCIE_MC_ADDR1
+#define BIFPLR1_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR1_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR1_2_PCIE_MC_RCV0
+#define BIFPLR1_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR1_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR1_2_PCIE_MC_RCV1
+#define BIFPLR1_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR1_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR1_2_PCIE_MC_BLOCK_ALL0
+#define BIFPLR1_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR1_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR1_2_PCIE_MC_BLOCK_ALL1
+#define BIFPLR1_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR1_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR1_2_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR1_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR1_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR1_2_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR1_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR1_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR1_2_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR1_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR1_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR1_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR1_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR1_2_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR1_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR1_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR1_2_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_2_PCIE_L1_PM_SUB_CAP
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR1_2_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR1_2_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR1_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR1_2_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR1_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_2_PCIE_DPC_CAP_LIST
+#define BIFPLR1_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR1_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR1_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR1_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR1_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR1_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR1_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR1_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR1_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR1_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR1_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR1_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR1_2_PCIE_DPC_CNTL
+#define BIFPLR1_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR1_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR1_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR1_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR1_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR1_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR1_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR1_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR1_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR1_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR1_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR1_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR1_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR1_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR1_2_PCIE_DPC_STATUS
+#define BIFPLR1_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR1_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR1_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR1_2_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR1_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR1_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR1_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR1_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR1_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR1_2_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR1_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR1_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR1_2_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR1_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR1_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR1_2_PCIE_RP_PIO_STATUS
+#define BIFPLR1_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR1_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR1_2_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR1_2_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR1_2_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR1_2_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR1_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR1_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR1_2_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR1_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR1_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR1_2_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR1_2_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR1_2_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR1_2_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR1_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR1_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR1_2_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR1_2_PCIE_RP_PIO_MASK
+#define BIFPLR1_2_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR1_2_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR1_2_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR1_2_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR1_2_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR1_2_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR1_2_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR1_2_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR1_2_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR1_2_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR1_2_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR1_2_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR1_2_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR1_2_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR1_2_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR1_2_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR1_2_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR1_2_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR1_2_PCIE_RP_PIO_SEVERITY
+#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR1_2_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR1_2_PCIE_RP_PIO_SYSERROR
+#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR1_2_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR1_2_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR1_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR1_2_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR1_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_2_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR1_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_2_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR1_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_2_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR1_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_2_PCIE_RP_PIO_IMPSPEC_LOG
+#define BIFPLR1_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_2_PCIE_ESM_CAP_LIST
+#define BIFPLR1_2_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_2_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_2_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_2_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_2_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_2_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_2_PCIE_ESM_HEADER_1
+#define BIFPLR1_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR1_2_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR1_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR1_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR1_2_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR1_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR1_2_PCIE_ESM_HEADER_2
+#define BIFPLR1_2_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR1_2_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR1_2_PCIE_ESM_STATUS
+#define BIFPLR1_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR1_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR1_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR1_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR1_2_PCIE_ESM_CTRL
+#define BIFPLR1_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0
+#define BIFPLR1_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8
+#define BIFPLR1_2_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR1_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL
+#define BIFPLR1_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L
+#define BIFPLR1_2_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR1_2_PCIE_ESM_CAP_1
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR1_2_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR1_2_PCIE_ESM_CAP_2
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR1_2_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR1_2_PCIE_ESM_CAP_3
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR1_2_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR1_2_PCIE_ESM_CAP_4
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR1_2_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR1_2_PCIE_ESM_CAP_5
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR1_2_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR1_2_PCIE_ESM_CAP_6
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR1_2_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR1_2_PCIE_ESM_CAP_7
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR1_2_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+
+
+// addressBlock: nbio_pcie0_bifplr2_cfgdecp
+//BIFPLR2_2_VENDOR_ID
+#define BIFPLR2_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR2_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR2_2_DEVICE_ID
+#define BIFPLR2_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR2_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR2_2_COMMAND
+#define BIFPLR2_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR2_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR2_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR2_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR2_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR2_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR2_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR2_2_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR2_2_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR2_2_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR2_2_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR2_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR2_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR2_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR2_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR2_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR2_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR2_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR2_2_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR2_2_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR2_2_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR2_2_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR2_2_STATUS
+#define BIFPLR2_2_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR2_2_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR2_2_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR2_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR2_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR2_2_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR2_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR2_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR2_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR2_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR2_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR2_2_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR2_2_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR2_2_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR2_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR2_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR2_2_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR2_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR2_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR2_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR2_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR2_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR2_2_REVISION_ID
+#define BIFPLR2_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR2_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR2_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR2_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR2_2_PROG_INTERFACE
+#define BIFPLR2_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR2_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR2_2_SUB_CLASS
+#define BIFPLR2_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR2_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR2_2_BASE_CLASS
+#define BIFPLR2_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR2_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR2_2_CACHE_LINE
+#define BIFPLR2_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR2_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR2_2_LATENCY
+#define BIFPLR2_2_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR2_2_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR2_2_HEADER
+#define BIFPLR2_2_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR2_2_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR2_2_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR2_2_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR2_2_BIST
+#define BIFPLR2_2_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR2_2_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR2_2_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR2_2_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR2_2_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR2_2_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR2_2_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR2_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR2_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR2_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR2_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR2_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR2_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR2_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR2_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR2_2_IO_BASE_LIMIT
+#define BIFPLR2_2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR2_2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR2_2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR2_2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR2_2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR2_2_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR2_2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR2_2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR2_2_SECONDARY_STATUS
+#define BIFPLR2_2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR2_2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR2_2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR2_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR2_2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR2_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR2_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR2_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR2_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR2_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR2_2_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR2_2_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR2_2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR2_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR2_2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR2_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR2_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR2_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR2_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR2_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR2_2_MEM_BASE_LIMIT
+#define BIFPLR2_2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR2_2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR2_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR2_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR2_2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR2_2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR2_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR2_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR2_2_PREF_BASE_LIMIT
+#define BIFPLR2_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR2_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR2_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR2_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR2_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR2_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR2_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR2_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR2_2_PREF_BASE_UPPER
+#define BIFPLR2_2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR2_2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR2_2_PREF_LIMIT_UPPER
+#define BIFPLR2_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR2_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR2_2_IO_BASE_LIMIT_HI
+#define BIFPLR2_2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR2_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR2_2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR2_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR2_2_CAP_PTR
+#define BIFPLR2_2_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR2_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIFPLR2_2_INTERRUPT_LINE
+#define BIFPLR2_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR2_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR2_2_INTERRUPT_PIN
+#define BIFPLR2_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR2_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR2_2_IRQ_BRIDGE_CNTL
+#define BIFPLR2_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR2_2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR2_2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR2_2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR2_2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR2_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR2_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR2_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR2_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR2_2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR2_2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR2_2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR2_2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR2_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR2_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR2_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+//BIFPLR2_2_EXT_BRIDGE_CNTL
+#define BIFPLR2_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR2_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR2_2_PMI_CAP_LIST
+#define BIFPLR2_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR2_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR2_2_PMI_CAP
+#define BIFPLR2_2_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR2_2_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR2_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR2_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR2_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR2_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR2_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR2_2_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR2_2_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR2_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR2_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR2_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR2_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR2_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR2_2_PMI_STATUS_CNTL
+#define BIFPLR2_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR2_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR2_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR2_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR2_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR2_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR2_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR2_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR2_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR2_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR2_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR2_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR2_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR2_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR2_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR2_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR2_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR2_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR2_2_PCIE_CAP_LIST
+#define BIFPLR2_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR2_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR2_2_PCIE_CAP
+#define BIFPLR2_2_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR2_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR2_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR2_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR2_2_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR2_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR2_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR2_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR2_2_DEVICE_CAP
+#define BIFPLR2_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR2_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR2_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR2_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR2_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR2_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR2_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR2_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR2_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR2_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR2_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR2_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR2_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR2_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR2_2_DEVICE_CNTL
+#define BIFPLR2_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR2_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR2_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR2_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR2_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR2_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR2_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR2_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR2_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR2_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR2_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR2_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR2_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR2_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR2_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR2_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR2_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR2_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR2_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR2_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR2_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR2_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR2_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR2_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR2_2_DEVICE_STATUS
+#define BIFPLR2_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR2_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR2_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR2_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR2_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR2_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR2_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR2_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR2_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR2_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR2_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR2_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIFPLR2_2_LINK_CAP
+#define BIFPLR2_2_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR2_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR2_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR2_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR2_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR2_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR2_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR2_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR2_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR2_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR2_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR2_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR2_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR2_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR2_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR2_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR2_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR2_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR2_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR2_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR2_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR2_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR2_2_LINK_CNTL
+#define BIFPLR2_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR2_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR2_2_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR2_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR2_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR2_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR2_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR2_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR2_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR2_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR2_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR2_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR2_2_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR2_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR2_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR2_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR2_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR2_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR2_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR2_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIFPLR2_2_LINK_STATUS
+#define BIFPLR2_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR2_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR2_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR2_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR2_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR2_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR2_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR2_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR2_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR2_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR2_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR2_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR2_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR2_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR2_2_SLOT_CAP
+#define BIFPLR2_2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR2_2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR2_2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR2_2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR2_2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR2_2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR2_2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR2_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR2_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR2_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR2_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR2_2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR2_2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR2_2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR2_2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR2_2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR2_2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR2_2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR2_2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR2_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR2_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR2_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR2_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR2_2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR2_2_SLOT_CNTL
+#define BIFPLR2_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR2_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR2_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR2_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR2_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR2_2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR2_2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR2_2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR2_2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR2_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR2_2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR2_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR2_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR2_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR2_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR2_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR2_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR2_2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR2_2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR2_2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR2_2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR2_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR2_2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR2_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR2_2_SLOT_STATUS
+#define BIFPLR2_2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR2_2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR2_2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR2_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR2_2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR2_2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR2_2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR2_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR2_2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR2_2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR2_2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR2_2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR2_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR2_2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR2_2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR2_2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR2_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR2_2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR2_2_ROOT_CNTL
+#define BIFPLR2_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR2_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR2_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR2_2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR2_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR2_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR2_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR2_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR2_2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR2_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR2_2_ROOT_CAP
+#define BIFPLR2_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR2_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR2_2_ROOT_STATUS
+#define BIFPLR2_2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR2_2_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR2_2_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR2_2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR2_2_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR2_2_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR2_2_DEVICE_CAP2
+#define BIFPLR2_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR2_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR2_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR2_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR2_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR2_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR2_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR2_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR2_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR2_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR2_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR2_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR2_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR2_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR2_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR2_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR2_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR2_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR2_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR2_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR2_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR2_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR2_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR2_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR2_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR2_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR2_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR2_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIFPLR2_2_DEVICE_CNTL2
+#define BIFPLR2_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR2_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR2_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR2_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR2_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR2_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR2_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR2_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR2_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR2_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR2_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR2_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR2_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR2_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR2_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR2_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR2_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR2_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR2_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR2_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR2_2_DEVICE_STATUS2
+#define BIFPLR2_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR2_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR2_2_LINK_CAP2
+#define BIFPLR2_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR2_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR2_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIFPLR2_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR2_2_LINK_CAP2__RESERVED__SHIFT 0x13
+#define BIFPLR2_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR2_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR2_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L
+#define BIFPLR2_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L
+#define BIFPLR2_2_LINK_CAP2__RESERVED_MASK 0xFFF80000L
+//BIFPLR2_2_LINK_CNTL2
+#define BIFPLR2_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR2_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR2_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR2_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR2_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR2_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR2_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR2_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR2_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR2_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR2_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR2_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR2_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR2_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR2_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR2_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR2_2_LINK_STATUS2
+#define BIFPLR2_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR2_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIFPLR2_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIFPLR2_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIFPLR2_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIFPLR2_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIFPLR2_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR2_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIFPLR2_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIFPLR2_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIFPLR2_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIFPLR2_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIFPLR2_2_SLOT_CAP2
+#define BIFPLR2_2_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR2_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR2_2_SLOT_CNTL2
+#define BIFPLR2_2_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR2_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR2_2_SLOT_STATUS2
+#define BIFPLR2_2_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR2_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR2_2_MSI_CAP_LIST
+#define BIFPLR2_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR2_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR2_2_MSI_MSG_CNTL
+#define BIFPLR2_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR2_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR2_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR2_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR2_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR2_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR2_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR2_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR2_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR2_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR2_2_MSI_MSG_ADDR_LO
+#define BIFPLR2_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR2_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR2_2_MSI_MSG_ADDR_HI
+#define BIFPLR2_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR2_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR2_2_MSI_MSG_DATA
+#define BIFPLR2_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR2_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIFPLR2_2_MSI_MSG_DATA_64
+#define BIFPLR2_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR2_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR2_2_SSID_CAP_LIST
+#define BIFPLR2_2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_2_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR2_2_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR2_2_SSID_CAP
+#define BIFPLR2_2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR2_2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR2_2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR2_2_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR2_2_MSI_MAP_CAP_LIST
+#define BIFPLR2_2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR2_2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR2_2_MSI_MAP_CAP
+#define BIFPLR2_2_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR2_2_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR2_2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR2_2_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR2_2_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR2_2_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR2_2_MSI_MAP_ADDR_LO
+#define BIFPLR2_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define BIFPLR2_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L
+//BIFPLR2_2_MSI_MAP_ADDR_HI
+#define BIFPLR2_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define BIFPLR2_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_2_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR2_2_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR2_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR2_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR2_2_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR2_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR2_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR2_2_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR2_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_2_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR2_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR2_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR2_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR2_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR2_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR2_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR2_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR2_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR2_2_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR2_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR2_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR2_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR2_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR2_2_PCIE_PORT_VC_CNTL
+#define BIFPLR2_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR2_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR2_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR2_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR2_2_PCIE_PORT_VC_STATUS
+#define BIFPLR2_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR2_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR2_2_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR2_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR2_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR2_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR2_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR2_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR2_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR2_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR2_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR2_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR2_2_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR2_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR2_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR2_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR2_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR2_2_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR2_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR2_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR2_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR2_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR2_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR2_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR2_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR2_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR2_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR2_2_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR2_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR2_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR2_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR2_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR2_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR2_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_2_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR2_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR2_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR2_2_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR2_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR2_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_2_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR2_2_PCIE_UNCORR_ERR_MASK
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR2_2_PCIE_CORR_ERR_STATUS
+#define BIFPLR2_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR2_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR2_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR2_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR2_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR2_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR2_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR2_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR2_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR2_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR2_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR2_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR2_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR2_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR2_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR2_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR2_2_PCIE_CORR_ERR_MASK
+#define BIFPLR2_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR2_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR2_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR2_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR2_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR2_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR2_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR2_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR2_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR2_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR2_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR2_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR2_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR2_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR2_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR2_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIFPLR2_2_PCIE_HDR_LOG0
+#define BIFPLR2_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_2_PCIE_HDR_LOG1
+#define BIFPLR2_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_2_PCIE_HDR_LOG2
+#define BIFPLR2_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_2_PCIE_HDR_LOG3
+#define BIFPLR2_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_2_PCIE_ROOT_ERR_CMD
+#define BIFPLR2_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR2_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR2_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR2_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR2_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR2_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR2_2_PCIE_ROOT_ERR_STATUS
+#define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR2_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR2_2_PCIE_ERR_SRC_ID
+#define BIFPLR2_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR2_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR2_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR2_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR2_2_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR2_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_2_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR2_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_2_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR2_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_2_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR2_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_2_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR2_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_2_PCIE_LINK_CNTL3
+#define BIFPLR2_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR2_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR2_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define BIFPLR2_2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10
+#define BIFPLR2_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR2_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIFPLR2_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+#define BIFPLR2_2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L
+//BIFPLR2_2_PCIE_LANE_ERROR_STATUS
+#define BIFPLR2_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR2_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIFPLR2_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIFPLR2_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_2_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR2_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_2_PCIE_ACS_CAP
+#define BIFPLR2_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR2_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR2_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR2_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR2_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR2_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR2_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR2_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR2_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR2_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR2_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR2_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR2_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR2_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR2_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR2_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR2_2_PCIE_ACS_CNTL
+#define BIFPLR2_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR2_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR2_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR2_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR2_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR2_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR2_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR2_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR2_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR2_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR2_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR2_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR2_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR2_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR2_2_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR2_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_2_PCIE_MC_CAP
+#define BIFPLR2_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR2_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR2_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR2_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR2_2_PCIE_MC_CNTL
+#define BIFPLR2_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR2_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR2_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR2_2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR2_2_PCIE_MC_ADDR0
+#define BIFPLR2_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR2_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR2_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR2_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR2_2_PCIE_MC_ADDR1
+#define BIFPLR2_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR2_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR2_2_PCIE_MC_RCV0
+#define BIFPLR2_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR2_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR2_2_PCIE_MC_RCV1
+#define BIFPLR2_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR2_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR2_2_PCIE_MC_BLOCK_ALL0
+#define BIFPLR2_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR2_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR2_2_PCIE_MC_BLOCK_ALL1
+#define BIFPLR2_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR2_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR2_2_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR2_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR2_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR2_2_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR2_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR2_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR2_2_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR2_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR2_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR2_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR2_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR2_2_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR2_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR2_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR2_2_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_2_PCIE_L1_PM_SUB_CAP
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR2_2_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR2_2_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR2_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR2_2_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR2_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_2_PCIE_DPC_CAP_LIST
+#define BIFPLR2_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR2_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR2_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR2_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR2_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR2_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR2_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR2_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR2_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR2_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR2_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR2_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR2_2_PCIE_DPC_CNTL
+#define BIFPLR2_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR2_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR2_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR2_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR2_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR2_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR2_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR2_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR2_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR2_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR2_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR2_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR2_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR2_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR2_2_PCIE_DPC_STATUS
+#define BIFPLR2_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR2_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR2_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR2_2_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR2_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR2_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR2_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR2_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR2_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR2_2_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR2_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR2_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR2_2_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR2_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR2_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR2_2_PCIE_RP_PIO_STATUS
+#define BIFPLR2_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR2_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR2_2_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR2_2_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR2_2_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR2_2_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR2_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR2_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR2_2_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR2_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR2_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR2_2_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR2_2_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR2_2_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR2_2_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR2_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR2_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR2_2_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR2_2_PCIE_RP_PIO_MASK
+#define BIFPLR2_2_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR2_2_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR2_2_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR2_2_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR2_2_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR2_2_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR2_2_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR2_2_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR2_2_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR2_2_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR2_2_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR2_2_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR2_2_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR2_2_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR2_2_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR2_2_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR2_2_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR2_2_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR2_2_PCIE_RP_PIO_SEVERITY
+#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR2_2_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR2_2_PCIE_RP_PIO_SYSERROR
+#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR2_2_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR2_2_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR2_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR2_2_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR2_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_2_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR2_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_2_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR2_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_2_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR2_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_2_PCIE_RP_PIO_IMPSPEC_LOG
+#define BIFPLR2_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_2_PCIE_ESM_CAP_LIST
+#define BIFPLR2_2_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_2_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_2_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_2_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_2_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_2_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_2_PCIE_ESM_HEADER_1
+#define BIFPLR2_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR2_2_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR2_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR2_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR2_2_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR2_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR2_2_PCIE_ESM_HEADER_2
+#define BIFPLR2_2_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR2_2_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR2_2_PCIE_ESM_STATUS
+#define BIFPLR2_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR2_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR2_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR2_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR2_2_PCIE_ESM_CTRL
+#define BIFPLR2_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0
+#define BIFPLR2_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8
+#define BIFPLR2_2_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR2_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL
+#define BIFPLR2_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L
+#define BIFPLR2_2_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR2_2_PCIE_ESM_CAP_1
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR2_2_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR2_2_PCIE_ESM_CAP_2
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR2_2_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR2_2_PCIE_ESM_CAP_3
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR2_2_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR2_2_PCIE_ESM_CAP_4
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR2_2_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR2_2_PCIE_ESM_CAP_5
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR2_2_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR2_2_PCIE_ESM_CAP_6
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR2_2_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR2_2_PCIE_ESM_CAP_7
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR2_2_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+
+
+// addressBlock: nbio_pcie0_bifplr3_cfgdecp
+//BIFPLR3_2_VENDOR_ID
+#define BIFPLR3_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR3_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR3_2_DEVICE_ID
+#define BIFPLR3_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR3_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR3_2_COMMAND
+#define BIFPLR3_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR3_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR3_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR3_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR3_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR3_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR3_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR3_2_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR3_2_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR3_2_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR3_2_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR3_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR3_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR3_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR3_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR3_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR3_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR3_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR3_2_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR3_2_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR3_2_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR3_2_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR3_2_STATUS
+#define BIFPLR3_2_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR3_2_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR3_2_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR3_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR3_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR3_2_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR3_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR3_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR3_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR3_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR3_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR3_2_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR3_2_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR3_2_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR3_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR3_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR3_2_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR3_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR3_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR3_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR3_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR3_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR3_2_REVISION_ID
+#define BIFPLR3_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR3_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR3_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR3_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR3_2_PROG_INTERFACE
+#define BIFPLR3_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR3_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR3_2_SUB_CLASS
+#define BIFPLR3_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR3_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR3_2_BASE_CLASS
+#define BIFPLR3_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR3_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR3_2_CACHE_LINE
+#define BIFPLR3_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR3_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR3_2_LATENCY
+#define BIFPLR3_2_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR3_2_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR3_2_HEADER
+#define BIFPLR3_2_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR3_2_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR3_2_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR3_2_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR3_2_BIST
+#define BIFPLR3_2_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR3_2_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR3_2_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR3_2_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR3_2_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR3_2_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR3_2_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR3_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR3_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR3_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR3_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR3_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR3_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR3_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR3_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR3_2_IO_BASE_LIMIT
+#define BIFPLR3_2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR3_2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR3_2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR3_2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR3_2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR3_2_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR3_2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR3_2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR3_2_SECONDARY_STATUS
+#define BIFPLR3_2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR3_2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR3_2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR3_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR3_2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR3_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR3_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR3_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR3_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR3_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR3_2_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR3_2_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR3_2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR3_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR3_2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR3_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR3_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR3_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR3_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR3_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR3_2_MEM_BASE_LIMIT
+#define BIFPLR3_2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR3_2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR3_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR3_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR3_2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR3_2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR3_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR3_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR3_2_PREF_BASE_LIMIT
+#define BIFPLR3_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR3_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR3_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR3_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR3_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR3_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR3_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR3_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR3_2_PREF_BASE_UPPER
+#define BIFPLR3_2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR3_2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR3_2_PREF_LIMIT_UPPER
+#define BIFPLR3_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR3_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR3_2_IO_BASE_LIMIT_HI
+#define BIFPLR3_2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR3_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR3_2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR3_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR3_2_CAP_PTR
+#define BIFPLR3_2_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR3_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIFPLR3_2_INTERRUPT_LINE
+#define BIFPLR3_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR3_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR3_2_INTERRUPT_PIN
+#define BIFPLR3_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR3_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR3_2_IRQ_BRIDGE_CNTL
+#define BIFPLR3_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR3_2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR3_2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR3_2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR3_2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR3_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR3_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR3_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR3_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR3_2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR3_2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR3_2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR3_2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR3_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR3_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR3_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+//BIFPLR3_2_EXT_BRIDGE_CNTL
+#define BIFPLR3_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR3_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR3_2_PMI_CAP_LIST
+#define BIFPLR3_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR3_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR3_2_PMI_CAP
+#define BIFPLR3_2_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR3_2_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR3_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR3_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR3_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR3_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR3_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR3_2_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR3_2_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR3_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR3_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR3_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR3_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR3_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR3_2_PMI_STATUS_CNTL
+#define BIFPLR3_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR3_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR3_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR3_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR3_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR3_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR3_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR3_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR3_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR3_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR3_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR3_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR3_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR3_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR3_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR3_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR3_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR3_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR3_2_PCIE_CAP_LIST
+#define BIFPLR3_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR3_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR3_2_PCIE_CAP
+#define BIFPLR3_2_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR3_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR3_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR3_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR3_2_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR3_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR3_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR3_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR3_2_DEVICE_CAP
+#define BIFPLR3_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR3_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR3_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR3_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR3_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR3_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR3_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR3_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR3_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR3_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR3_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR3_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR3_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR3_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR3_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR3_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR3_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR3_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR3_2_DEVICE_CNTL
+#define BIFPLR3_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR3_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR3_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR3_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR3_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR3_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR3_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR3_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR3_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR3_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR3_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR3_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR3_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR3_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR3_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR3_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR3_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR3_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR3_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR3_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR3_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR3_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR3_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR3_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR3_2_DEVICE_STATUS
+#define BIFPLR3_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR3_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR3_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR3_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR3_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR3_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR3_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR3_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR3_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR3_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR3_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR3_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIFPLR3_2_LINK_CAP
+#define BIFPLR3_2_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR3_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR3_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR3_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR3_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR3_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR3_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR3_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR3_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR3_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR3_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR3_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR3_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR3_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR3_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR3_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR3_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR3_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR3_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR3_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR3_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR3_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR3_2_LINK_CNTL
+#define BIFPLR3_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR3_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR3_2_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR3_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR3_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR3_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR3_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR3_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR3_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR3_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR3_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR3_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR3_2_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR3_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR3_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR3_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR3_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR3_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR3_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR3_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIFPLR3_2_LINK_STATUS
+#define BIFPLR3_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR3_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR3_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR3_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR3_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR3_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR3_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR3_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR3_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR3_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR3_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR3_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR3_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR3_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR3_2_SLOT_CAP
+#define BIFPLR3_2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR3_2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR3_2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR3_2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR3_2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR3_2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR3_2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR3_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR3_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR3_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR3_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR3_2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR3_2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR3_2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR3_2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR3_2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR3_2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR3_2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR3_2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR3_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR3_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR3_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR3_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR3_2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR3_2_SLOT_CNTL
+#define BIFPLR3_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR3_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR3_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR3_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR3_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR3_2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR3_2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR3_2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR3_2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR3_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR3_2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR3_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR3_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR3_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR3_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR3_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR3_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR3_2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR3_2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR3_2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR3_2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR3_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR3_2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR3_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR3_2_SLOT_STATUS
+#define BIFPLR3_2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR3_2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR3_2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR3_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR3_2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR3_2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR3_2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR3_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR3_2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR3_2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR3_2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR3_2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR3_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR3_2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR3_2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR3_2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR3_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR3_2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR3_2_ROOT_CNTL
+#define BIFPLR3_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR3_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR3_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR3_2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR3_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR3_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR3_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR3_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR3_2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR3_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR3_2_ROOT_CAP
+#define BIFPLR3_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR3_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR3_2_ROOT_STATUS
+#define BIFPLR3_2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR3_2_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR3_2_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR3_2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR3_2_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR3_2_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR3_2_DEVICE_CAP2
+#define BIFPLR3_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR3_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR3_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR3_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR3_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR3_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR3_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR3_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR3_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR3_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR3_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR3_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR3_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR3_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR3_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR3_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR3_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR3_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR3_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR3_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR3_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR3_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR3_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR3_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR3_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR3_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR3_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR3_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIFPLR3_2_DEVICE_CNTL2
+#define BIFPLR3_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR3_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR3_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR3_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR3_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR3_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR3_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR3_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR3_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR3_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR3_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR3_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR3_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR3_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR3_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR3_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR3_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR3_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR3_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR3_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR3_2_DEVICE_STATUS2
+#define BIFPLR3_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR3_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR3_2_LINK_CAP2
+#define BIFPLR3_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR3_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR3_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIFPLR3_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR3_2_LINK_CAP2__RESERVED__SHIFT 0x13
+#define BIFPLR3_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR3_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR3_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L
+#define BIFPLR3_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L
+#define BIFPLR3_2_LINK_CAP2__RESERVED_MASK 0xFFF80000L
+//BIFPLR3_2_LINK_CNTL2
+#define BIFPLR3_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR3_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR3_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR3_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR3_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR3_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR3_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR3_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR3_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR3_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR3_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR3_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR3_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR3_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR3_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR3_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR3_2_LINK_STATUS2
+#define BIFPLR3_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR3_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIFPLR3_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIFPLR3_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIFPLR3_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIFPLR3_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIFPLR3_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR3_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIFPLR3_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIFPLR3_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIFPLR3_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIFPLR3_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIFPLR3_2_SLOT_CAP2
+#define BIFPLR3_2_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR3_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR3_2_SLOT_CNTL2
+#define BIFPLR3_2_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR3_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR3_2_SLOT_STATUS2
+#define BIFPLR3_2_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR3_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR3_2_MSI_CAP_LIST
+#define BIFPLR3_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR3_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR3_2_MSI_MSG_CNTL
+#define BIFPLR3_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR3_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR3_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR3_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR3_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR3_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR3_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR3_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR3_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR3_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR3_2_MSI_MSG_ADDR_LO
+#define BIFPLR3_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR3_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR3_2_MSI_MSG_ADDR_HI
+#define BIFPLR3_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR3_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR3_2_MSI_MSG_DATA
+#define BIFPLR3_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR3_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIFPLR3_2_MSI_MSG_DATA_64
+#define BIFPLR3_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR3_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR3_2_SSID_CAP_LIST
+#define BIFPLR3_2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_2_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR3_2_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR3_2_SSID_CAP
+#define BIFPLR3_2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR3_2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR3_2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR3_2_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR3_2_MSI_MAP_CAP_LIST
+#define BIFPLR3_2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR3_2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR3_2_MSI_MAP_CAP
+#define BIFPLR3_2_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR3_2_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR3_2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR3_2_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR3_2_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR3_2_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR3_2_MSI_MAP_ADDR_LO
+#define BIFPLR3_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define BIFPLR3_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L
+//BIFPLR3_2_MSI_MAP_ADDR_HI
+#define BIFPLR3_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define BIFPLR3_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_2_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR3_2_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR3_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR3_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR3_2_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR3_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR3_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR3_2_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR3_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_2_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR3_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR3_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR3_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR3_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR3_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR3_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR3_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR3_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR3_2_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR3_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR3_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR3_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR3_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR3_2_PCIE_PORT_VC_CNTL
+#define BIFPLR3_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR3_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR3_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR3_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR3_2_PCIE_PORT_VC_STATUS
+#define BIFPLR3_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR3_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR3_2_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR3_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR3_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR3_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR3_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR3_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR3_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR3_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR3_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR3_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR3_2_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR3_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR3_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR3_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR3_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR3_2_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR3_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR3_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR3_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR3_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR3_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR3_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR3_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR3_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR3_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR3_2_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR3_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR3_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR3_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR3_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR3_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR3_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_2_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR3_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR3_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR3_2_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR3_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR3_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_2_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR3_2_PCIE_UNCORR_ERR_MASK
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR3_2_PCIE_CORR_ERR_STATUS
+#define BIFPLR3_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR3_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR3_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR3_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR3_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR3_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR3_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR3_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR3_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR3_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR3_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR3_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR3_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR3_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR3_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR3_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR3_2_PCIE_CORR_ERR_MASK
+#define BIFPLR3_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR3_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR3_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR3_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR3_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR3_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR3_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR3_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR3_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR3_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR3_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR3_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR3_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR3_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR3_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR3_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIFPLR3_2_PCIE_HDR_LOG0
+#define BIFPLR3_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_2_PCIE_HDR_LOG1
+#define BIFPLR3_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_2_PCIE_HDR_LOG2
+#define BIFPLR3_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_2_PCIE_HDR_LOG3
+#define BIFPLR3_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_2_PCIE_ROOT_ERR_CMD
+#define BIFPLR3_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR3_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR3_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR3_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR3_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR3_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR3_2_PCIE_ROOT_ERR_STATUS
+#define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR3_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR3_2_PCIE_ERR_SRC_ID
+#define BIFPLR3_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR3_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR3_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR3_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR3_2_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR3_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_2_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR3_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_2_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR3_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_2_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR3_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_2_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR3_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_2_PCIE_LINK_CNTL3
+#define BIFPLR3_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR3_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR3_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define BIFPLR3_2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10
+#define BIFPLR3_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR3_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIFPLR3_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+#define BIFPLR3_2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L
+//BIFPLR3_2_PCIE_LANE_ERROR_STATUS
+#define BIFPLR3_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR3_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIFPLR3_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIFPLR3_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_2_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR3_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_2_PCIE_ACS_CAP
+#define BIFPLR3_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR3_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR3_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR3_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR3_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR3_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR3_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR3_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR3_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR3_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR3_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR3_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR3_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR3_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR3_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR3_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR3_2_PCIE_ACS_CNTL
+#define BIFPLR3_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR3_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR3_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR3_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR3_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR3_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR3_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR3_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR3_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR3_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR3_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR3_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR3_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR3_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR3_2_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR3_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_2_PCIE_MC_CAP
+#define BIFPLR3_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR3_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR3_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR3_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR3_2_PCIE_MC_CNTL
+#define BIFPLR3_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR3_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR3_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR3_2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR3_2_PCIE_MC_ADDR0
+#define BIFPLR3_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR3_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR3_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR3_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR3_2_PCIE_MC_ADDR1
+#define BIFPLR3_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR3_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR3_2_PCIE_MC_RCV0
+#define BIFPLR3_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR3_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR3_2_PCIE_MC_RCV1
+#define BIFPLR3_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR3_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR3_2_PCIE_MC_BLOCK_ALL0
+#define BIFPLR3_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR3_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR3_2_PCIE_MC_BLOCK_ALL1
+#define BIFPLR3_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR3_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR3_2_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR3_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR3_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR3_2_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR3_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR3_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR3_2_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR3_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR3_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR3_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR3_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR3_2_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR3_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR3_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR3_2_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_2_PCIE_L1_PM_SUB_CAP
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR3_2_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR3_2_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR3_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR3_2_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR3_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_2_PCIE_DPC_CAP_LIST
+#define BIFPLR3_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR3_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR3_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR3_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR3_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR3_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR3_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR3_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR3_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR3_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR3_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR3_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR3_2_PCIE_DPC_CNTL
+#define BIFPLR3_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR3_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR3_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR3_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR3_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR3_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR3_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR3_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR3_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR3_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR3_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR3_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR3_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR3_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR3_2_PCIE_DPC_STATUS
+#define BIFPLR3_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR3_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR3_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR3_2_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR3_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR3_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR3_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR3_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR3_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR3_2_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR3_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR3_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR3_2_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR3_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR3_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR3_2_PCIE_RP_PIO_STATUS
+#define BIFPLR3_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR3_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR3_2_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR3_2_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR3_2_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR3_2_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR3_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR3_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR3_2_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR3_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR3_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR3_2_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR3_2_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR3_2_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR3_2_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR3_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR3_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR3_2_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR3_2_PCIE_RP_PIO_MASK
+#define BIFPLR3_2_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR3_2_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR3_2_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR3_2_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR3_2_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR3_2_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR3_2_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR3_2_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR3_2_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR3_2_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR3_2_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR3_2_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR3_2_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR3_2_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR3_2_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR3_2_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR3_2_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR3_2_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR3_2_PCIE_RP_PIO_SEVERITY
+#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR3_2_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR3_2_PCIE_RP_PIO_SYSERROR
+#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR3_2_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR3_2_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR3_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR3_2_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR3_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_2_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR3_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_2_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR3_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_2_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR3_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_2_PCIE_RP_PIO_IMPSPEC_LOG
+#define BIFPLR3_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_2_PCIE_ESM_CAP_LIST
+#define BIFPLR3_2_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_2_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_2_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_2_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_2_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_2_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_2_PCIE_ESM_HEADER_1
+#define BIFPLR3_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR3_2_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR3_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR3_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR3_2_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR3_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR3_2_PCIE_ESM_HEADER_2
+#define BIFPLR3_2_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR3_2_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR3_2_PCIE_ESM_STATUS
+#define BIFPLR3_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR3_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR3_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR3_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR3_2_PCIE_ESM_CTRL
+#define BIFPLR3_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0
+#define BIFPLR3_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8
+#define BIFPLR3_2_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR3_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL
+#define BIFPLR3_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L
+#define BIFPLR3_2_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR3_2_PCIE_ESM_CAP_1
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR3_2_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR3_2_PCIE_ESM_CAP_2
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR3_2_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR3_2_PCIE_ESM_CAP_3
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR3_2_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR3_2_PCIE_ESM_CAP_4
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR3_2_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR3_2_PCIE_ESM_CAP_5
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR3_2_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR3_2_PCIE_ESM_CAP_6
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR3_2_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR3_2_PCIE_ESM_CAP_7
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR3_2_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+
+
+// addressBlock: nbio_pcie0_bifplr4_cfgdecp
+//BIFPLR4_2_VENDOR_ID
+#define BIFPLR4_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR4_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR4_2_DEVICE_ID
+#define BIFPLR4_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR4_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR4_2_COMMAND
+#define BIFPLR4_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR4_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR4_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR4_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR4_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR4_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR4_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR4_2_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR4_2_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR4_2_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR4_2_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR4_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR4_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR4_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR4_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR4_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR4_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR4_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR4_2_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR4_2_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR4_2_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR4_2_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR4_2_STATUS
+#define BIFPLR4_2_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR4_2_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR4_2_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR4_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR4_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR4_2_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR4_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR4_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR4_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR4_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR4_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR4_2_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR4_2_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR4_2_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR4_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR4_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR4_2_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR4_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR4_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR4_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR4_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR4_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR4_2_REVISION_ID
+#define BIFPLR4_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR4_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR4_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR4_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR4_2_PROG_INTERFACE
+#define BIFPLR4_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR4_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR4_2_SUB_CLASS
+#define BIFPLR4_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR4_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR4_2_BASE_CLASS
+#define BIFPLR4_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR4_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR4_2_CACHE_LINE
+#define BIFPLR4_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR4_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR4_2_LATENCY
+#define BIFPLR4_2_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR4_2_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR4_2_HEADER
+#define BIFPLR4_2_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR4_2_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR4_2_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR4_2_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR4_2_BIST
+#define BIFPLR4_2_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR4_2_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR4_2_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR4_2_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR4_2_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR4_2_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR4_2_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR4_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR4_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR4_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR4_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR4_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR4_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR4_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR4_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR4_2_IO_BASE_LIMIT
+#define BIFPLR4_2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR4_2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR4_2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR4_2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR4_2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR4_2_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR4_2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR4_2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR4_2_SECONDARY_STATUS
+#define BIFPLR4_2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR4_2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR4_2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR4_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR4_2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR4_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR4_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR4_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR4_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR4_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR4_2_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR4_2_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR4_2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR4_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR4_2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR4_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR4_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR4_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR4_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR4_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR4_2_MEM_BASE_LIMIT
+#define BIFPLR4_2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR4_2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR4_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR4_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR4_2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR4_2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR4_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR4_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR4_2_PREF_BASE_LIMIT
+#define BIFPLR4_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR4_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR4_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR4_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR4_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR4_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR4_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR4_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR4_2_PREF_BASE_UPPER
+#define BIFPLR4_2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR4_2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR4_2_PREF_LIMIT_UPPER
+#define BIFPLR4_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR4_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR4_2_IO_BASE_LIMIT_HI
+#define BIFPLR4_2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR4_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR4_2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR4_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR4_2_CAP_PTR
+#define BIFPLR4_2_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR4_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIFPLR4_2_INTERRUPT_LINE
+#define BIFPLR4_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR4_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR4_2_INTERRUPT_PIN
+#define BIFPLR4_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR4_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR4_2_IRQ_BRIDGE_CNTL
+#define BIFPLR4_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR4_2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR4_2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR4_2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR4_2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR4_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR4_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR4_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR4_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR4_2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR4_2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR4_2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR4_2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR4_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR4_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR4_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+//BIFPLR4_2_EXT_BRIDGE_CNTL
+#define BIFPLR4_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR4_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR4_2_PMI_CAP_LIST
+#define BIFPLR4_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR4_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR4_2_PMI_CAP
+#define BIFPLR4_2_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR4_2_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR4_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR4_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR4_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR4_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR4_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR4_2_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR4_2_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR4_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR4_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR4_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR4_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR4_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR4_2_PMI_STATUS_CNTL
+#define BIFPLR4_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR4_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR4_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR4_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR4_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR4_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR4_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR4_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR4_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR4_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR4_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR4_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR4_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR4_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR4_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR4_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR4_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR4_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR4_2_PCIE_CAP_LIST
+#define BIFPLR4_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR4_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR4_2_PCIE_CAP
+#define BIFPLR4_2_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR4_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR4_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR4_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR4_2_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR4_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR4_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR4_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR4_2_DEVICE_CAP
+#define BIFPLR4_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR4_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR4_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR4_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR4_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR4_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR4_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR4_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR4_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR4_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR4_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR4_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR4_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR4_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR4_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR4_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR4_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR4_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR4_2_DEVICE_CNTL
+#define BIFPLR4_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR4_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR4_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR4_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR4_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR4_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR4_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR4_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR4_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR4_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR4_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR4_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR4_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR4_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR4_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR4_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR4_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR4_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR4_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR4_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR4_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR4_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR4_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR4_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR4_2_DEVICE_STATUS
+#define BIFPLR4_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR4_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR4_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR4_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR4_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR4_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR4_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR4_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR4_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR4_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR4_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR4_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIFPLR4_2_LINK_CAP
+#define BIFPLR4_2_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR4_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR4_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR4_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR4_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR4_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR4_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR4_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR4_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR4_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR4_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR4_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR4_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR4_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR4_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR4_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR4_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR4_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR4_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR4_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR4_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR4_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR4_2_LINK_CNTL
+#define BIFPLR4_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR4_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR4_2_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR4_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR4_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR4_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR4_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR4_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR4_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR4_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR4_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR4_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR4_2_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR4_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR4_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR4_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR4_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR4_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR4_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR4_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIFPLR4_2_LINK_STATUS
+#define BIFPLR4_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR4_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR4_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR4_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR4_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR4_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR4_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR4_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR4_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR4_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR4_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR4_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR4_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR4_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR4_2_SLOT_CAP
+#define BIFPLR4_2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR4_2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR4_2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR4_2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR4_2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR4_2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR4_2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR4_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR4_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR4_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR4_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR4_2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR4_2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR4_2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR4_2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR4_2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR4_2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR4_2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR4_2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR4_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR4_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR4_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR4_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR4_2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR4_2_SLOT_CNTL
+#define BIFPLR4_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR4_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR4_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR4_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR4_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR4_2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR4_2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR4_2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR4_2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR4_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR4_2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR4_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR4_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR4_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR4_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR4_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR4_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR4_2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR4_2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR4_2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR4_2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR4_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR4_2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR4_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR4_2_SLOT_STATUS
+#define BIFPLR4_2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR4_2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR4_2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR4_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR4_2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR4_2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR4_2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR4_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR4_2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR4_2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR4_2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR4_2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR4_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR4_2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR4_2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR4_2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR4_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR4_2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR4_2_ROOT_CNTL
+#define BIFPLR4_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR4_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR4_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR4_2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR4_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR4_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR4_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR4_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR4_2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR4_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR4_2_ROOT_CAP
+#define BIFPLR4_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR4_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR4_2_ROOT_STATUS
+#define BIFPLR4_2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR4_2_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR4_2_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR4_2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR4_2_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR4_2_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR4_2_DEVICE_CAP2
+#define BIFPLR4_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR4_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR4_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR4_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR4_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR4_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR4_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR4_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR4_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR4_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR4_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR4_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR4_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR4_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR4_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR4_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR4_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR4_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR4_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR4_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR4_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR4_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR4_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR4_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR4_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR4_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR4_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR4_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIFPLR4_2_DEVICE_CNTL2
+#define BIFPLR4_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR4_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR4_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR4_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR4_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR4_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR4_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR4_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR4_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR4_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR4_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR4_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR4_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR4_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR4_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR4_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR4_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR4_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR4_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR4_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR4_2_DEVICE_STATUS2
+#define BIFPLR4_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR4_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR4_2_LINK_CAP2
+#define BIFPLR4_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR4_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR4_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIFPLR4_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR4_2_LINK_CAP2__RESERVED__SHIFT 0x13
+#define BIFPLR4_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR4_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR4_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L
+#define BIFPLR4_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L
+#define BIFPLR4_2_LINK_CAP2__RESERVED_MASK 0xFFF80000L
+//BIFPLR4_2_LINK_CNTL2
+#define BIFPLR4_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR4_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR4_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR4_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR4_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR4_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR4_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR4_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR4_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR4_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR4_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR4_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR4_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR4_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR4_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR4_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR4_2_LINK_STATUS2
+#define BIFPLR4_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR4_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIFPLR4_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIFPLR4_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIFPLR4_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIFPLR4_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIFPLR4_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR4_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIFPLR4_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIFPLR4_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIFPLR4_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIFPLR4_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIFPLR4_2_SLOT_CAP2
+#define BIFPLR4_2_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR4_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR4_2_SLOT_CNTL2
+#define BIFPLR4_2_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR4_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR4_2_SLOT_STATUS2
+#define BIFPLR4_2_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR4_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR4_2_MSI_CAP_LIST
+#define BIFPLR4_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR4_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR4_2_MSI_MSG_CNTL
+#define BIFPLR4_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR4_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR4_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR4_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR4_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR4_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR4_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR4_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR4_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR4_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR4_2_MSI_MSG_ADDR_LO
+#define BIFPLR4_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR4_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR4_2_MSI_MSG_ADDR_HI
+#define BIFPLR4_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR4_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR4_2_MSI_MSG_DATA
+#define BIFPLR4_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR4_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIFPLR4_2_MSI_MSG_DATA_64
+#define BIFPLR4_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR4_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR4_2_SSID_CAP_LIST
+#define BIFPLR4_2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_2_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR4_2_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR4_2_SSID_CAP
+#define BIFPLR4_2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR4_2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR4_2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR4_2_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR4_2_MSI_MAP_CAP_LIST
+#define BIFPLR4_2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR4_2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR4_2_MSI_MAP_CAP
+#define BIFPLR4_2_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR4_2_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR4_2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR4_2_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR4_2_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR4_2_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR4_2_MSI_MAP_ADDR_LO
+#define BIFPLR4_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define BIFPLR4_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L
+//BIFPLR4_2_MSI_MAP_ADDR_HI
+#define BIFPLR4_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define BIFPLR4_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_2_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR4_2_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR4_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR4_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR4_2_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR4_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR4_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR4_2_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR4_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_2_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR4_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR4_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR4_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR4_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR4_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR4_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR4_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR4_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR4_2_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR4_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR4_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR4_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR4_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR4_2_PCIE_PORT_VC_CNTL
+#define BIFPLR4_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR4_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR4_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR4_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR4_2_PCIE_PORT_VC_STATUS
+#define BIFPLR4_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR4_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR4_2_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR4_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR4_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR4_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR4_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR4_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR4_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR4_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR4_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR4_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR4_2_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR4_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR4_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR4_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR4_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR4_2_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR4_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR4_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR4_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR4_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR4_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR4_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR4_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR4_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR4_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR4_2_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR4_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR4_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR4_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR4_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR4_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR4_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_2_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR4_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR4_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR4_2_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR4_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR4_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_2_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR4_2_PCIE_UNCORR_ERR_MASK
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR4_2_PCIE_CORR_ERR_STATUS
+#define BIFPLR4_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR4_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR4_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR4_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR4_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR4_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR4_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR4_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR4_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR4_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR4_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR4_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR4_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR4_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR4_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR4_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR4_2_PCIE_CORR_ERR_MASK
+#define BIFPLR4_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR4_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR4_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR4_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR4_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR4_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR4_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR4_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR4_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR4_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR4_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR4_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR4_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR4_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR4_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR4_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIFPLR4_2_PCIE_HDR_LOG0
+#define BIFPLR4_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_2_PCIE_HDR_LOG1
+#define BIFPLR4_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_2_PCIE_HDR_LOG2
+#define BIFPLR4_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_2_PCIE_HDR_LOG3
+#define BIFPLR4_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_2_PCIE_ROOT_ERR_CMD
+#define BIFPLR4_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR4_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR4_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR4_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR4_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR4_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR4_2_PCIE_ROOT_ERR_STATUS
+#define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR4_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR4_2_PCIE_ERR_SRC_ID
+#define BIFPLR4_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR4_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR4_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR4_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR4_2_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR4_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_2_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR4_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_2_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR4_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_2_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR4_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_2_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR4_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_2_PCIE_LINK_CNTL3
+#define BIFPLR4_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR4_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR4_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define BIFPLR4_2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10
+#define BIFPLR4_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR4_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIFPLR4_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+#define BIFPLR4_2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L
+//BIFPLR4_2_PCIE_LANE_ERROR_STATUS
+#define BIFPLR4_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR4_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIFPLR4_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIFPLR4_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_2_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR4_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_2_PCIE_ACS_CAP
+#define BIFPLR4_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR4_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR4_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR4_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR4_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR4_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR4_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR4_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR4_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR4_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR4_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR4_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR4_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR4_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR4_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR4_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR4_2_PCIE_ACS_CNTL
+#define BIFPLR4_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR4_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR4_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR4_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR4_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR4_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR4_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR4_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR4_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR4_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR4_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR4_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR4_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR4_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR4_2_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR4_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_2_PCIE_MC_CAP
+#define BIFPLR4_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR4_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR4_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR4_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR4_2_PCIE_MC_CNTL
+#define BIFPLR4_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR4_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR4_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR4_2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR4_2_PCIE_MC_ADDR0
+#define BIFPLR4_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR4_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR4_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR4_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR4_2_PCIE_MC_ADDR1
+#define BIFPLR4_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR4_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR4_2_PCIE_MC_RCV0
+#define BIFPLR4_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR4_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR4_2_PCIE_MC_RCV1
+#define BIFPLR4_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR4_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR4_2_PCIE_MC_BLOCK_ALL0
+#define BIFPLR4_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR4_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR4_2_PCIE_MC_BLOCK_ALL1
+#define BIFPLR4_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR4_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR4_2_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR4_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR4_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR4_2_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR4_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR4_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR4_2_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR4_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR4_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR4_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR4_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR4_2_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR4_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR4_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR4_2_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_2_PCIE_L1_PM_SUB_CAP
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR4_2_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR4_2_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR4_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR4_2_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR4_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_2_PCIE_DPC_CAP_LIST
+#define BIFPLR4_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR4_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR4_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR4_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR4_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR4_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR4_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR4_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR4_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR4_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR4_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR4_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR4_2_PCIE_DPC_CNTL
+#define BIFPLR4_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR4_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR4_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR4_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR4_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR4_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR4_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR4_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR4_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR4_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR4_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR4_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR4_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR4_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR4_2_PCIE_DPC_STATUS
+#define BIFPLR4_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR4_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR4_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR4_2_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR4_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR4_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR4_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR4_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR4_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR4_2_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR4_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR4_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR4_2_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR4_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR4_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR4_2_PCIE_RP_PIO_STATUS
+#define BIFPLR4_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR4_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR4_2_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR4_2_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR4_2_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR4_2_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR4_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR4_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR4_2_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR4_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR4_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR4_2_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR4_2_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR4_2_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR4_2_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR4_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR4_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR4_2_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR4_2_PCIE_RP_PIO_MASK
+#define BIFPLR4_2_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR4_2_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR4_2_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR4_2_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR4_2_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR4_2_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR4_2_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR4_2_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR4_2_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR4_2_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR4_2_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR4_2_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR4_2_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR4_2_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR4_2_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR4_2_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR4_2_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR4_2_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR4_2_PCIE_RP_PIO_SEVERITY
+#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR4_2_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR4_2_PCIE_RP_PIO_SYSERROR
+#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR4_2_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR4_2_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR4_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR4_2_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR4_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_2_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR4_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_2_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR4_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_2_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR4_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_2_PCIE_RP_PIO_IMPSPEC_LOG
+#define BIFPLR4_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_2_PCIE_ESM_CAP_LIST
+#define BIFPLR4_2_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_2_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_2_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_2_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_2_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_2_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_2_PCIE_ESM_HEADER_1
+#define BIFPLR4_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR4_2_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR4_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR4_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR4_2_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR4_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR4_2_PCIE_ESM_HEADER_2
+#define BIFPLR4_2_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR4_2_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR4_2_PCIE_ESM_STATUS
+#define BIFPLR4_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR4_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR4_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR4_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR4_2_PCIE_ESM_CTRL
+#define BIFPLR4_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0
+#define BIFPLR4_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8
+#define BIFPLR4_2_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR4_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL
+#define BIFPLR4_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L
+#define BIFPLR4_2_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR4_2_PCIE_ESM_CAP_1
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR4_2_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR4_2_PCIE_ESM_CAP_2
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR4_2_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR4_2_PCIE_ESM_CAP_3
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR4_2_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR4_2_PCIE_ESM_CAP_4
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR4_2_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR4_2_PCIE_ESM_CAP_5
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR4_2_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR4_2_PCIE_ESM_CAP_6
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR4_2_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR4_2_PCIE_ESM_CAP_7
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR4_2_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+
+
+// addressBlock: nbio_pcie0_bifplr5_cfgdecp
+//BIFPLR5_2_VENDOR_ID
+#define BIFPLR5_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR5_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR5_2_DEVICE_ID
+#define BIFPLR5_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR5_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR5_2_COMMAND
+#define BIFPLR5_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR5_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR5_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR5_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR5_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR5_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR5_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR5_2_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR5_2_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR5_2_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR5_2_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR5_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR5_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR5_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR5_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR5_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR5_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR5_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR5_2_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR5_2_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR5_2_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR5_2_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR5_2_STATUS
+#define BIFPLR5_2_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR5_2_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR5_2_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR5_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR5_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR5_2_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR5_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR5_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR5_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR5_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR5_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR5_2_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR5_2_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR5_2_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR5_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR5_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR5_2_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR5_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR5_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR5_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR5_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR5_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR5_2_REVISION_ID
+#define BIFPLR5_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR5_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR5_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR5_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR5_2_PROG_INTERFACE
+#define BIFPLR5_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR5_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR5_2_SUB_CLASS
+#define BIFPLR5_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR5_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR5_2_BASE_CLASS
+#define BIFPLR5_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR5_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR5_2_CACHE_LINE
+#define BIFPLR5_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR5_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR5_2_LATENCY
+#define BIFPLR5_2_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR5_2_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR5_2_HEADER
+#define BIFPLR5_2_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR5_2_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR5_2_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR5_2_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR5_2_BIST
+#define BIFPLR5_2_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR5_2_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR5_2_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR5_2_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR5_2_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR5_2_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR5_2_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR5_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR5_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR5_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR5_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR5_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR5_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR5_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR5_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR5_2_IO_BASE_LIMIT
+#define BIFPLR5_2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR5_2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR5_2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR5_2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR5_2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR5_2_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR5_2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR5_2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR5_2_SECONDARY_STATUS
+#define BIFPLR5_2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR5_2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR5_2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR5_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR5_2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR5_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR5_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR5_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR5_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR5_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR5_2_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR5_2_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR5_2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR5_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR5_2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR5_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR5_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR5_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR5_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR5_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR5_2_MEM_BASE_LIMIT
+#define BIFPLR5_2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR5_2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR5_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR5_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR5_2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR5_2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR5_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR5_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR5_2_PREF_BASE_LIMIT
+#define BIFPLR5_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR5_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR5_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR5_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR5_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR5_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR5_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR5_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR5_2_PREF_BASE_UPPER
+#define BIFPLR5_2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR5_2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR5_2_PREF_LIMIT_UPPER
+#define BIFPLR5_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR5_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR5_2_IO_BASE_LIMIT_HI
+#define BIFPLR5_2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR5_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR5_2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR5_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR5_2_CAP_PTR
+#define BIFPLR5_2_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR5_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIFPLR5_2_INTERRUPT_LINE
+#define BIFPLR5_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR5_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR5_2_INTERRUPT_PIN
+#define BIFPLR5_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR5_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR5_2_IRQ_BRIDGE_CNTL
+#define BIFPLR5_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR5_2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR5_2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR5_2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR5_2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR5_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR5_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR5_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR5_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR5_2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR5_2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR5_2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR5_2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR5_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR5_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR5_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+//BIFPLR5_2_EXT_BRIDGE_CNTL
+#define BIFPLR5_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR5_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR5_2_PMI_CAP_LIST
+#define BIFPLR5_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR5_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR5_2_PMI_CAP
+#define BIFPLR5_2_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR5_2_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR5_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR5_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR5_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR5_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR5_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR5_2_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR5_2_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR5_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR5_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR5_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR5_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR5_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR5_2_PMI_STATUS_CNTL
+#define BIFPLR5_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR5_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR5_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR5_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR5_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR5_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR5_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR5_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR5_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR5_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR5_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR5_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR5_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR5_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR5_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR5_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR5_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR5_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR5_2_PCIE_CAP_LIST
+#define BIFPLR5_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR5_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR5_2_PCIE_CAP
+#define BIFPLR5_2_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR5_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR5_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR5_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR5_2_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR5_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR5_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR5_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR5_2_DEVICE_CAP
+#define BIFPLR5_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR5_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR5_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR5_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR5_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR5_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR5_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR5_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR5_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR5_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR5_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR5_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR5_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR5_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR5_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR5_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR5_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR5_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR5_2_DEVICE_CNTL
+#define BIFPLR5_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR5_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR5_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR5_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR5_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR5_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR5_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR5_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR5_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR5_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR5_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR5_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR5_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR5_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR5_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR5_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR5_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR5_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR5_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR5_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR5_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR5_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR5_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR5_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR5_2_DEVICE_STATUS
+#define BIFPLR5_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR5_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR5_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR5_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR5_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR5_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR5_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR5_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR5_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR5_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR5_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR5_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIFPLR5_2_LINK_CAP
+#define BIFPLR5_2_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR5_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR5_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR5_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR5_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR5_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR5_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR5_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR5_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR5_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR5_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR5_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR5_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR5_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR5_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR5_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR5_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR5_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR5_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR5_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR5_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR5_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR5_2_LINK_CNTL
+#define BIFPLR5_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR5_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR5_2_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR5_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR5_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR5_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR5_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR5_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR5_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR5_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR5_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR5_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR5_2_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR5_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR5_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR5_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR5_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR5_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR5_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR5_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIFPLR5_2_LINK_STATUS
+#define BIFPLR5_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR5_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR5_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR5_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR5_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR5_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR5_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR5_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR5_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR5_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR5_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR5_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR5_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR5_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR5_2_SLOT_CAP
+#define BIFPLR5_2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR5_2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR5_2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR5_2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR5_2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR5_2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR5_2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR5_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR5_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR5_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR5_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR5_2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR5_2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR5_2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR5_2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR5_2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR5_2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR5_2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR5_2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR5_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR5_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR5_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR5_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR5_2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR5_2_SLOT_CNTL
+#define BIFPLR5_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR5_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR5_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR5_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR5_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR5_2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR5_2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR5_2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR5_2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR5_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR5_2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR5_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR5_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR5_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR5_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR5_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR5_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR5_2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR5_2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR5_2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR5_2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR5_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR5_2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR5_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR5_2_SLOT_STATUS
+#define BIFPLR5_2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR5_2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR5_2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR5_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR5_2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR5_2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR5_2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR5_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR5_2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR5_2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR5_2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR5_2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR5_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR5_2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR5_2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR5_2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR5_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR5_2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR5_2_ROOT_CNTL
+#define BIFPLR5_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR5_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR5_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR5_2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR5_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR5_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR5_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR5_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR5_2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR5_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR5_2_ROOT_CAP
+#define BIFPLR5_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR5_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR5_2_ROOT_STATUS
+#define BIFPLR5_2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR5_2_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR5_2_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR5_2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR5_2_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR5_2_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR5_2_DEVICE_CAP2
+#define BIFPLR5_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR5_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR5_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR5_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR5_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR5_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR5_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR5_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR5_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR5_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR5_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR5_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR5_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR5_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR5_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR5_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR5_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR5_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR5_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR5_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR5_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR5_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR5_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR5_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR5_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR5_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR5_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR5_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIFPLR5_2_DEVICE_CNTL2
+#define BIFPLR5_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR5_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR5_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR5_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR5_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR5_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR5_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR5_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR5_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR5_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR5_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR5_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR5_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR5_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR5_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR5_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR5_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR5_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR5_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR5_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR5_2_DEVICE_STATUS2
+#define BIFPLR5_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR5_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR5_2_LINK_CAP2
+#define BIFPLR5_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR5_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR5_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIFPLR5_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR5_2_LINK_CAP2__RESERVED__SHIFT 0x13
+#define BIFPLR5_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR5_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR5_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L
+#define BIFPLR5_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L
+#define BIFPLR5_2_LINK_CAP2__RESERVED_MASK 0xFFF80000L
+//BIFPLR5_2_LINK_CNTL2
+#define BIFPLR5_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR5_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR5_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR5_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR5_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR5_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR5_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR5_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR5_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR5_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR5_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR5_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR5_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR5_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR5_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR5_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR5_2_LINK_STATUS2
+#define BIFPLR5_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR5_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIFPLR5_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIFPLR5_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIFPLR5_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIFPLR5_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIFPLR5_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR5_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIFPLR5_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIFPLR5_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIFPLR5_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIFPLR5_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIFPLR5_2_SLOT_CAP2
+#define BIFPLR5_2_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR5_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR5_2_SLOT_CNTL2
+#define BIFPLR5_2_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR5_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR5_2_SLOT_STATUS2
+#define BIFPLR5_2_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR5_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR5_2_MSI_CAP_LIST
+#define BIFPLR5_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR5_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR5_2_MSI_MSG_CNTL
+#define BIFPLR5_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR5_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR5_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR5_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR5_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR5_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR5_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR5_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR5_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR5_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR5_2_MSI_MSG_ADDR_LO
+#define BIFPLR5_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR5_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR5_2_MSI_MSG_ADDR_HI
+#define BIFPLR5_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR5_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR5_2_MSI_MSG_DATA
+#define BIFPLR5_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR5_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIFPLR5_2_MSI_MSG_DATA_64
+#define BIFPLR5_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR5_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR5_2_SSID_CAP_LIST
+#define BIFPLR5_2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_2_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR5_2_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR5_2_SSID_CAP
+#define BIFPLR5_2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR5_2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR5_2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR5_2_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR5_2_MSI_MAP_CAP_LIST
+#define BIFPLR5_2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR5_2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR5_2_MSI_MAP_CAP
+#define BIFPLR5_2_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR5_2_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR5_2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR5_2_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR5_2_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR5_2_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR5_2_MSI_MAP_ADDR_LO
+#define BIFPLR5_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define BIFPLR5_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L
+//BIFPLR5_2_MSI_MAP_ADDR_HI
+#define BIFPLR5_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define BIFPLR5_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_2_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR5_2_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR5_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR5_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR5_2_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR5_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR5_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR5_2_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR5_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_2_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR5_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR5_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR5_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR5_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR5_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR5_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR5_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR5_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR5_2_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR5_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR5_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR5_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR5_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR5_2_PCIE_PORT_VC_CNTL
+#define BIFPLR5_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR5_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR5_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR5_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR5_2_PCIE_PORT_VC_STATUS
+#define BIFPLR5_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR5_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR5_2_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR5_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR5_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR5_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR5_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR5_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR5_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR5_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR5_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR5_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR5_2_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR5_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR5_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR5_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR5_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR5_2_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR5_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR5_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR5_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR5_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR5_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR5_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR5_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR5_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR5_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR5_2_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR5_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR5_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR5_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR5_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR5_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR5_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_2_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR5_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR5_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR5_2_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR5_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR5_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_2_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR5_2_PCIE_UNCORR_ERR_MASK
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR5_2_PCIE_CORR_ERR_STATUS
+#define BIFPLR5_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR5_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR5_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR5_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR5_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR5_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR5_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR5_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR5_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR5_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR5_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR5_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR5_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR5_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR5_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR5_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR5_2_PCIE_CORR_ERR_MASK
+#define BIFPLR5_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR5_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR5_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR5_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR5_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR5_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR5_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR5_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR5_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR5_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR5_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR5_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR5_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR5_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR5_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR5_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIFPLR5_2_PCIE_HDR_LOG0
+#define BIFPLR5_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_2_PCIE_HDR_LOG1
+#define BIFPLR5_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_2_PCIE_HDR_LOG2
+#define BIFPLR5_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_2_PCIE_HDR_LOG3
+#define BIFPLR5_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_2_PCIE_ROOT_ERR_CMD
+#define BIFPLR5_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR5_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR5_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR5_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR5_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR5_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR5_2_PCIE_ROOT_ERR_STATUS
+#define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR5_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR5_2_PCIE_ERR_SRC_ID
+#define BIFPLR5_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR5_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR5_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR5_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR5_2_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR5_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_2_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR5_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_2_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR5_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_2_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR5_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_2_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR5_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_2_PCIE_LINK_CNTL3
+#define BIFPLR5_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR5_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR5_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define BIFPLR5_2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10
+#define BIFPLR5_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR5_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIFPLR5_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+#define BIFPLR5_2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L
+//BIFPLR5_2_PCIE_LANE_ERROR_STATUS
+#define BIFPLR5_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR5_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIFPLR5_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIFPLR5_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_2_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR5_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_2_PCIE_ACS_CAP
+#define BIFPLR5_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR5_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR5_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR5_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR5_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR5_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR5_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR5_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR5_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR5_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR5_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR5_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR5_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR5_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR5_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR5_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR5_2_PCIE_ACS_CNTL
+#define BIFPLR5_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR5_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR5_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR5_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR5_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR5_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR5_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR5_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR5_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR5_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR5_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR5_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR5_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR5_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR5_2_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR5_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_2_PCIE_MC_CAP
+#define BIFPLR5_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR5_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR5_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR5_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR5_2_PCIE_MC_CNTL
+#define BIFPLR5_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR5_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR5_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR5_2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR5_2_PCIE_MC_ADDR0
+#define BIFPLR5_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR5_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR5_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR5_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR5_2_PCIE_MC_ADDR1
+#define BIFPLR5_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR5_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR5_2_PCIE_MC_RCV0
+#define BIFPLR5_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR5_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR5_2_PCIE_MC_RCV1
+#define BIFPLR5_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR5_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR5_2_PCIE_MC_BLOCK_ALL0
+#define BIFPLR5_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR5_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR5_2_PCIE_MC_BLOCK_ALL1
+#define BIFPLR5_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR5_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR5_2_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR5_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR5_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR5_2_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR5_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR5_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR5_2_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR5_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR5_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR5_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR5_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR5_2_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR5_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR5_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR5_2_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_2_PCIE_L1_PM_SUB_CAP
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR5_2_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR5_2_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR5_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR5_2_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR5_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_2_PCIE_DPC_CAP_LIST
+#define BIFPLR5_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR5_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR5_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR5_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR5_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR5_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR5_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR5_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR5_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR5_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR5_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR5_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR5_2_PCIE_DPC_CNTL
+#define BIFPLR5_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR5_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR5_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR5_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR5_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR5_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR5_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR5_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR5_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR5_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR5_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR5_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR5_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR5_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR5_2_PCIE_DPC_STATUS
+#define BIFPLR5_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR5_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR5_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR5_2_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR5_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR5_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR5_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR5_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR5_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR5_2_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR5_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR5_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR5_2_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR5_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR5_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR5_2_PCIE_RP_PIO_STATUS
+#define BIFPLR5_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR5_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR5_2_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR5_2_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR5_2_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR5_2_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR5_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR5_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR5_2_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR5_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR5_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR5_2_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR5_2_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR5_2_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR5_2_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR5_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR5_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR5_2_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR5_2_PCIE_RP_PIO_MASK
+#define BIFPLR5_2_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR5_2_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR5_2_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR5_2_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR5_2_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR5_2_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR5_2_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR5_2_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR5_2_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR5_2_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR5_2_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR5_2_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR5_2_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR5_2_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR5_2_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR5_2_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR5_2_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR5_2_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR5_2_PCIE_RP_PIO_SEVERITY
+#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR5_2_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR5_2_PCIE_RP_PIO_SYSERROR
+#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR5_2_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR5_2_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR5_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR5_2_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR5_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_2_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR5_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_2_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR5_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_2_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR5_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_2_PCIE_RP_PIO_IMPSPEC_LOG
+#define BIFPLR5_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_2_PCIE_ESM_CAP_LIST
+#define BIFPLR5_2_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_2_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_2_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_2_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_2_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_2_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_2_PCIE_ESM_HEADER_1
+#define BIFPLR5_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR5_2_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR5_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR5_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR5_2_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR5_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR5_2_PCIE_ESM_HEADER_2
+#define BIFPLR5_2_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR5_2_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR5_2_PCIE_ESM_STATUS
+#define BIFPLR5_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR5_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR5_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR5_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR5_2_PCIE_ESM_CTRL
+#define BIFPLR5_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0
+#define BIFPLR5_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8
+#define BIFPLR5_2_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR5_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL
+#define BIFPLR5_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L
+#define BIFPLR5_2_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR5_2_PCIE_ESM_CAP_1
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR5_2_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR5_2_PCIE_ESM_CAP_2
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR5_2_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR5_2_PCIE_ESM_CAP_3
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR5_2_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR5_2_PCIE_ESM_CAP_4
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR5_2_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR5_2_PCIE_ESM_CAP_5
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR5_2_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR5_2_PCIE_ESM_CAP_6
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR5_2_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR5_2_PCIE_ESM_CAP_7
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR5_2_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+
+
+// addressBlock: nbio_pcie0_bifplr6_cfgdecp
+//BIFPLR6_2_VENDOR_ID
+#define BIFPLR6_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR6_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR6_2_DEVICE_ID
+#define BIFPLR6_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR6_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR6_2_COMMAND
+#define BIFPLR6_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR6_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR6_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR6_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR6_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR6_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR6_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR6_2_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR6_2_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR6_2_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR6_2_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR6_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR6_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR6_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR6_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR6_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR6_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR6_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR6_2_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR6_2_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR6_2_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR6_2_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR6_2_STATUS
+#define BIFPLR6_2_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR6_2_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR6_2_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR6_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR6_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR6_2_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR6_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR6_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR6_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR6_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR6_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR6_2_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR6_2_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR6_2_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR6_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR6_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR6_2_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR6_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR6_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR6_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR6_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR6_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR6_2_REVISION_ID
+#define BIFPLR6_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR6_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR6_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR6_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR6_2_PROG_INTERFACE
+#define BIFPLR6_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR6_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR6_2_SUB_CLASS
+#define BIFPLR6_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR6_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR6_2_BASE_CLASS
+#define BIFPLR6_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR6_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR6_2_CACHE_LINE
+#define BIFPLR6_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR6_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR6_2_LATENCY
+#define BIFPLR6_2_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR6_2_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR6_2_HEADER
+#define BIFPLR6_2_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR6_2_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR6_2_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR6_2_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR6_2_BIST
+#define BIFPLR6_2_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR6_2_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR6_2_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR6_2_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR6_2_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR6_2_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR6_2_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR6_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR6_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR6_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR6_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR6_2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR6_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR6_2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR6_2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR6_2_IO_BASE_LIMIT
+#define BIFPLR6_2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR6_2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR6_2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR6_2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR6_2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR6_2_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR6_2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR6_2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR6_2_SECONDARY_STATUS
+#define BIFPLR6_2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR6_2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIFPLR6_2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR6_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR6_2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR6_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR6_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR6_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR6_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR6_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR6_2_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR6_2_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIFPLR6_2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR6_2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR6_2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR6_2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR6_2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR6_2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR6_2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR6_2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR6_2_MEM_BASE_LIMIT
+#define BIFPLR6_2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR6_2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR6_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR6_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR6_2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR6_2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR6_2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR6_2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR6_2_PREF_BASE_LIMIT
+#define BIFPLR6_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR6_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR6_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR6_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR6_2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR6_2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR6_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR6_2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR6_2_PREF_BASE_UPPER
+#define BIFPLR6_2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR6_2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR6_2_PREF_LIMIT_UPPER
+#define BIFPLR6_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR6_2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR6_2_IO_BASE_LIMIT_HI
+#define BIFPLR6_2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR6_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR6_2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR6_2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR6_2_CAP_PTR
+#define BIFPLR6_2_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR6_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIFPLR6_2_INTERRUPT_LINE
+#define BIFPLR6_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR6_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR6_2_INTERRUPT_PIN
+#define BIFPLR6_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR6_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR6_2_IRQ_BRIDGE_CNTL
+#define BIFPLR6_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR6_2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR6_2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR6_2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR6_2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR6_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR6_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR6_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR6_2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR6_2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR6_2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR6_2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR6_2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR6_2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR6_2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR6_2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+//BIFPLR6_2_EXT_BRIDGE_CNTL
+#define BIFPLR6_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR6_2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR6_2_PMI_CAP_LIST
+#define BIFPLR6_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR6_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR6_2_PMI_CAP
+#define BIFPLR6_2_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR6_2_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR6_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR6_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR6_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR6_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR6_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR6_2_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR6_2_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR6_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR6_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR6_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR6_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR6_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR6_2_PMI_STATUS_CNTL
+#define BIFPLR6_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR6_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR6_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR6_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR6_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR6_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR6_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR6_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR6_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR6_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR6_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR6_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR6_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR6_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR6_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR6_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR6_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR6_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR6_2_PCIE_CAP_LIST
+#define BIFPLR6_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR6_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR6_2_PCIE_CAP
+#define BIFPLR6_2_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR6_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR6_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR6_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR6_2_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR6_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR6_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR6_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR6_2_DEVICE_CAP
+#define BIFPLR6_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR6_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR6_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR6_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR6_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR6_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR6_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR6_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR6_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR6_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR6_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR6_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR6_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR6_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR6_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR6_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR6_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR6_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR6_2_DEVICE_CNTL
+#define BIFPLR6_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR6_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR6_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR6_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR6_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR6_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR6_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR6_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR6_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR6_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR6_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR6_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR6_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR6_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR6_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR6_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR6_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR6_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR6_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR6_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR6_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR6_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR6_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR6_2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR6_2_DEVICE_STATUS
+#define BIFPLR6_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR6_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR6_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR6_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR6_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR6_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR6_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR6_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR6_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR6_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR6_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR6_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIFPLR6_2_LINK_CAP
+#define BIFPLR6_2_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR6_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR6_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR6_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR6_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR6_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR6_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR6_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR6_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR6_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR6_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR6_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR6_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR6_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR6_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR6_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR6_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR6_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR6_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR6_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR6_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR6_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR6_2_LINK_CNTL
+#define BIFPLR6_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR6_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR6_2_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR6_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR6_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR6_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR6_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR6_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR6_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR6_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR6_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR6_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR6_2_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR6_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR6_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR6_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR6_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR6_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR6_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR6_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIFPLR6_2_LINK_STATUS
+#define BIFPLR6_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR6_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR6_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR6_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR6_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR6_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR6_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR6_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR6_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR6_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR6_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR6_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR6_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR6_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR6_2_SLOT_CAP
+#define BIFPLR6_2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR6_2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR6_2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR6_2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR6_2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR6_2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR6_2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR6_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR6_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR6_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR6_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR6_2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR6_2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR6_2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR6_2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR6_2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR6_2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR6_2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR6_2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR6_2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR6_2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR6_2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR6_2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR6_2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR6_2_SLOT_CNTL
+#define BIFPLR6_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR6_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR6_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR6_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR6_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR6_2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR6_2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR6_2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR6_2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR6_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR6_2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR6_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR6_2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR6_2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR6_2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR6_2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR6_2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR6_2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR6_2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR6_2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR6_2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR6_2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR6_2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR6_2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR6_2_SLOT_STATUS
+#define BIFPLR6_2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR6_2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR6_2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR6_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR6_2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR6_2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR6_2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR6_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR6_2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR6_2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR6_2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR6_2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR6_2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR6_2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR6_2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR6_2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR6_2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR6_2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR6_2_ROOT_CNTL
+#define BIFPLR6_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR6_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR6_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR6_2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR6_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR6_2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR6_2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR6_2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR6_2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR6_2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR6_2_ROOT_CAP
+#define BIFPLR6_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR6_2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR6_2_ROOT_STATUS
+#define BIFPLR6_2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR6_2_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR6_2_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR6_2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR6_2_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR6_2_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR6_2_DEVICE_CAP2
+#define BIFPLR6_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR6_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR6_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR6_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR6_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR6_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR6_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR6_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR6_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR6_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR6_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR6_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR6_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR6_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR6_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR6_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR6_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR6_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR6_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR6_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR6_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR6_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR6_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR6_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR6_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR6_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR6_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR6_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIFPLR6_2_DEVICE_CNTL2
+#define BIFPLR6_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR6_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR6_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR6_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR6_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR6_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR6_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR6_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR6_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR6_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR6_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR6_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR6_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR6_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR6_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR6_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR6_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR6_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR6_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR6_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR6_2_DEVICE_STATUS2
+#define BIFPLR6_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR6_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR6_2_LINK_CAP2
+#define BIFPLR6_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR6_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR6_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIFPLR6_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR6_2_LINK_CAP2__RESERVED__SHIFT 0x13
+#define BIFPLR6_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR6_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR6_2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L
+#define BIFPLR6_2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L
+#define BIFPLR6_2_LINK_CAP2__RESERVED_MASK 0xFFF80000L
+//BIFPLR6_2_LINK_CNTL2
+#define BIFPLR6_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR6_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR6_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR6_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR6_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR6_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR6_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR6_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR6_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR6_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR6_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR6_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR6_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR6_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR6_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR6_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR6_2_LINK_STATUS2
+#define BIFPLR6_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR6_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIFPLR6_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIFPLR6_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIFPLR6_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIFPLR6_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIFPLR6_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR6_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIFPLR6_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIFPLR6_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIFPLR6_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIFPLR6_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIFPLR6_2_SLOT_CAP2
+#define BIFPLR6_2_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR6_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR6_2_SLOT_CNTL2
+#define BIFPLR6_2_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR6_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR6_2_SLOT_STATUS2
+#define BIFPLR6_2_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR6_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR6_2_MSI_CAP_LIST
+#define BIFPLR6_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR6_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR6_2_MSI_MSG_CNTL
+#define BIFPLR6_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR6_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR6_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR6_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR6_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR6_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR6_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR6_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR6_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR6_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR6_2_MSI_MSG_ADDR_LO
+#define BIFPLR6_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR6_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR6_2_MSI_MSG_ADDR_HI
+#define BIFPLR6_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR6_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR6_2_MSI_MSG_DATA
+#define BIFPLR6_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR6_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIFPLR6_2_MSI_MSG_DATA_64
+#define BIFPLR6_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR6_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR6_2_SSID_CAP_LIST
+#define BIFPLR6_2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_2_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR6_2_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR6_2_SSID_CAP
+#define BIFPLR6_2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR6_2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR6_2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR6_2_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR6_2_MSI_MAP_CAP_LIST
+#define BIFPLR6_2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR6_2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR6_2_MSI_MAP_CAP
+#define BIFPLR6_2_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR6_2_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR6_2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR6_2_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR6_2_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR6_2_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR6_2_MSI_MAP_ADDR_LO
+#define BIFPLR6_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define BIFPLR6_2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L
+//BIFPLR6_2_MSI_MAP_ADDR_HI
+#define BIFPLR6_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define BIFPLR6_2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_2_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR6_2_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR6_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR6_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR6_2_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR6_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR6_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR6_2_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR6_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_2_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR6_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR6_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR6_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR6_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR6_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR6_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR6_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR6_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR6_2_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR6_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR6_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR6_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR6_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR6_2_PCIE_PORT_VC_CNTL
+#define BIFPLR6_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR6_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR6_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR6_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR6_2_PCIE_PORT_VC_STATUS
+#define BIFPLR6_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR6_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR6_2_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR6_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR6_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR6_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR6_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR6_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR6_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR6_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR6_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR6_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR6_2_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR6_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR6_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR6_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR6_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR6_2_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR6_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR6_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR6_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR6_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR6_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR6_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR6_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIFPLR6_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR6_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR6_2_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR6_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR6_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR6_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR6_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR6_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR6_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_2_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR6_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR6_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR6_2_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR6_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR6_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_2_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR6_2_PCIE_UNCORR_ERR_MASK
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR6_2_PCIE_CORR_ERR_STATUS
+#define BIFPLR6_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR6_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR6_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR6_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR6_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR6_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR6_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR6_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR6_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR6_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR6_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR6_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR6_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR6_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR6_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR6_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR6_2_PCIE_CORR_ERR_MASK
+#define BIFPLR6_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR6_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR6_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR6_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR6_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR6_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR6_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR6_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR6_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR6_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR6_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR6_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR6_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR6_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR6_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR6_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIFPLR6_2_PCIE_HDR_LOG0
+#define BIFPLR6_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_2_PCIE_HDR_LOG1
+#define BIFPLR6_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_2_PCIE_HDR_LOG2
+#define BIFPLR6_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_2_PCIE_HDR_LOG3
+#define BIFPLR6_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_2_PCIE_ROOT_ERR_CMD
+#define BIFPLR6_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR6_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR6_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR6_2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR6_2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR6_2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR6_2_PCIE_ROOT_ERR_STATUS
+#define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR6_2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR6_2_PCIE_ERR_SRC_ID
+#define BIFPLR6_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR6_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR6_2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR6_2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR6_2_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR6_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_2_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR6_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_2_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR6_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_2_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR6_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_2_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR6_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_2_PCIE_LINK_CNTL3
+#define BIFPLR6_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR6_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR6_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define BIFPLR6_2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10
+#define BIFPLR6_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR6_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIFPLR6_2_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+#define BIFPLR6_2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L
+//BIFPLR6_2_PCIE_LANE_ERROR_STATUS
+#define BIFPLR6_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR6_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIFPLR6_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIFPLR6_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_2_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR6_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_2_PCIE_ACS_CAP
+#define BIFPLR6_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR6_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR6_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR6_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR6_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR6_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR6_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR6_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR6_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR6_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR6_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR6_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR6_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR6_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR6_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR6_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR6_2_PCIE_ACS_CNTL
+#define BIFPLR6_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR6_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR6_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR6_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR6_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR6_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR6_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR6_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR6_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR6_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR6_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR6_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR6_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR6_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR6_2_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR6_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_2_PCIE_MC_CAP
+#define BIFPLR6_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR6_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR6_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR6_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR6_2_PCIE_MC_CNTL
+#define BIFPLR6_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR6_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR6_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR6_2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR6_2_PCIE_MC_ADDR0
+#define BIFPLR6_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR6_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR6_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR6_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR6_2_PCIE_MC_ADDR1
+#define BIFPLR6_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR6_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR6_2_PCIE_MC_RCV0
+#define BIFPLR6_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR6_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR6_2_PCIE_MC_RCV1
+#define BIFPLR6_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR6_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR6_2_PCIE_MC_BLOCK_ALL0
+#define BIFPLR6_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR6_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR6_2_PCIE_MC_BLOCK_ALL1
+#define BIFPLR6_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR6_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR6_2_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR6_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR6_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR6_2_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR6_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR6_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR6_2_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR6_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR6_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR6_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR6_2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR6_2_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR6_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR6_2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR6_2_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_2_PCIE_L1_PM_SUB_CAP
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR6_2_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR6_2_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR6_2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR6_2_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR6_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_2_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_2_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_2_PCIE_DPC_CAP_LIST
+#define BIFPLR6_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR6_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR6_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR6_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR6_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR6_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR6_2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR6_2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR6_2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR6_2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR6_2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR6_2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR6_2_PCIE_DPC_CNTL
+#define BIFPLR6_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR6_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR6_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR6_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR6_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR6_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR6_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR6_2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR6_2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR6_2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR6_2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR6_2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR6_2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR6_2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR6_2_PCIE_DPC_STATUS
+#define BIFPLR6_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR6_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR6_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR6_2_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR6_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR6_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR6_2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR6_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR6_2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR6_2_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR6_2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR6_2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR6_2_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR6_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR6_2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR6_2_PCIE_RP_PIO_STATUS
+#define BIFPLR6_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR6_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR6_2_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR6_2_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR6_2_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR6_2_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR6_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR6_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR6_2_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR6_2_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR6_2_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR6_2_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR6_2_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR6_2_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR6_2_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR6_2_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR6_2_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR6_2_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR6_2_PCIE_RP_PIO_MASK
+#define BIFPLR6_2_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR6_2_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR6_2_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR6_2_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR6_2_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR6_2_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR6_2_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR6_2_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR6_2_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR6_2_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR6_2_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR6_2_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR6_2_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR6_2_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR6_2_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR6_2_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR6_2_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR6_2_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR6_2_PCIE_RP_PIO_SEVERITY
+#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR6_2_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR6_2_PCIE_RP_PIO_SYSERROR
+#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR6_2_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR6_2_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR6_2_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR6_2_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR6_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_2_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR6_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_2_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR6_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_2_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR6_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_2_PCIE_RP_PIO_IMPSPEC_LOG
+#define BIFPLR6_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_2_PCIE_RP_PIO_IMPSPEC_LOG__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_2_PCIE_ESM_CAP_LIST
+#define BIFPLR6_2_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_2_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_2_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_2_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_2_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_2_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_2_PCIE_ESM_HEADER_1
+#define BIFPLR6_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR6_2_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR6_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR6_2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR6_2_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR6_2_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR6_2_PCIE_ESM_HEADER_2
+#define BIFPLR6_2_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR6_2_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR6_2_PCIE_ESM_STATUS
+#define BIFPLR6_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR6_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR6_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR6_2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR6_2_PCIE_ESM_CTRL
+#define BIFPLR6_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0
+#define BIFPLR6_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8
+#define BIFPLR6_2_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR6_2_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL
+#define BIFPLR6_2_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L
+#define BIFPLR6_2_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR6_2_PCIE_ESM_CAP_1
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR6_2_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR6_2_PCIE_ESM_CAP_2
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR6_2_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR6_2_PCIE_ESM_CAP_3
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR6_2_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR6_2_PCIE_ESM_CAP_4
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR6_2_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR6_2_PCIE_ESM_CAP_5
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR6_2_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR6_2_PCIE_ESM_CAP_6
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR6_2_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR6_2_PCIE_ESM_CAP_7
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR6_2_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+
+
+// addressBlock: nbio_iohub_nb_pciedummy1_pciedummy_cfgdec
+//NB_PCIEDUMMY1_2_DEVICE_VENDOR_ID
+#define NB_PCIEDUMMY1_2_DEVICE_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define NB_PCIEDUMMY1_2_DEVICE_VENDOR_ID__DEVICE_ID__SHIFT 0x10
+#define NB_PCIEDUMMY1_2_DEVICE_VENDOR_ID__VENDOR_ID_MASK 0x0000FFFFL
+#define NB_PCIEDUMMY1_2_DEVICE_VENDOR_ID__DEVICE_ID_MASK 0xFFFF0000L
+//NB_PCIEDUMMY1_2_STATUS_COMMAND
+#define NB_PCIEDUMMY1_2_STATUS_COMMAND__COMMAND__SHIFT 0x0
+#define NB_PCIEDUMMY1_2_STATUS_COMMAND__STATUS__SHIFT 0x10
+#define NB_PCIEDUMMY1_2_STATUS_COMMAND__COMMAND_MASK 0x0000FFFFL
+#define NB_PCIEDUMMY1_2_STATUS_COMMAND__STATUS_MASK 0xFFFF0000L
+//NB_PCIEDUMMY1_2_CLASS_CODE_REVID
+#define NB_PCIEDUMMY1_2_CLASS_CODE_REVID__REVID__SHIFT 0x0
+#define NB_PCIEDUMMY1_2_CLASS_CODE_REVID__CLASS_CODE__SHIFT 0x8
+#define NB_PCIEDUMMY1_2_CLASS_CODE_REVID__REVID_MASK 0x000000FFL
+#define NB_PCIEDUMMY1_2_CLASS_CODE_REVID__CLASS_CODE_MASK 0xFFFFFF00L
+//NB_PCIEDUMMY1_2_HEADER_TYPE
+#define NB_PCIEDUMMY1_2_HEADER_TYPE__HEADER_TYPE__SHIFT 0x10
+#define NB_PCIEDUMMY1_2_HEADER_TYPE__DEVICE_TYPE__SHIFT 0x17
+#define NB_PCIEDUMMY1_2_HEADER_TYPE__HEADER_TYPE_MASK 0x007F0000L
+#define NB_PCIEDUMMY1_2_HEADER_TYPE__DEVICE_TYPE_MASK 0x00800000L
+//NB_PCIEDUMMY1_2_HEADER_TYPE_W
+#define NB_PCIEDUMMY1_2_HEADER_TYPE_W__DEVICE_TYPE__SHIFT 0x7
+#define NB_PCIEDUMMY1_2_HEADER_TYPE_W__DEVICE_TYPE_MASK 0x00000080L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp
+//BIF_CFG_DEV0_RC2_VENDOR_ID
+#define BIF_CFG_DEV0_RC2_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC2_DEVICE_ID
+#define BIF_CFG_DEV0_RC2_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC2_COMMAND
+#define BIF_CFG_DEV0_RC2_COMMAND__IOEN_DN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_COMMAND__MEMEN_DN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_RC2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_RC2_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_RC2_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_RC2_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_RC2_COMMAND__IOEN_DN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC2_COMMAND__MEMEN_DN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC2_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_RC2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_RC2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_RC2_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_RC2_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_RC2_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_RC2_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_RC2_STATUS
+#define BIF_CFG_DEV0_RC2_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC2_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_RC2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_RC2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_RC2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_RC2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_RC2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_RC2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC2_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_RC2_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_RC2_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_RC2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_RC2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_RC2_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_RC2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_RC2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_RC2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_RC2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_RC2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_RC2_REVISION_ID
+#define BIF_CFG_DEV0_RC2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_RC2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_RC2_PROG_INTERFACE
+#define BIF_CFG_DEV0_RC2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_RC2_SUB_CLASS
+#define BIF_CFG_DEV0_RC2_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_RC2_BASE_CLASS
+#define BIF_CFG_DEV0_RC2_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_RC2_CACHE_LINE
+#define BIF_CFG_DEV0_RC2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_RC2_LATENCY
+#define BIF_CFG_DEV0_RC2_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_RC2_HEADER
+#define BIF_CFG_DEV0_RC2_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_RC2_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_RC2_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_RC2_BIST
+#define BIF_CFG_DEV0_RC2_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_RC2_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_RC2_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_RC2_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_RC2_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_RC2_BASE_ADDR_1
+#define BIF_CFG_DEV0_RC2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY
+#define BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC2_IO_BASE_LIMIT
+#define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIF_CFG_DEV0_RC2_SECONDARY_STATUS
+#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_RC2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT
+#define BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT
+#define BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC2_PREF_BASE_UPPER
+#define BIF_CFG_DEV0_RC2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC2_PREF_LIMIT_UPPER
+#define BIF_CFG_DEV0_RC2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC2_IO_BASE_LIMIT_HI
+#define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_RC2_CAP_PTR
+#define BIF_CFG_DEV0_RC2_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_RC2_INTERRUPT_LINE
+#define BIF_CFG_DEV0_RC2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_RC2_INTERRUPT_PIN
+#define BIF_CFG_DEV0_RC2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL
+#define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+//BIF_CFG_DEV0_RC2_EXT_BRIDGE_CNTL
+#define BIF_CFG_DEV0_RC2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIF_CFG_DEV0_RC2_PMI_CAP_LIST
+#define BIF_CFG_DEV0_RC2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_RC2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_RC2_PMI_CAP
+#define BIF_CFG_DEV0_RC2_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_RC2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_RC2_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_RC2_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_RC2_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_RC2_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_RC2_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_RC2_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_RC2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_RC2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_RC2_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_RC2_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_RC2_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_RC2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC2_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_RC2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_RC2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_RC2_PCIE_CAP
+#define BIF_CFG_DEV0_RC2_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_RC2_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_RC2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_RC2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_RC2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_RC2_DEVICE_CAP
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_RC2_DEVICE_CNTL
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIF_CFG_DEV0_RC2_DEVICE_STATUS
+#define BIF_CFG_DEV0_RC2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_RC2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_RC2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_RC2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_RC2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_RC2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_RC2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_RC2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_RC2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_RC2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_RC2_LINK_CAP
+#define BIF_CFG_DEV0_RC2_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_RC2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_RC2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_RC2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_RC2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_RC2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_RC2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_RC2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_RC2_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_RC2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_RC2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_RC2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_RC2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_RC2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_RC2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_RC2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_RC2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_RC2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_RC2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_RC2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC2_LINK_CNTL
+#define BIF_CFG_DEV0_RC2_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_RC2_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_RC2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_RC2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_RC2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_RC2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_RC2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_RC2_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_RC2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_RC2_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_RC2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_RC2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_RC2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_RC2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_RC2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_RC2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_RC2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_RC2_LINK_STATUS
+#define BIF_CFG_DEV0_RC2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_RC2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_RC2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_RC2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_RC2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_RC2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_RC2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_RC2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_RC2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_RC2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_RC2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_RC2_SLOT_CAP
+#define BIF_CFG_DEV0_RC2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIF_CFG_DEV0_RC2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIF_CFG_DEV0_RC2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIF_CFG_DEV0_RC2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIF_CFG_DEV0_RC2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIF_CFG_DEV0_RC2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIF_CFG_DEV0_RC2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIF_CFG_DEV0_RC2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIF_CFG_DEV0_RC2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_RC2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIF_CFG_DEV0_RC2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIF_CFG_DEV0_RC2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIF_CFG_DEV0_RC2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIF_CFG_DEV0_RC2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIF_CFG_DEV0_RC2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIF_CFG_DEV0_RC2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIF_CFG_DEV0_RC2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIF_CFG_DEV0_RC2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIF_CFG_DEV0_RC2_SLOT_CNTL
+#define BIF_CFG_DEV0_RC2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_RC2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIF_CFG_DEV0_RC2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIF_CFG_DEV0_RC2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIF_CFG_DEV0_RC2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_RC2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_RC2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIF_CFG_DEV0_RC2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIF_CFG_DEV0_RC2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIF_CFG_DEV0_RC2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIF_CFG_DEV0_RC2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+//BIF_CFG_DEV0_RC2_SLOT_STATUS
+#define BIF_CFG_DEV0_RC2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIF_CFG_DEV0_RC2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIF_CFG_DEV0_RC2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIF_CFG_DEV0_RC2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIF_CFG_DEV0_RC2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIF_CFG_DEV0_RC2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_RC2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIF_CFG_DEV0_RC2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIF_CFG_DEV0_RC2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIF_CFG_DEV0_RC2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIF_CFG_DEV0_RC2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIF_CFG_DEV0_RC2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIF_CFG_DEV0_RC2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIF_CFG_DEV0_RC2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIF_CFG_DEV0_RC2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIF_CFG_DEV0_RC2_ROOT_CNTL
+#define BIF_CFG_DEV0_RC2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIF_CFG_DEV0_RC2_ROOT_CAP
+#define BIF_CFG_DEV0_RC2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIF_CFG_DEV0_RC2_ROOT_STATUS
+#define BIF_CFG_DEV0_RC2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_RC2_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIF_CFG_DEV0_RC2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC2_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC2_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIF_CFG_DEV0_RC2_DEVICE_CAP2
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_RC2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_RC2_DEVICE_CNTL2
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_RC2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_RC2_DEVICE_STATUS2
+#define BIF_CFG_DEV0_RC2_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC2_LINK_CAP2
+#define BIF_CFG_DEV0_RC2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_RC2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_RC2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_RC2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_RC2_LINK_CNTL2
+#define BIF_CFG_DEV0_RC2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_RC2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_RC2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_RC2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_RC2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_RC2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_RC2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_RC2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_RC2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_RC2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_RC2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_RC2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_RC2_LINK_STATUS2
+#define BIF_CFG_DEV0_RC2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_RC2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_RC2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_RC2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_RC2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_RC2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_RC2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_RC2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_RC2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_RC2_SLOT_CAP2
+#define BIF_CFG_DEV0_RC2_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC2_SLOT_CNTL2
+#define BIF_CFG_DEV0_RC2_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC2_SLOT_STATUS2
+#define BIF_CFG_DEV0_RC2_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC2_MSI_CAP_LIST
+#define BIF_CFG_DEV0_RC2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_RC2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_RC2_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_RC2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_RC2_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_RC2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_RC2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_RC2_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_RC2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC2_MSI_MSG_DATA
+#define BIF_CFG_DEV0_RC2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_RC2_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_RC2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_RC2_SSID_CAP_LIST
+#define BIF_CFG_DEV0_RC2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_RC2_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_RC2_SSID_CAP
+#define BIF_CFG_DEV0_RC2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_RC2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC2_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_RC2_MSI_MAP_CAP_LIST
+#define BIF_CFG_DEV0_RC2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_RC2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_RC2_MSI_MAP_CAP
+#define BIF_CFG_DEV0_RC2_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIF_CFG_DEV0_RC2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIF_CFG_DEV0_RC2_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC2_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIF_CFG_DEV0_RC2_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIF_CFG_DEV0_RC2_MSI_MAP_ADDR_LO
+#define BIF_CFG_DEV0_RC2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define BIF_CFG_DEV0_RC2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC2_MSI_MAP_ADDR_HI
+#define BIF_CFG_DEV0_RC2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC2_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_RC2_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_RC2_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_RC2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC2_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_RC2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC2_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_RC2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC2_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_RC2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_CMD
+#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS
+#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIF_CFG_DEV0_RC2_PCIE_ERR_SRC_ID
+#define BIF_CFG_DEV0_RC2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_RC2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC2_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC2_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_RC2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define BIF_CFG_DEV0_RC2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_RC2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_RC2_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC2_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC2_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_RC2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp
+//BIF_CFG_DEV1_RC2_VENDOR_ID
+#define BIF_CFG_DEV1_RC2_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC2_DEVICE_ID
+#define BIF_CFG_DEV1_RC2_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC2_COMMAND
+#define BIF_CFG_DEV1_RC2_COMMAND__IOEN_DN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_COMMAND__MEMEN_DN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_RC2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV1_RC2_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV1_RC2_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_RC2_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV1_RC2_COMMAND__IOEN_DN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC2_COMMAND__MEMEN_DN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC2_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_RC2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_RC2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV1_RC2_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV1_RC2_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_RC2_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_RC2_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV1_RC2_STATUS
+#define BIF_CFG_DEV1_RC2_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC2_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_RC2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV1_RC2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV1_RC2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV1_RC2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV1_RC2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV1_RC2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC2_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV1_RC2_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV1_RC2_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_RC2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV1_RC2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV1_RC2_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV1_RC2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV1_RC2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV1_RC2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV1_RC2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV1_RC2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV1_RC2_REVISION_ID
+#define BIF_CFG_DEV1_RC2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV1_RC2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV1_RC2_PROG_INTERFACE
+#define BIF_CFG_DEV1_RC2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV1_RC2_SUB_CLASS
+#define BIF_CFG_DEV1_RC2_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_RC2_BASE_CLASS
+#define BIF_CFG_DEV1_RC2_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_RC2_CACHE_LINE
+#define BIF_CFG_DEV1_RC2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV1_RC2_LATENCY
+#define BIF_CFG_DEV1_RC2_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV1_RC2_HEADER
+#define BIF_CFG_DEV1_RC2_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV1_RC2_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV1_RC2_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV1_RC2_BIST
+#define BIF_CFG_DEV1_RC2_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV1_RC2_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_RC2_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV1_RC2_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV1_RC2_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV1_RC2_BASE_ADDR_1
+#define BIF_CFG_DEV1_RC2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY
+#define BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC2_IO_BASE_LIMIT
+#define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIF_CFG_DEV1_RC2_SECONDARY_STATUS
+#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV1_RC2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT
+#define BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT
+#define BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC2_PREF_BASE_UPPER
+#define BIF_CFG_DEV1_RC2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC2_PREF_LIMIT_UPPER
+#define BIF_CFG_DEV1_RC2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC2_IO_BASE_LIMIT_HI
+#define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_RC2_CAP_PTR
+#define BIF_CFG_DEV1_RC2_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV1_RC2_INTERRUPT_LINE
+#define BIF_CFG_DEV1_RC2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV1_RC2_INTERRUPT_PIN
+#define BIF_CFG_DEV1_RC2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL
+#define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+//BIF_CFG_DEV1_RC2_EXT_BRIDGE_CNTL
+#define BIF_CFG_DEV1_RC2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIF_CFG_DEV1_RC2_PMI_CAP_LIST
+#define BIF_CFG_DEV1_RC2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_RC2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_RC2_PMI_CAP
+#define BIF_CFG_DEV1_RC2_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV1_RC2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV1_RC2_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV1_RC2_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV1_RC2_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_RC2_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV1_RC2_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV1_RC2_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV1_RC2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV1_RC2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV1_RC2_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV1_RC2_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV1_RC2_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL
+#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV1_RC2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC2_PCIE_CAP_LIST
+#define BIF_CFG_DEV1_RC2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_RC2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_RC2_PCIE_CAP
+#define BIF_CFG_DEV1_RC2_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV1_RC2_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV1_RC2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV1_RC2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV1_RC2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV1_RC2_DEVICE_CAP
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV1_RC2_DEVICE_CNTL
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIF_CFG_DEV1_RC2_DEVICE_STATUS
+#define BIF_CFG_DEV1_RC2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV1_RC2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV1_RC2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV1_RC2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV1_RC2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV1_RC2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV1_RC2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV1_RC2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV1_RC2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV1_RC2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV1_RC2_LINK_CAP
+#define BIF_CFG_DEV1_RC2_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_RC2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV1_RC2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV1_RC2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV1_RC2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV1_RC2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV1_RC2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV1_RC2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV1_RC2_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV1_RC2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_RC2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV1_RC2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV1_RC2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV1_RC2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV1_RC2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV1_RC2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV1_RC2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV1_RC2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV1_RC2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV1_RC2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC2_LINK_CNTL
+#define BIF_CFG_DEV1_RC2_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV1_RC2_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV1_RC2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV1_RC2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV1_RC2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_RC2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_RC2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_RC2_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV1_RC2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV1_RC2_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_RC2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV1_RC2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV1_RC2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV1_RC2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_RC2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_RC2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_RC2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV1_RC2_LINK_STATUS
+#define BIF_CFG_DEV1_RC2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV1_RC2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV1_RC2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV1_RC2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_RC2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_RC2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV1_RC2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV1_RC2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV1_RC2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV1_RC2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV1_RC2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV1_RC2_SLOT_CAP
+#define BIF_CFG_DEV1_RC2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIF_CFG_DEV1_RC2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIF_CFG_DEV1_RC2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIF_CFG_DEV1_RC2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIF_CFG_DEV1_RC2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIF_CFG_DEV1_RC2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIF_CFG_DEV1_RC2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIF_CFG_DEV1_RC2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIF_CFG_DEV1_RC2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV1_RC2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIF_CFG_DEV1_RC2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIF_CFG_DEV1_RC2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIF_CFG_DEV1_RC2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIF_CFG_DEV1_RC2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIF_CFG_DEV1_RC2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIF_CFG_DEV1_RC2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIF_CFG_DEV1_RC2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIF_CFG_DEV1_RC2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIF_CFG_DEV1_RC2_SLOT_CNTL
+#define BIF_CFG_DEV1_RC2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_RC2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIF_CFG_DEV1_RC2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIF_CFG_DEV1_RC2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIF_CFG_DEV1_RC2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_RC2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_RC2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIF_CFG_DEV1_RC2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIF_CFG_DEV1_RC2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIF_CFG_DEV1_RC2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIF_CFG_DEV1_RC2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+//BIF_CFG_DEV1_RC2_SLOT_STATUS
+#define BIF_CFG_DEV1_RC2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIF_CFG_DEV1_RC2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIF_CFG_DEV1_RC2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIF_CFG_DEV1_RC2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIF_CFG_DEV1_RC2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIF_CFG_DEV1_RC2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV1_RC2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIF_CFG_DEV1_RC2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIF_CFG_DEV1_RC2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIF_CFG_DEV1_RC2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIF_CFG_DEV1_RC2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIF_CFG_DEV1_RC2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIF_CFG_DEV1_RC2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIF_CFG_DEV1_RC2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIF_CFG_DEV1_RC2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIF_CFG_DEV1_RC2_ROOT_CNTL
+#define BIF_CFG_DEV1_RC2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIF_CFG_DEV1_RC2_ROOT_CAP
+#define BIF_CFG_DEV1_RC2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIF_CFG_DEV1_RC2_ROOT_STATUS
+#define BIF_CFG_DEV1_RC2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV1_RC2_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIF_CFG_DEV1_RC2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC2_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC2_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIF_CFG_DEV1_RC2_DEVICE_CAP2
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV1_RC2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV1_RC2_DEVICE_CNTL2
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV1_RC2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV1_RC2_DEVICE_STATUS2
+#define BIF_CFG_DEV1_RC2_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC2_LINK_CAP2
+#define BIF_CFG_DEV1_RC2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV1_RC2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV1_RC2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV1_RC2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV1_RC2_LINK_CNTL2
+#define BIF_CFG_DEV1_RC2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV1_RC2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV1_RC2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV1_RC2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV1_RC2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV1_RC2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_RC2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV1_RC2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV1_RC2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV1_RC2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV1_RC2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV1_RC2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV1_RC2_LINK_STATUS2
+#define BIF_CFG_DEV1_RC2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV1_RC2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV1_RC2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV1_RC2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV1_RC2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV1_RC2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV1_RC2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV1_RC2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV1_RC2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV1_RC2_SLOT_CAP2
+#define BIF_CFG_DEV1_RC2_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC2_SLOT_CNTL2
+#define BIF_CFG_DEV1_RC2_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC2_SLOT_STATUS2
+#define BIF_CFG_DEV1_RC2_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC2_MSI_CAP_LIST
+#define BIF_CFG_DEV1_RC2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_RC2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_RC2_MSI_MSG_CNTL
+#define BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV1_RC2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV1_RC2_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV1_RC2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV1_RC2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV1_RC2_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV1_RC2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC2_MSI_MSG_DATA
+#define BIF_CFG_DEV1_RC2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_RC2_MSI_MSG_DATA_64
+#define BIF_CFG_DEV1_RC2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_RC2_SSID_CAP_LIST
+#define BIF_CFG_DEV1_RC2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_RC2_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_RC2_SSID_CAP
+#define BIF_CFG_DEV1_RC2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_RC2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC2_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_RC2_MSI_MAP_CAP_LIST
+#define BIF_CFG_DEV1_RC2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_RC2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_RC2_MSI_MAP_CAP
+#define BIF_CFG_DEV1_RC2_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIF_CFG_DEV1_RC2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIF_CFG_DEV1_RC2_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC2_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIF_CFG_DEV1_RC2_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIF_CFG_DEV1_RC2_MSI_MAP_ADDR_LO
+#define BIF_CFG_DEV1_RC2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define BIF_CFG_DEV1_RC2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC2_MSI_MAP_ADDR_HI
+#define BIF_CFG_DEV1_RC2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC2_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV1_RC2_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV1_RC2_PCIE_HDR_LOG0
+#define BIF_CFG_DEV1_RC2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC2_PCIE_HDR_LOG1
+#define BIF_CFG_DEV1_RC2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC2_PCIE_HDR_LOG2
+#define BIF_CFG_DEV1_RC2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC2_PCIE_HDR_LOG3
+#define BIF_CFG_DEV1_RC2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_CMD
+#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS
+#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIF_CFG_DEV1_RC2_PCIE_ERR_SRC_ID
+#define BIF_CFG_DEV1_RC2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_RC2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC2_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC2_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV1_RC2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define BIF_CFG_DEV1_RC2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIF_CFG_DEV1_RC2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV1_RC2_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC2_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC2_PCIE_ACS_CAP
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_RC2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_3_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_3_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_3_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_3_COMMAND
+#define BIF_CFG_DEV0_EPF0_3_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_3_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_3_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_3_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_3_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_3_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_3_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_3_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_3_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_3_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_3_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_3_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_3_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_3_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_3_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_3_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_3_STATUS
+#define BIF_CFG_DEV0_EPF0_3_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_3_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_3_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_3_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_3_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_3_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_3_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_3_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_3_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_3_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_3_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_3_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_3_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_3_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_3_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_3_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_3_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_3_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_3_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_3_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_3_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_3_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_3_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_3_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_3_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_3_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_3_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_3_LATENCY
+#define BIF_CFG_DEV0_EPF0_3_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_3_HEADER
+#define BIF_CFG_DEV0_EPF0_3_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_3_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_3_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_3_BIST
+#define BIF_CFG_DEV0_EPF0_3_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_3_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_3_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_3_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_3_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_3_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_3_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_3_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_3_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_3_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_3_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_3_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_3_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_3_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_3_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_3_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_3_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_3_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF0_3_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF0_3_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF0_3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_3_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_3_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_3_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_3_PMI_CAP
+#define BIF_CFG_DEV0_EPF0_3_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_3_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_3_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_3_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_3_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_3_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_3_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_3_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_3_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_3_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF0_3_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_3_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_3_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_3_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_3_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_3_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_3_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_3_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF0_3_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_3_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_3_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF0_3_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_3_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_3_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF0_3_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF0_3_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_3_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF0_3_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_3_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_3_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_3_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_3_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_3_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_3_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_3_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_3_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_3_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_3_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_3_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_3_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_3_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_3_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_3_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_3_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_3_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_3_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_3_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_3_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_3_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_3_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_3_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_3_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_3_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF0_3_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_3_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
+#define BIF_CFG_DEV0_EPF0_3_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define BIF_CFG_DEV0_EPF0_3_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF0_3_PCIE_MC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_MC_CAP
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_MC_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_MC_RCV0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_MC_RCV1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_ALL0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_ALL1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CAP
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L
+//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_STATUS
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_INITIAL_VFS
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_TOTAL_VFS
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_NUM_VFS
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_FUNC_DEP_LINK
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0x00FFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_FIRST_VF_OFFSET
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_STRIDE
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x00000002L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp
+//BIF_CFG_DEV0_EPF1_2_VENDOR_ID
+#define BIF_CFG_DEV0_EPF1_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_2_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_2_COMMAND
+#define BIF_CFG_DEV0_EPF1_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_2_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_2_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_2_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_2_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_2_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_2_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_2_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF1_2_STATUS
+#define BIF_CFG_DEV0_EPF1_2_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_2_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_2_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_2_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_2_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF1_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF1_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF1_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_2_REVISION_ID
+#define BIF_CFG_DEV0_EPF1_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_2_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF1_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_2_SUB_CLASS
+#define BIF_CFG_DEV0_EPF1_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_2_BASE_CLASS
+#define BIF_CFG_DEV0_EPF1_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_2_CACHE_LINE
+#define BIF_CFG_DEV0_EPF1_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_2_LATENCY
+#define BIF_CFG_DEV0_EPF1_2_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_2_HEADER
+#define BIF_CFG_DEV0_EPF1_2_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_2_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF1_2_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF1_2_BIST
+#define BIF_CFG_DEV0_EPF1_2_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_2_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_2_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_2_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF1_2_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF1_2_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF1_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_2_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF1_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_CAP_PTR
+#define BIF_CFG_DEV0_EPF1_2_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF1_2_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF1_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_2_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF1_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_2_MIN_GRANT
+#define BIF_CFG_DEV0_EPF1_2_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_2_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF1_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_2_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF1_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF1_2_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF1_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_2_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_2_PMI_CAP
+#define BIF_CFG_DEV0_EPF1_2_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_2_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_2_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF1_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_2_PCIE_CAP
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF1_2_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF1_2_LINK_CAP
+#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_2_LINK_CNTL
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF1_2_LINK_STATUS
+#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_2_LINK_CAP2
+#define BIF_CFG_DEV0_EPF1_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF1_2_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF1_2_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF1_2_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF1_2_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF1_2_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_2_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF1_2_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_2_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF1_2_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF1_2_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_2_MSI_MASK
+#define BIF_CFG_DEV0_EPF1_2_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_2_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF1_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_MSI_PENDING
+#define BIF_CFG_DEV0_EPF1_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF1_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_2_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF1_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_2_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF1_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_2_MSIX_PBA
+#define BIF_CFG_DEV0_EPF1_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF1_2_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF1_2_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
+#define BIF_CFG_DEV0_EPF1_2_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define BIF_CFG_DEV0_EPF1_2_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF1_2_PCIE_MC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_MC_CAP
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_MC_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_MC_RCV0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_MC_RCV1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_ALL0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_ALL1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CAP
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L
+//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_STATUS
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_INITIAL_VFS
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_TOTAL_VFS
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_NUM_VFS
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_FUNC_DEP_LINK
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0x00FFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_FIRST_VF_OFFSET
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_STRIDE
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x00000002L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp
+//BIF_CFG_DEV0_EPF2_2_VENDOR_ID
+#define BIF_CFG_DEV0_EPF2_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_2_DEVICE_ID
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_2_COMMAND
+#define BIF_CFG_DEV0_EPF2_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_2_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_2_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_2_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_2_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_2_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_2_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_2_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_2_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF2_2_STATUS
+#define BIF_CFG_DEV0_EPF2_2_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_2_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_2_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_2_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_2_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_2_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_2_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_2_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF2_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF2_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF2_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF2_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_2_REVISION_ID
+#define BIF_CFG_DEV0_EPF2_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF2_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF2_2_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF2_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_2_SUB_CLASS
+#define BIF_CFG_DEV0_EPF2_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_2_BASE_CLASS
+#define BIF_CFG_DEV0_EPF2_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_2_CACHE_LINE
+#define BIF_CFG_DEV0_EPF2_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_2_LATENCY
+#define BIF_CFG_DEV0_EPF2_2_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_2_HEADER
+#define BIF_CFG_DEV0_EPF2_2_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_2_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF2_2_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF2_2_BIST
+#define BIF_CFG_DEV0_EPF2_2_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_2_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_2_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF2_2_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF2_2_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF2_2_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_2_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_2_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_2_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_2_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_2_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_2_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF2_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_2_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF2_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_2_CAP_PTR
+#define BIF_CFG_DEV0_EPF2_2_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF2_2_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF2_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_2_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF2_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_2_MIN_GRANT
+#define BIF_CFG_DEV0_EPF2_2_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_2_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF2_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_2_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF2_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF2_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF2_2_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF2_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_2_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_2_PMI_CAP
+#define BIF_CFG_DEV0_EPF2_2_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_2_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF2_2_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF2_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_2_SBRN
+#define BIF_CFG_DEV0_EPF2_2_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_2_FLADJ
+#define BIF_CFG_DEV0_EPF2_2_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_FLADJ__FLADJ_MASK 0x3FL
+//BIF_CFG_DEV0_EPF2_2_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF2_2_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_2_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF2_2_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF2_2_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_2_PCIE_CAP
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF2_2_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF2_2_LINK_CAP
+#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_2_LINK_CNTL
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF2_2_LINK_STATUS
+#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_2_LINK_CAP2
+#define BIF_CFG_DEV0_EPF2_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_2_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF2_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF2_2_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF2_2_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF2_2_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF2_2_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_2_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF2_2_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_2_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF2_2_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_2_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF2_2_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF2_2_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_2_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF2_2_MSI_MASK
+#define BIF_CFG_DEV0_EPF2_2_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_2_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF2_2_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF2_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_2_MSI_PENDING
+#define BIF_CFG_DEV0_EPF2_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_2_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF2_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_2_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_2_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF2_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF2_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF2_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_2_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF2_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF2_2_MSIX_PBA
+#define BIF_CFG_DEV0_EPF2_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF2_2_SATA_CAP_0
+#define BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV0_EPF2_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_2_SATA_CAP_1
+#define BIF_CFG_DEV0_EPF2_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF2_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV0_EPF2_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_2_SATA_IDP_INDEX
+#define BIF_CFG_DEV0_EPF2_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF2_2_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV0_EPF2_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF2_2_SATA_IDP_DATA
+#define BIF_CFG_DEV0_EPF2_2_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_2_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF2_2_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_2_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_2_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_2_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF2_2_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp
+//BIF_CFG_DEV0_EPF3_2_VENDOR_ID
+#define BIF_CFG_DEV0_EPF3_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_2_DEVICE_ID
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_2_COMMAND
+#define BIF_CFG_DEV0_EPF3_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_2_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_2_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_2_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_2_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_2_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_2_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_2_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_2_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF3_2_STATUS
+#define BIF_CFG_DEV0_EPF3_2_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_2_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_2_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_2_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_2_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_2_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_2_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_2_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF3_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF3_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF3_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF3_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_2_REVISION_ID
+#define BIF_CFG_DEV0_EPF3_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF3_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF3_2_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF3_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_2_SUB_CLASS
+#define BIF_CFG_DEV0_EPF3_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_2_BASE_CLASS
+#define BIF_CFG_DEV0_EPF3_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_2_CACHE_LINE
+#define BIF_CFG_DEV0_EPF3_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_2_LATENCY
+#define BIF_CFG_DEV0_EPF3_2_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_2_HEADER
+#define BIF_CFG_DEV0_EPF3_2_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_2_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF3_2_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF3_2_BIST
+#define BIF_CFG_DEV0_EPF3_2_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_2_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_2_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF3_2_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF3_2_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF3_2_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_2_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_2_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_2_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_2_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_2_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_2_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF3_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_2_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF3_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_2_CAP_PTR
+#define BIF_CFG_DEV0_EPF3_2_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF3_2_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF3_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_2_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF3_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_2_MIN_GRANT
+#define BIF_CFG_DEV0_EPF3_2_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_2_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF3_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_2_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF3_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF3_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF3_2_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF3_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_2_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_2_PMI_CAP
+#define BIF_CFG_DEV0_EPF3_2_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_2_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF3_2_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF3_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_2_SBRN
+#define BIF_CFG_DEV0_EPF3_2_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_2_FLADJ
+#define BIF_CFG_DEV0_EPF3_2_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_FLADJ__FLADJ_MASK 0x3FL
+//BIF_CFG_DEV0_EPF3_2_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF3_2_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_2_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF3_2_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF3_2_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_2_PCIE_CAP
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF3_2_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF3_2_LINK_CAP
+#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_2_LINK_CNTL
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF3_2_LINK_STATUS
+#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_2_LINK_CAP2
+#define BIF_CFG_DEV0_EPF3_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_2_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF3_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF3_2_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF3_2_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF3_2_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF3_2_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_2_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF3_2_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_2_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF3_2_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_2_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF3_2_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF3_2_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_2_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF3_2_MSI_MASK
+#define BIF_CFG_DEV0_EPF3_2_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_2_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF3_2_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF3_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_2_MSI_PENDING
+#define BIF_CFG_DEV0_EPF3_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_2_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF3_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_2_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_2_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF3_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF3_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF3_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_2_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF3_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF3_2_MSIX_PBA
+#define BIF_CFG_DEV0_EPF3_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF3_2_SATA_CAP_0
+#define BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV0_EPF3_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_2_SATA_CAP_1
+#define BIF_CFG_DEV0_EPF3_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF3_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV0_EPF3_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_2_SATA_IDP_INDEX
+#define BIF_CFG_DEV0_EPF3_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF3_2_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV0_EPF3_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF3_2_SATA_IDP_DATA
+#define BIF_CFG_DEV0_EPF3_2_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_2_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF3_2_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_2_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_2_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_2_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF3_2_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp
+//BIF_CFG_DEV0_EPF4_2_VENDOR_ID
+#define BIF_CFG_DEV0_EPF4_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_2_DEVICE_ID
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_2_COMMAND
+#define BIF_CFG_DEV0_EPF4_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_2_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_2_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_2_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_2_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_2_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_2_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_2_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_2_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF4_2_STATUS
+#define BIF_CFG_DEV0_EPF4_2_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_2_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_2_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_2_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_2_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_2_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_2_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_2_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF4_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF4_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF4_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF4_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF4_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_2_REVISION_ID
+#define BIF_CFG_DEV0_EPF4_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF4_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF4_2_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF4_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_2_SUB_CLASS
+#define BIF_CFG_DEV0_EPF4_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_2_BASE_CLASS
+#define BIF_CFG_DEV0_EPF4_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_2_CACHE_LINE
+#define BIF_CFG_DEV0_EPF4_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_2_LATENCY
+#define BIF_CFG_DEV0_EPF4_2_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_2_HEADER
+#define BIF_CFG_DEV0_EPF4_2_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_2_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF4_2_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF4_2_BIST
+#define BIF_CFG_DEV0_EPF4_2_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_2_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_2_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF4_2_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF4_2_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF4_2_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_2_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_2_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_2_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_2_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_2_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_2_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF4_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_2_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF4_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_2_CAP_PTR
+#define BIF_CFG_DEV0_EPF4_2_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF4_2_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF4_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_2_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF4_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_2_MIN_GRANT
+#define BIF_CFG_DEV0_EPF4_2_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_2_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF4_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_2_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF4_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF4_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF4_2_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF4_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_2_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_2_PMI_CAP
+#define BIF_CFG_DEV0_EPF4_2_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_2_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF4_2_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF4_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF4_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF4_2_SBRN
+#define BIF_CFG_DEV0_EPF4_2_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_2_FLADJ
+#define BIF_CFG_DEV0_EPF4_2_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_FLADJ__FLADJ_MASK 0x3FL
+//BIF_CFG_DEV0_EPF4_2_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF4_2_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_2_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF4_2_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF4_2_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_2_PCIE_CAP
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF4_2_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF4_2_LINK_CAP
+#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF4_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF4_2_LINK_CNTL
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF4_2_LINK_STATUS
+#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_2_LINK_CAP2
+#define BIF_CFG_DEV0_EPF4_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_2_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF4_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF4_2_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF4_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF4_2_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF4_2_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF4_2_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_2_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF4_2_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_2_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF4_2_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_2_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF4_2_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF4_2_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_2_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF4_2_MSI_MASK
+#define BIF_CFG_DEV0_EPF4_2_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_2_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF4_2_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF4_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_2_MSI_PENDING
+#define BIF_CFG_DEV0_EPF4_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_2_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF4_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_2_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_2_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF4_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF4_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF4_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_2_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF4_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF4_2_MSIX_PBA
+#define BIF_CFG_DEV0_EPF4_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF4_2_SATA_CAP_0
+#define BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV0_EPF4_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF4_2_SATA_CAP_1
+#define BIF_CFG_DEV0_EPF4_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF4_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV0_EPF4_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF4_2_SATA_IDP_INDEX
+#define BIF_CFG_DEV0_EPF4_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF4_2_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV0_EPF4_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF4_2_SATA_IDP_DATA
+#define BIF_CFG_DEV0_EPF4_2_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_2_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF4_2_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF4_2_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_2_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_2_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF4_2_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp
+//BIF_CFG_DEV0_EPF5_2_VENDOR_ID
+#define BIF_CFG_DEV0_EPF5_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_2_DEVICE_ID
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_2_COMMAND
+#define BIF_CFG_DEV0_EPF5_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_2_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_2_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_2_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_2_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_2_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_2_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_2_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_2_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF5_2_STATUS
+#define BIF_CFG_DEV0_EPF5_2_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_2_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_2_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_2_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_2_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_2_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_2_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_2_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF5_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF5_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF5_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF5_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF5_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_2_REVISION_ID
+#define BIF_CFG_DEV0_EPF5_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF5_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF5_2_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF5_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_2_SUB_CLASS
+#define BIF_CFG_DEV0_EPF5_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_2_BASE_CLASS
+#define BIF_CFG_DEV0_EPF5_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_2_CACHE_LINE
+#define BIF_CFG_DEV0_EPF5_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_2_LATENCY
+#define BIF_CFG_DEV0_EPF5_2_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_2_HEADER
+#define BIF_CFG_DEV0_EPF5_2_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_2_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF5_2_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF5_2_BIST
+#define BIF_CFG_DEV0_EPF5_2_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_2_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_2_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF5_2_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF5_2_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF5_2_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_2_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_2_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_2_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_2_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_2_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_2_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF5_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_2_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF5_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_2_CAP_PTR
+#define BIF_CFG_DEV0_EPF5_2_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF5_2_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF5_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_2_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF5_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_2_MIN_GRANT
+#define BIF_CFG_DEV0_EPF5_2_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_2_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF5_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_2_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF5_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF5_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF5_2_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF5_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_2_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_2_PMI_CAP
+#define BIF_CFG_DEV0_EPF5_2_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_2_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF5_2_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF5_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF5_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF5_2_SBRN
+#define BIF_CFG_DEV0_EPF5_2_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_2_FLADJ
+#define BIF_CFG_DEV0_EPF5_2_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_FLADJ__FLADJ_MASK 0x3FL
+//BIF_CFG_DEV0_EPF5_2_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF5_2_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_2_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF5_2_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF5_2_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_2_PCIE_CAP
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF5_2_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF5_2_LINK_CAP
+#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF5_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF5_2_LINK_CNTL
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF5_2_LINK_STATUS
+#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_2_LINK_CAP2
+#define BIF_CFG_DEV0_EPF5_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_2_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF5_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF5_2_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF5_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF5_2_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF5_2_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF5_2_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_2_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF5_2_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_2_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF5_2_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_2_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF5_2_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF5_2_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_2_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF5_2_MSI_MASK
+#define BIF_CFG_DEV0_EPF5_2_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_2_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF5_2_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF5_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_2_MSI_PENDING
+#define BIF_CFG_DEV0_EPF5_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_2_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF5_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_2_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_2_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF5_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF5_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF5_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_2_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF5_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF5_2_MSIX_PBA
+#define BIF_CFG_DEV0_EPF5_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF5_2_SATA_CAP_0
+#define BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV0_EPF5_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF5_2_SATA_CAP_1
+#define BIF_CFG_DEV0_EPF5_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF5_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV0_EPF5_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF5_2_SATA_IDP_INDEX
+#define BIF_CFG_DEV0_EPF5_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF5_2_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV0_EPF5_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF5_2_SATA_IDP_DATA
+#define BIF_CFG_DEV0_EPF5_2_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_2_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF5_2_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF5_2_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_2_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_2_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF5_2_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp
+//BIF_CFG_DEV0_EPF6_2_VENDOR_ID
+#define BIF_CFG_DEV0_EPF6_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_2_DEVICE_ID
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_2_COMMAND
+#define BIF_CFG_DEV0_EPF6_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_2_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_2_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_2_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_2_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_2_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_2_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_2_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_2_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF6_2_STATUS
+#define BIF_CFG_DEV0_EPF6_2_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_2_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_2_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_2_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_2_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_2_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_2_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_2_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF6_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF6_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF6_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF6_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF6_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_2_REVISION_ID
+#define BIF_CFG_DEV0_EPF6_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF6_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF6_2_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF6_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_2_SUB_CLASS
+#define BIF_CFG_DEV0_EPF6_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_2_BASE_CLASS
+#define BIF_CFG_DEV0_EPF6_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_2_CACHE_LINE
+#define BIF_CFG_DEV0_EPF6_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_2_LATENCY
+#define BIF_CFG_DEV0_EPF6_2_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_2_HEADER
+#define BIF_CFG_DEV0_EPF6_2_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_2_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF6_2_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF6_2_BIST
+#define BIF_CFG_DEV0_EPF6_2_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_2_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_2_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF6_2_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF6_2_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF6_2_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_2_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_2_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_2_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_2_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_2_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_2_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF6_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_2_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF6_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_2_CAP_PTR
+#define BIF_CFG_DEV0_EPF6_2_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF6_2_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF6_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_2_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF6_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_2_MIN_GRANT
+#define BIF_CFG_DEV0_EPF6_2_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_2_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF6_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_2_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF6_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF6_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF6_2_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF6_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_2_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_2_PMI_CAP
+#define BIF_CFG_DEV0_EPF6_2_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_2_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF6_2_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF6_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF6_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF6_2_SBRN
+#define BIF_CFG_DEV0_EPF6_2_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_2_FLADJ
+#define BIF_CFG_DEV0_EPF6_2_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_FLADJ__FLADJ_MASK 0x3FL
+//BIF_CFG_DEV0_EPF6_2_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF6_2_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_2_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF6_2_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF6_2_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_2_PCIE_CAP
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF6_2_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF6_2_LINK_CAP
+#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF6_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF6_2_LINK_CNTL
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF6_2_LINK_STATUS
+#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_2_LINK_CAP2
+#define BIF_CFG_DEV0_EPF6_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_2_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF6_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF6_2_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF6_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF6_2_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF6_2_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF6_2_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_2_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF6_2_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_2_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF6_2_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_2_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF6_2_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF6_2_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_2_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF6_2_MSI_MASK
+#define BIF_CFG_DEV0_EPF6_2_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_2_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF6_2_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF6_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_2_MSI_PENDING
+#define BIF_CFG_DEV0_EPF6_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_2_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF6_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_2_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_2_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF6_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF6_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF6_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_2_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF6_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF6_2_MSIX_PBA
+#define BIF_CFG_DEV0_EPF6_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF6_2_SATA_CAP_0
+#define BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV0_EPF6_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF6_2_SATA_CAP_1
+#define BIF_CFG_DEV0_EPF6_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF6_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV0_EPF6_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF6_2_SATA_IDP_INDEX
+#define BIF_CFG_DEV0_EPF6_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF6_2_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV0_EPF6_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF6_2_SATA_IDP_DATA
+#define BIF_CFG_DEV0_EPF6_2_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_2_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF6_2_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF6_2_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_2_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_2_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF6_2_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf7_bifcfgdecp
+//BIF_CFG_DEV0_EPF7_2_VENDOR_ID
+#define BIF_CFG_DEV0_EPF7_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF7_2_DEVICE_ID
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF7_2_COMMAND
+#define BIF_CFG_DEV0_EPF7_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_2_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_2_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_2_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_2_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF7_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF7_2_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF7_2_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF7_2_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF7_2_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF7_2_STATUS
+#define BIF_CFG_DEV0_EPF7_2_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_2_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_2_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_2_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_2_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_2_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_2_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF7_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF7_2_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF7_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF7_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF7_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF7_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF7_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF7_2_REVISION_ID
+#define BIF_CFG_DEV0_EPF7_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF7_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF7_2_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF7_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_2_SUB_CLASS
+#define BIF_CFG_DEV0_EPF7_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_2_BASE_CLASS
+#define BIF_CFG_DEV0_EPF7_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_2_CACHE_LINE
+#define BIF_CFG_DEV0_EPF7_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_2_LATENCY
+#define BIF_CFG_DEV0_EPF7_2_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_2_HEADER
+#define BIF_CFG_DEV0_EPF7_2_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_2_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF7_2_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF7_2_BIST
+#define BIF_CFG_DEV0_EPF7_2_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_2_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_2_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF7_2_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF7_2_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF7_2_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_2_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_2_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_2_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_2_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_2_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_2_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF7_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_2_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF7_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_2_CAP_PTR
+#define BIF_CFG_DEV0_EPF7_2_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF7_2_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF7_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_2_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF7_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_2_MIN_GRANT
+#define BIF_CFG_DEV0_EPF7_2_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_2_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF7_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_2_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF7_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF7_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF7_2_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF7_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_2_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_2_PMI_CAP
+#define BIF_CFG_DEV0_EPF7_2_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_2_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF7_2_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF7_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF7_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF7_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF7_2_SBRN
+#define BIF_CFG_DEV0_EPF7_2_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_2_FLADJ
+#define BIF_CFG_DEV0_EPF7_2_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_FLADJ__FLADJ_MASK 0x3FL
+//BIF_CFG_DEV0_EPF7_2_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF7_2_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_2_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF7_2_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF7_2_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_2_PCIE_CAP
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF7_2_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV0_EPF7_2_LINK_CAP
+#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF7_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF7_2_LINK_CNTL
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV0_EPF7_2_LINK_STATUS
+#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF7_2_LINK_CAP2
+#define BIF_CFG_DEV0_EPF7_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_2_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF7_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF7_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV0_EPF7_2_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF7_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF7_2_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV0_EPF7_2_SLOT_CAP2
+#define BIF_CFG_DEV0_EPF7_2_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_2_SLOT_CNTL2
+#define BIF_CFG_DEV0_EPF7_2_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF7_2_SLOT_STATUS2
+#define BIF_CFG_DEV0_EPF7_2_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF7_2_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF7_2_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF7_2_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_2_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF7_2_MSI_MASK
+#define BIF_CFG_DEV0_EPF7_2_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_2_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF7_2_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF7_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_2_MSI_PENDING
+#define BIF_CFG_DEV0_EPF7_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_2_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF7_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_2_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_2_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF7_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF7_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF7_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF7_2_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF7_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF7_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF7_2_MSIX_PBA
+#define BIF_CFG_DEV0_EPF7_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF7_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF7_2_SATA_CAP_0
+#define BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV0_EPF7_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF7_2_SATA_CAP_1
+#define BIF_CFG_DEV0_EPF7_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF7_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV0_EPF7_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF7_2_SATA_IDP_INDEX
+#define BIF_CFG_DEV0_EPF7_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF7_2_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV0_EPF7_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF7_2_SATA_IDP_DATA
+#define BIF_CFG_DEV0_EPF7_2_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_2_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF7_2_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF7_2_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_2_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_2_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF7_2_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_epf0_bifcfgdecp
+//BIF_CFG_DEV1_EPF0_2_VENDOR_ID
+#define BIF_CFG_DEV1_EPF0_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF0_2_DEVICE_ID
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF0_2_COMMAND
+#define BIF_CFG_DEV1_EPF0_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_2_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_2_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_2_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF0_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_2_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF0_2_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF0_2_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF0_2_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV1_EPF0_2_STATUS
+#define BIF_CFG_DEV1_EPF0_2_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_2_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_2_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_2_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_2_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF0_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF0_2_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV1_EPF0_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF0_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV1_EPF0_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV1_EPF0_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF0_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_2_REVISION_ID
+#define BIF_CFG_DEV1_EPF0_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_2_PROG_INTERFACE
+#define BIF_CFG_DEV1_EPF0_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_2_SUB_CLASS
+#define BIF_CFG_DEV1_EPF0_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_2_BASE_CLASS
+#define BIF_CFG_DEV1_EPF0_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_2_CACHE_LINE
+#define BIF_CFG_DEV1_EPF0_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_2_LATENCY
+#define BIF_CFG_DEV1_EPF0_2_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_2_HEADER
+#define BIF_CFG_DEV1_EPF0_2_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_2_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV1_EPF0_2_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV1_EPF0_2_BIST
+#define BIF_CFG_DEV1_EPF0_2_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_2_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_2_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_2_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV1_EPF0_2_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV1_EPF0_2_BASE_ADDR_1
+#define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_2_BASE_ADDR_2
+#define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_2_BASE_ADDR_3
+#define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_2_BASE_ADDR_4
+#define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_2_BASE_ADDR_5
+#define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_2_BASE_ADDR_6
+#define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_2_ADAPTER_ID
+#define BIF_CFG_DEV1_EPF0_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_2_ROM_BASE_ADDR
+#define BIF_CFG_DEV1_EPF0_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_2_CAP_PTR
+#define BIF_CFG_DEV1_EPF0_2_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV1_EPF0_2_INTERRUPT_LINE
+#define BIF_CFG_DEV1_EPF0_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_2_INTERRUPT_PIN
+#define BIF_CFG_DEV1_EPF0_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_2_MIN_GRANT
+#define BIF_CFG_DEV1_EPF0_2_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_2_MAX_LATENCY
+#define BIF_CFG_DEV1_EPF0_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_2_VENDOR_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF0_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV1_EPF0_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV1_EPF0_2_ADAPTER_ID_W
+#define BIF_CFG_DEV1_EPF0_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_2_PMI_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_2_PMI_CAP
+#define BIF_CFG_DEV1_EPF0_2_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_2_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_2_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV1_EPF0_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF0_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF0_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL
+#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_2_PCIE_CAP
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV1_EPF0_2_DEVICE_CAP
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV1_EPF0_2_LINK_CAP
+#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF0_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_2_LINK_CNTL
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV1_EPF0_2_LINK_STATUS
+#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS2
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF0_2_LINK_CAP2
+#define BIF_CFG_DEV1_EPF0_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV1_EPF0_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF0_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV1_EPF0_2_LINK_CNTL2
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF0_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV1_EPF0_2_LINK_STATUS2
+#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV1_EPF0_2_SLOT_CAP2
+#define BIF_CFG_DEV1_EPF0_2_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_2_SLOT_CNTL2
+#define BIF_CFG_DEV1_EPF0_2_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF0_2_SLOT_STATUS2
+#define BIF_CFG_DEV1_EPF0_2_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF0_2_MSI_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL
+#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV1_EPF0_2_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV1_EPF0_2_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_2_MSI_MSG_DATA
+#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_EPF0_2_MSI_MASK
+#define BIF_CFG_DEV1_EPF0_2_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_2_MSI_MSG_DATA_64
+#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_EPF0_2_MSI_MASK_64
+#define BIF_CFG_DEV1_EPF0_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_2_MSI_PENDING
+#define BIF_CFG_DEV1_EPF0_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_2_MSI_PENDING_64
+#define BIF_CFG_DEV1_EPF0_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_2_MSIX_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_2_MSIX_MSG_CNTL
+#define BIF_CFG_DEV1_EPF0_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV1_EPF0_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF0_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_2_MSIX_TABLE
+#define BIF_CFG_DEV1_EPF0_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF0_2_MSIX_PBA
+#define BIF_CFG_DEV1_EPF0_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF0_2_SATA_CAP_0
+#define BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV1_EPF0_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_2_SATA_CAP_1
+#define BIF_CFG_DEV1_EPF0_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF0_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV1_EPF0_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_2_SATA_IDP_INDEX
+#define BIF_CFG_DEV1_EPF0_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV1_EPF0_2_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV1_EPF0_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV1_EPF0_2_SATA_IDP_DATA
+#define BIF_CFG_DEV1_EPF0_2_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_2_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG1
+#define BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG2
+#define BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG3
+#define BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_2_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CAP
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CAP
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CAP
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CAP
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CAP
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CAP
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV1_EPF0_2_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_2_PCIE_DPA_STATUS
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CNTL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV1_EPF0_2_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CAP
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CNTL
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_epf1_bifcfgdecp
+//BIF_CFG_DEV1_EPF1_2_VENDOR_ID
+#define BIF_CFG_DEV1_EPF1_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF1_2_DEVICE_ID
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF1_2_COMMAND
+#define BIF_CFG_DEV1_EPF1_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_2_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_2_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_2_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_2_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF1_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF1_2_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF1_2_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF1_2_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF1_2_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV1_EPF1_2_STATUS
+#define BIF_CFG_DEV1_EPF1_2_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_2_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_2_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_2_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_2_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_2_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_2_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF1_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF1_2_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV1_EPF1_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF1_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV1_EPF1_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV1_EPF1_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF1_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF1_2_REVISION_ID
+#define BIF_CFG_DEV1_EPF1_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF1_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV1_EPF1_2_PROG_INTERFACE
+#define BIF_CFG_DEV1_EPF1_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_2_SUB_CLASS
+#define BIF_CFG_DEV1_EPF1_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_2_BASE_CLASS
+#define BIF_CFG_DEV1_EPF1_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_2_CACHE_LINE
+#define BIF_CFG_DEV1_EPF1_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_2_LATENCY
+#define BIF_CFG_DEV1_EPF1_2_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_2_HEADER
+#define BIF_CFG_DEV1_EPF1_2_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_2_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV1_EPF1_2_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV1_EPF1_2_BIST
+#define BIF_CFG_DEV1_EPF1_2_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_2_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_2_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF1_2_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV1_EPF1_2_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV1_EPF1_2_BASE_ADDR_1
+#define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_2_BASE_ADDR_2
+#define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_2_BASE_ADDR_3
+#define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_2_BASE_ADDR_4
+#define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_2_BASE_ADDR_5
+#define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_2_BASE_ADDR_6
+#define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_2_ADAPTER_ID
+#define BIF_CFG_DEV1_EPF1_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_2_ROM_BASE_ADDR
+#define BIF_CFG_DEV1_EPF1_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_2_CAP_PTR
+#define BIF_CFG_DEV1_EPF1_2_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV1_EPF1_2_INTERRUPT_LINE
+#define BIF_CFG_DEV1_EPF1_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_2_INTERRUPT_PIN
+#define BIF_CFG_DEV1_EPF1_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_2_MIN_GRANT
+#define BIF_CFG_DEV1_EPF1_2_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_2_MAX_LATENCY
+#define BIF_CFG_DEV1_EPF1_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_2_VENDOR_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF1_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV1_EPF1_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV1_EPF1_2_ADAPTER_ID_W
+#define BIF_CFG_DEV1_EPF1_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_2_PMI_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_2_PMI_CAP
+#define BIF_CFG_DEV1_EPF1_2_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_2_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF1_2_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV1_EPF1_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF1_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF1_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL
+#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF1_2_SBRN
+#define BIF_CFG_DEV1_EPF1_2_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_2_FLADJ
+#define BIF_CFG_DEV1_EPF1_2_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_FLADJ__FLADJ_MASK 0x3FL
+//BIF_CFG_DEV1_EPF1_2_DBESL_DBESLD
+#define BIF_CFG_DEV1_EPF1_2_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_2_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF1_2_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV1_EPF1_2_PCIE_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_2_PCIE_CAP
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV1_EPF1_2_DEVICE_CAP
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV1_EPF1_2_LINK_CAP
+#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF1_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF1_2_LINK_CNTL
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV1_EPF1_2_LINK_STATUS
+#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS2
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF1_2_LINK_CAP2
+#define BIF_CFG_DEV1_EPF1_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_2_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV1_EPF1_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF1_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV1_EPF1_2_LINK_CNTL2
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF1_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV1_EPF1_2_LINK_STATUS2
+#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV1_EPF1_2_SLOT_CAP2
+#define BIF_CFG_DEV1_EPF1_2_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_2_SLOT_CNTL2
+#define BIF_CFG_DEV1_EPF1_2_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF1_2_SLOT_STATUS2
+#define BIF_CFG_DEV1_EPF1_2_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF1_2_MSI_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL
+#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV1_EPF1_2_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV1_EPF1_2_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_2_MSI_MSG_DATA
+#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_EPF1_2_MSI_MASK
+#define BIF_CFG_DEV1_EPF1_2_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_2_MSI_MSG_DATA_64
+#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_EPF1_2_MSI_MASK_64
+#define BIF_CFG_DEV1_EPF1_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_2_MSI_PENDING
+#define BIF_CFG_DEV1_EPF1_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_2_MSI_PENDING_64
+#define BIF_CFG_DEV1_EPF1_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_2_MSIX_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_2_MSIX_MSG_CNTL
+#define BIF_CFG_DEV1_EPF1_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV1_EPF1_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF1_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV1_EPF1_2_MSIX_TABLE
+#define BIF_CFG_DEV1_EPF1_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF1_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF1_2_MSIX_PBA
+#define BIF_CFG_DEV1_EPF1_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF1_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF1_2_SATA_CAP_0
+#define BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV1_EPF1_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF1_2_SATA_CAP_1
+#define BIF_CFG_DEV1_EPF1_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF1_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV1_EPF1_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF1_2_SATA_IDP_INDEX
+#define BIF_CFG_DEV1_EPF1_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV1_EPF1_2_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV1_EPF1_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV1_EPF1_2_SATA_IDP_DATA
+#define BIF_CFG_DEV1_EPF1_2_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG1
+#define BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG2
+#define BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG3
+#define BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_2_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CAP
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CAP
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CAP
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CAP
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CAP
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CAP
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV1_EPF1_2_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF1_2_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_2_PCIE_DPA_STATUS
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CNTL
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_2_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV1_EPF1_2_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CAP
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CNTL
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_epf2_bifcfgdecp
+//BIF_CFG_DEV1_EPF2_2_VENDOR_ID
+#define BIF_CFG_DEV1_EPF2_2_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF2_2_DEVICE_ID
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF2_2_COMMAND
+#define BIF_CFG_DEV1_EPF2_2_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF2_2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF2_2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_2_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_2_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_2_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_2_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF2_2_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF2_2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF2_2_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF2_2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF2_2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF2_2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF2_2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF2_2_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF2_2_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF2_2_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF2_2_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV1_EPF2_2_STATUS
+#define BIF_CFG_DEV1_EPF2_2_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_2_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_2_STATUS__PCI_66_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_2_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF2_2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF2_2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF2_2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_2_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF2_2_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF2_2_STATUS__PCI_66_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF2_2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF2_2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF2_2_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV1_EPF2_2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF2_2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV1_EPF2_2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV1_EPF2_2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF2_2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF2_2_REVISION_ID
+#define BIF_CFG_DEV1_EPF2_2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF2_2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV1_EPF2_2_PROG_INTERFACE
+#define BIF_CFG_DEV1_EPF2_2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_2_SUB_CLASS
+#define BIF_CFG_DEV1_EPF2_2_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_2_BASE_CLASS
+#define BIF_CFG_DEV1_EPF2_2_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_2_CACHE_LINE
+#define BIF_CFG_DEV1_EPF2_2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_2_LATENCY
+#define BIF_CFG_DEV1_EPF2_2_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_2_HEADER
+#define BIF_CFG_DEV1_EPF2_2_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_2_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV1_EPF2_2_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV1_EPF2_2_BIST
+#define BIF_CFG_DEV1_EPF2_2_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_2_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_2_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF2_2_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV1_EPF2_2_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV1_EPF2_2_BASE_ADDR_1
+#define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_2_BASE_ADDR_2
+#define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_2_BASE_ADDR_3
+#define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_2_BASE_ADDR_4
+#define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_2_BASE_ADDR_5
+#define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_2_BASE_ADDR_6
+#define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_2_ADAPTER_ID
+#define BIF_CFG_DEV1_EPF2_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF2_2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF2_2_ROM_BASE_ADDR
+#define BIF_CFG_DEV1_EPF2_2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_2_CAP_PTR
+#define BIF_CFG_DEV1_EPF2_2_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_CAP_PTR__CAP_PTR_MASK 0x000000FFL
+//BIF_CFG_DEV1_EPF2_2_INTERRUPT_LINE
+#define BIF_CFG_DEV1_EPF2_2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_2_INTERRUPT_PIN
+#define BIF_CFG_DEV1_EPF2_2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_2_MIN_GRANT
+#define BIF_CFG_DEV1_EPF2_2_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_2_MAX_LATENCY
+#define BIF_CFG_DEV1_EPF2_2_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_2_VENDOR_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF2_2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV1_EPF2_2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV1_EPF2_2_ADAPTER_ID_W
+#define BIF_CFG_DEV1_EPF2_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF2_2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF2_2_PMI_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF2_2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF2_2_PMI_CAP
+#define BIF_CFG_DEV1_EPF2_2_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_2_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_2_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_2_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF2_2_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF2_2_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF2_2_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF2_2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF2_2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV1_EPF2_2_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF2_2_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF2_2_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL
+#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF2_2_SBRN
+#define BIF_CFG_DEV1_EPF2_2_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_2_FLADJ
+#define BIF_CFG_DEV1_EPF2_2_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_FLADJ__FLADJ_MASK 0x3FL
+//BIF_CFG_DEV1_EPF2_2_DBESL_DBESLD
+#define BIF_CFG_DEV1_EPF2_2_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_2_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF2_2_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV1_EPF2_2_PCIE_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF2_2_PCIE_CAP
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV1_EPF2_2_DEVICE_CAP
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//BIF_CFG_DEV1_EPF2_2_LINK_CAP
+#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF2_2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF2_2_LINK_CNTL
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+//BIF_CFG_DEV1_EPF2_2_LINK_STATUS
+#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+//BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS2
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF2_2_LINK_CAP2
+#define BIF_CFG_DEV1_EPF2_2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF2_2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_2_LINK_CAP2__RESERVED__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV1_EPF2_2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF2_2_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L
+//BIF_CFG_DEV1_EPF2_2_LINK_CNTL2
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF2_2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV1_EPF2_2_LINK_STATUS2
+#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF2_2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L
+//BIF_CFG_DEV1_EPF2_2_SLOT_CAP2
+#define BIF_CFG_DEV1_EPF2_2_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_2_SLOT_CNTL2
+#define BIF_CFG_DEV1_EPF2_2_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF2_2_SLOT_STATUS2
+#define BIF_CFG_DEV1_EPF2_2_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF2_2_MSI_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF2_2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL
+#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV1_EPF2_2_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV1_EPF2_2_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_2_MSI_MSG_DATA
+#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_EPF2_2_MSI_MASK
+#define BIF_CFG_DEV1_EPF2_2_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_2_MSI_MSG_DATA_64
+#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_EPF2_2_MSI_MASK_64
+#define BIF_CFG_DEV1_EPF2_2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_2_MSI_PENDING
+#define BIF_CFG_DEV1_EPF2_2_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_2_MSI_PENDING_64
+#define BIF_CFG_DEV1_EPF2_2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_2_MSIX_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF2_2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF2_2_MSIX_MSG_CNTL
+#define BIF_CFG_DEV1_EPF2_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF2_2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV1_EPF2_2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF2_2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV1_EPF2_2_MSIX_TABLE
+#define BIF_CFG_DEV1_EPF2_2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF2_2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF2_2_MSIX_PBA
+#define BIF_CFG_DEV1_EPF2_2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF2_2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF2_2_SATA_CAP_0
+#define BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV1_EPF2_2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF2_2_SATA_CAP_1
+#define BIF_CFG_DEV1_EPF2_2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF2_2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF2_2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV1_EPF2_2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF2_2_SATA_IDP_INDEX
+#define BIF_CFG_DEV1_EPF2_2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF2_2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_2_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV1_EPF2_2_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV1_EPF2_2_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV1_EPF2_2_SATA_IDP_DATA
+#define BIF_CFG_DEV1_EPF2_2_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+//BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG1
+#define BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG2
+#define BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG3
+#define BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF2_2_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CAP
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CAP
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CAP
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CAP
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CAP
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CAP
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L
+//BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV1_EPF2_2_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF2_2_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_2_PCIE_DPA_STATUS
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CNTL
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL
+//BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF2_2_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV1_EPF2_2_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CAP
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CNTL
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF2_2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC
+//BIF_BX_PF1_MM_INDEX
+#define BIF_BX_PF1_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_PF1_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_PF1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_PF1_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_PF1_MM_DATA
+#define BIF_BX_PF1_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MM_INDEX_HI
+#define BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_SYSDEC
+//BIF_BX_PF1_SYSHUB_INDEX_OVLP
+#define BIF_BX_PF1_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__SHIFT 0x0
+#define BIF_BX_PF1_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET_MASK 0x003FFFFFL
+//BIF_BX_PF1_SYSHUB_DATA_OVLP
+#define BIF_BX_PF1_SYSHUB_DATA_OVLP__SYSHUB_DATA__SHIFT 0x0
+#define BIF_BX_PF1_SYSHUB_DATA_OVLP__SYSHUB_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_PCIE_INDEX
+#define BIF_BX_PF1_PCIE_INDEX__PCIE_INDEX__SHIFT 0x0
+#define BIF_BX_PF1_PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_PCIE_DATA
+#define BIF_BX_PF1_PCIE_DATA__PCIE_DATA__SHIFT 0x0
+#define BIF_BX_PF1_PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_PCIE_INDEX2
+#define BIF_BX_PF1_PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0
+#define BIF_BX_PF1_PCIE_INDEX2__PCIE_INDEX2_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_PCIE_DATA2
+#define BIF_BX_PF1_PCIE_DATA2__PCIE_DATA2__SHIFT 0x0
+#define BIF_BX_PF1_PCIE_DATA2__PCIE_DATA2_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_SBIOS_SCRATCH_0
+#define BIF_BX_PF1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define BIF_BX_PF1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_SBIOS_SCRATCH_1
+#define BIF_BX_PF1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define BIF_BX_PF1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_SBIOS_SCRATCH_2
+#define BIF_BX_PF1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define BIF_BX_PF1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_SBIOS_SCRATCH_3
+#define BIF_BX_PF1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define BIF_BX_PF1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIOS_SCRATCH_0
+#define BIF_BX_PF1_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0
+#define BIF_BX_PF1_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIOS_SCRATCH_1
+#define BIF_BX_PF1_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0
+#define BIF_BX_PF1_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIOS_SCRATCH_2
+#define BIF_BX_PF1_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0
+#define BIF_BX_PF1_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIOS_SCRATCH_3
+#define BIF_BX_PF1_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0
+#define BIF_BX_PF1_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIOS_SCRATCH_4
+#define BIF_BX_PF1_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0
+#define BIF_BX_PF1_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIOS_SCRATCH_5
+#define BIF_BX_PF1_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0
+#define BIF_BX_PF1_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIOS_SCRATCH_6
+#define BIF_BX_PF1_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0
+#define BIF_BX_PF1_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIOS_SCRATCH_7
+#define BIF_BX_PF1_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0
+#define BIF_BX_PF1_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIOS_SCRATCH_8
+#define BIF_BX_PF1_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0
+#define BIF_BX_PF1_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIOS_SCRATCH_9
+#define BIF_BX_PF1_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0
+#define BIF_BX_PF1_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIOS_SCRATCH_10
+#define BIF_BX_PF1_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0
+#define BIF_BX_PF1_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIOS_SCRATCH_11
+#define BIF_BX_PF1_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0
+#define BIF_BX_PF1_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIOS_SCRATCH_12
+#define BIF_BX_PF1_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0
+#define BIF_BX_PF1_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIOS_SCRATCH_13
+#define BIF_BX_PF1_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0
+#define BIF_BX_PF1_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIOS_SCRATCH_14
+#define BIF_BX_PF1_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0
+#define BIF_BX_PF1_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIOS_SCRATCH_15
+#define BIF_BX_PF1_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0
+#define BIF_BX_PF1_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIF_RLC_INTR_CNTL
+#define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT 0x0
+#define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT 0x1
+#define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT 0x2
+#define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT 0x3
+#define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED_MASK 0x00000002L
+#define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR_MASK 0x00000004L
+#define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION_MASK 0x00000008L
+//BIF_BX_PF1_BIF_VCE_INTR_CNTL
+#define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT 0x0
+#define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT 0x1
+#define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT 0x3
+#define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED_MASK 0x00000002L
+#define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR_MASK 0x00000004L
+#define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION_MASK 0x00000008L
+//BIF_BX_PF1_BIF_UVD_INTR_CNTL
+#define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT 0x0
+#define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT 0x1
+#define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT 0x2
+#define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT 0x3
+#define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED_MASK 0x00000002L
+#define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR_MASK 0x00000004L
+#define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION_MASK 0x00000008L
+//BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000FFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000FFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR1
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000FFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR1
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000FFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR2
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000FFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR2
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000FFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR3
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000FFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR3
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000FFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR4
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000FFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR4
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000FFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR5
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000FFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR5
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000FFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR6
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000FFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR6
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000FFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR7
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000FFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR7
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000FFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_CNTL
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000FFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_ZERO_CPL
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_ONE_CPL
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0
+#define BIF_BX_PF1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_syshub_mmreg_ind_syshubdec
+//SYSHUB_MMREG_IND0_SYSHUB_INDEX
+#define SYSHUB_MMREG_IND0_SYSHUB_INDEX__INDEX__SHIFT 0x0
+#define SYSHUB_MMREG_IND0_SYSHUB_INDEX__INDEX_MASK 0xFFFFFFFFL
+//SYSHUB_MMREG_IND0_SYSHUB_DATA
+#define SYSHUB_MMREG_IND0_SYSHUB_DATA__DATA__SHIFT 0x0
+#define SYSHUB_MMREG_IND0_SYSHUB_DATA__DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1
+//RCC_EP_DEV0_2_EP_PCIE_SCRATCH
+#define RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//RCC_EP_DEV0_2_EP_PCIE_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
+#define RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
+#define RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L
+#define RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L
+#define RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//RCC_EP_DEV0_2_EP_PCIE_INT_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L
+//RCC_EP_DEV0_2_EP_PCIE_INT_STATUS
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L
+//RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L
+//RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+//RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+//RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL
+#define RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL
+//RCC_EP_DEV0_2_EP_PCIEP_RESERVED
+#define RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL
+//RCC_EP_DEV0_2_EP_PCIE_TX_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L
+//RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID
+#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L
+//RCC_EP_DEV0_2_EP_PCIE_RX_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+//RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+
+
+// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1
+//RCC_DWN_DEV0_2_DN_PCIE_RESERVED
+#define RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
+#define RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DWN_DEV0_2_DN_PCIE_SCRATCH
+#define RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//RCC_DWN_DEV0_2_DN_PCIE_CNTL
+#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
+#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7
+#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L
+#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L
+#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL
+#define RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
+#define RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L
+//RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2
+#define RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
+#define RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L
+//RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL
+#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8
+#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L
+//RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1
+//RCC_DWNP_DEV0_2_PCIE_ERR_CNTL
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+//RCC_DWNP_DEV0_2_PCIE_RX_CNTL
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+//RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+//RCC_DWNP_DEV0_2_PCIE_LC_CNTL2
+#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+//RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC
+#define RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa
+#define RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L
+//RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP
+#define RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0
+#define RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_BIFDEC1
+//BIF_BX_PF1_BIF_MM_INDACCESS_CNTL
+#define BIF_BX_PF1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
+#define BIF_BX_PF1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L
+//BIF_BX_PF1_BUS_CNTL
+#define BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_EP__SHIFT 0x3
+#define BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_DN__SHIFT 0x4
+#define BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_SWUS__SHIFT 0x5
+#define BIF_BX_PF1_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6
+#define BIF_BX_PF1_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7
+#define BIF_BX_PF1_BUS_CNTL__SET_AZ_TC__SHIFT 0xa
+#define BIF_BX_PF1_BUS_CNTL__SET_MC_TC__SHIFT 0xd
+#define BIF_BX_PF1_BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10
+#define BIF_BX_PF1_BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11
+#define BIF_BX_PF1_BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12
+#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT 0x13
+#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT 0x14
+#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT 0x15
+#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT 0x16
+#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT 0x17
+#define BIF_BX_PF1_BUS_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT 0x18
+#define BIF_BX_PF1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT 0x19
+#define BIF_BX_PF1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT 0x1a
+#define BIF_BX_PF1_BUS_CNTL__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT 0x1b
+#define BIF_BX_PF1_BUS_CNTL__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT 0x1c
+#define BIF_BX_PF1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT 0x1d
+#define BIF_BX_PF1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT 0x1e
+#define BIF_BX_PF1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT 0x1f
+#define BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_EP_MASK 0x00000008L
+#define BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_DN_MASK 0x00000010L
+#define BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_SWUS_MASK 0x00000020L
+#define BIF_BX_PF1_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L
+#define BIF_BX_PF1_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L
+#define BIF_BX_PF1_BUS_CNTL__SET_AZ_TC_MASK 0x00001C00L
+#define BIF_BX_PF1_BUS_CNTL__SET_MC_TC_MASK 0x0000E000L
+#define BIF_BX_PF1_BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L
+#define BIF_BX_PF1_BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L
+#define BIF_BX_PF1_BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L
+#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK 0x00080000L
+#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK 0x00100000L
+#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK 0x00200000L
+#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK 0x00400000L
+#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK 0x00800000L
+#define BIF_BX_PF1_BUS_CNTL__UR_OVRD_FOR_ECRC_EN_MASK 0x01000000L
+#define BIF_BX_PF1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK 0x02000000L
+#define BIF_BX_PF1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK 0x04000000L
+#define BIF_BX_PF1_BUS_CNTL__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK 0x08000000L
+#define BIF_BX_PF1_BUS_CNTL__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK 0x10000000L
+#define BIF_BX_PF1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK 0x20000000L
+#define BIF_BX_PF1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK 0x40000000L
+#define BIF_BX_PF1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK 0x80000000L
+//BIF_BX_PF1_BIF_SCRATCH0
+#define BIF_BX_PF1_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0
+#define BIF_BX_PF1_BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIF_SCRATCH1
+#define BIF_BX_PF1_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0
+#define BIF_BX_PF1_BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BX_RESET_EN
+#define BIF_BX_PF1_BX_RESET_EN__COR_RESET_EN__SHIFT 0x0
+#define BIF_BX_PF1_BX_RESET_EN__REG_RESET_EN__SHIFT 0x1
+#define BIF_BX_PF1_BX_RESET_EN__STY_RESET_EN__SHIFT 0x2
+#define BIF_BX_PF1_BX_RESET_EN__FLR_TWICE_EN__SHIFT 0x8
+#define BIF_BX_PF1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10
+#define BIF_BX_PF1_BX_RESET_EN__COR_RESET_EN_MASK 0x00000001L
+#define BIF_BX_PF1_BX_RESET_EN__REG_RESET_EN_MASK 0x00000002L
+#define BIF_BX_PF1_BX_RESET_EN__STY_RESET_EN_MASK 0x00000004L
+#define BIF_BX_PF1_BX_RESET_EN__FLR_TWICE_EN_MASK 0x00000100L
+#define BIF_BX_PF1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L
+//BIF_BX_PF1_MM_CFGREGS_CNTL
+#define BIF_BX_PF1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0
+#define BIF_BX_PF1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6
+#define BIF_BX_PF1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f
+#define BIF_BX_PF1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L
+#define BIF_BX_PF1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000C0L
+#define BIF_BX_PF1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L
+//BIF_BX_PF1_BX_RESET_CNTL
+#define BIF_BX_PF1_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0
+#define BIF_BX_PF1_BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L
+//BIF_BX_PF1_INTERRUPT_CNTL
+#define BIF_BX_PF1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0
+#define BIF_BX_PF1_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1
+#define BIF_BX_PF1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3
+#define BIF_BX_PF1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4
+#define BIF_BX_PF1_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8
+#define BIF_BX_PF1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf
+#define BIF_BX_PF1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10
+#define BIF_BX_PF1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11
+#define BIF_BX_PF1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L
+#define BIF_BX_PF1_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L
+#define BIF_BX_PF1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L
+#define BIF_BX_PF1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L
+#define BIF_BX_PF1_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L
+#define BIF_BX_PF1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L
+#define BIF_BX_PF1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L
+#define BIF_BX_PF1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L
+//BIF_BX_PF1_INTERRUPT_CNTL2
+#define BIF_BX_PF1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0
+#define BIF_BX_PF1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_CLKREQB_PAD_CNTL
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L
+#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L
+//BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__SHIFT 0x11
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__SHIFT 0x12
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x18
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS_MASK 0x00020000L
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS_MASK 0x00040000L
+#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK 0x01000000L
+//BIF_BX_PF1_BIF_DOORBELL_CNTL
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L
+#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L
+//BIF_BX_PF1_BIF_DOORBELL_INT_CNTL
+#define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0
+#define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS__SHIFT 0x1
+#define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10
+#define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR__SHIFT 0x11
+#define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS_MASK 0x00000002L
+#define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L
+#define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR_MASK 0x00020000L
+//BIF_BX_PF1_BIF_FB_EN
+#define BIF_BX_PF1_BIF_FB_EN__FB_READ_EN__SHIFT 0x0
+#define BIF_BX_PF1_BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1
+#define BIF_BX_PF1_BIF_FB_EN__FB_READ_EN_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L
+//BIF_BX_PF1_BIF_BUSY_DELAY_CNTR
+#define BIF_BX_PF1_BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0
+#define BIF_BX_PF1_BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x0000003FL
+//BIF_BX_PF1_BIF_MST_TRANS_PENDING_VF
+#define BIF_BX_PF1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_PF1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x0000FFFFL
+//BIF_BX_PF1_BIF_SLV_TRANS_PENDING_VF
+#define BIF_BX_PF1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_PF1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x0000FFFFL
+//BIF_BX_PF1_BACO_CNTL
+#define BIF_BX_PF1_BACO_CNTL__BACO_EN__SHIFT 0x0
+#define BIF_BX_PF1_BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT 0x1
+#define BIF_BX_PF1_BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2
+#define BIF_BX_PF1_BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3
+#define BIF_BX_PF1_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5
+#define BIF_BX_PF1_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6
+#define BIF_BX_PF1_BACO_CNTL__BACO_MODE__SHIFT 0x8
+#define BIF_BX_PF1_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9
+#define BIF_BX_PF1_BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f
+#define BIF_BX_PF1_BACO_CNTL__BACO_EN_MASK 0x00000001L
+#define BIF_BX_PF1_BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK 0x00000002L
+#define BIF_BX_PF1_BACO_CNTL__BACO_DUMMY_EN_MASK 0x00000004L
+#define BIF_BX_PF1_BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L
+#define BIF_BX_PF1_BACO_CNTL__BACO_DSTATE_BYPASS_MASK 0x00000020L
+#define BIF_BX_PF1_BACO_CNTL__BACO_RST_INTR_MASK_MASK 0x00000040L
+#define BIF_BX_PF1_BACO_CNTL__BACO_MODE_MASK 0x00000100L
+#define BIF_BX_PF1_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000200L
+#define BIF_BX_PF1_BACO_CNTL__BACO_AUTO_EXIT_MASK 0x80000000L
+//BIF_BX_PF1_BIF_BACO_EXIT_TIME0
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK 0x000FFFFFL
+//BIF_BX_PF1_BIF_BACO_EXIT_TIMER1
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT 0x18
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR__SHIFT 0x19
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK 0x000FFFFFL
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK 0x01000000L
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR_MASK 0x02000000L
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK 0x04000000L
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK 0x08000000L
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK 0x10000000L
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK 0x60000000L
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK 0x80000000L
+//BIF_BX_PF1_BIF_BACO_EXIT_TIMER2
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK 0x000FFFFFL
+//BIF_BX_PF1_BIF_BACO_EXIT_TIMER3
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK 0x000FFFFFL
+//BIF_BX_PF1_BIF_BACO_EXIT_TIMER4
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0
+#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK 0x000FFFFFL
+//BIF_BX_PF1_MEM_TYPE_CNTL
+#define BIF_BX_PF1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0
+#define BIF_BX_PF1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L
+//BIF_BX_PF1_SMU_BIF_VDDGFX_PWR_STATUS
+#define BIF_BX_PF1_SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT 0x0
+#define BIF_BX_PF1_SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF_MASK 0x00000001L
+//BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER
+#define BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e
+#define BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f
+#define BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN_MASK 0x40000000L
+#define BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN_MASK 0x80000000L
+//BIF_BX_PF1_BIF_VDDGFX_GFX0_UPPER
+#define BIF_BX_PF1_BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER_MASK 0x0003FFFCL
+//BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER
+#define BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e
+#define BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f
+#define BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN_MASK 0x40000000L
+#define BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN_MASK 0x80000000L
+//BIF_BX_PF1_BIF_VDDGFX_GFX1_UPPER
+#define BIF_BX_PF1_BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER_MASK 0x0003FFFCL
+//BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER
+#define BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e
+#define BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f
+#define BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN_MASK 0x40000000L
+#define BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN_MASK 0x80000000L
+//BIF_BX_PF1_BIF_VDDGFX_GFX2_UPPER
+#define BIF_BX_PF1_BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER_MASK 0x0003FFFCL
+//BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER
+#define BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e
+#define BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f
+#define BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN_MASK 0x40000000L
+#define BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN_MASK 0x80000000L
+//BIF_BX_PF1_BIF_VDDGFX_GFX3_UPPER
+#define BIF_BX_PF1_BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER_MASK 0x0003FFFCL
+//BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER
+#define BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e
+#define BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f
+#define BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN_MASK 0x40000000L
+#define BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN_MASK 0x80000000L
+//BIF_BX_PF1_BIF_VDDGFX_GFX4_UPPER
+#define BIF_BX_PF1_BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER_MASK 0x0003FFFCL
+//BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER
+#define BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e
+#define BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f
+#define BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK 0x40000000L
+#define BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN_MASK 0x80000000L
+//BIF_BX_PF1_BIF_VDDGFX_GFX5_UPPER
+#define BIF_BX_PF1_BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER_MASK 0x0003FFFCL
+//BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER
+#define BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e
+#define BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f
+#define BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN_MASK 0x40000000L
+#define BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN_MASK 0x80000000L
+//BIF_BX_PF1_BIF_VDDGFX_RSV1_UPPER
+#define BIF_BX_PF1_BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER_MASK 0x0003FFFCL
+//BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER
+#define BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e
+#define BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f
+#define BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN_MASK 0x40000000L
+#define BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN_MASK 0x80000000L
+//BIF_BX_PF1_BIF_VDDGFX_RSV2_UPPER
+#define BIF_BX_PF1_BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER_MASK 0x0003FFFCL
+//BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER
+#define BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e
+#define BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f
+#define BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN_MASK 0x40000000L
+#define BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN_MASK 0x80000000L
+//BIF_BX_PF1_BIF_VDDGFX_RSV3_UPPER
+#define BIF_BX_PF1_BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER_MASK 0x0003FFFCL
+//BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER
+#define BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e
+#define BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f
+#define BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN_MASK 0x40000000L
+#define BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN_MASK 0x80000000L
+//BIF_BX_PF1_BIF_VDDGFX_RSV4_UPPER
+#define BIF_BX_PF1_BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER_MASK 0x0003FFFCL
+//BIF_BX_PF1_BIF_VDDGFX_FB_CMP
+#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0
+#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1
+#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2
+#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3
+#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4
+#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5
+#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN_MASK 0x00000002L
+#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN_MASK 0x00000004L
+#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN_MASK 0x00000008L
+#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN_MASK 0x00000010L
+#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN_MASK 0x00000020L
+//BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER
+#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT 0x1f
+#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER_MASK 0x00000FFCL
+#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN_MASK 0x80000000L
+//BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_UPPER
+#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER_MASK 0x00000FFCL
+//BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER
+#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT 0x1f
+#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER_MASK 0x00000FFCL
+#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN_MASK 0x80000000L
+//BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_UPPER
+#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2
+#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER_MASK 0x00000FFCL
+//BIF_BX_PF1_REMAP_HDP_MEM_FLUSH_CNTL
+#define BIF_BX_PF1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2
+#define BIF_BX_PF1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL
+//BIF_BX_PF1_REMAP_HDP_REG_FLUSH_CNTL
+#define BIF_BX_PF1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2
+#define BIF_BX_PF1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL
+//BIF_BX_PF1_BIF_RB_CNTL
+#define BIF_BX_PF1_BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define BIF_BX_PF1_BIF_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define BIF_BX_PF1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
+#define BIF_BX_PF1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9
+#define BIF_BX_PF1_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11
+#define BIF_BX_PF1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
+#define BIF_BX_PF1_BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define BIF_BX_PF1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L
+#define BIF_BX_PF1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003E00L
+#define BIF_BX_PF1_BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L
+#define BIF_BX_PF1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L
+//BIF_BX_PF1_BIF_RB_BASE
+#define BIF_BX_PF1_BIF_RB_BASE__ADDR__SHIFT 0x0
+#define BIF_BX_PF1_BIF_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_BIF_RB_RPTR
+#define BIF_BX_PF1_BIF_RB_RPTR__OFFSET__SHIFT 0x2
+#define BIF_BX_PF1_BIF_RB_RPTR__OFFSET_MASK 0x0003FFFCL
+//BIF_BX_PF1_BIF_RB_WPTR
+#define BIF_BX_PF1_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0
+#define BIF_BX_PF1_BIF_RB_WPTR__OFFSET__SHIFT 0x2
+#define BIF_BX_PF1_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_RB_WPTR__OFFSET_MASK 0x0003FFFCL
+//BIF_BX_PF1_BIF_RB_WPTR_ADDR_HI
+#define BIF_BX_PF1_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define BIF_BX_PF1_BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000FFL
+//BIF_BX_PF1_BIF_RB_WPTR_ADDR_LO
+#define BIF_BX_PF1_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define BIF_BX_PF1_BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//BIF_BX_PF1_MAILBOX_INDEX
+#define BIF_BX_PF1_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_INDEX__MAILBOX_INDEX_MASK 0x0000001FL
+//BIF_BX_PF1_BIF_UVD_GPUIOV_CFG_SIZE
+#define BIF_BX_PF1_BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE__SHIFT 0x0
+#define BIF_BX_PF1_BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE_MASK 0x0000000FL
+//BIF_BX_PF1_BIF_VCE_GPUIOV_CFG_SIZE
+#define BIF_BX_PF1_BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE__SHIFT 0x0
+#define BIF_BX_PF1_BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE_MASK 0x0000000FL
+//BIF_BX_PF1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE
+#define BIF_BX_PF1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT 0x0
+#define BIF_BX_PF1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK 0x0000000FL
+//BIF_BX_PF1_BIF_PERSTB_PAD_CNTL
+#define BIF_BX_PF1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0
+#define BIF_BX_PF1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK 0x0000FFFFL
+//BIF_BX_PF1_BIF_PX_EN_PAD_CNTL
+#define BIF_BX_PF1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0
+#define BIF_BX_PF1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK 0x000000FFL
+//BIF_BX_PF1_BIF_REFPADKIN_PAD_CNTL
+#define BIF_BX_PF1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0
+#define BIF_BX_PF1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK 0x000000FFL
+//BIF_BX_PF1_BIF_CLKREQB_PAD_CNTL
+#define BIF_BX_PF1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0
+#define BIF_BX_PF1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK 0x00FFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1
+//BIF_BX_PF1_BIF_BME_STATUS
+#define BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_PF1_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_PF1_GPU_HDP_FLUSH_REQ
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_PF1_GPU_HDP_FLUSH_DONE
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_PF1_BIF_TRANS_PENDING
+#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_CONTROL
+#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_PF1_MAILBOX_INT_CNTL
+#define BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_PF1_BIF_VMHV_MAILBOX
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_gdc_GDCDEC
+//GDC1_NGDC_SDP_PORT_CTRL
+#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0
+#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK 0x0000003FL
+//GDC1_SHUB_REGS_IF_CTL
+#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0
+#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L
+//GDC1_NGDC_RESERVED_0
+#define GDC1_NGDC_RESERVED_0__RESERVED__SHIFT 0x0
+#define GDC1_NGDC_RESERVED_0__RESERVED_MASK 0xFFFFFFFFL
+//GDC1_NGDC_RESERVED_1
+#define GDC1_NGDC_RESERVED_1__RESERVED__SHIFT 0x0
+#define GDC1_NGDC_RESERVED_1__RESERVED_MASK 0xFFFFFFFFL
+//GDC1_NGDC_SDP_PORT_CTRL_SOCCLK
+#define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK__SHIFT 0x0
+#define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK_MASK 0x0000003FL
+//GDC1_BIF_SDMA0_DOORBELL_RANGE
+#define GDC1_BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define GDC1_BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define GDC1_BIF_SDMA0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define GDC1_BIF_SDMA0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//GDC1_BIF_SDMA1_DOORBELL_RANGE
+#define GDC1_BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define GDC1_BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define GDC1_BIF_SDMA1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define GDC1_BIF_SDMA1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//GDC1_BIF_IH_DOORBELL_RANGE
+#define GDC1_BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define GDC1_BIF_IH_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define GDC1_BIF_IH_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define GDC1_BIF_IH_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//GDC1_BIF_MMSCH0_DOORBELL_RANGE
+#define GDC1_BIF_MMSCH0_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define GDC1_BIF_MMSCH0_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define GDC1_BIF_MMSCH0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define GDC1_BIF_MMSCH0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//GDC1_ATDMA_MISC_CNTL
+#define GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT 0x0
+#define GDC1_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0x1
+#define GDC1_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT 0x10
+#define GDC1_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT 0x18
+#define GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK 0x00000001L
+#define GDC1_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000002L
+#define GDC1_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK 0x00FF0000L
+#define GDC1_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK 0xFF000000L
+//GDC1_BIF_DOORBELL_FENCE_CNTL
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE__SHIFT 0x0
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE_MASK 0x00000001L
+//GDC1_S2A_MISC_CNTL
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__SHIFT 0x0
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__SHIFT 0x1
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__SHIFT 0x2
+#define GDC1_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT 0x3
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS_MASK 0x00000001L
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS_MASK 0x00000002L
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS_MASK 0x00000004L
+#define GDC1_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK 0x00000008L
+//GDC1_GDC_PG_MISC_CNTL
+#define GDC1_GDC_PG_MISC_CNTL__GDC_PG_RESET_SELECT_COLD_RESET__SHIFT 0x0
+#define GDC1_GDC_PG_MISC_CNTL__GDC_PG_RESET_SELECT_COLD_RESET_MASK 0x00000001L
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC
+//MM_INDEX
+#define MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define MM_INDEX__MM_APER__SHIFT 0x1f
+#define MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define MM_INDEX__MM_APER_MASK 0x80000000L
+//MM_DATA
+#define MM_DATA__MM_DATA__SHIFT 0x0
+#define MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//MM_INDEX_HI
+#define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_SYSDEC
+//SYSHUB_INDEX_OVLP
+#define SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__SHIFT 0x0
+#define SYSHUB_INDEX_OVLP__SYSHUB_OFFSET_MASK 0x003FFFFFL
+//SYSHUB_DATA_OVLP
+#define SYSHUB_DATA_OVLP__SYSHUB_DATA__SHIFT 0x0
+#define SYSHUB_DATA_OVLP__SYSHUB_DATA_MASK 0xFFFFFFFFL
+//PCIE_INDEX
+#define PCIE_INDEX__PCIE_INDEX__SHIFT 0x0
+#define PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL
+//PCIE_DATA
+#define PCIE_DATA__PCIE_DATA__SHIFT 0x0
+#define PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL
+//PCIE_INDEX2
+#define PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0
+#define PCIE_INDEX2__PCIE_INDEX2_MASK 0xFFFFFFFFL
+//PCIE_DATA2
+#define PCIE_DATA2__PCIE_DATA2__SHIFT 0x0
+#define PCIE_DATA2__PCIE_DATA2_MASK 0xFFFFFFFFL
+//SBIOS_SCRATCH_0
+#define SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//SBIOS_SCRATCH_1
+#define SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//SBIOS_SCRATCH_2
+#define SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//SBIOS_SCRATCH_3
+#define SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_0
+#define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0
+#define BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_1
+#define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0
+#define BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_2
+#define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0
+#define BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_3
+#define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0
+#define BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_4
+#define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0
+#define BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_5
+#define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0
+#define BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_6
+#define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0
+#define BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_7
+#define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0
+#define BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_8
+#define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0
+#define BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_9
+#define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0
+#define BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_10
+#define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0
+#define BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_11
+#define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0
+#define BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_12
+#define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0
+#define BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_13
+#define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0
+#define BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_14
+#define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0
+#define BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_15
+#define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0
+#define BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xFFFFFFFFL
+//BIF_RLC_INTR_CNTL
+#define BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT 0x0
+#define BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT 0x1
+#define BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT 0x2
+#define BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT 0x3
+#define BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE_MASK 0x00000001L
+#define BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED_MASK 0x00000002L
+#define BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR_MASK 0x00000004L
+#define BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION_MASK 0x00000008L
+//BIF_VCE_INTR_CNTL
+#define BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT 0x0
+#define BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT 0x1
+#define BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT 0x2
+#define BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT 0x3
+#define BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE_MASK 0x00000001L
+#define BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED_MASK 0x00000002L
+#define BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR_MASK 0x00000004L
+#define BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION_MASK 0x00000008L
+//BIF_UVD_INTR_CNTL
+#define BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT 0x0
+#define BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT 0x1
+#define BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT 0x2
+#define BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT 0x3
+#define BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE_MASK 0x00000001L
+#define BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED_MASK 0x00000002L
+#define BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR_MASK 0x00000004L
+#define BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION_MASK 0x00000008L
+//GFX_MMIOREG_CAM_ADDR0
+#define GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0
+#define GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_REMAP_ADDR0
+#define GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0
+#define GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_ADDR1
+#define GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0
+#define GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_REMAP_ADDR1
+#define GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0
+#define GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_ADDR2
+#define GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0
+#define GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_REMAP_ADDR2
+#define GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0
+#define GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_ADDR3
+#define GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0
+#define GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_REMAP_ADDR3
+#define GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0
+#define GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_ADDR4
+#define GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0
+#define GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_REMAP_ADDR4
+#define GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0
+#define GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_ADDR5
+#define GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0
+#define GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_REMAP_ADDR5
+#define GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0
+#define GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_ADDR6
+#define GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0
+#define GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_REMAP_ADDR6
+#define GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0
+#define GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_ADDR7
+#define GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0
+#define GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_REMAP_ADDR7
+#define GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0
+#define GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_CNTL
+#define GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0
+#define GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000FFL
+//GFX_MMIOREG_CAM_ZERO_CPL
+#define GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0
+#define GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xFFFFFFFFL
+//GFX_MMIOREG_CAM_ONE_CPL
+#define GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0
+#define GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xFFFFFFFFL
+//GFX_MMIOREG_CAM_PROGRAMMABLE_CPL
+#define GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0
+#define GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_syshub_mmreg_ind_syshubdec
+//SYSHUB_INDEX
+#define SYSHUB_INDEX__INDEX__SHIFT 0x0
+#define SYSHUB_INDEX__INDEX_MASK 0xFFFFFFFFL
+//SYSHUB_DATA
+#define SYSHUB_DATA__DATA__SHIFT 0x0
+#define SYSHUB_DATA__DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1
+//RCC_DEV0_EPF0_STRAP0
+#define RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0
+#define RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10
+#define RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14
+#define RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18
+#define RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d
+#define RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e
+#define RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f
+#define RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L
+#define RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L
+#define RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L
+#define RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L
+#define RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L
+#define RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1
+//EP_PCIE_SCRATCH
+#define EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//EP_PCIE_CNTL
+#define EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
+#define EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
+#define EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L
+#define EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L
+#define EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//EP_PCIE_INT_CNTL
+#define EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0
+#define EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1
+#define EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2
+#define EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3
+#define EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4
+#define EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6
+#define EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L
+#define EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L
+#define EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L
+#define EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L
+#define EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L
+#define EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L
+//EP_PCIE_INT_STATUS
+#define EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0
+#define EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1
+#define EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2
+#define EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3
+#define EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4
+#define EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6
+#define EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L
+#define EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L
+#define EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L
+#define EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L
+#define EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L
+#define EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L
+//EP_PCIE_RX_CNTL2
+#define EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
+#define EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L
+//EP_PCIE_BUS_CNTL
+#define EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+//EP_PCIE_CFG_CNTL
+#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+//EP_PCIE_TX_LTR_CNTL
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf
+#define EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10
+#define EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L
+#define EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L
+#define EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L
+//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//EP_PCIE_F0_DPA_CAP
+#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//EP_PCIE_F0_DPA_LATENCY_INDICATOR
+#define EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//EP_PCIE_F0_DPA_CNTL
+#define EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0
+#define EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8
+#define EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL
+#define EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//EP_PCIE_PME_CONTROL
+#define EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0
+#define EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL
+//EP_PCIEP_RESERVED
+#define EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL
+//EP_PCIE_TX_CNTL
+#define EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18
+#define EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19
+#define EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a
+#define EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L
+#define EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L
+#define EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L
+//EP_PCIE_TX_REQUESTER_ID
+#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//EP_PCIE_ERR_CNTL
+#define EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f
+#define EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L
+//EP_PCIE_RX_CNTL
+#define EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+//EP_PCIE_LC_SPEED_CNTL
+#define EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+
+
+// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1
+//DN_PCIE_RESERVED
+#define DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
+#define DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL
+//DN_PCIE_SCRATCH
+#define DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//DN_PCIE_CNTL
+#define DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
+#define DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7
+#define DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L
+#define DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L
+#define DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//DN_PCIE_CONFIG_CNTL
+#define DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
+#define DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L
+//DN_PCIE_RX_CNTL2
+#define DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
+#define DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L
+//DN_PCIE_BUS_CNTL
+#define DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8
+#define DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+#define DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L
+//DN_PCIE_CFG_CNTL
+#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1
+//PCIE_ERR_CNTL
+#define PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+//PCIE_RX_CNTL
+#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9
+#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15
+#define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L
+#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L
+#define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+//PCIE_LC_SPEED_CNTL
+#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+//PCIE_LC_CNTL2
+#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+//PCIEP_STRAP_MISC
+#define PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa
+#define PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L
+//LTR_MSG_INFO_FROM_EP
+#define LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0
+#define LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_BIFPFVFDEC1
+//RCC_ERR_LOG
+#define RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DOORBELL_APER_EN
+#define RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_CONFIG_MEMSIZE
+#define RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_CONFIG_RESERVED
+#define RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_IOV_FUNC_IDENTIFIER
+#define RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1
+//RCC_ERR_INT_CNTL
+#define RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT 0x0
+#define RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK 0x00000001L
+//RCC_BACO_CNTL_MISC
+#define RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0
+#define RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1
+#define RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x00000001L
+#define RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x00000002L
+//RCC_RESET_EN
+#define RCC_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf
+#define RCC_RESET_EN__DB_APER_RESET_EN_MASK 0x00008000L
+//RCC_VDM_SUPPORT
+#define RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0
+#define RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1
+#define RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2
+#define RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3
+#define RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4
+#define RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L
+#define RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L
+#define RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L
+#define RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L
+#define RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L
+//RCC_PEER_REG_RANGE0
+#define RCC_PEER_REG_RANGE0__START_ADDR__SHIFT 0x0
+#define RCC_PEER_REG_RANGE0__END_ADDR__SHIFT 0x10
+#define RCC_PEER_REG_RANGE0__START_ADDR_MASK 0x0000FFFFL
+#define RCC_PEER_REG_RANGE0__END_ADDR_MASK 0xFFFF0000L
+//RCC_PEER_REG_RANGE1
+#define RCC_PEER_REG_RANGE1__START_ADDR__SHIFT 0x0
+#define RCC_PEER_REG_RANGE1__END_ADDR__SHIFT 0x10
+#define RCC_PEER_REG_RANGE1__START_ADDR_MASK 0x0000FFFFL
+#define RCC_PEER_REG_RANGE1__END_ADDR_MASK 0xFFFF0000L
+//RCC_BUS_CNTL
+#define RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2
+#define RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3
+#define RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4
+#define RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5
+#define RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6
+#define RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7
+#define RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8
+#define RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc
+#define RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd
+#define RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10
+#define RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11
+#define RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12
+#define RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13
+#define RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14
+#define RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15
+#define RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18
+#define RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19
+#define RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c
+#define RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d
+#define RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L
+#define RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L
+#define RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L
+#define RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L
+#define RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L
+#define RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L
+#define RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L
+#define RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L
+#define RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L
+#define RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L
+#define RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L
+#define RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L
+#define RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L
+#define RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L
+#define RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L
+#define RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L
+#define RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L
+#define RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L
+#define RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L
+//RCC_CONFIG_CNTL
+#define RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0
+#define RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2
+#define RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3
+#define RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x00000001L
+#define RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x00000004L
+#define RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK 0x00000018L
+//RCC_CONFIG_F0_BASE
+#define RCC_CONFIG_F0_BASE__F0_BASE__SHIFT 0x0
+#define RCC_CONFIG_F0_BASE__F0_BASE_MASK 0xFFFFFFFFL
+//RCC_CONFIG_APER_SIZE
+#define RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0
+#define RCC_CONFIG_APER_SIZE__APER_SIZE_MASK 0xFFFFFFFFL
+//RCC_CONFIG_REG_APER_SIZE
+#define RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0
+#define RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0x000FFFFFL
+//RCC_XDMA_LO
+#define RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0
+#define RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f
+#define RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x7FFFFFFFL
+#define RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000L
+//RCC_XDMA_HI
+#define RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0
+#define RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x7FFFFFFFL
+//RCC_FEATURES_CONTROL_MISC
+#define RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4
+#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5
+#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6
+#define RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7
+#define RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd
+#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe
+#define RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf
+#define RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10
+#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11
+#define RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12
+#define RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13
+#define RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x00000010L
+#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x00000020L
+#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x00000040L
+#define RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L
+#define RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L
+#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L
+#define RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK 0x00008000L
+#define RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L
+#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L
+#define RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L
+#define RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L
+//RCC_BUSNUM_CNTL1
+#define RCC_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0
+#define RCC_BUSNUM_CNTL1__ID_MASK_MASK 0x000000FFL
+//RCC_BUSNUM_LIST0
+#define RCC_BUSNUM_LIST0__ID0__SHIFT 0x0
+#define RCC_BUSNUM_LIST0__ID1__SHIFT 0x8
+#define RCC_BUSNUM_LIST0__ID2__SHIFT 0x10
+#define RCC_BUSNUM_LIST0__ID3__SHIFT 0x18
+#define RCC_BUSNUM_LIST0__ID0_MASK 0x000000FFL
+#define RCC_BUSNUM_LIST0__ID1_MASK 0x0000FF00L
+#define RCC_BUSNUM_LIST0__ID2_MASK 0x00FF0000L
+#define RCC_BUSNUM_LIST0__ID3_MASK 0xFF000000L
+//RCC_BUSNUM_LIST1
+#define RCC_BUSNUM_LIST1__ID4__SHIFT 0x0
+#define RCC_BUSNUM_LIST1__ID5__SHIFT 0x8
+#define RCC_BUSNUM_LIST1__ID6__SHIFT 0x10
+#define RCC_BUSNUM_LIST1__ID7__SHIFT 0x18
+#define RCC_BUSNUM_LIST1__ID4_MASK 0x000000FFL
+#define RCC_BUSNUM_LIST1__ID5_MASK 0x0000FF00L
+#define RCC_BUSNUM_LIST1__ID6_MASK 0x00FF0000L
+#define RCC_BUSNUM_LIST1__ID7_MASK 0xFF000000L
+//RCC_BUSNUM_CNTL2
+#define RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0
+#define RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8
+#define RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10
+#define RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11
+#define RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0x000000FFL
+#define RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x00000100L
+#define RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x00010000L
+#define RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x00020000L
+//RCC_CAPTURE_HOST_BUSNUM
+#define RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0
+#define RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x00000001L
+//RCC_HOST_BUSNUM
+#define RCC_HOST_BUSNUM__HOST_ID__SHIFT 0x0
+#define RCC_HOST_BUSNUM__HOST_ID_MASK 0x0000FFFFL
+//RCC_PEER0_FB_OFFSET_HI
+#define RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0
+#define RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0x000FFFFFL
+//RCC_PEER0_FB_OFFSET_LO
+#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f
+#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0x000FFFFFL
+#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000L
+//RCC_PEER1_FB_OFFSET_HI
+#define RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0
+#define RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0x000FFFFFL
+//RCC_PEER1_FB_OFFSET_LO
+#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f
+#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0x000FFFFFL
+#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000L
+//RCC_PEER2_FB_OFFSET_HI
+#define RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0
+#define RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0x000FFFFFL
+//RCC_PEER2_FB_OFFSET_LO
+#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f
+#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0x000FFFFFL
+#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000L
+//RCC_PEER3_FB_OFFSET_HI
+#define RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0
+#define RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0x000FFFFFL
+//RCC_PEER3_FB_OFFSET_LO
+#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f
+#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0x000FFFFFL
+#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000L
+//RCC_CMN_LINK_CNTL
+#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0
+#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1
+#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2
+#define RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3
+#define RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10
+#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L
+#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L
+#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L
+#define RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L
+#define RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L
+//RCC_EP_REQUESTERID_RESTORE
+#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0
+#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8
+#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL
+#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L
+//RCC_LTR_LSWITCH_CNTL
+#define RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0
+#define RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL
+//RCC_MH_ARB_CNTL
+#define RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0
+#define RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1
+#define RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L
+#define RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x00007FFEL
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_BIFDEC1
+//BIF_MM_INDACCESS_CNTL
+#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
+#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L
+//BUS_CNTL
+#define BUS_CNTL__PMI_INT_DIS_EP__SHIFT 0x3
+#define BUS_CNTL__PMI_INT_DIS_DN__SHIFT 0x4
+#define BUS_CNTL__PMI_INT_DIS_SWUS__SHIFT 0x5
+#define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6
+#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7
+#define BUS_CNTL__SET_AZ_TC__SHIFT 0xa
+#define BUS_CNTL__SET_MC_TC__SHIFT 0xd
+#define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10
+#define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11
+#define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12
+#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT 0x13
+#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT 0x14
+#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT 0x15
+#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT 0x16
+#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT 0x17
+#define BUS_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT 0x18
+#define BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT 0x19
+#define BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT 0x1a
+#define BUS_CNTL__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT 0x1b
+#define BUS_CNTL__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT 0x1c
+#define BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT 0x1d
+#define BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT 0x1e
+#define BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT 0x1f
+#define BUS_CNTL__PMI_INT_DIS_EP_MASK 0x00000008L
+#define BUS_CNTL__PMI_INT_DIS_DN_MASK 0x00000010L
+#define BUS_CNTL__PMI_INT_DIS_SWUS_MASK 0x00000020L
+#define BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L
+#define BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L
+#define BUS_CNTL__SET_AZ_TC_MASK 0x00001C00L
+#define BUS_CNTL__SET_MC_TC_MASK 0x0000E000L
+#define BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L
+#define BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L
+#define BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L
+#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK 0x00080000L
+#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK 0x00100000L
+#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK 0x00200000L
+#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK 0x00400000L
+#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK 0x00800000L
+#define BUS_CNTL__UR_OVRD_FOR_ECRC_EN_MASK 0x01000000L
+#define BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK 0x02000000L
+#define BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK 0x04000000L
+#define BUS_CNTL__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK 0x08000000L
+#define BUS_CNTL__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK 0x10000000L
+#define BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK 0x20000000L
+#define BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK 0x40000000L
+#define BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK 0x80000000L
+//BIF_SCRATCH0
+#define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0
+#define BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xFFFFFFFFL
+//BIF_SCRATCH1
+#define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0
+#define BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xFFFFFFFFL
+//BX_RESET_EN
+#define BX_RESET_EN__COR_RESET_EN__SHIFT 0x0
+#define BX_RESET_EN__REG_RESET_EN__SHIFT 0x1
+#define BX_RESET_EN__STY_RESET_EN__SHIFT 0x2
+#define BX_RESET_EN__FLR_TWICE_EN__SHIFT 0x8
+#define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10
+#define BX_RESET_EN__COR_RESET_EN_MASK 0x00000001L
+#define BX_RESET_EN__REG_RESET_EN_MASK 0x00000002L
+#define BX_RESET_EN__STY_RESET_EN_MASK 0x00000004L
+#define BX_RESET_EN__FLR_TWICE_EN_MASK 0x00000100L
+#define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L
+//MM_CFGREGS_CNTL
+#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0
+#define MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6
+#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f
+#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L
+#define MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000C0L
+#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L
+//BX_RESET_CNTL
+#define BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0
+#define BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L
+//INTERRUPT_CNTL
+#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0
+#define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1
+#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3
+#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4
+#define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8
+#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf
+#define INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10
+#define INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11
+#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L
+#define INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L
+#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L
+#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L
+#define INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L
+#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L
+#define INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L
+#define INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L
+//INTERRUPT_CNTL2
+#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0
+#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL
+//CLKREQB_PAD_CNTL
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L
+//BIF_FEATURES_CONTROL_MISC
+#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0
+#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1
+#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2
+#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3
+#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc
+#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd
+#define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf
+#define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__SHIFT 0x11
+#define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__SHIFT 0x12
+#define BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x18
+#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L
+#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L
+#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L
+#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L
+#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L
+#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L
+#define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L
+#define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS_MASK 0x00020000L
+#define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS_MASK 0x00040000L
+#define BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK 0x01000000L
+//BIF_DOORBELL_CNTL
+#define BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0
+#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1
+#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2
+#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3
+#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b
+#define BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L
+#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L
+#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L
+#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L
+#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L
+//BIF_DOORBELL_INT_CNTL
+#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0
+#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS__SHIFT 0x1
+#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10
+#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR__SHIFT 0x11
+#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L
+#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS_MASK 0x00000002L
+#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L
+#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR_MASK 0x00020000L
+//BIF_FB_EN
+#define BIF_FB_EN__FB_READ_EN__SHIFT 0x0
+#define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1
+#define BIF_FB_EN__FB_READ_EN_MASK 0x00000001L
+#define BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L
+//BIF_BUSY_DELAY_CNTR
+#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0
+#define BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x0000003FL
+//BIF_MST_TRANS_PENDING_VF
+#define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x0000FFFFL
+//BIF_SLV_TRANS_PENDING_VF
+#define BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0
+#define BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x0000FFFFL
+//BACO_CNTL
+#define BACO_CNTL__BACO_EN__SHIFT 0x0
+#define BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT 0x1
+#define BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2
+#define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3
+#define BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5
+#define BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6
+#define BACO_CNTL__BACO_MODE__SHIFT 0x8
+#define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9
+#define BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f
+#define BACO_CNTL__BACO_EN_MASK 0x00000001L
+#define BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK 0x00000002L
+#define BACO_CNTL__BACO_DUMMY_EN_MASK 0x00000004L
+#define BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L
+#define BACO_CNTL__BACO_DSTATE_BYPASS_MASK 0x00000020L
+#define BACO_CNTL__BACO_RST_INTR_MASK_MASK 0x00000040L
+#define BACO_CNTL__BACO_MODE_MASK 0x00000100L
+#define BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000200L
+#define BACO_CNTL__BACO_AUTO_EXIT_MASK 0x80000000L
+//BIF_BACO_EXIT_TIME0
+#define BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0
+#define BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK 0x000FFFFFL
+//BIF_BACO_EXIT_TIMER1
+#define BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0
+#define BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT 0x18
+#define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR__SHIFT 0x19
+#define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a
+#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b
+#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c
+#define BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d
+#define BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f
+#define BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK 0x000FFFFFL
+#define BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK 0x01000000L
+#define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR_MASK 0x02000000L
+#define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK 0x04000000L
+#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK 0x08000000L
+#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK 0x10000000L
+#define BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK 0x60000000L
+#define BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK 0x80000000L
+//BIF_BACO_EXIT_TIMER2
+#define BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0
+#define BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK 0x000FFFFFL
+//BIF_BACO_EXIT_TIMER3
+#define BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0
+#define BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK 0x000FFFFFL
+//BIF_BACO_EXIT_TIMER4
+#define BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0
+#define BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK 0x000FFFFFL
+//MEM_TYPE_CNTL
+#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0
+#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L
+//SMU_BIF_VDDGFX_PWR_STATUS
+#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT 0x0
+#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF_MASK 0x00000001L
+//BIF_VDDGFX_GFX0_LOWER
+#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN_MASK 0x40000000L
+#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN_MASK 0x80000000L
+//BIF_VDDGFX_GFX0_UPPER
+#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER_MASK 0x0003FFFCL
+//BIF_VDDGFX_GFX1_LOWER
+#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN_MASK 0x40000000L
+#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN_MASK 0x80000000L
+//BIF_VDDGFX_GFX1_UPPER
+#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER_MASK 0x0003FFFCL
+//BIF_VDDGFX_GFX2_LOWER
+#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN_MASK 0x40000000L
+#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN_MASK 0x80000000L
+//BIF_VDDGFX_GFX2_UPPER
+#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER_MASK 0x0003FFFCL
+//BIF_VDDGFX_GFX3_LOWER
+#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN_MASK 0x40000000L
+#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN_MASK 0x80000000L
+//BIF_VDDGFX_GFX3_UPPER
+#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER_MASK 0x0003FFFCL
+//BIF_VDDGFX_GFX4_LOWER
+#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN_MASK 0x40000000L
+#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN_MASK 0x80000000L
+//BIF_VDDGFX_GFX4_UPPER
+#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER_MASK 0x0003FFFCL
+//BIF_VDDGFX_GFX5_LOWER
+#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK 0x40000000L
+#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN_MASK 0x80000000L
+//BIF_VDDGFX_GFX5_UPPER
+#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER_MASK 0x0003FFFCL
+//BIF_VDDGFX_RSV1_LOWER
+#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN_MASK 0x40000000L
+#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN_MASK 0x80000000L
+//BIF_VDDGFX_RSV1_UPPER
+#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER_MASK 0x0003FFFCL
+//BIF_VDDGFX_RSV2_LOWER
+#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN_MASK 0x40000000L
+#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN_MASK 0x80000000L
+//BIF_VDDGFX_RSV2_UPPER
+#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER_MASK 0x0003FFFCL
+//BIF_VDDGFX_RSV3_LOWER
+#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN_MASK 0x40000000L
+#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN_MASK 0x80000000L
+//BIF_VDDGFX_RSV3_UPPER
+#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER_MASK 0x0003FFFCL
+//BIF_VDDGFX_RSV4_LOWER
+#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER_MASK 0x0003FFFCL
+#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN_MASK 0x40000000L
+#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN_MASK 0x80000000L
+//BIF_VDDGFX_RSV4_UPPER
+#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER_MASK 0x0003FFFCL
+//BIF_VDDGFX_FB_CMP
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN_MASK 0x00000001L
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN_MASK 0x00000002L
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN_MASK 0x00000004L
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN_MASK 0x00000008L
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN_MASK 0x00000010L
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN_MASK 0x00000020L
+//BIF_DOORBELL_GBLAPER1_LOWER
+#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2
+#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT 0x1f
+#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER_MASK 0x00000FFCL
+#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN_MASK 0x80000000L
+//BIF_DOORBELL_GBLAPER1_UPPER
+#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2
+#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER_MASK 0x00000FFCL
+//BIF_DOORBELL_GBLAPER2_LOWER
+#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2
+#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT 0x1f
+#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER_MASK 0x00000FFCL
+#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN_MASK 0x80000000L
+//BIF_DOORBELL_GBLAPER2_UPPER
+#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2
+#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER_MASK 0x00000FFCL
+//REMAP_HDP_MEM_FLUSH_CNTL
+#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2
+#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL
+//REMAP_HDP_REG_FLUSH_CNTL
+#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2
+#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL
+//BIF_RB_CNTL
+#define BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define BIF_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
+#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9
+#define BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11
+#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
+#define BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define BIF_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L
+#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003E00L
+#define BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L
+#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L
+//BIF_RB_BASE
+#define BIF_RB_BASE__ADDR__SHIFT 0x0
+#define BIF_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//BIF_RB_RPTR
+#define BIF_RB_RPTR__OFFSET__SHIFT 0x2
+#define BIF_RB_RPTR__OFFSET_MASK 0x0003FFFCL
+//BIF_RB_WPTR
+#define BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0
+#define BIF_RB_WPTR__OFFSET__SHIFT 0x2
+#define BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L
+#define BIF_RB_WPTR__OFFSET_MASK 0x0003FFFCL
+//BIF_RB_WPTR_ADDR_HI
+#define BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000FFL
+//BIF_RB_WPTR_ADDR_LO
+#define BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//MAILBOX_INDEX
+#define MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0
+#define MAILBOX_INDEX__MAILBOX_INDEX_MASK 0x0000001FL
+//BIF_UVD_GPUIOV_CFG_SIZE
+#define BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE__SHIFT 0x0
+#define BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE_MASK 0x0000000FL
+//BIF_VCE_GPUIOV_CFG_SIZE
+#define BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE__SHIFT 0x0
+#define BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE_MASK 0x0000000FL
+//BIF_GFX_SDMA_GPUIOV_CFG_SIZE
+#define BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT 0x0
+#define BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK 0x0000000FL
+//BIF_PERSTB_PAD_CNTL
+#define BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0
+#define BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK 0x0000FFFFL
+//BIF_PX_EN_PAD_CNTL
+#define BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0
+#define BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK 0x000000FFL
+//BIF_REFPADKIN_PAD_CNTL
+#define BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0
+#define BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK 0x000000FFL
+//BIF_CLKREQB_PAD_CNTL
+#define BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0
+#define BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK 0x00FFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1
+//BIF_BME_STATUS
+#define BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_ATOMIC_ERR_LOG
+#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//DOORBELL_SELFRING_GPA_APER_CNTL
+#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//HDP_REG_COHERENCY_FLUSH_CNTL
+#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//HDP_MEM_COHERENCY_FLUSH_CNTL
+#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//GPU_HDP_FLUSH_REQ
+#define GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//GPU_HDP_FLUSH_DONE
+#define GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_TRANS_PENDING
+#define BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//MAILBOX_MSGBUF_TRN_DW0
+#define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//MAILBOX_MSGBUF_TRN_DW1
+#define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//MAILBOX_MSGBUF_TRN_DW2
+#define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//MAILBOX_MSGBUF_TRN_DW3
+#define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//MAILBOX_MSGBUF_RCV_DW0
+#define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//MAILBOX_MSGBUF_RCV_DW1
+#define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//MAILBOX_MSGBUF_RCV_DW2
+#define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//MAILBOX_MSGBUF_RCV_DW3
+#define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//MAILBOX_CONTROL
+#define MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//MAILBOX_INT_CNTL
+#define MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_VMHV_MAILBOX
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_gdc_GDCDEC
+//NGDC_SDP_PORT_CTRL
+#define NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0
+#define NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK 0x0000003FL
+//SHUB_REGS_IF_CTL
+#define SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0
+#define SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L
+//NGDC_RESERVED_0
+#define NGDC_RESERVED_0__RESERVED__SHIFT 0x0
+#define NGDC_RESERVED_0__RESERVED_MASK 0xFFFFFFFFL
+//NGDC_RESERVED_1
+#define NGDC_RESERVED_1__RESERVED__SHIFT 0x0
+#define NGDC_RESERVED_1__RESERVED_MASK 0xFFFFFFFFL
+//NGDC_SDP_PORT_CTRL_SOCCLK
+#define NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK__SHIFT 0x0
+#define NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK_MASK 0x0000003FL
+//BIF_SDMA0_DOORBELL_RANGE
+#define BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define BIF_SDMA0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define BIF_SDMA0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//BIF_SDMA1_DOORBELL_RANGE
+#define BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define BIF_SDMA1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define BIF_SDMA1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//BIF_IH_DOORBELL_RANGE
+#define BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define BIF_IH_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define BIF_IH_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define BIF_IH_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//BIF_MMSCH0_DOORBELL_RANGE
+#define BIF_MMSCH0_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define BIF_MMSCH0_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define BIF_MMSCH0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define BIF_MMSCH0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//ATDMA_MISC_CNTL
+#define ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT 0x0
+#define ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0x1
+#define ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT 0x10
+#define ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT 0x18
+#define ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK 0x00000001L
+#define ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000002L
+#define ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK 0x00FF0000L
+#define ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK 0xFF000000L
+//BIF_DOORBELL_FENCE_CNTL
+#define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE__SHIFT 0x0
+#define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE_MASK 0x00000001L
+//S2A_MISC_CNTL
+#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__SHIFT 0x0
+#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__SHIFT 0x1
+#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__SHIFT 0x2
+#define S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT 0x3
+#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS_MASK 0x00000001L
+#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS_MASK 0x00000002L
+#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS_MASK 0x00000004L
+#define S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK 0x00000008L
+//GDC_PG_MISC_CNTL
+#define GDC_PG_MISC_CNTL__GDC_PG_RESET_SELECT_COLD_RESET__SHIFT 0x0
+#define GDC_PG_MISC_CNTL__GDC_PG_RESET_SELECT_COLD_RESET_MASK 0x00000001L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC2
+//GFXMSIX_VECT0_ADDR_LO
+#define GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//GFXMSIX_VECT0_ADDR_HI
+#define GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//GFXMSIX_VECT0_MSG_DATA
+#define GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//GFXMSIX_VECT0_CONTROL
+#define GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//GFXMSIX_VECT1_ADDR_LO
+#define GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//GFXMSIX_VECT1_ADDR_HI
+#define GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//GFXMSIX_VECT1_MSG_DATA
+#define GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//GFXMSIX_VECT1_CONTROL
+#define GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//GFXMSIX_VECT2_ADDR_LO
+#define GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//GFXMSIX_VECT2_ADDR_HI
+#define GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//GFXMSIX_VECT2_MSG_DATA
+#define GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//GFXMSIX_VECT2_CONTROL
+#define GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//GFXMSIX_PBA
+#define GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+
+
+// addressBlock: syshub_mmreg_ind_syshubind
+//SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__SHIFT 0x1f
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000004L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000008L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000010L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000020L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000040L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000080L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00010000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00020000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00040000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00080000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00100000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00200000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00400000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00800000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x10000000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN_MASK 0x80000000L
+//SYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SOCCLK
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__SHIFT 0x0
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER_MASK 0x0000FFFFL
+//SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__SHIFT 0x0
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__SHIFT 0x1
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__SHIFT 0xf
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__SHIFT 0x10
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__SHIFT 0x11
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en_MASK 0x00008000L
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en_MASK 0x00010000L
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en_MASK 0x00020000L
+//SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__SHIFT 0x0
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__SHIFT 0x1
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__SHIFT 0xf
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__SHIFT 0x10
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__SHIFT 0x11
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en_MASK 0x00008000L
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en_MASK 0x00010000L
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en_MASK 0x00020000L
+//SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L
+//SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L
+//SYSHUB_MMREG_IND_DMA_CLK0_SW2_SYSHUB_QOS_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L
+//SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL
+#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//SYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL
+#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//SYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL
+#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//SYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//SYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//SYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//SYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//SYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//SYSHUB_MMREG_IND_SYSHUB_CG_CNTL
+#define SYSHUB_MMREG_IND_SYSHUB_CG_CNTL__SYSHUB_CG_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__SHIFT 0x8
+#define SYSHUB_MMREG_IND_SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__SHIFT 0x10
+#define SYSHUB_MMREG_IND_SYSHUB_CG_CNTL__SYSHUB_CG_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER_MASK 0x0000FF00L
+#define SYSHUB_MMREG_IND_SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER_MASK 0x00FF0000L
+//SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__SHIFT 0x0
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__SHIFT 0x1
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__SHIFT 0x2
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__SHIFT 0x3
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__SHIFT 0x4
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__SHIFT 0x5
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__SHIFT 0x6
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__SHIFT 0x7
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__SHIFT 0x8
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__SHIFT 0x9
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__SHIFT 0xa
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__SHIFT 0xb
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__SHIFT 0xc
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__SHIFT 0xd
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__SHIFT 0xe
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__SHIFT 0xf
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__SHIFT 0x10
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2_MASK 0x00000004L
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3_MASK 0x00000008L
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4_MASK 0x00000010L
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5_MASK 0x00000020L
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6_MASK 0x00000040L
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7_MASK 0x00000080L
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9_MASK 0x00000200L
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10_MASK 0x00000400L
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11_MASK 0x00000800L
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12_MASK 0x00001000L
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13_MASK 0x00002000L
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14_MASK 0x00004000L
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15_MASK 0x00008000L
+#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF_MASK 0x00010000L
+//SYSHUB_MMREG_IND_SYSHUB_HP_TIMER
+#define SYSHUB_MMREG_IND_SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__SHIFT 0x0
+#define SYSHUB_MMREG_IND_SYSHUB_HP_TIMER__SYSHUB_HP_TIMER_MASK 0xFFFFFFFFL
+//SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK__SHIFT 0x0
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_MODE_SOCCLK__SHIFT 0x1
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HYSTERESIS_SOCCLK__SHIFT 0x2
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HST_DIS_SOCCLK__SHIFT 0xa
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DMA_DIS_SOCCLK__SHIFT 0xb
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_REGS_DIS_SOCCLK__SHIFT 0xc
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_AER_DIS_SOCCLK__SHIFT 0xd
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_MODE_SOCCLK_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HYSTERESIS_SOCCLK_MASK 0x000003FCL
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HST_DIS_SOCCLK_MASK 0x00000400L
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DMA_DIS_SOCCLK_MASK 0x00000800L
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_REGS_DIS_SOCCLK_MASK 0x00001000L
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_AER_DIS_SOCCLK_MASK 0x00002000L
+//SYSHUB_MMREG_IND_SYSUB_CPF_DOORBELL_RS_RESET
+#define SYSHUB_MMREG_IND_SYSUB_CPF_DOORBELL_RS_RESET__SYSHUB_CPF_DOORBELL_RS_RESET__SHIFT 0x0
+#define SYSHUB_MMREG_IND_SYSUB_CPF_DOORBELL_RS_RESET__SYSHUB_CPF_DOORBELL_RS_RESET_MASK 0x00000001L
+//SYSHUB_MMREG_IND_SYSHUB_SCRATCH
+#define SYSHUB_MMREG_IND_SYSHUB_SCRATCH__SCRATCH__SHIFT 0x0
+#define SYSHUB_MMREG_IND_SYSHUB_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL
+//SYSHUB_MMREG_IND_SYSHUB_CL_MASK
+#define SYSHUB_MMREG_IND_SYSHUB_CL_MASK__MP1DRAM_MASK_DIS__SHIFT 0x1
+#define SYSHUB_MMREG_IND_SYSHUB_CL_MASK__MP1_MASK_DIS__SHIFT 0x2
+#define SYSHUB_MMREG_IND_SYSHUB_CL_MASK__MP1DRAM_MASK_DIS_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_SYSHUB_CL_MASK__MP1_MASK_DIS_MASK 0x00000004L
+//SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__SHIFT 0x1f
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000004L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000008L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000010L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000020L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000040L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000080L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00010000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00020000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00040000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00080000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00100000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00200000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00400000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00800000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x10000000L
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN_MASK 0x80000000L
+//SYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SHUBCLK
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__SHIFT 0x0
+#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER_MASK 0x0000FFFFL
+//SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__SHIFT 0xf
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__SHIFT 0x10
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en_MASK 0x00008000L
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en_MASK 0x00010000L
+//SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__SHIFT 0xf
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__SHIFT 0x10
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en_MASK 0x00008000L
+#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en_MASK 0x00010000L
+//SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L
+//SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L
+//SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK__SHIFT 0x0
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_MODE_SHUBCLK__SHIFT 0x1
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HYSTERESIS_SHUBCLK__SHIFT 0x2
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HST_DIS_SHUBCLK__SHIFT 0xa
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_DMA_DIS_SHUBCLK__SHIFT 0xb
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_REGS_DIS_SHUBCLK__SHIFT 0xc
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_MODE_SHUBCLK_MASK 0x00000002L
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HYSTERESIS_SHUBCLK_MASK 0x000003FCL
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HST_DIS_SHUBCLK_MASK 0x00000400L
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_DMA_DIS_SHUBCLK_MASK 0x00000800L
+#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_REGS_DIS_SHUBCLK_MASK 0x00001000L
+//SYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD
+#define SYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS
+#define SYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS
+#define SYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD
+#define SYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD
+#define SYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD
+#define SYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD
+#define SYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD
+#define SYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD
+#define SYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD
+#define SYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_2_ASIB_3_FN_MOD
+#define SYSHUB_MMREG_IND_NIC400_2_ASIB_3_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_2_ASIB_3_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_2_ASIB_3_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_2_ASIB_3_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_2_ASIB_4_FN_MOD
+#define SYSHUB_MMREG_IND_NIC400_2_ASIB_4_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_2_ASIB_4_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_2_ASIB_4_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_2_ASIB_4_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS
+#define SYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_5_ASIB_0_FN_MOD
+#define SYSHUB_MMREG_IND_NIC400_5_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_5_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_5_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_5_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_5_ASIB_1_FN_MOD
+#define SYSHUB_MMREG_IND_NIC400_5_ASIB_1_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_5_ASIB_1_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_5_ASIB_1_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_5_ASIB_1_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_5_ASIB_2_FN_MOD
+#define SYSHUB_MMREG_IND_NIC400_5_ASIB_2_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_5_ASIB_2_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_5_ASIB_2_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_5_ASIB_2_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_5_ASIB_3_FN_MOD
+#define SYSHUB_MMREG_IND_NIC400_5_ASIB_3_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_5_ASIB_3_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_5_ASIB_3_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_5_ASIB_3_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_5_ASIB_4_FN_MOD
+#define SYSHUB_MMREG_IND_NIC400_5_ASIB_4_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_5_ASIB_4_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_5_ASIB_4_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_5_ASIB_4_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_5_AMIB_0_FN_MOD
+#define SYSHUB_MMREG_IND_NIC400_5_AMIB_0_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_5_AMIB_0_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_5_AMIB_0_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_5_AMIB_0_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_4_ASIB_0_FN_MOD
+#define SYSHUB_MMREG_IND_NIC400_4_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_4_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_4_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_4_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_4_ASIB_1_FN_MOD
+#define SYSHUB_MMREG_IND_NIC400_4_ASIB_1_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_4_ASIB_1_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_4_ASIB_1_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_4_ASIB_1_FN_MOD__write_iss_override_MASK 0x00000002L
+//SYSHUB_MMREG_IND_NIC400_4_AMIB_0_FN_MOD
+#define SYSHUB_MMREG_IND_NIC400_4_AMIB_0_FN_MOD__read_iss_override__SHIFT 0x0
+#define SYSHUB_MMREG_IND_NIC400_4_AMIB_0_FN_MOD__write_iss_override__SHIFT 0x1
+#define SYSHUB_MMREG_IND_NIC400_4_AMIB_0_FN_MOD__read_iss_override_MASK 0x00000001L
+#define SYSHUB_MMREG_IND_NIC400_4_AMIB_0_FN_MOD__write_iss_override_MASK 0x00000002L
+
+#endif
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