diff options
Diffstat (limited to 'drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h | 323 |
1 files changed, 323 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h new file mode 100644 index 000000000000..5df70484bc7d --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h @@ -0,0 +1,323 @@ +/* + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _smuio_11_0_0_OFFSET_HEADER +#define _smuio_11_0_0_OFFSET_HEADER + + + +// addressBlock: smuio_smuio_SmuSmuioDec +// base address: 0x5a000 +#define mmSMUSVI0_TEL_PLANE0 0x0004 +#define mmSMUSVI0_TEL_PLANE0_BASE_IDX 0 +#define mmSMUIO_MCM_CONFIG 0x0024 +#define mmSMUIO_MCM_CONFIG_BASE_IDX 0 +#define mmSMUIO_MP_RESET_INTR 0x00c1 +#define mmSMUIO_MP_RESET_INTR_BASE_IDX 0 +#define mmSMUIO_SOC_HALT 0x00c2 +#define mmSMUIO_SOC_HALT_BASE_IDX 0 +#define mmSMUIO_PWRMGT 0x00c8 +#define mmSMUIO_PWRMGT_BASE_IDX 0 +#define mmROM_CNTL 0x00e0 +#define mmROM_CNTL_BASE_IDX 0 +#define mmPAGE_MIRROR_CNTL 0x00e1 +#define mmPAGE_MIRROR_CNTL_BASE_IDX 0 +#define mmROM_STATUS 0x00e2 +#define mmROM_STATUS_BASE_IDX 0 +#define mmCGTT_ROM_CLK_CTRL0 0x00e3 +#define mmCGTT_ROM_CLK_CTRL0_BASE_IDX 0 +#define mmROM_INDEX 0x00e4 +#define mmROM_INDEX_BASE_IDX 0 +#define mmROM_DATA 0x00e5 +#define mmROM_DATA_BASE_IDX 0 +#define mmROM_START 0x00e6 +#define mmROM_START_BASE_IDX 0 +#define mmROM_SW_CNTL 0x00e7 +#define mmROM_SW_CNTL_BASE_IDX 0 +#define mmROM_SW_STATUS 0x00e8 +#define mmROM_SW_STATUS_BASE_IDX 0 +#define mmROM_SW_COMMAND 0x00e9 +#define mmROM_SW_COMMAND_BASE_IDX 0 +#define mmROM_SW_DATA_1 0x00ea +#define mmROM_SW_DATA_1_BASE_IDX 0 +#define mmROM_SW_DATA_2 0x00eb +#define mmROM_SW_DATA_2_BASE_IDX 0 +#define mmROM_SW_DATA_3 0x00ec +#define mmROM_SW_DATA_3_BASE_IDX 0 +#define mmROM_SW_DATA_4 0x00ed +#define mmROM_SW_DATA_4_BASE_IDX 0 +#define mmROM_SW_DATA_5 0x00ee +#define mmROM_SW_DATA_5_BASE_IDX 0 +#define mmROM_SW_DATA_6 0x00ef +#define mmROM_SW_DATA_6_BASE_IDX 0 +#define mmROM_SW_DATA_7 0x00f0 +#define mmROM_SW_DATA_7_BASE_IDX 0 +#define mmROM_SW_DATA_8 0x00f1 +#define mmROM_SW_DATA_8_BASE_IDX 0 +#define mmROM_SW_DATA_9 0x00f2 +#define mmROM_SW_DATA_9_BASE_IDX 0 +#define mmROM_SW_DATA_10 0x00f3 +#define mmROM_SW_DATA_10_BASE_IDX 0 +#define mmROM_SW_DATA_11 0x00f4 +#define mmROM_SW_DATA_11_BASE_IDX 0 +#define mmROM_SW_DATA_12 0x00f5 +#define mmROM_SW_DATA_12_BASE_IDX 0 +#define mmROM_SW_DATA_13 0x00f6 +#define mmROM_SW_DATA_13_BASE_IDX 0 +#define mmROM_SW_DATA_14 0x00f7 +#define mmROM_SW_DATA_14_BASE_IDX 0 +#define mmROM_SW_DATA_15 0x00f8 +#define mmROM_SW_DATA_15_BASE_IDX 0 +#define mmROM_SW_DATA_16 0x00f9 +#define mmROM_SW_DATA_16_BASE_IDX 0 +#define mmROM_SW_DATA_17 0x00fa +#define mmROM_SW_DATA_17_BASE_IDX 0 +#define mmROM_SW_DATA_18 0x00fb +#define mmROM_SW_DATA_18_BASE_IDX 0 +#define mmROM_SW_DATA_19 0x00fc +#define mmROM_SW_DATA_19_BASE_IDX 0 +#define mmROM_SW_DATA_20 0x00fd +#define mmROM_SW_DATA_20_BASE_IDX 0 +#define mmROM_SW_DATA_21 0x00fe +#define mmROM_SW_DATA_21_BASE_IDX 0 +#define mmROM_SW_DATA_22 0x00ff +#define mmROM_SW_DATA_22_BASE_IDX 0 +#define mmROM_SW_DATA_23 0x0100 +#define mmROM_SW_DATA_23_BASE_IDX 0 +#define mmROM_SW_DATA_24 0x0101 +#define mmROM_SW_DATA_24_BASE_IDX 0 +#define mmROM_SW_DATA_25 0x0102 +#define mmROM_SW_DATA_25_BASE_IDX 0 +#define mmROM_SW_DATA_26 0x0103 +#define mmROM_SW_DATA_26_BASE_IDX 0 +#define mmROM_SW_DATA_27 0x0104 +#define mmROM_SW_DATA_27_BASE_IDX 0 +#define mmROM_SW_DATA_28 0x0105 +#define mmROM_SW_DATA_28_BASE_IDX 0 +#define mmROM_SW_DATA_29 0x0106 +#define mmROM_SW_DATA_29_BASE_IDX 0 +#define mmROM_SW_DATA_30 0x0107 +#define mmROM_SW_DATA_30_BASE_IDX 0 +#define mmROM_SW_DATA_31 0x0108 +#define mmROM_SW_DATA_31_BASE_IDX 0 +#define mmROM_SW_DATA_32 0x0109 +#define mmROM_SW_DATA_32_BASE_IDX 0 +#define mmROM_SW_DATA_33 0x010a +#define mmROM_SW_DATA_33_BASE_IDX 0 +#define mmROM_SW_DATA_34 0x010b +#define mmROM_SW_DATA_34_BASE_IDX 0 +#define mmROM_SW_DATA_35 0x010c +#define mmROM_SW_DATA_35_BASE_IDX 0 +#define mmROM_SW_DATA_36 0x010d +#define mmROM_SW_DATA_36_BASE_IDX 0 +#define mmROM_SW_DATA_37 0x010e +#define mmROM_SW_DATA_37_BASE_IDX 0 +#define mmROM_SW_DATA_38 0x010f +#define mmROM_SW_DATA_38_BASE_IDX 0 +#define mmROM_SW_DATA_39 0x0110 +#define mmROM_SW_DATA_39_BASE_IDX 0 +#define mmROM_SW_DATA_40 0x0111 +#define mmROM_SW_DATA_40_BASE_IDX 0 +#define mmROM_SW_DATA_41 0x0112 +#define mmROM_SW_DATA_41_BASE_IDX 0 +#define mmROM_SW_DATA_42 0x0113 +#define mmROM_SW_DATA_42_BASE_IDX 0 +#define mmROM_SW_DATA_43 0x0114 +#define mmROM_SW_DATA_43_BASE_IDX 0 +#define mmROM_SW_DATA_44 0x0115 +#define mmROM_SW_DATA_44_BASE_IDX 0 +#define mmROM_SW_DATA_45 0x0116 +#define mmROM_SW_DATA_45_BASE_IDX 0 +#define mmROM_SW_DATA_46 0x0117 +#define mmROM_SW_DATA_46_BASE_IDX 0 +#define mmROM_SW_DATA_47 0x0118 +#define mmROM_SW_DATA_47_BASE_IDX 0 +#define mmROM_SW_DATA_48 0x0119 +#define mmROM_SW_DATA_48_BASE_IDX 0 +#define mmROM_SW_DATA_49 0x011a +#define mmROM_SW_DATA_49_BASE_IDX 0 +#define mmROM_SW_DATA_50 0x011b +#define mmROM_SW_DATA_50_BASE_IDX 0 +#define mmROM_SW_DATA_51 0x011c +#define mmROM_SW_DATA_51_BASE_IDX 0 +#define mmROM_SW_DATA_52 0x011d +#define mmROM_SW_DATA_52_BASE_IDX 0 +#define mmROM_SW_DATA_53 0x011e +#define mmROM_SW_DATA_53_BASE_IDX 0 +#define mmROM_SW_DATA_54 0x011f +#define mmROM_SW_DATA_54_BASE_IDX 0 +#define mmROM_SW_DATA_55 0x0120 +#define mmROM_SW_DATA_55_BASE_IDX 0 +#define mmROM_SW_DATA_56 0x0121 +#define mmROM_SW_DATA_56_BASE_IDX 0 +#define mmROM_SW_DATA_57 0x0122 +#define mmROM_SW_DATA_57_BASE_IDX 0 +#define mmROM_SW_DATA_58 0x0123 +#define mmROM_SW_DATA_58_BASE_IDX 0 +#define mmROM_SW_DATA_59 0x0124 +#define mmROM_SW_DATA_59_BASE_IDX 0 +#define mmROM_SW_DATA_60 0x0125 +#define mmROM_SW_DATA_60_BASE_IDX 0 +#define mmROM_SW_DATA_61 0x0126 +#define mmROM_SW_DATA_61_BASE_IDX 0 +#define mmROM_SW_DATA_62 0x0127 +#define mmROM_SW_DATA_62_BASE_IDX 0 +#define mmROM_SW_DATA_63 0x0128 +#define mmROM_SW_DATA_63_BASE_IDX 0 +#define mmROM_SW_DATA_64 0x0129 +#define mmROM_SW_DATA_64_BASE_IDX 0 +#define mmSMU_GPIOPAD_SW_INT_STAT 0x0140 +#define mmSMU_GPIOPAD_SW_INT_STAT_BASE_IDX 0 +#define mmSMU_GPIOPAD_MASK 0x0141 +#define mmSMU_GPIOPAD_MASK_BASE_IDX 0 +#define mmSMU_GPIOPAD_A 0x0142 +#define mmSMU_GPIOPAD_A_BASE_IDX 0 +#define mmSMU_GPIOPAD_TXIMPSEL 0x0143 +#define mmSMU_GPIOPAD_TXIMPSEL_BASE_IDX 0 +#define mmSMU_GPIOPAD_EN 0x0144 +#define mmSMU_GPIOPAD_EN_BASE_IDX 0 +#define mmSMU_GPIOPAD_Y 0x0145 +#define mmSMU_GPIOPAD_Y_BASE_IDX 0 +#define mmSMU_GPIOPAD_RXEN 0x0146 +#define mmSMU_GPIOPAD_RXEN_BASE_IDX 0 +#define mmSMU_GPIOPAD_RCVR_SEL0 0x0147 +#define mmSMU_GPIOPAD_RCVR_SEL0_BASE_IDX 0 +#define mmSMU_GPIOPAD_RCVR_SEL1 0x0148 +#define mmSMU_GPIOPAD_RCVR_SEL1_BASE_IDX 0 +#define mmSMU_GPIOPAD_PU_EN 0x0149 +#define mmSMU_GPIOPAD_PU_EN_BASE_IDX 0 +#define mmSMU_GPIOPAD_PD_EN 0x014a +#define mmSMU_GPIOPAD_PD_EN_BASE_IDX 0 +#define mmSMU_GPIOPAD_PINSTRAPS 0x014b +#define mmSMU_GPIOPAD_PINSTRAPS_BASE_IDX 0 +#define mmDFT_PINSTRAPS 0x014c +#define mmDFT_PINSTRAPS_BASE_IDX 0 +#define mmSMU_GPIOPAD_INT_STAT_EN 0x014d +#define mmSMU_GPIOPAD_INT_STAT_EN_BASE_IDX 0 +#define mmSMU_GPIOPAD_INT_STAT 0x014e +#define mmSMU_GPIOPAD_INT_STAT_BASE_IDX 0 +#define mmSMU_GPIOPAD_INT_STAT_AK 0x014f +#define mmSMU_GPIOPAD_INT_STAT_AK_BASE_IDX 0 +#define mmSMU_GPIOPAD_INT_EN 0x0150 +#define mmSMU_GPIOPAD_INT_EN_BASE_IDX 0 +#define mmSMU_GPIOPAD_INT_TYPE 0x0151 +#define mmSMU_GPIOPAD_INT_TYPE_BASE_IDX 0 +#define mmSMU_GPIOPAD_INT_POLARITY 0x0152 +#define mmSMU_GPIOPAD_INT_POLARITY_BASE_IDX 0 +#define mmROM_CC_BIF_PINSTRAP 0x0153 +#define mmROM_CC_BIF_PINSTRAP_BASE_IDX 0 +#define mmIO_SMUIO_PINSTRAP 0x0154 +#define mmIO_SMUIO_PINSTRAP_BASE_IDX 0 +#define mmSMUIO_PCC_CONTROL 0x0155 +#define mmSMUIO_PCC_CONTROL_BASE_IDX 0 +#define mmSMUIO_PCC_GPIO_SELECT 0x0156 +#define mmSMUIO_PCC_GPIO_SELECT_BASE_IDX 0 +#define mmSMUIO_GPIO_INT0_SELECT 0x0157 +#define mmSMUIO_GPIO_INT0_SELECT_BASE_IDX 0 +#define mmSMUIO_GPIO_INT1_SELECT 0x0158 +#define mmSMUIO_GPIO_INT1_SELECT_BASE_IDX 0 +#define mmSMUIO_GPIO_INT2_SELECT 0x0159 +#define mmSMUIO_GPIO_INT2_SELECT_BASE_IDX 0 +#define mmSMUIO_GPIO_INT3_SELECT 0x015a +#define mmSMUIO_GPIO_INT3_SELECT_BASE_IDX 0 +#define mmSMU_GPIOPAD_MP_INT0_STAT 0x015b +#define mmSMU_GPIOPAD_MP_INT0_STAT_BASE_IDX 0 +#define mmSMU_GPIOPAD_MP_INT1_STAT 0x015c +#define mmSMU_GPIOPAD_MP_INT1_STAT_BASE_IDX 0 +#define mmSMU_GPIOPAD_MP_INT2_STAT 0x015d +#define mmSMU_GPIOPAD_MP_INT2_STAT_BASE_IDX 0 +#define mmSMU_GPIOPAD_MP_INT3_STAT 0x015e +#define mmSMU_GPIOPAD_MP_INT3_STAT_BASE_IDX 0 +#define mmSMIO_INDEX 0x015f +#define mmSMIO_INDEX_BASE_IDX 0 +#define mmS0_VID_SMIO_CNTL 0x0160 +#define mmS0_VID_SMIO_CNTL_BASE_IDX 0 +#define mmS1_VID_SMIO_CNTL 0x0161 +#define mmS1_VID_SMIO_CNTL_BASE_IDX 0 +#define mmOPEN_DRAIN_SELECT 0x0162 +#define mmOPEN_DRAIN_SELECT_BASE_IDX 0 +#define mmSMIO_ENABLE 0x0163 +#define mmSMIO_ENABLE_BASE_IDX 0 +#define mmSMU_GPIOPAD_S0 0x0166 +#define mmSMU_GPIOPAD_S0_BASE_IDX 0 +#define mmSMU_GPIOPAD_S1 0x0167 +#define mmSMU_GPIOPAD_S1_BASE_IDX 0 +#define mmSMU_GPIOPAD_SCL_EN 0x0168 +#define mmSMU_GPIOPAD_SCL_EN_BASE_IDX 0 +#define mmSMU_GPIOPAD_SDA_EN 0x0169 +#define mmSMU_GPIOPAD_SDA_EN_BASE_IDX 0 +#define mmSMU_GPIOPAD_SCHMEN 0x016a +#define mmSMU_GPIOPAD_SCHMEN_BASE_IDX 0 + + +// addressBlock: smuio_smuio_pwr_SmuSmuioDec +// base address: 0x5a800 +#define mmIP_DISCOVERY_VERSION 0x0000 +#define mmIP_DISCOVERY_VERSION_BASE_IDX 1 +#define mmSOC_GAP_PWROK 0x00f8 +#define mmSOC_GAP_PWROK_BASE_IDX 1 +#define mmGFX_GAP_PWROK 0x00f9 +#define mmGFX_GAP_PWROK_BASE_IDX 1 +#define mmPWROK_REFCLK_GAP_CYCLES 0x00fa +#define mmPWROK_REFCLK_GAP_CYCLES_BASE_IDX 1 +#define mmGOLDEN_TSC_INCREMENT_UPPER 0x0100 +#define mmGOLDEN_TSC_INCREMENT_UPPER_BASE_IDX 1 +#define mmGOLDEN_TSC_INCREMENT_LOWER 0x0101 +#define mmGOLDEN_TSC_INCREMENT_LOWER_BASE_IDX 1 +#define mmGOLDEN_TSC_COUNT_UPPER 0x0102 +#define mmGOLDEN_TSC_COUNT_UPPER_BASE_IDX 1 +#define mmGOLDEN_TSC_COUNT_LOWER 0x0103 +#define mmGOLDEN_TSC_COUNT_LOWER_BASE_IDX 1 +#define mmSOC_GOLDEN_TSC_SHADOW_UPPER 0x0104 +#define mmSOC_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX 1 +#define mmSOC_GOLDEN_TSC_SHADOW_LOWER 0x0105 +#define mmSOC_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX 1 +#define mmGFX_GOLDEN_TSC_SHADOW_UPPER 0x0106 +#define mmGFX_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX 1 +#define mmGFX_GOLDEN_TSC_SHADOW_LOWER 0x0107 +#define mmGFX_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX 1 +#define mmPWR_VIRT_RESET_REQ 0x0108 +#define mmPWR_VIRT_RESET_REQ_BASE_IDX 1 +#define mmSCRATCH_REGISTER0 0x0110 +#define mmSCRATCH_REGISTER0_BASE_IDX 1 +#define mmSCRATCH_REGISTER1 0x0111 +#define mmSCRATCH_REGISTER1_BASE_IDX 1 +#define mmSCRATCH_REGISTER2 0x0112 +#define mmSCRATCH_REGISTER2_BASE_IDX 1 +#define mmSCRATCH_REGISTER3 0x0113 +#define mmSCRATCH_REGISTER3_BASE_IDX 1 +#define mmSCRATCH_REGISTER4 0x0114 +#define mmSCRATCH_REGISTER4_BASE_IDX 1 +#define mmSCRATCH_REGISTER5 0x0115 +#define mmSCRATCH_REGISTER5_BASE_IDX 1 +#define mmSCRATCH_REGISTER6 0x0116 +#define mmSCRATCH_REGISTER6_BASE_IDX 1 +#define mmSCRATCH_REGISTER7 0x0117 +#define mmSCRATCH_REGISTER7_BASE_IDX 1 +#define mmPWR_DISP_TIMER_CONTROL 0x012c +#define mmPWR_DISP_TIMER_CONTROL_BASE_IDX 1 +#define mmPWR_DISP_TIMER2_CONTROL 0x012e +#define mmPWR_DISP_TIMER2_CONTROL_BASE_IDX 1 +#define mmPWR_DISP_TIMER_GLOBAL_CONTROL 0x0130 +#define mmPWR_DISP_TIMER_GLOBAL_CONTROL_BASE_IDX 1 +#define mmPWR_IH_CONTROL 0x0131 +#define mmPWR_IH_CONTROL_BASE_IDX 1 + +#endif |