diff options
Diffstat (limited to 'drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h new file mode 100644 index 000000000000..2176548e9203 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h @@ -0,0 +1,64 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VCE_1_0_D_H +#define VCE_1_0_D_H + +#define mmVCE_CLOCK_GATING_A 0x80BE +#define mmVCE_CLOCK_GATING_B 0x80BF +#define mmVCE_LMI_CACHE_CTRL 0x83BD +#define mmVCE_LMI_CTRL 0x83A6 +#define mmVCE_LMI_CTRL2 0x839D +#define mmVCE_LMI_MISC_CTRL 0x83B5 +#define mmVCE_LMI_STATUS 0x83A7 +#define mmVCE_LMI_SWAP_CNTL 0x83AD +#define mmVCE_LMI_SWAP_CNTL1 0x83AE +#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR 0x8397 +#define mmVCE_LMI_VM_CTRL 0x83A8 +#define mmVCE_RB_ARB_CTRL 0x809F +#define mmVCE_RB_BASE_HI 0x8061 +#define mmVCE_RB_BASE_HI2 0x805C +#define mmVCE_RB_BASE_LO 0x8060 +#define mmVCE_RB_BASE_LO2 0x805B +#define mmVCE_RB_RPTR 0x8063 +#define mmVCE_RB_RPTR2 0x805E +#define mmVCE_RB_SIZE 0x8062 +#define mmVCE_RB_SIZE2 0x805D +#define mmVCE_RB_WPTR 0x8064 +#define mmVCE_RB_WPTR2 0x805F +#define mmVCE_SOFT_RESET 0x8048 +#define mmVCE_STATUS 0x8001 +#define mmVCE_SYS_INT_ACK 0x8341 +#define mmVCE_SYS_INT_EN 0x8340 +#define mmVCE_SYS_INT_STATUS 0x8341 +#define mmVCE_UENC_CLOCK_GATING 0x816F +#define mmVCE_UENC_DMA_DCLK_CTRL 0x8250 +#define mmVCE_UENC_REG_CLOCK_GATING 0x8170 +#define mmVCE_VCPU_CACHE_OFFSET0 0x8009 +#define mmVCE_VCPU_CACHE_OFFSET1 0x800B +#define mmVCE_VCPU_CACHE_OFFSET2 0x800D +#define mmVCE_VCPU_CACHE_SIZE0 0x800A +#define mmVCE_VCPU_CACHE_SIZE1 0x800C +#define mmVCE_VCPU_CACHE_SIZE2 0x800E +#define mmVCE_VCPU_CNTL 0x8005 + +#endif |