diff options
Diffstat (limited to 'drivers/gpu/drm/amd/include/ivsrcid')
| -rw-r--r-- | drivers/gpu/drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h (renamed from drivers/gpu/drm/amd/include/ivsrcid/irqsrcs_dcn_1_0.h) | 0 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/include/ivsrcid/gfx/irqsrcs_gfx_10_1.h | 53 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/include/ivsrcid/sdma0/irqsrcs_sdma0_5_0.h | 43 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/include/ivsrcid/sdma1/irqsrcs_sdma1_5_0.h | 44 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/include/ivsrcid/vcn/irqsrcs_vcn_2_0.h | 32 |
5 files changed, 172 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/ivsrcid/irqsrcs_dcn_1_0.h b/drivers/gpu/drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h index ac9fa3a9bd07..ac9fa3a9bd07 100644 --- a/drivers/gpu/drm/amd/include/ivsrcid/irqsrcs_dcn_1_0.h +++ b/drivers/gpu/drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h diff --git a/drivers/gpu/drm/amd/include/ivsrcid/gfx/irqsrcs_gfx_10_1.h b/drivers/gpu/drm/amd/include/ivsrcid/gfx/irqsrcs_gfx_10_1.h new file mode 100644 index 000000000000..d6e478cf0c4a --- /dev/null +++ b/drivers/gpu/drm/amd/include/ivsrcid/gfx/irqsrcs_gfx_10_1.h @@ -0,0 +1,53 @@ +/* + * Copyright 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __IRQSRCS_GFX_10_1_H__ +#define __IRQSRCS_GFX_10_1_H__ + + +#define GFX_10_1__SRCID__CP_RB_INTERRUPT_PKT 176 // B0 CP_INTERRUPT pkt in RB +#define GFX_10_1__SRCID__CP_GENERIC_INT 177 // B1 MES GENERIC INT +#define GFX_10_1__SRCID__CP_IB1_INTERRUPT_PKT 177 // B1 CP_INTERRUPT pkt in IB1 +#define GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT 178 // B2 CP_INTERRUPT pkt in IB2 +#define GFX_10_1__SRCID__CP_PM4_PKT_RSVD_BIT_ERROR 180 // B4 PM4 Pkt Rsvd Bits Error +#define GFX_10_1__SRCID__CP_EOP_INTERRUPT 181 // B5 End-of-Pipe Interrupt +#define GFX_10_1__SRCID__CP_BAD_OPCODE_ERROR 183 // B7 Bad Opcode Error +#define GFX_10_1__SRCID__CP_PRIV_REG_FAULT 184 // B8 Privileged Register Fault +#define GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT 185 // B9 Privileged Instr Fault +#define GFX_10_1__SRCID__CP_WAIT_MEM_SEM_FAULT 186 // BA Wait Memory Semaphore Fault (Synchronization Object Fault) +#define GFX_10_1__SRCID__CP_CTX_EMPTY_INTERRUPT 187 // BB Context Empty Interrupt +#define GFX_10_1__SRCID__CP_CTX_BUSY_INTERRUPT 188 // BC Context Busy Interrupt +#define GFX_10_1__SRCID__CP_ME_WAIT_REG_MEM_POLL_TIMEOUT 192 // C0 CP.ME Wait_Reg_Mem Poll Timeout +#define GFX_10_1__SRCID__CP_SIG_INCOMPLETE 193 // C1 "Surface Probe Fault Signal Incomplete" +#define GFX_10_1__SRCID__CP_PREEMPT_ACK 194 // C2 Preemption Ack-wledge +#define GFX_10_1__SRCID__CP_GPF 195 // C3 General Protection Fault (GPF) +#define GFX_10_1__SRCID__CP_GDS_ALLOC_ERROR 196 // C4 GDS Alloc Error +#define GFX_10_1__SRCID__CP_ECC_ERROR 197 // C5 ECC Error +#define GFX_10_1__SRCID__CP_COMPUTE_QUERY_STATUS 199 // C7 Compute query status +#define GFX_10_1__SRCID__CP_VM_DOORBELL 200 // C8 Unattached VM Doorbell Received +#define GFX_10_1__SRCID__CP_FUE_ERROR 201 // C9 ECC FUE Error +#define GFX_10_1__SRCID__RLC_STRM_PERF_MONITOR_INTERRUPT 202 // CA Streaming Perf Monitor Interrupt +#define GFX_10_1__SRCID__GRBM_RD_TIMEOUT_ERROR 232 // E8 CRead timeout error +#define GFX_10_1__SRCID__GRBM_REG_GUI_IDLE 233 // E9 Register GUI Idle +#define GFX_10_1__SRCID__SQ_INTERRUPT_ID 239 // EF SQ Interrupt (ttrace wrap, errors) + +#endif diff --git a/drivers/gpu/drm/amd/include/ivsrcid/sdma0/irqsrcs_sdma0_5_0.h b/drivers/gpu/drm/amd/include/ivsrcid/sdma0/irqsrcs_sdma0_5_0.h new file mode 100644 index 000000000000..c3652b863bd8 --- /dev/null +++ b/drivers/gpu/drm/amd/include/ivsrcid/sdma0/irqsrcs_sdma0_5_0.h @@ -0,0 +1,43 @@ +/* + * Copyright 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __IRQSRCS_SDMA0_5_0_H__ +#define __IRQSRCS_SDMA0_5_0_H__ + +#define SDMA0_5_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 // 0xD9 SDMA atomic*_rtn ops complete +#define SDMA0_5_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 // 0xDA SDMA atomic CMPSWAP loop timeout +#define SDMA0_5_0__SRCID__SDMA_IB_PREEMPT 219 // 0xDB sdma mid-command buffer preempt interrupt +#define SDMA0_5_0__SRCID__SDMA_ECC 220 // 0xDC ECC Error +#define SDMA0_5_0__SRCID__SDMA_PAGE_FAULT 221 // 0xDD Page Fault Error from UTCL2 when nack=3 +#define SDMA0_5_0__SRCID__SDMA_PAGE_NULL 222 // 0xDE Page Null from UTCL2 when nack=2 +#define SDMA0_5_0__SRCID__SDMA_XNACK 223 // 0xDF Page retry timeout after UTCL2 return nack=1 +#define SDMA0_5_0__SRCID__SDMA_TRAP 224 // 0xE0 Trap +#define SDMA0_5_0__SRCID__SDMA_SEM_INCOMPLETE_TIMEOUT 225 // 0xE1 0xDAGPF (Sem incomplete timeout) +#define SDMA0_5_0__SRCID__SDMA_SEM_WAIT_FAIL_TIMEOUT 226 // 0xE2 Semaphore wait fail timeout +#define SDMA0_5_0__SRCID__SDMA_SRAM_ECC 228 // 0xE4 SRAM ECC Error +#define SDMA0_5_0__SRCID__SDMA_PREEMPT 240 // 0xF0 SDMA New Run List +#define SDMA0_5_0__SRCID__SDMA_VM_HOLE 242 // 0xF2 MC or SEM address in VM hole +#define SDMA0_5_0__SRCID__SDMA_CTXEMPTY 243 // 0xF3 Context Empty +#define SDMA0_5_0__SRCID__SDMA_DOORBELL_INVALID 244 // 0xF4 Doorbell BE invalid +#define SDMA0_5_0__SRCID__SDMA_FROZEN 245 // 0xF5 SDMA Frozen +#define SDMA0_5_0__SRCID__SDMA_POLL_TIMEOUT 246 // 0xF6 SRBM read poll timeout +#define SDMA0_5_0__SRCID__SDMA_SRBMWRITE 247 // 0xF7 SRBM write Protection +#endif diff --git a/drivers/gpu/drm/amd/include/ivsrcid/sdma1/irqsrcs_sdma1_5_0.h b/drivers/gpu/drm/amd/include/ivsrcid/sdma1/irqsrcs_sdma1_5_0.h new file mode 100644 index 000000000000..7b68c466cab0 --- /dev/null +++ b/drivers/gpu/drm/amd/include/ivsrcid/sdma1/irqsrcs_sdma1_5_0.h @@ -0,0 +1,44 @@ +/* + * Copyright 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __IRQSRCS_SDMA1_5_0_H__ +#define __IRQSRCS_SDMA1_5_0_H__ + +#define SDMA1_5_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 // 0xD9 SDMA atomic*_rtn ops complete +#define SDMA1_5_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 // 0xDA SDMA atomic CMPSWAP loop timeout +#define SDMA1_5_0__SRCID__SDMA_IB_PREEMPT 219 // 0xDB sdma mid-command buffer preempt interrupt +#define SDMA1_5_0__SRCID__SDMA_ECC 220 // 0xDC ECC Error +#define SDMA1_5_0__SRCID__SDMA_PAGE_FAULT 221 // 0xDD Page Fault Error from UTCL2 when nack=3 +#define SDMA1_5_0__SRCID__SDMA_PAGE_NULL 222 // 0xDE Page Null from UTCL2 when nack=2 +#define SDMA1_5_0__SRCID__SDMA_XNACK 223 // 0xDF Page retry timeout after UTCL2 return nack=1 +#define SDMA1_5_0__SRCID__SDMA_TRAP 224 // 0xE0 Trap +#define SDMA1_5_0__SRCID__SDMA_SEM_INCOMPLETE_TIMEOUT 225 // 0xE1 0xDAGPF (Sem incomplete timeout) +#define SDMA1_5_0__SRCID__SDMA_SEM_WAIT_FAIL_TIMEOUT 226 // 0xE2 Semaphore wait fail timeout +#define SDMA1_5_0__SRCID__SDMA_SRAM_ECC 228 // 0xE4 SRAM ECC Error +#define SDMA1_5_0__SRCID__SDMA_PREEMPT 240 // 0xF0 SDMA New Run List +#define SDMA1_5_0__SRCID__SDMA_VM_HOLE 242 // 0xF2 MC or SEM address in VM hole +#define SDMA1_5_0__SRCID__SDMA_CTXEMPTY 243 // 0xF3 Context Empty +#define SDMA1_5_0__SRCID__SDMA_DOORBELL_INVALID 244 // 0xF4 Doorbell BE invalid +#define SDMA1_5_0__SRCID__SDMA_FROZEN 245 // 0xF5 SDMA Frozen +#define SDMA1_5_0__SRCID__SDMA_POLL_TIMEOUT 246 // 0xF6 SRBM read poll timeout +#define SDMA1_5_0__SRCID__SDMA_SRBMWRITE 247 // 0xF7 SRBM write Protection + +#endif diff --git a/drivers/gpu/drm/amd/include/ivsrcid/vcn/irqsrcs_vcn_2_0.h b/drivers/gpu/drm/amd/include/ivsrcid/vcn/irqsrcs_vcn_2_0.h new file mode 100644 index 000000000000..17acac147013 --- /dev/null +++ b/drivers/gpu/drm/amd/include/ivsrcid/vcn/irqsrcs_vcn_2_0.h @@ -0,0 +1,32 @@ +/* + * Copyright 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __IRQSRCS_VCN_2_0_H__ +#define __IRQSRCS_VCN_2_0_H__ + +#define VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE 119 // 0x77 Encoder General Purpose +#define VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY 120 // 0x78 Encoder Low Latency +#define VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT 124 // 0x7c UVD system message interrupt +#define VCN_2_0__SRCID__JPEG_ENCODE 151 // 0x97 JRBC Encode interrupt +#define VCN_2_0__SRCID__JPEG_DECODE 153 // 0x99 JRBC Decode interrupt + +#endif |