diff options
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/inc')
29 files changed, 18109 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h new file mode 100644 index 000000000000..e61a3e67852e --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h @@ -0,0 +1,299 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _AMD_POWERPLAY_H_ +#define _AMD_POWERPLAY_H_ + +#include <linux/seq_file.h> +#include <linux/types.h> +#include <linux/errno.h> +#include "amd_shared.h" +#include "cgs_common.h" + +enum amd_pp_event { + AMD_PP_EVENT_INITIALIZE = 0, + AMD_PP_EVENT_UNINITIALIZE, + AMD_PP_EVENT_POWER_SOURCE_CHANGE, + AMD_PP_EVENT_SUSPEND, + AMD_PP_EVENT_RESUME, + AMD_PP_EVENT_ENTER_REST_STATE, + AMD_PP_EVENT_EXIT_REST_STATE, + AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE, + AMD_PP_EVENT_THERMAL_NOTIFICATION, + AMD_PP_EVENT_VBIOS_NOTIFICATION, + AMD_PP_EVENT_ENTER_THERMAL_STATE, + AMD_PP_EVENT_EXIT_THERMAL_STATE, + AMD_PP_EVENT_ENTER_FORCED_STATE, + AMD_PP_EVENT_EXIT_FORCED_STATE, + AMD_PP_EVENT_ENTER_EXCLUSIVE_MODE, + AMD_PP_EVENT_EXIT_EXCLUSIVE_MODE, + AMD_PP_EVENT_ENTER_SCREEN_SAVER, + AMD_PP_EVENT_EXIT_SCREEN_SAVER, + AMD_PP_EVENT_VPU_RECOVERY_BEGIN, + AMD_PP_EVENT_VPU_RECOVERY_END, + AMD_PP_EVENT_ENABLE_POWER_PLAY, + AMD_PP_EVENT_DISABLE_POWER_PLAY, + AMD_PP_EVENT_CHANGE_POWER_SOURCE_UI_LABEL, + AMD_PP_EVENT_ENABLE_USER2D_PERFORMANCE, + AMD_PP_EVENT_DISABLE_USER2D_PERFORMANCE, + AMD_PP_EVENT_ENABLE_USER3D_PERFORMANCE, + AMD_PP_EVENT_DISABLE_USER3D_PERFORMANCE, + AMD_PP_EVENT_ENABLE_OVER_DRIVE_TEST, + AMD_PP_EVENT_DISABLE_OVER_DRIVE_TEST, + AMD_PP_EVENT_ENABLE_REDUCED_REFRESH_RATE, + AMD_PP_EVENT_DISABLE_REDUCED_REFRESH_RATE, + AMD_PP_EVENT_ENABLE_GFX_CLOCK_GATING, + AMD_PP_EVENT_DISABLE_GFX_CLOCK_GATING, + AMD_PP_EVENT_ENABLE_CGPG, + AMD_PP_EVENT_DISABLE_CGPG, + AMD_PP_EVENT_ENTER_TEXT_MODE, + AMD_PP_EVENT_EXIT_TEXT_MODE, + AMD_PP_EVENT_VIDEO_START, + AMD_PP_EVENT_VIDEO_STOP, + AMD_PP_EVENT_ENABLE_USER_STATE, + AMD_PP_EVENT_DISABLE_USER_STATE, + AMD_PP_EVENT_READJUST_POWER_STATE, + AMD_PP_EVENT_START_INACTIVITY, + AMD_PP_EVENT_STOP_INACTIVITY, + AMD_PP_EVENT_LINKED_ADAPTERS_READY, + AMD_PP_EVENT_ADAPTER_SAFE_TO_DISABLE, + AMD_PP_EVENT_COMPLETE_INIT, + AMD_PP_EVENT_CRITICAL_THERMAL_FAULT, + AMD_PP_EVENT_BACKLIGHT_CHANGED, + AMD_PP_EVENT_ENABLE_VARI_BRIGHT, + AMD_PP_EVENT_DISABLE_VARI_BRIGHT, + AMD_PP_EVENT_ENABLE_VARI_BRIGHT_ON_POWER_XPRESS, + AMD_PP_EVENT_DISABLE_VARI_BRIGHT_ON_POWER_XPRESS, + AMD_PP_EVENT_SET_VARI_BRIGHT_LEVEL, + AMD_PP_EVENT_VARI_BRIGHT_MONITOR_MEASUREMENT, + AMD_PP_EVENT_SCREEN_ON, + AMD_PP_EVENT_SCREEN_OFF, + AMD_PP_EVENT_PRE_DISPLAY_CONFIG_CHANGE, + AMD_PP_EVENT_ENTER_ULP_STATE, + AMD_PP_EVENT_EXIT_ULP_STATE, + AMD_PP_EVENT_REGISTER_IP_STATE, + AMD_PP_EVENT_UNREGISTER_IP_STATE, + AMD_PP_EVENT_ENTER_MGPU_MODE, + AMD_PP_EVENT_EXIT_MGPU_MODE, + AMD_PP_EVENT_ENTER_MULTI_GPU_MODE, + AMD_PP_EVENT_PRE_SUSPEND, + AMD_PP_EVENT_PRE_RESUME, + AMD_PP_EVENT_ENTER_BACOS, + AMD_PP_EVENT_EXIT_BACOS, + AMD_PP_EVENT_RESUME_BACO, + AMD_PP_EVENT_RESET_BACO, + AMD_PP_EVENT_PRE_DISPLAY_PHY_ACCESS, + AMD_PP_EVENT_POST_DISPLAY_PHY_CCESS, + AMD_PP_EVENT_START_COMPUTE_APPLICATION, + AMD_PP_EVENT_STOP_COMPUTE_APPLICATION, + AMD_PP_EVENT_REDUCE_POWER_LIMIT, + AMD_PP_EVENT_ENTER_FRAME_LOCK, + AMD_PP_EVENT_EXIT_FRAME_LOOCK, + AMD_PP_EVENT_LONG_IDLE_REQUEST_BACO, + AMD_PP_EVENT_LONG_IDLE_ENTER_BACO, + AMD_PP_EVENT_LONG_IDLE_EXIT_BACO, + AMD_PP_EVENT_HIBERNATE, + AMD_PP_EVENT_CONNECTED_STANDBY, + AMD_PP_EVENT_ENTER_SELF_REFRESH, + AMD_PP_EVENT_EXIT_SELF_REFRESH, + AMD_PP_EVENT_START_AVFS_BTC, + AMD_PP_EVENT_MAX +}; + +enum amd_dpm_forced_level { + AMD_DPM_FORCED_LEVEL_AUTO = 0, + AMD_DPM_FORCED_LEVEL_LOW = 1, + AMD_DPM_FORCED_LEVEL_HIGH = 2, +}; + +struct amd_pp_init { + struct cgs_device *device; + uint32_t chip_family; + uint32_t chip_id; + uint32_t rev_id; +}; +enum amd_pp_display_config_type{ + AMD_PP_DisplayConfigType_None = 0, + AMD_PP_DisplayConfigType_DP54 , + AMD_PP_DisplayConfigType_DP432 , + AMD_PP_DisplayConfigType_DP324 , + AMD_PP_DisplayConfigType_DP27, + AMD_PP_DisplayConfigType_DP243, + AMD_PP_DisplayConfigType_DP216, + AMD_PP_DisplayConfigType_DP162, + AMD_PP_DisplayConfigType_HDMI6G , + AMD_PP_DisplayConfigType_HDMI297 , + AMD_PP_DisplayConfigType_HDMI162, + AMD_PP_DisplayConfigType_LVDS, + AMD_PP_DisplayConfigType_DVI, + AMD_PP_DisplayConfigType_WIRELESS, + AMD_PP_DisplayConfigType_VGA +}; + +struct single_display_configuration +{ + uint32_t controller_index; + uint32_t controller_id; + uint32_t signal_type; + uint32_t display_state; + /* phy id for the primary internal transmitter */ + uint8_t primary_transmitter_phyi_d; + /* bitmap with the active lanes */ + uint8_t primary_transmitter_active_lanemap; + /* phy id for the secondary internal transmitter (for dual-link dvi) */ + uint8_t secondary_transmitter_phy_id; + /* bitmap with the active lanes */ + uint8_t secondary_transmitter_active_lanemap; + /* misc phy settings for SMU. */ + uint32_t config_flags; + uint32_t display_type; + uint32_t view_resolution_cx; + uint32_t view_resolution_cy; + enum amd_pp_display_config_type displayconfigtype; + uint32_t vertical_refresh; /* for active display */ +}; + +#define MAX_NUM_DISPLAY 32 + +struct amd_pp_display_configuration { + bool nb_pstate_switch_disable;/* controls NB PState switch */ + bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */ + bool cpu_pstate_disable; + uint32_t cpu_pstate_separation_time; + + uint32_t num_display; /* total number of display*/ + uint32_t num_path_including_non_display; + uint32_t crossfire_display_index; + uint32_t min_mem_set_clock; + uint32_t min_core_set_clock; + /* unit 10KHz x bit*/ + uint32_t min_bus_bandwidth; + /* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/ + uint32_t min_core_set_clock_in_sr; + + struct single_display_configuration displays[MAX_NUM_DISPLAY]; + + uint32_t vrefresh; /* for active display*/ + + uint32_t min_vblank_time; /* for active display*/ + bool multi_monitor_in_sync; + /* Controller Index of primary display - used in MCLK SMC switching hang + * SW Workaround*/ + uint32_t crtc_index; + /* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/ + uint32_t line_time_in_us; + bool invalid_vblank_time; + + uint32_t display_clk; + /* + * for given display configuration if multimonitormnsync == false then + * Memory clock DPMS with this latency or below is allowed, DPMS with + * higher latency not allowed. + */ + uint32_t dce_tolerable_mclk_in_active_latency; +}; + +struct amd_pp_dal_clock_info { + uint32_t engine_max_clock; + uint32_t memory_max_clock; + uint32_t level; +}; + +enum { + PP_GROUP_UNKNOWN = 0, + PP_GROUP_GFX = 1, + PP_GROUP_SYS, + PP_GROUP_MAX +}; + +#define PP_GROUP_MASK 0xF0000000 +#define PP_GROUP_SHIFT 28 + +#define PP_BLOCK_MASK 0x0FFFFF00 +#define PP_BLOCK_SHIFT 8 + +#define PP_BLOCK_GFX_CG 0x01 +#define PP_BLOCK_GFX_MG 0x02 +#define PP_BLOCK_SYS_BIF 0x01 +#define PP_BLOCK_SYS_MC 0x02 +#define PP_BLOCK_SYS_ROM 0x04 +#define PP_BLOCK_SYS_DRM 0x08 +#define PP_BLOCK_SYS_HDP 0x10 +#define PP_BLOCK_SYS_SDMA 0x20 + +#define PP_STATE_MASK 0x0000000F +#define PP_STATE_SHIFT 0 +#define PP_STATE_SUPPORT_MASK 0x000000F0 +#define PP_STATE_SUPPORT_SHIFT 0 + +#define PP_STATE_CG 0x01 +#define PP_STATE_LS 0x02 +#define PP_STATE_DS 0x04 +#define PP_STATE_SD 0x08 +#define PP_STATE_SUPPORT_CG 0x10 +#define PP_STATE_SUPPORT_LS 0x20 +#define PP_STATE_SUPPORT_DS 0x40 +#define PP_STATE_SUPPORT_SD 0x80 + +#define PP_CG_MSG_ID(group, block, support, state) (group << PP_GROUP_SHIFT |\ + block << PP_BLOCK_SHIFT |\ + support << PP_STATE_SUPPORT_SHIFT |\ + state << PP_STATE_SHIFT) + +struct amd_powerplay_funcs { + int (*get_temperature)(void *handle); + int (*load_firmware)(void *handle); + int (*wait_for_fw_loading_complete)(void *handle); + int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); + enum amd_dpm_forced_level (*get_performance_level)(void *handle); + enum amd_pm_state_type (*get_current_power_state)(void *handle); + int (*get_sclk)(void *handle, bool low); + int (*get_mclk)(void *handle, bool low); + int (*powergate_vce)(void *handle, bool gate); + int (*powergate_uvd)(void *handle, bool gate); + int (*dispatch_tasks)(void *handle, enum amd_pp_event event_id, + void *input, void *output); + void (*print_current_performance_level)(void *handle, + struct seq_file *m); + int (*set_fan_control_mode)(void *handle, uint32_t mode); + int (*get_fan_control_mode)(void *handle); + int (*set_fan_speed_percent)(void *handle, uint32_t percent); + int (*get_fan_speed_percent)(void *handle, uint32_t *speed); +}; + +struct amd_powerplay { + void *pp_handle; + const struct amd_ip_funcs *ip_funcs; + const struct amd_powerplay_funcs *pp_funcs; +}; + +int amd_powerplay_init(struct amd_pp_init *pp_init, + struct amd_powerplay *amd_pp); +int amd_powerplay_fini(void *handle); + +int amd_powerplay_display_configuration_change(void *handle, const void *input); + +int amd_powerplay_get_display_power_level(void *handle, + struct amd_pp_dal_clock_info *output); + + +#endif /* _AMD_POWERPLAY_H_ */ diff --git a/drivers/gpu/drm/amd/powerplay/inc/cz_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/cz_ppsmc.h new file mode 100644 index 000000000000..9b698780aed8 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/cz_ppsmc.h @@ -0,0 +1,186 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef CZ_PP_SMC_H +#define CZ_PP_SMC_H + +#pragma pack(push, 1) + +/* Fan control algorithm:*/ +#define FDO_MODE_HARDWARE 0 +#define FDO_MODE_PIECE_WISE_LINEAR 1 + +enum FAN_CONTROL { + FAN_CONTROL_FUZZY, + FAN_CONTROL_TABLE +}; + +enum DPM_ARRAY { + DPM_ARRAY_HARD_MAX, + DPM_ARRAY_HARD_MIN, + DPM_ARRAY_SOFT_MAX, + DPM_ARRAY_SOFT_MIN +}; + +/* + * Return codes for driver to SMC communication. + * Leave these #define-s, enums might not be exactly 8-bits on the microcontroller. + */ +#define PPSMC_Result_OK ((uint16_t)0x01) +#define PPSMC_Result_NoMore ((uint16_t)0x02) +#define PPSMC_Result_NotNow ((uint16_t)0x03) +#define PPSMC_Result_Failed ((uint16_t)0xFF) +#define PPSMC_Result_UnknownCmd ((uint16_t)0xFE) +#define PPSMC_Result_UnknownVT ((uint16_t)0xFD) + +#define PPSMC_isERROR(x) ((uint16_t)0x80 & (x)) + +/* + * Supported driver messages + */ +#define PPSMC_MSG_Test ((uint16_t) 0x1) +#define PPSMC_MSG_GetFeatureStatus ((uint16_t) 0x2) +#define PPSMC_MSG_EnableAllSmuFeatures ((uint16_t) 0x3) +#define PPSMC_MSG_DisableAllSmuFeatures ((uint16_t) 0x4) +#define PPSMC_MSG_OptimizeBattery ((uint16_t) 0x5) +#define PPSMC_MSG_MaximizePerf ((uint16_t) 0x6) +#define PPSMC_MSG_UVDPowerOFF ((uint16_t) 0x7) +#define PPSMC_MSG_UVDPowerON ((uint16_t) 0x8) +#define PPSMC_MSG_VCEPowerOFF ((uint16_t) 0x9) +#define PPSMC_MSG_VCEPowerON ((uint16_t) 0xA) +#define PPSMC_MSG_ACPPowerOFF ((uint16_t) 0xB) +#define PPSMC_MSG_ACPPowerON ((uint16_t) 0xC) +#define PPSMC_MSG_SDMAPowerOFF ((uint16_t) 0xD) +#define PPSMC_MSG_SDMAPowerON ((uint16_t) 0xE) +#define PPSMC_MSG_XDMAPowerOFF ((uint16_t) 0xF) +#define PPSMC_MSG_XDMAPowerON ((uint16_t) 0x10) +#define PPSMC_MSG_SetMinDeepSleepSclk ((uint16_t) 0x11) +#define PPSMC_MSG_SetSclkSoftMin ((uint16_t) 0x12) +#define PPSMC_MSG_SetSclkSoftMax ((uint16_t) 0x13) +#define PPSMC_MSG_SetSclkHardMin ((uint16_t) 0x14) +#define PPSMC_MSG_SetSclkHardMax ((uint16_t) 0x15) +#define PPSMC_MSG_SetLclkSoftMin ((uint16_t) 0x16) +#define PPSMC_MSG_SetLclkSoftMax ((uint16_t) 0x17) +#define PPSMC_MSG_SetLclkHardMin ((uint16_t) 0x18) +#define PPSMC_MSG_SetLclkHardMax ((uint16_t) 0x19) +#define PPSMC_MSG_SetUvdSoftMin ((uint16_t) 0x1A) +#define PPSMC_MSG_SetUvdSoftMax ((uint16_t) 0x1B) +#define PPSMC_MSG_SetUvdHardMin ((uint16_t) 0x1C) +#define PPSMC_MSG_SetUvdHardMax ((uint16_t) 0x1D) +#define PPSMC_MSG_SetEclkSoftMin ((uint16_t) 0x1E) +#define PPSMC_MSG_SetEclkSoftMax ((uint16_t) 0x1F) +#define PPSMC_MSG_SetEclkHardMin ((uint16_t) 0x20) +#define PPSMC_MSG_SetEclkHardMax ((uint16_t) 0x21) +#define PPSMC_MSG_SetAclkSoftMin ((uint16_t) 0x22) +#define PPSMC_MSG_SetAclkSoftMax ((uint16_t) 0x23) +#define PPSMC_MSG_SetAclkHardMin ((uint16_t) 0x24) +#define PPSMC_MSG_SetAclkHardMax ((uint16_t) 0x25) +#define PPSMC_MSG_SetNclkSoftMin ((uint16_t) 0x26) +#define PPSMC_MSG_SetNclkSoftMax ((uint16_t) 0x27) +#define PPSMC_MSG_SetNclkHardMin ((uint16_t) 0x28) +#define PPSMC_MSG_SetNclkHardMax ((uint16_t) 0x29) +#define PPSMC_MSG_SetPstateSoftMin ((uint16_t) 0x2A) +#define PPSMC_MSG_SetPstateSoftMax ((uint16_t) 0x2B) +#define PPSMC_MSG_SetPstateHardMin ((uint16_t) 0x2C) +#define PPSMC_MSG_SetPstateHardMax ((uint16_t) 0x2D) +#define PPSMC_MSG_DisableLowMemoryPstate ((uint16_t) 0x2E) +#define PPSMC_MSG_EnableLowMemoryPstate ((uint16_t) 0x2F) +#define PPSMC_MSG_UcodeAddressLow ((uint16_t) 0x30) +#define PPSMC_MSG_UcodeAddressHigh ((uint16_t) 0x31) +#define PPSMC_MSG_UcodeLoadStatus ((uint16_t) 0x32) +#define PPSMC_MSG_DriverDramAddrHi ((uint16_t) 0x33) +#define PPSMC_MSG_DriverDramAddrLo ((uint16_t) 0x34) +#define PPSMC_MSG_CondExecDramAddrHi ((uint16_t) 0x35) +#define PPSMC_MSG_CondExecDramAddrLo ((uint16_t) 0x36) +#define PPSMC_MSG_LoadUcodes ((uint16_t) 0x37) +#define PPSMC_MSG_DriverResetMode ((uint16_t) 0x38) +#define PPSMC_MSG_PowerStateNotify ((uint16_t) 0x39) +#define PPSMC_MSG_SetDisplayPhyConfig ((uint16_t) 0x3A) +#define PPSMC_MSG_GetMaxSclkLevel ((uint16_t) 0x3B) +#define PPSMC_MSG_GetMaxLclkLevel ((uint16_t) 0x3C) +#define PPSMC_MSG_GetMaxUvdLevel ((uint16_t) 0x3D) +#define PPSMC_MSG_GetMaxEclkLevel ((uint16_t) 0x3E) +#define PPSMC_MSG_GetMaxAclkLevel ((uint16_t) 0x3F) +#define PPSMC_MSG_GetMaxNclkLevel ((uint16_t) 0x40) +#define PPSMC_MSG_GetMaxPstate ((uint16_t) 0x41) +#define PPSMC_MSG_DramAddrHiVirtual ((uint16_t) 0x42) +#define PPSMC_MSG_DramAddrLoVirtual ((uint16_t) 0x43) +#define PPSMC_MSG_DramAddrHiPhysical ((uint16_t) 0x44) +#define PPSMC_MSG_DramAddrLoPhysical ((uint16_t) 0x45) +#define PPSMC_MSG_DramBufferSize ((uint16_t) 0x46) +#define PPSMC_MSG_SetMmPwrLogDramAddrHi ((uint16_t) 0x47) +#define PPSMC_MSG_SetMmPwrLogDramAddrLo ((uint16_t) 0x48) +#define PPSMC_MSG_SetClkTableAddrHi ((uint16_t) 0x49) +#define PPSMC_MSG_SetClkTableAddrLo ((uint16_t) 0x4A) +#define PPSMC_MSG_GetConservativePowerLimit ((uint16_t) 0x4B) + +#define PPSMC_MSG_InitJobs ((uint16_t) 0x252) +#define PPSMC_MSG_ExecuteJob ((uint16_t) 0x254) + +#define PPSMC_MSG_NBDPM_Enable ((uint16_t) 0x140) +#define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0x141) + +#define PPSMC_MSG_DPM_FPS_Mode ((uint16_t) 0x15d) +#define PPSMC_MSG_DPM_Activity_Mode ((uint16_t) 0x15e) + +#define PPSMC_MSG_PmStatusLogStart ((uint16_t) 0x170) +#define PPSMC_MSG_PmStatusLogSample ((uint16_t) 0x171) + +#define PPSMC_MSG_AllowLowSclkInterrupt ((uint16_t) 0x184) +#define PPSMC_MSG_MmPowerMonitorStart ((uint16_t) 0x18F) +#define PPSMC_MSG_MmPowerMonitorStop ((uint16_t) 0x190) +#define PPSMC_MSG_MmPowerMonitorRestart ((uint16_t) 0x191) + +#define PPSMC_MSG_SetClockGateMask ((uint16_t) 0x260) +#define PPSMC_MSG_SetFpsThresholdLo ((uint16_t) 0x264) +#define PPSMC_MSG_SetFpsThresholdHi ((uint16_t) 0x265) +#define PPSMC_MSG_SetLowSclkIntrThreshold ((uint16_t) 0x266) + +#define PPSMC_MSG_ClkTableXferToDram ((uint16_t) 0x267) +#define PPSMC_MSG_ClkTableXferToSmu ((uint16_t) 0x268) +#define PPSMC_MSG_GetAverageGraphicsActivity ((uint16_t) 0x269) +#define PPSMC_MSG_GetAverageGioActivity ((uint16_t) 0x26A) +#define PPSMC_MSG_SetLoggerBufferSize ((uint16_t) 0x26B) +#define PPSMC_MSG_SetLoggerAddressHigh ((uint16_t) 0x26C) +#define PPSMC_MSG_SetLoggerAddressLow ((uint16_t) 0x26D) +#define PPSMC_MSG_SetWatermarkFrequency ((uint16_t) 0x26E) +#define PPSMC_MSG_SetDisplaySizePowerParams ((uint16_t) 0x26F) + +/* REMOVE LATER*/ +#define PPSMC_MSG_DPM_ForceState ((uint16_t) 0x104) + +/* Feature Enable Masks*/ +#define NB_DPM_MASK 0x00000800 +#define VDDGFX_MASK 0x00800000 +#define VCE_DPM_MASK 0x00400000 +#define ACP_DPM_MASK 0x00040000 +#define UVD_DPM_MASK 0x00010000 +#define GFX_CU_PG_MASK 0x00004000 +#define SCLK_DPM_MASK 0x00080000 + +#if !defined(SMC_MICROCODE) +#pragma pack(pop) + +#endif + +#endif diff --git a/drivers/gpu/drm/amd/powerplay/inc/eventmanager.h b/drivers/gpu/drm/amd/powerplay/inc/eventmanager.h new file mode 100644 index 000000000000..b9d84de8a44d --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/eventmanager.h @@ -0,0 +1,109 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _EVENT_MANAGER_H_ +#define _EVENT_MANAGER_H_ + +#include "power_state.h" +#include "pp_power_source.h" +#include "hardwaremanager.h" +#include "pp_asicblocks.h" + +struct pp_eventmgr; +enum amd_pp_event; + +enum PEM_EventDataValid { + PEM_EventDataValid_RequestedStateID = 0, + PEM_EventDataValid_RequestedUILabel, + PEM_EventDataValid_NewPowerState, + PEM_EventDataValid_RequestedPowerSource, + PEM_EventDataValid_RequestedClocks, + PEM_EventDataValid_CurrentTemperature, + PEM_EventDataValid_AsicBlocks, + PEM_EventDataValid_ODParameters, + PEM_EventDataValid_PXAdapterPrefs, + PEM_EventDataValid_PXUserPrefs, + PEM_EventDataValid_PXSwitchReason, + PEM_EventDataValid_PXSwitchPhase, + PEM_EventDataValid_HdVideo, + PEM_EventDataValid_BacklightLevel, + PEM_EventDatavalid_VariBrightParams, + PEM_EventDataValid_VariBrightLevel, + PEM_EventDataValid_VariBrightImmediateChange, + PEM_EventDataValid_PercentWhite, + PEM_EventDataValid_SdVideo, + PEM_EventDataValid_HTLinkChangeReason, + PEM_EventDataValid_HWBlocks, + PEM_EventDataValid_RequestedThermalState, + PEM_EventDataValid_MvcVideo, + PEM_EventDataValid_Max +}; + +typedef enum PEM_EventDataValid PEM_EventDataValid; + +/* Number of bits in ULONG variable */ +#define PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD (sizeof(unsigned long)*8) + +/* Number of ULONG entries used by event data valid bits */ +#define PEM_MAX_NUM_EVENTDATAVALID_ULONG_ENTRIES \ + ((PEM_EventDataValid_Max + PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD - 1) / \ + PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD) + +static inline void pem_set_event_data_valid(unsigned long *fields, PEM_EventDataValid valid_field) +{ + fields[valid_field / PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD] |= + (1UL << (valid_field % PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD)); +} + +static inline void pem_unset_event_data_valid(unsigned long *fields, PEM_EventDataValid valid_field) +{ + fields[valid_field / PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD] &= + ~(1UL << (valid_field % PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD)); +} + +static inline unsigned long pem_is_event_data_valid(const unsigned long *fields, PEM_EventDataValid valid_field) +{ + return fields[valid_field / PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD] & + (1UL << (valid_field % PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD)); +} + +struct pem_event_data { + unsigned long valid_fields[100]; + unsigned long requested_state_id; + enum PP_StateUILabel requested_ui_label; + struct pp_power_state *pnew_power_state; + enum pp_power_source requested_power_source; + struct PP_Clocks requested_clocks; + bool skip_state_adjust_rules; + struct phm_asic_blocks asic_blocks; + /* to doPP_ThermalState requestedThermalState; + enum ThermalStateRequestSrc requestThermalStateSrc; + PP_Temperature currentTemperature;*/ + +}; + +int pem_handle_event(struct pp_eventmgr *eventmgr, enum amd_pp_event event, + struct pem_event_data *event_data); + +bool pem_is_hw_access_blocked(struct pp_eventmgr *eventmgr); + +#endif /* _EVENT_MANAGER_H_ */ diff --git a/drivers/gpu/drm/amd/powerplay/inc/eventmgr.h b/drivers/gpu/drm/amd/powerplay/inc/eventmgr.h new file mode 100644 index 000000000000..10437dcfd365 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/eventmgr.h @@ -0,0 +1,125 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _EVENTMGR_H_ +#define _EVENTMGR_H_ + +#include <linux/mutex.h> +#include "pp_instance.h" +#include "hardwaremanager.h" +#include "eventmanager.h" +#include "pp_feature.h" +#include "pp_power_source.h" +#include "power_state.h" + +typedef int (*pem_event_action)(struct pp_eventmgr *eventmgr, + struct pem_event_data *event_data); + +struct action_chain { + const char *description; /* action chain description for debugging purpose */ + const pem_event_action **action_chain; /* pointer to chain of event actions */ +}; + +struct pem_power_source_ui_state_info { + enum PP_StateUILabel current_ui_label; + enum PP_StateUILabel default_ui_lable; + unsigned long configurable_ui_mapping; +}; + +struct pp_clock_range { + uint32_t min_sclk_khz; + uint32_t max_sclk_khz; + + uint32_t min_mclk_khz; + uint32_t max_mclk_khz; + + uint32_t min_vclk_khz; + uint32_t max_vclk_khz; + + uint32_t min_dclk_khz; + uint32_t max_dclk_khz; + + uint32_t min_aclk_khz; + uint32_t max_aclk_khz; + + uint32_t min_eclk_khz; + uint32_t max_eclk_khz; +}; + +enum pp_state { + UNINITIALIZED, + INACTIVE, + ACTIVE +}; + +enum pp_ring_index { + PP_RING_TYPE_GFX_INDEX = 0, + PP_RING_TYPE_DMA_INDEX, + PP_RING_TYPE_DMA1_INDEX, + PP_RING_TYPE_UVD_INDEX, + PP_RING_TYPE_VCE0_INDEX, + PP_RING_TYPE_VCE1_INDEX, + PP_RING_TYPE_CP1_INDEX, + PP_RING_TYPE_CP2_INDEX, + PP_NUM_RINGS, +}; + +struct pp_request { + uint32_t flags; + uint32_t sclk; + uint32_t sclk_throttle; + uint32_t mclk; + uint32_t vclk; + uint32_t dclk; + uint32_t eclk; + uint32_t aclk; + uint32_t iclk; + uint32_t vp8clk; + uint32_t rsv[32]; +}; + +struct pp_eventmgr { + struct pp_hwmgr *hwmgr; + struct pp_smumgr *smumgr; + + struct pp_feature_info features[PP_Feature_Max]; + const struct action_chain *event_chain[AMD_PP_EVENT_MAX]; + struct phm_platform_descriptor *platform_descriptor; + struct pp_clock_range clock_range; + enum pp_power_source current_power_source; + struct pem_power_source_ui_state_info ui_state_info[PP_PowerSource_Max]; + enum pp_state states[PP_NUM_RINGS]; + struct pp_request hi_req; + struct list_head context_list; + struct mutex lock; + bool block_adjust_power_state; + bool enable_cg; + bool enable_gfx_cgpg; + int (*pp_eventmgr_init)(struct pp_eventmgr *eventmgr); + void (*pp_eventmgr_fini)(struct pp_eventmgr *eventmgr); +}; + +int eventmgr_init(struct pp_instance *handle); +int eventmgr_fini(struct pp_eventmgr *eventmgr); + +#endif /* _EVENTMGR_H_ */ diff --git a/drivers/gpu/drm/amd/powerplay/inc/fiji_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/fiji_ppsmc.h new file mode 100644 index 000000000000..7ae494569a60 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/fiji_ppsmc.h @@ -0,0 +1,412 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + + +#ifndef _FIJI_PP_SMC_H_ +#define _FIJI_PP_SMC_H_ + +#pragma pack(push, 1) + +#define PPSMC_SWSTATE_FLAG_DC 0x01 +#define PPSMC_SWSTATE_FLAG_UVD 0x02 +#define PPSMC_SWSTATE_FLAG_VCE 0x04 + +#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00 +#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01 +#define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff + +#define PPSMC_SYSTEMFLAG_GPIO_DC 0x01 +#define PPSMC_SYSTEMFLAG_STEPVDDC 0x02 +#define PPSMC_SYSTEMFLAG_GDDR5 0x04 + +#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08 + +#define PPSMC_SYSTEMFLAG_REGULATOR_HOT 0x10 +#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG 0x20 + +#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK 0x07 +#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK 0x08 + +#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE 0x00 +#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE 0x01 + +/* Defines for DPM 2.0 */ +#define PPSMC_DPM2FLAGS_TDPCLMP 0x01 +#define PPSMC_DPM2FLAGS_PWRSHFT 0x02 +#define PPSMC_DPM2FLAGS_OCP 0x04 + +/* Defines for display watermark level */ +#define PPSMC_DISPLAY_WATERMARK_LOW 0 +#define PPSMC_DISPLAY_WATERMARK_HIGH 1 + +/* In the HW performance level's state flags: */ +#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01 +#define PPSMC_STATEFLAG_POWERBOOST 0x02 +#define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT 0x04 +#define PPSMC_STATEFLAG_POWERSHIFT 0x08 +#define PPSMC_STATEFLAG_SLOW_READ_MARGIN 0x10 +#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20 +#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS 0x40 + +/* Fan control algorithm: */ +#define FDO_MODE_HARDWARE 0 +#define FDO_MODE_PIECE_WISE_LINEAR 1 + +enum FAN_CONTROL { + FAN_CONTROL_FUZZY, + FAN_CONTROL_TABLE +}; + +/* Gemini Modes*/ +#define PPSMC_GeminiModeNone 0 /*Single GPU board*/ +#define PPSMC_GeminiModeMaster 1 /*Master GPU on a Gemini board*/ +#define PPSMC_GeminiModeSlave 2 /*Slave GPU on a Gemini board*/ + + +/* Return codes for driver to SMC communication. */ +#define PPSMC_Result_OK ((uint16_t)0x01) +#define PPSMC_Result_NoMore ((uint16_t)0x02) + +#define PPSMC_Result_NotNow ((uint16_t)0x03) + +#define PPSMC_Result_Failed ((uint16_t)0xFF) +#define PPSMC_Result_UnknownCmd ((uint16_t)0xFE) +#define PPSMC_Result_UnknownVT ((uint16_t)0xFD) + +#define PPSMC_isERROR(x) ((uint16_t)0x80 & (x)) + + +#define PPSMC_MSG_Halt ((uint16_t)0x10) +#define PPSMC_MSG_Resume ((uint16_t)0x11) +#define PPSMC_MSG_EnableDPMLevel ((uint16_t)0x12) +#define PPSMC_MSG_ZeroLevelsDisabled ((uint16_t)0x13) +#define PPSMC_MSG_OneLevelsDisabled ((uint16_t)0x14) +#define PPSMC_MSG_TwoLevelsDisabled ((uint16_t)0x15) +#define PPSMC_MSG_EnableThermalInterrupt ((uint16_t)0x16) +#define PPSMC_MSG_RunningOnAC ((uint16_t)0x17) +#define PPSMC_MSG_LevelUp ((uint16_t)0x18) +#define PPSMC_MSG_LevelDown ((uint16_t)0x19) +#define PPSMC_MSG_ResetDPMCounters ((uint16_t)0x1a) +#define PPSMC_MSG_SwitchToSwState ((uint16_t)0x20) + +#define PPSMC_MSG_SwitchToSwStateLast ((uint16_t)0x3f) +#define PPSMC_MSG_SwitchToInitialState ((uint16_t)0x40) +#define PPSMC_MSG_NoForcedLevel ((uint16_t)0x41) +#define PPSMC_MSG_ForceHigh ((uint16_t)0x42) +#define PPSMC_MSG_ForceMediumOrHigh ((uint16_t)0x43) + +#define PPSMC_MSG_SwitchToMinimumPower ((uint16_t)0x51) +#define PPSMC_MSG_ResumeFromMinimumPower ((uint16_t)0x52) +#define PPSMC_MSG_EnableCac ((uint16_t)0x53) +#define PPSMC_MSG_DisableCac ((uint16_t)0x54) +#define PPSMC_DPMStateHistoryStart ((uint16_t)0x55) +#define PPSMC_DPMStateHistoryStop ((uint16_t)0x56) +#define PPSMC_CACHistoryStart ((uint16_t)0x57) +#define PPSMC_CACHistoryStop ((uint16_t)0x58) +#define PPSMC_TDPClampingActive ((uint16_t)0x59) +#define PPSMC_TDPClampingInactive ((uint16_t)0x5A) +#define PPSMC_StartFanControl ((uint16_t)0x5B) +#define PPSMC_StopFanControl ((uint16_t)0x5C) +#define PPSMC_NoDisplay ((uint16_t)0x5D) +#define PPSMC_HasDisplay ((uint16_t)0x5E) +#define PPSMC_MSG_UVDPowerOFF ((uint16_t)0x60) +#define PPSMC_MSG_UVDPowerON ((uint16_t)0x61) +#define PPSMC_MSG_EnableULV ((uint16_t)0x62) +#define PPSMC_MSG_DisableULV ((uint16_t)0x63) +#define PPSMC_MSG_EnterULV ((uint16_t)0x64) +#define PPSMC_MSG_ExitULV ((uint16_t)0x65) +#define PPSMC_PowerShiftActive ((uint16_t)0x6A) +#define PPSMC_PowerShiftInactive ((uint16_t)0x6B) +#define PPSMC_OCPActive ((uint16_t)0x6C) +#define PPSMC_OCPInactive ((uint16_t)0x6D) +#define PPSMC_CACLongTermAvgEnable ((uint16_t)0x6E) +#define PPSMC_CACLongTermAvgDisable ((uint16_t)0x6F) +#define PPSMC_MSG_InferredStateSweep_Start ((uint16_t)0x70) +#define PPSMC_MSG_InferredStateSweep_Stop ((uint16_t)0x71) +#define PPSMC_MSG_SwitchToLowestInfState ((uint16_t)0x72) +#define PPSMC_MSG_SwitchToNonInfState ((uint16_t)0x73) +#define PPSMC_MSG_AllStateSweep_Start ((uint16_t)0x74) +#define PPSMC_MSG_AllStateSweep_Stop ((uint16_t)0x75) +#define PPSMC_MSG_SwitchNextLowerInfState ((uint16_t)0x76) +#define PPSMC_MSG_SwitchNextHigherInfState ((uint16_t)0x77) +#define PPSMC_MSG_MclkRetrainingTest ((uint16_t)0x78) +#define PPSMC_MSG_ForceTDPClamping ((uint16_t)0x79) +#define PPSMC_MSG_CollectCAC_PowerCorreln ((uint16_t)0x7A) +#define PPSMC_MSG_CollectCAC_WeightCalib ((uint16_t)0x7B) +#define PPSMC_MSG_CollectCAC_SQonly ((uint16_t)0x7C) +#define PPSMC_MSG_CollectCAC_TemperaturePwr ((uint16_t)0x7D) + +#define PPSMC_MSG_ExtremitiesTest_Start ((uint16_t)0x7E) +#define PPSMC_MSG_ExtremitiesTest_Stop ((uint16_t)0x7F) +#define PPSMC_FlushDataCache ((uint16_t)0x80) +#define PPSMC_FlushInstrCache ((uint16_t)0x81) + +#define PPSMC_MSG_SetEnabledLevels ((uint16_t)0x82) +#define PPSMC_MSG_SetForcedLevels ((uint16_t)0x83) + +#define PPSMC_MSG_ResetToDefaults ((uint16_t)0x84) + +#define PPSMC_MSG_SetForcedLevelsAndJump ((uint16_t)0x85) +#define PPSMC_MSG_SetCACHistoryMode ((uint16_t)0x86) +#define PPSMC_MSG_EnableDTE ((uint16_t)0x87) +#define PPSMC_MSG_DisableDTE ((uint16_t)0x88) + +#define PPSMC_MSG_SmcSpaceSetAddress ((uint16_t)0x89) + +#define PPSMC_MSG_BREAK ((uint16_t)0xF8) + +/* Trinity Specific Messages*/ +#define PPSMC_MSG_Test ((uint16_t) 0x100) +#define PPSMC_MSG_DPM_Voltage_Pwrmgt ((uint16_t) 0x101) +#define PPSMC_MSG_DPM_Config ((uint16_t) 0x102) +#define PPSMC_MSG_PM_Controller_Start ((uint16_t) 0x103) +#define PPSMC_MSG_DPM_ForceState ((uint16_t) 0x104) +#define PPSMC_MSG_PG_PowerDownSIMD ((uint16_t) 0x105) +#define PPSMC_MSG_PG_PowerUpSIMD ((uint16_t) 0x106) +#define PPSMC_MSG_PM_Controller_Stop ((uint16_t) 0x107) +#define PPSMC_MSG_PG_SIMD_Config ((uint16_t) 0x108) +#define PPSMC_MSG_Voltage_Cntl_Enable ((uint16_t) 0x109) +#define PPSMC_MSG_Thermal_Cntl_Enable ((uint16_t) 0x10a) +#define PPSMC_MSG_Reset_Service ((uint16_t) 0x10b) +#define PPSMC_MSG_VCEPowerOFF ((uint16_t) 0x10e) +#define PPSMC_MSG_VCEPowerON ((uint16_t) 0x10f) +#define PPSMC_MSG_DPM_Disable_VCE_HS ((uint16_t) 0x110) +#define PPSMC_MSG_DPM_Enable_VCE_HS ((uint16_t) 0x111) +#define PPSMC_MSG_DPM_N_LevelsDisabled ((uint16_t) 0x112) +#define PPSMC_MSG_DCEPowerOFF ((uint16_t) 0x113) +#define PPSMC_MSG_DCEPowerON ((uint16_t) 0x114) +#define PPSMC_MSG_PCIE_DDIPowerDown ((uint16_t) 0x117) +#define PPSMC_MSG_PCIE_DDIPowerUp ((uint16_t) 0x118) +#define PPSMC_MSG_PCIE_CascadePLLPowerDown ((uint16_t) 0x119) +#define PPSMC_MSG_PCIE_CascadePLLPowerUp ((uint16_t) 0x11a) +#define PPSMC_MSG_SYSPLLPowerOff ((uint16_t) 0x11b) +#define PPSMC_MSG_SYSPLLPowerOn ((uint16_t) 0x11c) +#define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint16_t) 0x11d) +#define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint16_t) 0x11e) +#define PPSMC_MSG_DISPLAYPHYStatusNotify ((uint16_t) 0x11f) +#define PPSMC_MSG_EnableBAPM ((uint16_t) 0x120) +#define PPSMC_MSG_DisableBAPM ((uint16_t) 0x121) +#define PPSMC_MSG_Spmi_Enable ((uint16_t) 0x122) +#define PPSMC_MSG_Spmi_Timer ((uint16_t) 0x123) +#define PPSMC_MSG_LCLK_DPM_Config ((uint16_t) 0x124) +#define PPSMC_MSG_VddNB_Request ((uint16_t) 0x125) +#define PPSMC_MSG_PCIE_DDIPhyPowerDown ((uint32_t) 0x126) +#define PPSMC_MSG_PCIE_DDIPhyPowerUp ((uint32_t) 0x127) +#define PPSMC_MSG_MCLKDPM_Config ((uint16_t) 0x128) + +#define PPSMC_MSG_UVDDPM_Config ((uint16_t) 0x129) +#define PPSMC_MSG_VCEDPM_Config ((uint16_t) 0x12A) +#define PPSMC_MSG_ACPDPM_Config ((uint16_t) 0x12B) +#define PPSMC_MSG_SAMUDPM_Config ((uint16_t) 0x12C) +#define PPSMC_MSG_UVDDPM_SetEnabledMask ((uint16_t) 0x12D) +#define PPSMC_MSG_VCEDPM_SetEnabledMask ((uint16_t) 0x12E) +#define PPSMC_MSG_ACPDPM_SetEnabledMask ((uint16_t) 0x12F) +#define PPSMC_MSG_SAMUDPM_SetEnabledMask ((uint16_t) 0x130) +#define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131) +#define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132) +#define PPSMC_MSG_Thermal_Cntl_Disable ((uint16_t) 0x133) +#define PPSMC_MSG_SetTDPLimit ((uint16_t) 0x134) +#define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135) +#define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136) +#define PPSMC_MSG_ACPPowerOFF ((uint16_t) 0x137) +#define PPSMC_MSG_ACPPowerON ((uint16_t) 0x138) +#define PPSMC_MSG_SAMPowerOFF ((uint16_t) 0x139) +#define PPSMC_MSG_SAMPowerON ((uint16_t) 0x13a) +#define PPSMC_MSG_SDMAPowerOFF ((uint16_t) 0x13b) +#define PPSMC_MSG_SDMAPowerON ((uint16_t) 0x13c) +#define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d) +#define PPSMC_MSG_IOMMUPowerOFF ((uint16_t) 0x13e) +#define PPSMC_MSG_IOMMUPowerON ((uint16_t) 0x13f) +#define PPSMC_MSG_NBDPM_Enable ((uint16_t) 0x140) +#define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0x141) +#define PPSMC_MSG_NBDPM_ForceNominal ((uint16_t) 0x142) +#define PPSMC_MSG_NBDPM_ForcePerformance ((uint16_t) 0x143) +#define PPSMC_MSG_NBDPM_UnForce ((uint16_t) 0x144) +#define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0x145) +#define PPSMC_MSG_MCLKDPM_SetEnabledMask ((uint16_t) 0x146) +#define PPSMC_MSG_PCIeDPM_ForceLevel ((uint16_t) 0x147) +#define PPSMC_MSG_PCIeDPM_UnForceLevel ((uint16_t) 0x148) +#define PPSMC_MSG_EnableACDCGPIOInterrupt ((uint16_t) 0x149) +#define PPSMC_MSG_EnableVRHotGPIOInterrupt ((uint16_t) 0x14a) +#define PPSMC_MSG_SwitchToAC ((uint16_t) 0x14b) + +#define PPSMC_MSG_XDMAPowerOFF ((uint16_t) 0x14c) +#define PPSMC_MSG_XDMAPowerON ((uint16_t) 0x14d) + +#define PPSMC_MSG_DPM_Enable ((uint16_t) 0x14e) +#define PPSMC_MSG_DPM_Disable ((uint16_t) 0x14f) +#define PPSMC_MSG_MCLKDPM_Enable ((uint16_t) 0x150) +#define PPSMC_MSG_MCLKDPM_Disable ((uint16_t) 0x151) +#define PPSMC_MSG_LCLKDPM_Enable ((uint16_t) 0x152) +#define PPSMC_MSG_LCLKDPM_Disable ((uint16_t) 0x153) +#define PPSMC_MSG_UVDDPM_Enable ((uint16_t) 0x154) +#define PPSMC_MSG_UVDDPM_Disable ((uint16_t) 0x155) +#define PPSMC_MSG_SAMUDPM_Enable ((uint16_t) 0x156) +#define PPSMC_MSG_SAMUDPM_Disable ((uint16_t) 0x157) +#define PPSMC_MSG_ACPDPM_Enable ((uint16_t) 0x158) +#define PPSMC_MSG_ACPDPM_Disable ((uint16_t) 0x159) +#define PPSMC_MSG_VCEDPM_Enable ((uint16_t) 0x15a) +#define PPSMC_MSG_VCEDPM_Disable ((uint16_t) 0x15b) +#define PPSMC_MSG_LCLKDPM_SetEnabledMask ((uint16_t) 0x15c) +#define PPSMC_MSG_DPM_FPS_Mode ((uint16_t) 0x15d) +#define PPSMC_MSG_DPM_Activity_Mode ((uint16_t) 0x15e) +#define PPSMC_MSG_VddC_Request ((uint16_t) 0x15f) +#define PPSMC_MSG_MCLKDPM_GetEnabledMask ((uint16_t) 0x160) +#define PPSMC_MSG_LCLKDPM_GetEnabledMask ((uint16_t) 0x161) +#define PPSMC_MSG_SCLKDPM_GetEnabledMask ((uint16_t) 0x162) +#define PPSMC_MSG_UVDDPM_GetEnabledMask ((uint16_t) 0x163) +#define PPSMC_MSG_SAMUDPM_GetEnabledMask ((uint16_t) 0x164) +#define PPSMC_MSG_ACPDPM_GetEnabledMask ((uint16_t) 0x165) +#define PPSMC_MSG_VCEDPM_GetEnabledMask ((uint16_t) 0x166) +#define PPSMC_MSG_PCIeDPM_SetEnabledMask ((uint16_t) 0x167) +#define PPSMC_MSG_PCIeDPM_GetEnabledMask ((uint16_t) 0x168) +#define PPSMC_MSG_TDCLimitEnable ((uint16_t) 0x169) +#define PPSMC_MSG_TDCLimitDisable ((uint16_t) 0x16a) +#define PPSMC_MSG_DPM_AutoRotate_Mode ((uint16_t) 0x16b) +#define PPSMC_MSG_DISPCLK_FROM_FCH ((uint16_t) 0x16c) +#define PPSMC_MSG_DISPCLK_FROM_DFS ((uint16_t) 0x16d) +#define PPSMC_MSG_DPREFCLK_FROM_FCH ((uint16_t) 0x16e) +#define PPSMC_MSG_DPREFCLK_FROM_DFS ((uint16_t) 0x16f) +#define PPSMC_MSG_PmStatusLogStart ((uint16_t) 0x170) +#define PPSMC_MSG_PmStatusLogSample ((uint16_t) 0x171) +#define PPSMC_MSG_SCLK_AutoDPM_ON ((uint16_t) 0x172) +#define PPSMC_MSG_MCLK_AutoDPM_ON ((uint16_t) 0x173) +#define PPSMC_MSG_LCLK_AutoDPM_ON ((uint16_t) 0x174) +#define PPSMC_MSG_UVD_AutoDPM_ON ((uint16_t) 0x175) +#define PPSMC_MSG_SAMU_AutoDPM_ON ((uint16_t) 0x176) +#define PPSMC_MSG_ACP_AutoDPM_ON ((uint16_t) 0x177) +#define PPSMC_MSG_VCE_AutoDPM_ON ((uint16_t) 0x178) +#define PPSMC_MSG_PCIe_AutoDPM_ON ((uint16_t) 0x179) +#define PPSMC_MSG_MASTER_AutoDPM_ON ((uint16_t) 0x17a) +#define PPSMC_MSG_MASTER_AutoDPM_OFF ((uint16_t) 0x17b) +#define PPSMC_MSG_DYNAMICDISPPHYPOWER ((uint16_t) 0x17c) +#define PPSMC_MSG_CAC_COLLECTION_ON ((uint16_t) 0x17d) +#define PPSMC_MSG_CAC_COLLECTION_OFF ((uint16_t) 0x17e) +#define PPSMC_MSG_CAC_CORRELATION_ON ((uint16_t) 0x17f) +#define PPSMC_MSG_CAC_CORRELATION_OFF ((uint16_t) 0x180) +#define PPSMC_MSG_PM_STATUS_TO_DRAM_ON ((uint16_t) 0x181) +#define PPSMC_MSG_PM_STATUS_TO_DRAM_OFF ((uint16_t) 0x182) +#define PPSMC_MSG_ALLOW_LOWSCLK_INTERRUPT ((uint16_t) 0x184) +#define PPSMC_MSG_PkgPwrLimitEnable ((uint16_t) 0x185) +#define PPSMC_MSG_PkgPwrLimitDisable ((uint16_t) 0x186) +#define PPSMC_MSG_PkgPwrSetLimit ((uint16_t) 0x187) +#define PPSMC_MSG_OverDriveSetTargetTdp ((uint16_t) 0x188) +#define PPSMC_MSG_SCLKDPM_FreezeLevel ((uint16_t) 0x189) +#define PPSMC_MSG_SCLKDPM_UnfreezeLevel ((uint16_t) 0x18A) +#define PPSMC_MSG_MCLKDPM_FreezeLevel ((uint16_t) 0x18B) +#define PPSMC_MSG_MCLKDPM_UnfreezeLevel ((uint16_t) 0x18C) +#define PPSMC_MSG_START_DRAM_LOGGING ((uint16_t) 0x18D) +#define PPSMC_MSG_STOP_DRAM_LOGGING ((uint16_t) 0x18E) +#define PPSMC_MSG_MASTER_DeepSleep_ON ((uint16_t) 0x18F) +#define PPSMC_MSG_MASTER_DeepSleep_OFF ((uint16_t) 0x190) +#define PPSMC_MSG_Remove_DC_Clamp ((uint16_t) 0x191) +#define PPSMC_MSG_DisableACDCGPIOInterrupt ((uint16_t) 0x192) +#define PPSMC_MSG_OverrideVoltageControl_SetVddc ((uint16_t) 0x193) +#define PPSMC_MSG_OverrideVoltageControl_SetVddci ((uint16_t) 0x194) +#define PPSMC_MSG_SetVidOffset_1 ((uint16_t) 0x195) +#define PPSMC_MSG_SetVidOffset_2 ((uint16_t) 0x207) +#define PPSMC_MSG_GetVidOffset_1 ((uint16_t) 0x196) +#define PPSMC_MSG_GetVidOffset_2 ((uint16_t) 0x208) +#define PPSMC_MSG_THERMAL_OVERDRIVE_Enable ((uint16_t) 0x197) +#define PPSMC_MSG_THERMAL_OVERDRIVE_Disable ((uint16_t) 0x198) +#define PPSMC_MSG_SetTjMax ((uint16_t) 0x199) +#define PPSMC_MSG_SetFanPwmMax ((uint16_t) 0x19A) +#define PPSMC_MSG_WaitForMclkSwitchFinish ((uint16_t) 0x19B) +#define PPSMC_MSG_ENABLE_THERMAL_DPM ((uint16_t) 0x19C) +#define PPSMC_MSG_DISABLE_THERMAL_DPM ((uint16_t) 0x19D) + +#define PPSMC_MSG_API_GetSclkFrequency ((uint16_t) 0x200) +#define PPSMC_MSG_API_GetMclkFrequency ((uint16_t) 0x201) +#define PPSMC_MSG_API_GetSclkBusy ((uint16_t) 0x202) +#define PPSMC_MSG_API_GetMclkBusy ((uint16_t) 0x203) +#define PPSMC_MSG_API_GetAsicPower ((uint16_t) 0x204) +#define PPSMC_MSG_SetFanRpmMax ((uint16_t) 0x205) +#define PPSMC_MSG_SetFanSclkTarget ((uint16_t) 0x206) +#define PPSMC_MSG_SetFanMinPwm ((uint16_t) 0x209) +#define PPSMC_MSG_SetFanTemperatureTarget ((uint16_t) 0x20A) + +#define PPSMC_MSG_BACO_StartMonitor ((uint16_t) 0x240) +#define PPSMC_MSG_BACO_Cancel ((uint16_t) 0x241) +#define PPSMC_MSG_EnableVddGfx ((uint16_t) 0x242) +#define PPSMC_MSG_DisableVddGfx ((uint16_t) 0x243) +#define PPSMC_MSG_UcodeAddressLow ((uint16_t) 0x244) +#define PPSMC_MSG_UcodeAddressHigh ((uint16_t) 0x245) +#define PPSMC_MSG_UcodeLoadStatus ((uint16_t) 0x246) + +#define PPSMC_MSG_DRV_DRAM_ADDR_HI ((uint16_t) 0x250) +#define PPSMC_MSG_DRV_DRAM_ADDR_LO ((uint16_t) 0x251) +#define PPSMC_MSG_SMU_DRAM_ADDR_HI ((uint16_t) 0x252) +#define PPSMC_MSG_SMU_DRAM_ADDR_LO ((uint16_t) 0x253) +#define PPSMC_MSG_LoadUcodes ((uint16_t) 0x254) +#define PPSMC_MSG_PowerStateNotify ((uint16_t) 0x255) +#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_HI ((uint16_t) 0x256) +#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_LO ((uint16_t) 0x257) +#define PPSMC_MSG_VBIOS_DRAM_ADDR_HI ((uint16_t) 0x258) +#define PPSMC_MSG_VBIOS_DRAM_ADDR_LO ((uint16_t) 0x259) +#define PPSMC_MSG_LoadVBios ((uint16_t) 0x25A) +#define PPSMC_MSG_GetUcodeVersion ((uint16_t) 0x25B) +#define DMCUSMC_MSG_PSREntry ((uint16_t) 0x25C) +#define DMCUSMC_MSG_PSRExit ((uint16_t) 0x25D) +#define PPSMC_MSG_EnableClockGatingFeature ((uint16_t) 0x260) +#define PPSMC_MSG_DisableClockGatingFeature ((uint16_t) 0x261) +#define PPSMC_MSG_IsDeviceRunning ((uint16_t) 0x262) +#define PPSMC_MSG_LoadMetaData ((uint16_t) 0x263) +#define PPSMC_MSG_TMON_AutoCaliberate_Enable ((uint16_t) 0x264) +#define PPSMC_MSG_TMON_AutoCaliberate_Disable ((uint16_t) 0x265) +#define PPSMC_MSG_GetTelemetry1Slope ((uint16_t) 0x266) +#define PPSMC_MSG_GetTelemetry1Offset ((uint16_t) 0x267) +#define PPSMC_MSG_GetTelemetry2Slope ((uint16_t) 0x268) +#define PPSMC_MSG_GetTelemetry2Offset ((uint16_t) 0x269) +#define PPSMC_MSG_EnableAvfs ((uint16_t) 0x26A) +#define PPSMC_MSG_DisableAvfs ((uint16_t) 0x26B) +#define PPSMC_MSG_PerformBtc ((uint16_t) 0x26C) +#define PPSMC_MSG_GetHbmCode ((uint16_t) 0x26D) +#define PPSMC_MSG_GetVrVddcTemperature ((uint16_t) 0x26E) +#define PPSMC_MSG_GetVrMvddTemperature ((uint16_t) 0x26F) +#define PPSMC_MSG_GetLiquidTemperature ((uint16_t) 0x270) +#define PPSMC_MSG_GetPlxTemperature ((uint16_t) 0x271) +#define PPSMC_MSG_RequestI2CControl ((uint16_t) 0x272) +#define PPSMC_MSG_ReleaseI2CControl ((uint16_t) 0x273) +#define PPSMC_MSG_LedConfig ((uint16_t) 0x274) +#define PPSMC_MSG_SetHbmFanCode ((uint16_t) 0x275) +#define PPSMC_MSG_SetHbmThrottleCode ((uint16_t) 0x276) + +#define PPSMC_MSG_GetEnabledPsm ((uint16_t) 0x400) +#define PPSMC_MSG_AgmStartPsm ((uint16_t) 0x401) +#define PPSMC_MSG_AgmReadPsm ((uint16_t) 0x402) +#define PPSMC_MSG_AgmResetPsm ((uint16_t) 0x403) +#define PPSMC_MSG_ReadVftCell ((uint16_t) 0x404) + +/* AVFS Only - Remove Later */ +#define PPSMC_MSG_VftTableIsValid ((uint16_t) 0x666) + +/* If the SMC firmware has an event status soft register this is what the individual bits mean.*/ +#define PPSMC_EVENT_STATUS_THERMAL 0x00000001 +#define PPSMC_EVENT_STATUS_REGULATORHOT 0x00000002 +#define PPSMC_EVENT_STATUS_DC 0x00000004 + +typedef uint16_t PPSMC_Msg; + +#pragma pack(pop) + +#endif diff --git a/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h b/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h new file mode 100644 index 000000000000..0262ad35502a --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h @@ -0,0 +1,10299 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _FIJI_PWRVIRUS_H_ +#define _FIJI_PWRVIRUS_H_ + +#define mmCP_HYP_MEC1_UCODE_ADDR 0xf81a +#define mmCP_HYP_MEC1_UCODE_DATA 0xf81b +#define mmCP_HYP_MEC2_UCODE_ADDR 0xf81c +#define mmCP_HYP_MEC2_UCODE_DATA 0xf81d + +enum PWR_Command +{ + PwrCmdNull = 0, + PwrCmdWrite, + PwrCmdEnd, + PwrCmdMax +}; +typedef enum PWR_Command PWR_Command; + +struct PWR_Command_Table +{ + PWR_Command command; + ULONG data; + ULONG reg; +}; +typedef struct PWR_Command_Table PWR_Command_Table; + +#define PWR_VIRUS_TABLE_SIZE 10243 +static PWR_Command_Table PwrVirusTable[PWR_VIRUS_TABLE_SIZE] = +{ + { PwrCmdWrite, 0x100100b6, mmPCIE_INDEX }, + { PwrCmdWrite, 0x00000000, mmPCIE_DATA }, + { PwrCmdWrite, 0x100100b6, mmPCIE_INDEX }, + { PwrCmdWrite, 0x0300078c, mmPCIE_DATA }, + { PwrCmdWrite, 0x00000000, mmBIF_CLK_CTRL }, + { PwrCmdWrite, 0x00000001, mmBIF_CLK_CTRL }, + { PwrCmdWrite, 0x00000000, mmBIF_CLK_CTRL }, + { PwrCmdWrite, 0x00000003, mmBIF_FB_EN }, + { PwrCmdWrite, 0x00000000, mmBIF_FB_EN }, + { PwrCmdWrite, 0x00000001, mmBIF_DOORBELL_APER_EN }, + { PwrCmdWrite, 0x00000000, mmBIF_DOORBELL_APER_EN }, + { PwrCmdWrite, 0x014000c0, mmPCIE_INDEX }, + { PwrCmdWrite, 0x00000000, mmPCIE_DATA }, + { PwrCmdWrite, 0x014000c0, mmPCIE_INDEX }, + { PwrCmdWrite, 0x22000000, mmPCIE_DATA }, + { PwrCmdWrite, 0x014000c0, mmPCIE_INDEX }, + { PwrCmdWrite, 0x00000000, mmPCIE_DATA }, + /* + { PwrCmdWrite, 0x009f0090, mmMC_VM_FB_LOCATION }, + { PwrCmdWrite, 0x00000000, mmMC_CITF_CNTL }, + { PwrCmdWrite, 0x00000000, mmMC_VM_FB_LOCATION }, + { PwrCmdWrite, 0x009f0090, mmMC_VM_FB_LOCATION }, + { PwrCmdWrite, 0x00000000, mmMC_VM_FB_LOCATION }, + { PwrCmdWrite, 0x009f0090, mmMC_VM_FB_LOCATION }, + { PwrCmdWrite, 0x00000000, mmMC_VM_FB_OFFSET },*/ + { PwrCmdWrite, 0x00000000, mmRLC_CSIB_ADDR_LO }, + { PwrCmdWrite, 0x00000000, mmRLC_CSIB_ADDR_HI }, + { PwrCmdWrite, 0x00000000, mmRLC_CSIB_LENGTH }, + /* + { PwrCmdWrite, 0x00000000, mmMC_VM_MX_L1_TLB_CNTL }, + { PwrCmdWrite, 0x00000001, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR }, + { PwrCmdWrite, 0x00000000, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR }, + { PwrCmdWrite, 0x00000000, mmMC_VM_FB_LOCATION }, + { PwrCmdWrite, 0x009f0090, mmMC_VM_FB_LOCATION },*/ + { PwrCmdWrite, 0x00000000, mmVM_CONTEXT0_CNTL }, + { PwrCmdWrite, 0x00000000, mmVM_CONTEXT1_CNTL }, + /* + { PwrCmdWrite, 0x00000000, mmMC_VM_AGP_BASE }, + { PwrCmdWrite, 0x00000002, mmMC_VM_AGP_BOT }, + { PwrCmdWrite, 0x00000000, mmMC_VM_AGP_TOP },*/ + { PwrCmdWrite, 0x04000000, mmATC_VM_APERTURE0_LOW_ADDR }, + { PwrCmdWrite, 0x0400ff20, mmATC_VM_APERTURE0_HIGH_ADDR }, + { PwrCmdWrite, 0x00000002, mmATC_VM_APERTURE0_CNTL }, + { PwrCmdWrite, 0x0000ffff, mmATC_VM_APERTURE0_CNTL2 }, + { PwrCmdWrite, 0x00000001, mmATC_VM_APERTURE1_LOW_ADDR }, + { PwrCmdWrite, 0x00000000, mmATC_VM_APERTURE1_HIGH_ADDR }, + { PwrCmdWrite, 0x00000000, mmATC_VM_APERTURE1_CNTL }, + { PwrCmdWrite, 0x00000000, mmATC_VM_APERTURE1_CNTL2 }, + //{ PwrCmdWrite, 0x00000000, mmMC_ARB_RAMCFG }, + { PwrCmdWrite, 0x12011003, mmGB_ADDR_CONFIG }, + { PwrCmdWrite, 0x00800010, mmGB_TILE_MODE0 }, + { PwrCmdWrite, 0x00800810, mmGB_TILE_MODE1 }, + { PwrCmdWrite, 0x00801010, mmGB_TILE_MODE2 }, + { PwrCmdWrite, 0x00801810, mmGB_TILE_MODE3 }, + { PwrCmdWrite, 0x00802810, mmGB_TILE_MODE4 }, + { PwrCmdWrite, 0x00802808, mmGB_TILE_MODE5 }, + { PwrCmdWrite, 0x00802814, mmGB_TILE_MODE6 }, + { PwrCmdWrite, 0x00000000, mmGB_TILE_MODE7 }, + { PwrCmdWrite, 0x00000004, mmGB_TILE_MODE8 }, + { PwrCmdWrite, 0x02000008, mmGB_TILE_MODE9 }, + { PwrCmdWrite, 0x02000010, mmGB_TILE_MODE10 }, + { PwrCmdWrite, 0x06000014, mmGB_TILE_MODE11 }, + { PwrCmdWrite, 0x00000000, mmGB_TILE_MODE12 }, + { PwrCmdWrite, 0x02400008, mmGB_TILE_MODE13 }, + { PwrCmdWrite, 0x02400010, mmGB_TILE_MODE14 }, + { PwrCmdWrite, 0x02400030, mmGB_TILE_MODE15 }, + { PwrCmdWrite, 0x06400014, mmGB_TILE_MODE16 }, + { PwrCmdWrite, 0x00000000, mmGB_TILE_MODE17 }, + { PwrCmdWrite, 0x0040000c, mmGB_TILE_MODE18 }, + { PwrCmdWrite, 0x0100000c, mmGB_TILE_MODE19 }, + { PwrCmdWrite, 0x0100001c, mmGB_TILE_MODE20 }, + { PwrCmdWrite, 0x01000034, mmGB_TILE_MODE21 }, + { PwrCmdWrite, 0x01000024, mmGB_TILE_MODE22 }, + { PwrCmdWrite, 0x00000000, mmGB_TILE_MODE23 }, + { PwrCmdWrite, 0x0040001c, mmGB_TILE_MODE24 }, + { PwrCmdWrite, 0x01000020, mmGB_TILE_MODE25 }, + { PwrCmdWrite, 0x01000038, mmGB_TILE_MODE26 }, + { PwrCmdWrite, 0x02c00008, mmGB_TILE_MODE27 }, + { PwrCmdWrite, 0x02c00010, mmGB_TILE_MODE28 }, + { PwrCmdWrite, 0x06c00014, mmGB_TILE_MODE29 }, + { PwrCmdWrite, 0x00000000, mmGB_TILE_MODE30 }, + { PwrCmdWrite, 0x00000000, mmGB_TILE_MODE31 }, + { PwrCmdWrite, 0x000000a8, mmGB_MACROTILE_MODE0 }, + { PwrCmdWrite, 0x000000a4, mmGB_MACROTILE_MODE1 }, + { PwrCmdWrite, 0x00000090, mmGB_MACROTILE_MODE2 }, + { PwrCmdWrite, 0x00000090, mmGB_MACROTILE_MODE3 }, + { PwrCmdWrite, 0x00000090, mmGB_MACROTILE_MODE4 }, + { PwrCmdWrite, 0x00000090, mmGB_MACROTILE_MODE5 }, + { PwrCmdWrite, 0x00000090, mmGB_MACROTILE_MODE6 }, + { PwrCmdWrite, 0x00000000, mmGB_MACROTILE_MODE7 }, + { PwrCmdWrite, 0x000000ee, mmGB_MACROTILE_MODE8 }, + { PwrCmdWrite, 0x000000ea, mmGB_MACROTILE_MODE9 }, + { PwrCmdWrite, 0x000000e9, mmGB_MACROTILE_MODE10 }, + { PwrCmdWrite, 0x000000e5, mmGB_MACROTILE_MODE11 }, + { PwrCmdWrite, 0x000000e4, mmGB_MACROTILE_MODE12 }, + { PwrCmdWrite, 0x000000e0, mmGB_MACROTILE_MODE13 }, + { PwrCmdWrite, 0x00000090, mmGB_MACROTILE_MODE14 }, + { PwrCmdWrite, 0x00000000, mmGB_MACROTILE_MODE15 }, + { PwrCmdWrite, 0x00900000, mmHDP_NONSURFACE_BASE }, + { PwrCmdWrite, 0x00008000, mmHDP_NONSURFACE_INFO }, + { PwrCmdWrite, 0x3fffffff, mmHDP_NONSURFACE_SIZE }, + { PwrCmdWrite, 0x00000003, mmBIF_FB_EN }, + //{ PwrCmdWrite, 0x00000000, mmMC_VM_FB_OFFSET }, + { PwrCmdWrite, 0x00000000, mmSRBM_CNTL }, + { PwrCmdWrite, 0x00020000, mmSRBM_CNTL }, + { PwrCmdWrite, 0x80000000, mmATC_VMID0_PASID_MAPPING }, + { PwrCmdWrite, 0x00000000, mmATC_VMID_PASID_MAPPING_UPDATE_STATUS }, + { PwrCmdWrite, 0x00000000, mmRLC_CNTL }, + { PwrCmdWrite, 0x00000000, mmRLC_CNTL }, + { PwrCmdWrite, 0x00000000, mmRLC_CNTL }, + { PwrCmdWrite, 0xe0000000, mmGRBM_GFX_INDEX }, + { PwrCmdWrite, 0x00000000, mmCGTS_TCC_DISABLE }, + { PwrCmdWrite, 0x00000000, mmTCP_ADDR_CONFIG }, + { PwrCmdWrite, 0x000000ff, mmTCP_ADDR_CONFIG }, + { PwrCmdWrite, 0x76543210, mmTCP_CHAN_STEER_LO }, + { PwrCmdWrite, 0xfedcba98, mmTCP_CHAN_STEER_HI }, + { PwrCmdWrite, 0x00000000, mmDB_DEBUG2 }, + { PwrCmdWrite, 0x00000000, mmDB_DEBUG }, + { PwrCmdWrite, 0x00002b16, mmCP_QUEUE_THRESHOLDS }, + { PwrCmdWrite, 0x00006030, mmCP_MEQ_THRESHOLDS }, + { PwrCmdWrite, 0x01000104, mmSPI_CONFIG_CNTL_1 }, + { PwrCmdWrite, 0x98184020, mmPA_SC_FIFO_SIZE }, + { PwrCmdWrite, 0x00000001, mmVGT_NUM_INSTANCES }, + { PwrCmdWrite, 0x00000000, mmCP_PERFMON_CNTL }, + { PwrCmdWrite, 0x01180000, mmSQ_CONFIG }, + { PwrCmdWrite, 0x00000000, mmVGT_CACHE_INVALIDATION }, + { PwrCmdWrite, 0x00000000, mmSQ_THREAD_TRACE_BASE }, + { PwrCmdWrite, 0x0000df80, mmSQ_THREAD_TRACE_MASK }, + { PwrCmdWrite, 0x02249249, mmSQ_THREAD_TRACE_MODE }, + { PwrCmdWrite, 0x00000000, mmPA_SC_LINE_STIPPLE_STATE }, + { PwrCmdWrite, 0x00000000, mmCB_PERFCOUNTER0_SELECT1 }, + { PwrCmdWrite, 0x06000100, mmCGTT_VGT_CLK_CTRL }, + { PwrCmdWrite, 0x00000007, mmPA_CL_ENHANCE }, + { PwrCmdWrite, 0x00000001, mmPA_SC_ENHANCE }, + { PwrCmdWrite, 0x00ffffff, mmPA_SC_FORCE_EOV_MAX_CNTS }, + { PwrCmdWrite, 0x00000000, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG }, + { PwrCmdWrite, 0x00000010, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG }, + { PwrCmdWrite, 0x00000020, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG }, + { PwrCmdWrite, 0x00000030, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG }, + { PwrCmdWrite, 0x00000040, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG }, + { PwrCmdWrite, 0x00000050, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG }, + { PwrCmdWrite, 0x00000060, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG }, + { PwrCmdWrite, 0x00000070, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG }, + { PwrCmdWrite, 0x00000080, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG }, + { PwrCmdWrite, 0x00000090, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG }, + { PwrCmdWrite, 0x000000a0, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG }, + { PwrCmdWrite, 0x000000b0, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG }, + { PwrCmdWrite, 0x000000c0, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG }, + { PwrCmdWrite, 0x000000d0, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG }, + { PwrCmdWrite, 0x000000e0, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG }, + { PwrCmdWrite, 0x000000f0, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG }, + { PwrCmdWrite, 0x00000000, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmRLC_PG_CNTL }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS2 }, + { PwrCmdWrite, 0x15000000, mmCP_ME_CNTL }, + { PwrCmdWrite, 0x50000000, mmCP_MEC_CNTL }, + { PwrCmdWrite, 0x00000000, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x0000000e, mmSH_MEM_APE1_BASE }, + { PwrCmdWrite, 0x0000020d, mmSH_MEM_APE1_LIMIT }, + { PwrCmdWrite, 0x00000000, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmSH_MEM_CONFIG }, + { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG }, + { PwrCmdWrite, 0x00000000, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_RB_VMID }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmRLC_CNTL }, + { PwrCmdWrite, 0x00000000, mmRLC_CNTL }, + { PwrCmdWrite, 0x00000000, mmRLC_SRM_CNTL }, + { PwrCmdWrite, 0x00000002, mmRLC_SRM_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_ME_CNTL }, + { PwrCmdWrite, 0x15000000, mmCP_ME_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_MEC_CNTL }, + { PwrCmdWrite, 0x50000000, mmCP_MEC_CNTL }, + { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL }, + { PwrCmdWrite, 0x0840800a, mmCP_RB0_CNTL }, + { PwrCmdWrite, 0xf30fff0f, mmTCC_CTRL }, + { PwrCmdWrite, 0x00000002, mmTCC_EXE_DISABLE }, + { PwrCmdWrite, 0x000000ff, mmTCP_ADDR_CONFIG }, + { PwrCmdWrite, 0x540ff000, mmCP_CPC_IC_BASE_LO }, + { PwrCmdWrite, 0x000000b4, mmCP_CPC_IC_BASE_HI }, + { PwrCmdWrite, 0x00010000, mmCP_HYP_MEC1_UCODE_ADDR }, + { PwrCmdWrite, 0x00041b75, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000710e8, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000910dd, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000a1081, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000b016f, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000c0e3c, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000d10ec, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000e0188, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00101b5d, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00150a6c, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00170c5e, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x001d0c8c, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x001e0cfe, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00221408, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00370d7b, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00390dcb, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x003c142f, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x003f0b27, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00400e63, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00500f62, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00460fa7, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00490fa7, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x005811d4, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00680ad6, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00760b00, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00780b0c, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00790af7, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x007d1aba, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x007e1abe, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00591260, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x005a12fb, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00861ac7, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x008c1b01, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x008d1b34, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00a014b9, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00a1152e, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00a216fb, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00a41890, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00a31906, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00a50b14, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00621387, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x005c0b27, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00160a75, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA }, + { PwrCmdWrite, 0x00010000, mmCP_HYP_MEC2_UCODE_ADDR }, + { PwrCmdWrite, 0x00041b75, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000710e8, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000910dd, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000a1081, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000b016f, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000c0e3c, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000d10ec, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000e0188, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00101b5d, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00150a6c, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00170c5e, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x001d0c8c, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x001e0cfe, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00221408, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00370d7b, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00390dcb, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x003c142f, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x003f0b27, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00400e63, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00500f62, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00460fa7, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00490fa7, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x005811d4, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00680ad6, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00760b00, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00780b0c, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00790af7, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x007d1aba, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x007e1abe, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00591260, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x005a12fb, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00861ac7, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x008c1b01, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x008d1b34, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00a014b9, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00a1152e, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00a216fb, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00a41890, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00a31906, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00a50b14, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00621387, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x005c0b27, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x00160a75, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA }, + { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI }, + { PwrCmdWrite, 0x540fe800, mmCP_DFY_ADDR_LO }, + { PwrCmdWrite, 0x7e000200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e020201, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e040204, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e060205, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x54106f00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000400b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00004000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00804fac, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI }, + { PwrCmdWrite, 0x540fef00, mmCP_DFY_ADDR_LO }, + { PwrCmdWrite, 0xc0031502, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00001e00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI }, + { PwrCmdWrite, 0x540ff000, mmCP_DFY_ADDR_LO }, + { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000145, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc810000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdcc10000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdd010000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdd810000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4080061, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24ccffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3cd08000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9500fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1cd0ffcf, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d018001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4140004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x050c0019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x84c00000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000023, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000067, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000006a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000006d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000079, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000084, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000008f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000099, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800000a0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800000af, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4080007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x388c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x08880002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98800003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000002d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28080001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d808001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24cc0700, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113255, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d10ffdf, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x10cc0014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d10c017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d0d000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14cc0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000005d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14d00011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9500fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c01b10, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00e0080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00e0800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x280c0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x280c0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x280c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000069, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28080001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ca88004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800079, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc00006f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28180080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d10c017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97400001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc810000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd4c0380, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdcc0388, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55dc0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdcc038c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce0c0390, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce0c0394, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce4c0398, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56640020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce4c039c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce8c03a0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56a80020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce8c03a4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcecc03a8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcecc03ac, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf0c03b0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57300020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf0c03b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf4c03b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57740020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf4c03bc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf8c03c0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57b80020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf8c03c4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfcc03c8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57fc0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfcc03cc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c0fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05dc002f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc12009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d200a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc012009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25e01c00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12200013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25e40300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25e800c0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25ec003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e25c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eae400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de5c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xddc10000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31100006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9500007b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc1c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc1c200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4df0388, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4d7038c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d5dc01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4e30390, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4d70394, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d62001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4e70398, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4d7039c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d66401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4eb03a0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4d703a4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d6a801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4ef03a8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4d703ac, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d6ec01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4f303b0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4d703b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d73001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4f703b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4d703bc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d77401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4fb03c0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4d703c4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d7b801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4ff03c8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4d703cc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d7fc01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4d70380, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4080001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1c88001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc0e0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c0000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc01e3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3cd00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95000008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0085, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc006a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc01e3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3cd00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900fffa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4080001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1c88001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400051, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04180018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aac0027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce813265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd80002f1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04080002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x08880001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080230, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080228, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000367, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9880fff3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04080010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x08880001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd80c0309, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd80c0319, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9880fffc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00e0100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d0003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d4001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x155c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05e80180, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x202c003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc410001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000031, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900091a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05280196, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d4fe04, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800001b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000032b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000350, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000352, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000035f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000701, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000047c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000019f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc419325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d98001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd81325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4140004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0044, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27fc0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9400036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15540008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd40005b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd40005d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840006d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11540015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19a4003c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1998003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1af0007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1264001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15dc000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d65400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a38003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd5c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7df1c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800045, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411326a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc415326b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc419326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d326d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425326e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293279, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd000056, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800058, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00059, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x259c8000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce40005a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29988000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd000073, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411326f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17300019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25140fff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800003a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001b6d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4153279, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd00005f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000075, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26f00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15100010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d190004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd000035, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000035, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1af07fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04340022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4412e01, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0434001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdf030000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4412e40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c031, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43dc031, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04343000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf413267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd1c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45dc0160, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc810001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b4c0057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f4f400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55180020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x248dfffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc12e00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1af4007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33740003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26d80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1ae8003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9680000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26680001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce413277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253348, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce413348, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253348, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b400003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x958000d8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000315, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04303000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26680001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800041, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1714000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25540800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x459801b0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d77400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x199c01e2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e5e4002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3e5c0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3e540002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1334e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01334f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd413350, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813351, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd881334d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193273, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3275, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3271, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113270, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4153274, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50cc0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cdcc011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05900008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd00006a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc0006b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3272, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d594002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc12e23, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd012e24, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc12e25, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15540002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b340057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b280213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980198, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55e40020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd40000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd40000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x20cc003c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc13249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113274, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdd430000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc01e0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29dc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2d540002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x078c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07d40000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001239, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04f80000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x057c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc414000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd5c005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840007c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400069, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c018a6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4412e22, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800007c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c018a2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd4c005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9680fffc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800002e3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd0c002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9680fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800002e3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000069, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013273, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013275, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9540188f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc013cfff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd0c009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc13249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9680000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x38d00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04cc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdcc30000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c01882, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000304, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840002f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0016, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0016, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x49980198, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55e40020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x459801a0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000329, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc812e00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16ec001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1998003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00031, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce00000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a18003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d43c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4093249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1888003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc419324c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x259c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1598001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c0000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14d80011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24dc00ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31e00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31dc0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580fff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95801827, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840002f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14dc0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c0fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800006d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32200002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a0000ad, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04080000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27fc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c0015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1af4003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9740004d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4080060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ca88005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24880001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f4b4009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97400046, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313274, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d33400c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97400009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28240100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a4004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400079, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1eecffdd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf013273, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf013275, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800003c3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc429326f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aa80030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28240001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a8004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800035, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3272, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x10cc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19e80042, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc0006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e8e800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de9c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3271, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293270, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50cc0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ce8c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd30011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11e80007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd300001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b30003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4240059, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1660001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e320009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0328000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e72400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0430000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02ac000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d310002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa87600, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd0c011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd0c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280222, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4280058, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x22ec003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013273, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce813275, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800007b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8380018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57b00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04343108, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc429325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c3000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13740008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2374007e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32a80003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18ec0057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e40213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc0199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cecc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ce4c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800003e7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980104, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x49980104, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800003f2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000448, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c0016, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c0016, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c0015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf813279, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf41326e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01326d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c0000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x254c0700, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x10cc0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a641fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0726, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a640200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1237b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8813260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4240033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4280034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xde430000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce40000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c01755, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9680000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce80000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xde830000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce80000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c0174c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4393265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bb80040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf813265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100044, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19180024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x551c003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000043d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00c8000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840006c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28200000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000043f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x282000f0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113255, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000053, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x195c00e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2555fff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0360001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32200002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc5e124dc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef6c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e624001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80fff9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2555fff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3255, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353259, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980158, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x49980158, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980170, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16200010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc429324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd000008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d43c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x195400e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1154000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18dc00e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05e80488, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d0006c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18f807f0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e40077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18ec0199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000048e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000494, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800004de, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000685, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000686, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800006ac, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1ccc001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1264000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d79400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e7a400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52a8001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15180001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d69401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x202c007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95000008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aec0028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d325c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800004cc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc419324e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26e8003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aec003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12f4000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d324d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d75401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d290004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f8f4001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f52800f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50e00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800004d1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d0dc002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x6665fc00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e5e401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da1c011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd140000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a644000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f534002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x6665fc00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e76401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800004d7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aec003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3257, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213259, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12f4000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d75401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52200002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da1c011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd140000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a644000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x202c003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x259c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15980004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05e804e3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800004e7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800004f0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000505, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc435325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x277401ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf41325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9640fff4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17e00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd84131db, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26edf000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8413260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05a80507, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000050c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000528, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000057d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800005c2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800005f3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c004d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00063b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801326f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000624, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1be00fe4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce413260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000066, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400068, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c004d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400067, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00063b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801326f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000624, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c0060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ed6c005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113271, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4153270, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193272, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3273, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d51401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113274, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213275, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253276, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400061, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2730000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7db1800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05dc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00062, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd000063, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000064, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400065, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b700057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b680213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x46ec0188, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17e00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26e01000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9c131fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x191807e4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x192007ec, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x69dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de20014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x561c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013344, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc13345, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425334d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc419334e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d334f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213350, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253351, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x46ec01b0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800068, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2010007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1910003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9500fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd00001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc410000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd00001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc410000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2010003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x191807e4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9540000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013344, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013345, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180050, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0052, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280042, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813273, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc13275, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000068, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400067, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07d40000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00124f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x057c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x46ec0190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4153249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2154003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bd800e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd9c005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd80005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420004d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e1e000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd413249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01326f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28340001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f598004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800035, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1be800e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce80005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801327a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800005f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000075, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800007f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424004c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41326e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28240100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a4004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400079, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc435325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x277401ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41325e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf41325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xda000068, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9540002d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425334d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc419334e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d334f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213350, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253351, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x46ec01b0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1be000e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0360001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc63124dc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef6c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80fff9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fc14001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x194c1c03, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc0003b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c002d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000697, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420004a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x194c00e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc0005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c004c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431326d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27301fff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce00005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cf0c00d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25100007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31100005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900008e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000075e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x202c007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a9feff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d30b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce813265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00ac006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00e0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28880700, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c0006de, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14cc0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x30d4000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x10cc0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41530b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19980028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800006c8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8380023, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fa38011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x282c2002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd3800025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x202400d0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28240006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d8003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840003c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd81a2a4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c0000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420004a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x194c00e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc0005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c004c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431326d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27301fff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce00005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cf0c00d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000712, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x194c1c03, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc0003b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c002d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05e80714, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000071c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000720, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000747, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000071d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800007c4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000732, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000745, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000744, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000072e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c0000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a64008c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce413265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b301fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000075e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c0fff1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000723, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41f02f1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000743, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8813247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd000008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c0ffde, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000072e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd84131db, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8413260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c3000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc8000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c004a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x195800e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd80005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418004c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd81326e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc0005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dd7fff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc13265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51e00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e1a001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x46200200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04283247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1af80057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1af40213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f6f400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2000025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc6990000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x329c325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x329c3269, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x329c3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc01defff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d8009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000078a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25980000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fff2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03e7ff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f3f0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1f30001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf013249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03e4000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013255, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d30b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bf0003a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000b80, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x203c003a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300700, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf0130b7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x46200008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2000025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4080007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x259c0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31dc0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c3000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18ec0057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e40213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc0199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cecc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ce4c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000448, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31980002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19580066, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0120001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11980003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da18001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1c200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d24db, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd0c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd9c005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40fff8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580137b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00ee000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1c200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113269, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19080070, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x190c00e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2510003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2518000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05a80809, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000080e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000080f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000898, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000946, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800009e1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04a80811, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000815, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000834, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3045, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1c091, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31300021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd84002f1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293059, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56a8001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000241, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000084a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43130b6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02f0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec130b6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4252087, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5668001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a80005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd80130b6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000084a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431ecaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02e0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec130b6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd80130b6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31300021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd84002f1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293059, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56a8001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00021d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c0005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001a41, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43b02f1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec80278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56f00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf080280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8813247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd80802e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31100011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x950001fa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02e0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aec0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc01c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0180001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11a40006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de6000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x10e40008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e2e000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d10ffdf, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2110003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013255, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d10ff9e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0245301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801325f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0121fff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29108eff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0127ff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0131fff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801326d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801326e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013279, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x08cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0100010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd2400c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0180003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd1c002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04a8089a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000089e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800008fa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000945, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000945, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31300022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x459801e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2738000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8300011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8340011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9740002f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13b80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc79d3300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc7a13301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8393300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0260001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce793301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x964012a4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c028009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800008d2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce40001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x242c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06ec0400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02620c0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41c078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce81c080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01c082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57240020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41c083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0260400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eae8001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f2f0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800008d2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdf93300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce393301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000903, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31240022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ec30011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32f80000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x67180001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0bfc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd981325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000915, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9c1325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0fff6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f818001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001606, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d838001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3259, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16240014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a2801f0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e2a000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e5e400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013259, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00075e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4af0228, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x66d80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1330000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13f40014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07fc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33e80010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9680ffec, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04a80948, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000094c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000099b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800009e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800009e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x459801e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2738000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8300011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8340011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9740002c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13b80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc79d3300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc7a13301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8393300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0260001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce793301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x964011fe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c028009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000978, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce40001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x242c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06ec0400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0260010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41c078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01c080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57240020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41c081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce81c082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0260800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eae8001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f2f0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000978, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdf93300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce393301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dda801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e838011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001802, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x469c0390, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4240011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4280011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c0014df, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31280014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce8802ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800062, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31280034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04a809e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800009ec, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a45, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a59, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a59, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b30258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4a70250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x53300020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e72401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x66740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97400041, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04383000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4393267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b38007e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33b40003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b400003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x4598001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9740002f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf4002eb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf4002ec, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf4002ed, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf4002ee, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04382000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001715, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04382000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0ffbc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431ecaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a55, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43130b6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x233c0032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc130b6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf0130b6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49302ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04180001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5198001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193269, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2598000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd80002f1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013268, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x53b8001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7db9801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000a5e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c01106, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc412e01, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc412e02, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc412e03, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c010fd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50640020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ce4c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc80c0072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x58e801fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18dc01e2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e5e4002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3e5c0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3e540002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000aa2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9540000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x44cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55900020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4140011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000aa2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x44cc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd812e01, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd012e02, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd412e03, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc410001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4140028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95000005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1e64001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14d00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ab1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a0010ac, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd880003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c0003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc010ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d403f7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d0cc009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41b0367, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d958004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d85800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc1e0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d001fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05280adc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000af1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000adf, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ae7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000ace, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd8d2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d803f7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc010ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d0cc009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11940014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29544001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29544003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000af4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd44d2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd44dc000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d0003c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95000006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000ace, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd8d2c00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000b0a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd44d2c00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28148004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d800ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4593240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c0105e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x199c0034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313255, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef3400c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14e80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a8000af, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c01043, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18a01fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3620005c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a00000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2464003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc6290ce7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16ac001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ac003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ee6c00d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a00fff8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000367, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9640102e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x199c0037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19a00035, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c0005d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16f8001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9780000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc035f0ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e764009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19b401f8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13740008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e76400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce413248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x199c0034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1ae4003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000b7c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aec003c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19a4003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12ec001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02e4000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc01e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13fc0018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dbd800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d98ff15, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x592c00fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd80000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12e00016, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x592c007e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12e00015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11a0000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1264001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1620000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12e4001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5924007e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19a4003c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013257, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd413258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc429325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00fdb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9780f5ca, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001b6d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d324e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431324d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07740003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x269c003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e5e4004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f67000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f674002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x53740002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef6c011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1ab42010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1ab8c006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16a8000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a80800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b740000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf40001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000bec, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000b47, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b34060b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04340100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ec00ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03a8004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef6c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f3b000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc410001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc415325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18580037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x262001ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d15400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d54001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a80004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14f00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd280200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd680208, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcda80210, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b400014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a80004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc6930200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc6970208, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc69b0210, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd900003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd940003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9000040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9400040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14fc0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24f800ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33b80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d83c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4093249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1888003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc419324c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x259c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1598001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00016, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14d80011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24e000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x321c0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580ffee, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c30, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9480000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800f29, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800f23, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800f1a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9600f502, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c0f500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000f05, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1f30001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16e4001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9640f4f4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc434000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33740002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b40f4f1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aec003c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12ec001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02e4000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12780001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bb80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00ac005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00e0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc8000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28884900, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ff3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400ee1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c40a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c40c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c40d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d0007f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15580010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x255400ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01c411, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd81c40f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41c40e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c410, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e80033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18ec0034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c414, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c415, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd81c413, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41c412, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18dc0032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c030011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c038011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431c417, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc435c416, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439c419, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43dc418, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf413261, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf013262, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13263, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf813264, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18dc0030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d77000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000cd6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51b80020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x53300020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f97801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f37001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f3b000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000cd6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ca7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18dc0031, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc435c40b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9740fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4280032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f8cc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000cf4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc032800b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d42011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24cc007f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd4c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800e6c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x596001fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12200009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ce0c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x505c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50600020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc0001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd140001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8240010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e5e800c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x122c0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000d1f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8240010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x566c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce413261, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13262, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b740008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x566c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce413261, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec13262, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f8cc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000d57, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0328009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04143000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd413267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e51001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4153267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d2d0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19640057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19580213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19600199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da6400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1000025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04142000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd413267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4153267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d40030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d80034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05280d83, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c424001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000d8a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000d95, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000db1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000d95, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000dbc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11540010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e010001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d75400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4610000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580f3d8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000016, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x526c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e80058, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e2ec01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c00072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5ae0073a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ea2800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580f3c6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc3a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80fffb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980fff5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16200002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01c405, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd441c406, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580f3b1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439c409, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11540010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29540002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4610000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580f3a5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00da7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5aac007e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12d80017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56a00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e82400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e58c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19d4003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28182002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc011000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c908009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x20880188, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x54ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x20240090, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28240004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000016, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf80003a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd901a2a4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1624001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd841325f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000039, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc429325f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ac0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ac0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b301ff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9680000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400039, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c0001a2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1910003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2220003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e2a000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000039, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18dc003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d40030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18fc0034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24e8000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80e71, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000edd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000e91, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000e91, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ea1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000eaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000e7c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000e7f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000e7f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000e87, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000e8f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9e001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a200008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213262, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253261, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a200008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213264, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253263, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e82005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51e00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da1801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1800072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8180072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x59a001fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12200009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ea2800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15980002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd81c400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421c401, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400041, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425c401, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac2580, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac260c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac0800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac0828, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac2440, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac2390, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac0093, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac31dc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac31e6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ede, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39ac7c06, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db07c00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39acc337, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db0c330, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39acc335, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db0c336, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39ac9002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db09001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39ac9012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db09011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39acec70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db0ec6f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc5a10000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc5a50000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05280eea, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ef1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000efe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f11, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f2e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000efe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f1f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0f26f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e80058, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7daec01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c00072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5af8073a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eba800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0f25c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15980002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd81c405, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01c406, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41c406, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0f24e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439c409, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40f247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0f240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac2580, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac260c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac0800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac0828, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac2440, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac2390, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac0093, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac31dc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31ac31e6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ef2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39ac7c06, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db07c00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39acc337, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db0c330, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39acc335, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db0c336, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39acec70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db0ec6f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39ac9002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db09002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39ac9012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3db09012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ef1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc434000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b740008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b780001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c1325e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf80001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c034001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c038001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e0007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32240003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32240000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01c080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41c081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f88, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51640020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e52401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2400072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce81c080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56ac0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26f0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01c081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1af000fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1334000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24e02000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f63400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e00074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32240003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32240000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd81c082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc1c083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000f9d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51e40020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e5a401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2400072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce81c082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56ac0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26f0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01c083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1af000fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13380016, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e00039, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12200019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e0007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1220001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e00074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12200014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf81c078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc1c084, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18dc003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31140005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31140006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05280fb7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28140002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000fc2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000fd1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ff2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ff2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e80039, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52a8003b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d69401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd140004b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc414000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04180001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d958004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800035, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9500000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x159c0011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x259800ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31a00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31a40001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e25800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c0fff5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580fff4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000fef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411326f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d100010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01326f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc011000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33b40003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97400003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0340008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000ffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c908009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x282c2002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x208801a8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x20240030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28340000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x507c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d7d401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x557c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28342002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000102f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1cccfe08, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00b33, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840003c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da2400f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da28002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e1ac002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d2ac002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3ef40010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b40f11d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf81325e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xde410000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdcc10000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdd010000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdd810000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xddc10000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xde010000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c024001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8100086, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5510003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001075, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4140025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d15800f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d15c002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d520002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cde0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3e20001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c0030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1325e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001071, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00b01, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc200000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc1c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc240000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc240000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc40003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4080029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18a400e5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12500009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x248c0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x200c006d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd0c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x200c0228, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd0c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc410002b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18881fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d4072c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc00d1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd4c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3094000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x38d80000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x311c0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x30940007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1620001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000023, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800010c4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00041, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418002c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x259c007f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19a00030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc0001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400023, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800010cb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x199c0fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc0001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400023, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800010cb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000023, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000aac, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc434002e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2020002c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17780001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07a810d8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000104c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc400040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x200c007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28240007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xde430000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x192400fd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06681110, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19180070, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19100078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18f40058, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5978073a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001117, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001118, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000112d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001130, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001133, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24ec0f00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32ec0600, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24ec0f00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32ec0600, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc81c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00116b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02a0200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e8e8009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x22a8003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x22a80074, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2774001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13740014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eb6800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25ecffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55700020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15f40010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13740002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x275c001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15dc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39e00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dc1c01e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05e40008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dc2001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05e40008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e62000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da58001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001165, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dc2001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e1a0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e0d000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95000007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e02401e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06640008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05d80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dc2401e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da58001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05e00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da2000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9600ffe6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00116b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce00001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce81c078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1c080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41c082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01c083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x22640435, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0528117e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x312c0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001185, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001182, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001182, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03a0400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1198001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d81c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc130b7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf8130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0049, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19a000e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29a80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de2c00c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421325e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26200010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc415326d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc420007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce40003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800011a3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d654001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41326d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c020001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4240081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4140025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800011b6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253279, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc415326d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2730003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3b380006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3f38000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800011b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800011b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0430000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb10004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e57000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e578002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d67c002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0be40001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d3a4002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x202c002c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421325e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26200010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3e640010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce81325e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc434002e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17780001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07a811cf, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00feb8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x954009a7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1c07c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c07d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c08c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c079, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01c07e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18f0012f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18f40612, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc00c1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cf7400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x39600004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0140004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11600001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18fc003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400041, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800011ee, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a6c003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800011e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428002c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ac007f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1ab00030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aac0fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001205, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11600001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0fffa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27fc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd841c07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc0078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ffbc00c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03a2800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801c07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03ae000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf81c200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03a0800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03ae000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf81c200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03a4000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x30d00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000052, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9640090f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1514001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19180038, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x30dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d324e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431324d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1ab0c006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000127f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d3258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313257, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353259, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc429325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1ab0c012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a0003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e624004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f67800f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04340000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x53740002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef6c011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1ab42010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16a8000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a80800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b740000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf40001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1514001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c0012e1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x964008d7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9800036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300677, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800012aa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b34060b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04340100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ec00ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03a8002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef6c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7edec00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f3b000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4140032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc410001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1858003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99800007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d0cc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d0006c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d407f0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2598003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d190004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d5d4001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d52000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800012d8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d514002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800012d8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193259, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d958001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd5c002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813259, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc1325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1ccc001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14f00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b40000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd980003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9c0003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9800040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd9c00040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33f80003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800051, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b74003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b4c00f8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50700020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04e81324, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50600020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x30e40004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d71401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x596401fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b74008d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e76400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a640000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000132c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000133b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001344, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42530b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a68003a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2024003a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25980700, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11980014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d19000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce4130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce40001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4240011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de6800f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffea, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce40001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8240011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de6800f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffe0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28182002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x20240030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b4c00f8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28340000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x507c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x30e40004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d7d401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x557c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28342002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf81a2a4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c007eb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d0d001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x591c01fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45140210, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x595801fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11980009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29dc0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc0001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1624001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400069, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a307fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x23304076, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc00e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x10cc0015, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x4514020c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a2001e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12200014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a204001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a64003c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1264001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15dc000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dcdc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e5dc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04340022, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4412e01, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0434001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdf030000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4412e40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c030, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41c031, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x248dfffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc12e00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc812e00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45140248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013257, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0434000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdb000024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45540008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013259, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0337fff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f220009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55300020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d01c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c01d0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06ec0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f01c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8240072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd240001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19682011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5a6c01fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12ec0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eeac00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aec0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99800007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdf830000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfa0000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4380007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17b80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d40038, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9540073d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18c80066, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x30880001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd910000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x4220000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24e80007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24ec0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc5310000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001465, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18f02011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5aec01fc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12ec0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aec0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a8146a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f1f0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f1b400f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001478, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f1b400e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001478, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f1b400c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f1b400d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f1b400f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f1b400e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f334002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97400014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000147b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b400012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e024001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000144a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fbfc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94800007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd910000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800014a9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0328007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03a0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf8130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd9c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45dc0390, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b380057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b340213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c424001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c428001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c42c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c430001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a0800fd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x109c000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd9c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc13265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce080228, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9880000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce480250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce880258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080230, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0ec75, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26180001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce480250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce880258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52a80020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x66580001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc80260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec80288, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf080290, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec80298, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf0802a0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf4802a8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc802b0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd80802b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x178c000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27b8003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cf8c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf8802c0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc802c8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf8802d0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf8802d8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25b8ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f0238, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24cc000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd2800c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc5230309, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e3a400c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001539, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd08034b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd880353, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49b0353, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f0228, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd14005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000154f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd080238, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd08034b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x08cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3d200008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd900309, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8100319, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04340801, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd910ce7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4190ce6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d918005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d918004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd810ce6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdd1054f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000156e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x090c0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdcd050e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x110c0014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc4001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41230a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41230b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41230c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc41230d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc480329, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc48032a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc4802e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000055, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f02e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d8003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09940001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x44100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580002c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x69100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000157f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4970290, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49b0288, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49b02a0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49f0298, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x041c0040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dcdc002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d924019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d26400c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0fffa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001579, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d010021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d914019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd480298, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd8802a0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x10d40010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12180016, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc51f0309, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d95800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d62000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd9c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdd00309, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce113320, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f02e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49b02b0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18dc01e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd9400e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c0001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800015aa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f0238, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4a302b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12240004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e5e400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4ab02a8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce4c0319, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d9d8002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ea14005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800015bc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e624004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d25000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0fff4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd0d3330, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce0802b8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd8802b0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4ab02e0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aa807f0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f02d0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49702d8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49b02c8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49f02c0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96800028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d4e000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9600000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d964002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d694001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cde4002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de94001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd64002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d694001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800015cd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d698002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd4802d8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x129c0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc50f0319, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11a0000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11140001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e1e000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1198000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd953300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e0e000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a8000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce953301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce100319, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b70280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73800a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x536c0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9780eb68, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001609, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x30b40000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b400011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b70258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b30250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x53780020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb3801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7faf8019, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x67b40001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x57b80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4bb0260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fab8001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf880260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x66f40001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97400005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4353247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f7f4009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b40fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fff7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x269c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a00018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12200003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a00060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x269c0018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a00007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a40060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11dc0006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12200006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de5c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b70228, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f514005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001644, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b30248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd080240, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f130005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001688, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04340801, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f130004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01051e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42d051f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ed2c005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26ec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96c0fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01051f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000055, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc5170309, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x195c07f0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x196007f6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04340000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04340001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x53740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x6b740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001665, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4a702a0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4ab0298, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f634014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e76401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56680020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8113320, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce480298, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce8802a0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc5170319, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b702b0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x255c000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f5f4001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8113330, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf4802b0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11340001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x195c07e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x196007ee, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8353300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e1e4001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8353301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce4802d0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8100309, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8100319, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc48f0250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd4c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x64d80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x54cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580005c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dc24001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd2000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3255, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7df5c00c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25980040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800016f1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a7003e6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a7000e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a700064, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800016df, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800016f2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940ff9c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd80802e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18fc0064, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00042, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dd9801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x45980400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b380057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b340213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14f4001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x192807fa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4bf0258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4a70250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x53fc0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e7e401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x667c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eebc00c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fff8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x43300007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x53300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7db30011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd3000025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc03ec005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bfca200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x192807fa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d1d0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2110007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x203c003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c0017f5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18fc01e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00185b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b40ffd5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0ea24, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14d4001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d52400e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49f0258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4a30250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400017, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d534002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4af0270, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dae4005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32e0001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec80270, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000174f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00178a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b40fff3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4ab0268, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7daa4005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32a0001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001765, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d1d0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2110007d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8013256, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c0017f2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4113248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b3034b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f13000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf013248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001855, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32a4001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd080260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce880268, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940ffc0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ec28001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32e0001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9640005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253255, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431324f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e72400c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a80040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9680fff7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aa4003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400049, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aa400e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32680003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a800046, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9640000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4293260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1aa400e4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32640004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800017e2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc027ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2e6400ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a4009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a800ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4240009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19e403e6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26680003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12a80004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19e400e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19e40064, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16a40005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06640003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce412082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a640003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800017d0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16a40005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce412082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ea64002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4292083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ea68005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a80ffdf, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26a400ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40ffca, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2024007b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800017e3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4a70280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4ab0278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7eae8014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56680020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce480278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce880280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec80270, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800017fe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800017fe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43b02eb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42302ec, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf813245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fa3801a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x47b8020c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x15e00008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1220000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2a206032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x513c001e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e3e001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000180f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b3c0077, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ff3000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd200000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd3800002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dc30001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc1e0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04380032, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf80000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc413248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3269, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27fc000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33fc0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4413249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0bfc0021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd441326a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x173c0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300303, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f3f0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ff3c004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13084, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001842, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4413249, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x23fc003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc1326d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0bb80026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdf830000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd441326e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4393265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1fb8ffc6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xddc30000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf813265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc0000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001852, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc0000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001878, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49f02e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c00018, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c0012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001878, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41f02ed, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42302ee, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e2a0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013084, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28340001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x313c0bcc, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x393c051f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3d3c050e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x393c0560, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3d3c054f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x393c1538, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3d3c1537, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b740800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e8007c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c42c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a8189a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800018c5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800018f2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d0007e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09240002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc42130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a24002c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2020002c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1198001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x10cc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14cc0004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7cd8c00a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc130b7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce0130b5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x5978073a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bb80002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf800024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9600e8a8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9640e8a5, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800018a9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc55b0309, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3d5c0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09780001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dad800c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0ffd2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580fff9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x442c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7df9c00c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c13260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd901325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940fff1, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x66d80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26240007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940fff7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc023007f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19e4003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7de1c009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dee000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96000007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c13260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd901325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x261c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99c0fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940fff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18e00064, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06281911, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14f4001d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24cc0003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001915, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x800019af, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001a2b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc48032b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc480333, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc48033b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc480343, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98800011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x46640400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04203000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b3c0057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b200213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e3e000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04180000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f438001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00068, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213254, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a1c003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00065, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e1e0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97800062, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x43bc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fcbc001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc7df032b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e1fc00c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0101, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c0102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001994, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001982, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00ffcb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc1325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001995, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc1325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98800009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x41bc0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x53fc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e7fc011, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd3c00025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0012, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x653c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dbd8001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940ff8f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc55b0309, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x3d5c0010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x05540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d91800c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580fff8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09780001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9580005d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200101, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400058, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dc24001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7df9c00c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95c00053, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e41c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a70003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a7000e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33240003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a400046, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1a7000e4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001a21, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f270009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x266400ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27240003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06640002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16700005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001a0f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x16700005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e730002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4252083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e724005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a40ffdf, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x267000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001a22, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940ff9f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001a31, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213246, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4253245, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e26401a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x46640400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04203000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce013267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4213267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b180057, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b200213, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e1a000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce000024, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800060, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4193247, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200101, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x30f00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95800056, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001aa2, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001a90, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf00325b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001aa3, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49b02e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99800005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd2400025, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x4664001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940ff9c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc49b02e9, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99800008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc430000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2b300008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf000013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x244c00ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc4c0200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc44f0200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc410000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc414000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d158010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x059cc000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccdd0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0037, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000049, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c003a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9500e69a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d0003b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d40021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd840004a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c003c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x14cc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c00028, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000033, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc438000b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x27fc0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd841c07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1bfc0078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7ffbc00c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x99000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0120840, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x282c0040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001ae8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0121841, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x282c001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01c07c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04200004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9ac0fffb, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801c07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8000034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940e66b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800004a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0036, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9900fffe, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18cc0021, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc00047, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc000046, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0039, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c003d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24d003ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d47fea, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x18d87ff4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd00004c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd40004e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd80004d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41c405, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01c406, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c406, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c406, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x295c0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8c1325e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcdc0001a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11980002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x4110000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0160800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7d15000a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0164010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41c078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c080, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd81c082, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc01c083, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01c084, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400048, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c003b, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801c40a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd901c40d, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801c410, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801c40e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd801c40f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc40c0040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9940ffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04140096, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1c400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc411c401, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9500fffa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424003e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04d00001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x11100002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd01c40c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0180034, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd81c411, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd841c414, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0a540001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcd41c412, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x2468000f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc419c416, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x41980003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc41c003f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7dda0001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x12200002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x10cc0002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xccc1c40c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd901c411, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce41c412, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xce292e40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc412e01, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc412e02, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc412e03, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc120000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x31144000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xcc3c000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x33f80003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x9780e601, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x188cfff0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x04e40002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400006, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x96400003, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80001b74, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI }, + { PwrCmdWrite, 0x54106500, mmCP_DFY_ADDR_LO }, + { PwrCmdWrite, 0x7e000200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e020204, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc00a0505, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xbf8c007f, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb8900904, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb8911a04, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb8920304, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb8930b44, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x921c0d0c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x921c1c13, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x921d0c12, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x811c1d1c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x811c111c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x921cff1c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000400, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x921dff10, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000100, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x81181d1c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e040218, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI }, + { PwrCmdWrite, 0x54106900, mmCP_DFY_ADDR_LO }, + { PwrCmdWrite, 0x7e080200, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x7e100204, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xbefc00ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00010000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x24200087, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x262200ff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000001f0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x20222282, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x28182111, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI }, + { PwrCmdWrite, 0x54116f00, mmCP_DFY_ADDR_LO }, + { PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb4540fe8, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000041, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000000c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x54116f00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb454105e, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000c0, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x54117300, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb4541065, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000500, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000001c, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x54117700, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb4541069, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000444, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x0000008a, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x54117b00, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 }, + { PwrCmdWrite, 0x00000000, mmCP_MEC_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_MEC_CNTL }, + { PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x54116f00, mmCP_MQD_BASE_ADDR }, + { PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI }, + { PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI }, + { PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR }, + { PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI }, + { PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE }, + { PwrCmdWrite, 0x00010000, mmCP_HQD_VMID }, + { PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL }, + { PwrCmdWrite, 0x00000005, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x54117300, mmCP_MQD_BASE_ADDR }, + { PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI }, + { PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI }, + { PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR }, + { PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI }, + { PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE }, + { PwrCmdWrite, 0x00010000, mmCP_HQD_VMID }, + { PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL }, + { PwrCmdWrite, 0x00000006, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x54117700, mmCP_MQD_BASE_ADDR }, + { PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI }, + { PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI }, + { PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR }, + { PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI }, + { PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE }, + { PwrCmdWrite, 0x00010000, mmCP_HQD_VMID }, + { PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL }, + { PwrCmdWrite, 0x00000007, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x54117b00, mmCP_MQD_BASE_ADDR }, + { PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI }, + { PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI }, + { PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR }, + { PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI }, + { PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE }, + { PwrCmdWrite, 0x00010000, mmCP_HQD_VMID }, + { PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL }, + { PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000104, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000204, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000304, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000404, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000504, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000604, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000704, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000005, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000105, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000205, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000305, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000405, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000505, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000605, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000705, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000006, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000106, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000206, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000306, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000406, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000506, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000606, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000706, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000007, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000107, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000207, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000307, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000407, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000507, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000607, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000707, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000008, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000108, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000208, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000308, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000408, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000508, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000608, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000708, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000009, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000109, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000209, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000309, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000409, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000509, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000609, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000709, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR }, + { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR }, + { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE }, + { PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL }, + { PwrCmdWrite, 0x01010101, mmCP_PQ_WPTR_POLL_CNTL1 }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdWrite, 0x00000000, mmGRBM_STATUS }, + { PwrCmdEnd, 0x00000000, 0x00000000 }, +}; + +#endif diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h new file mode 100644 index 000000000000..91795efe1336 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h @@ -0,0 +1,385 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _HARDWARE_MANAGER_H_ +#define _HARDWARE_MANAGER_H_ + + + +struct pp_hwmgr; +struct pp_hw_power_state; +struct pp_power_state; +enum amd_dpm_forced_level; +struct PP_TemperatureRange; + +struct phm_fan_speed_info { + uint32_t min_percent; + uint32_t max_percent; + uint32_t min_rpm; + uint32_t max_rpm; + bool supports_percent_read; + bool supports_percent_write; + bool supports_rpm_read; + bool supports_rpm_write; +}; + +/* Automatic Power State Throttling */ +enum PHM_AutoThrottleSource +{ + PHM_AutoThrottleSource_Thermal, + PHM_AutoThrottleSource_External +}; + +typedef enum PHM_AutoThrottleSource PHM_AutoThrottleSource; + +enum phm_platform_caps { + PHM_PlatformCaps_AtomBiosPpV1 = 0, + PHM_PlatformCaps_PowerPlaySupport, + PHM_PlatformCaps_ACOverdriveSupport, + PHM_PlatformCaps_BacklightSupport, + PHM_PlatformCaps_ThermalController, + PHM_PlatformCaps_BiosPowerSourceControl, + PHM_PlatformCaps_DisableVoltageTransition, + PHM_PlatformCaps_DisableEngineTransition, + PHM_PlatformCaps_DisableMemoryTransition, + PHM_PlatformCaps_DynamicPowerManagement, + PHM_PlatformCaps_EnableASPML0s, + PHM_PlatformCaps_EnableASPML1, + PHM_PlatformCaps_OD5inACSupport, + PHM_PlatformCaps_OD5inDCSupport, + PHM_PlatformCaps_SoftStateOD5, + PHM_PlatformCaps_NoOD5Support, + PHM_PlatformCaps_ContinuousHardwarePerformanceRange, + PHM_PlatformCaps_ActivityReporting, + PHM_PlatformCaps_EnableBackbias, + PHM_PlatformCaps_OverdriveDisabledByPowerBudget, + PHM_PlatformCaps_ShowPowerBudgetWarning, + PHM_PlatformCaps_PowerBudgetWaiverAvailable, + PHM_PlatformCaps_GFXClockGatingSupport, + PHM_PlatformCaps_MMClockGatingSupport, + PHM_PlatformCaps_AutomaticDCTransition, + PHM_PlatformCaps_GeminiPrimary, + PHM_PlatformCaps_MemorySpreadSpectrumSupport, + PHM_PlatformCaps_EngineSpreadSpectrumSupport, + PHM_PlatformCaps_StepVddc, + PHM_PlatformCaps_DynamicPCIEGen2Support, + PHM_PlatformCaps_SMC, + PHM_PlatformCaps_FaultyInternalThermalReading, /* Internal thermal controller reports faulty temperature value when DAC2 is active */ + PHM_PlatformCaps_EnableVoltageControl, /* indicates voltage can be controlled */ + PHM_PlatformCaps_EnableSideportControl, /* indicates Sideport can be controlled */ + PHM_PlatformCaps_VideoPlaybackEEUNotification, /* indicates EEU notification of video start/stop is required */ + PHM_PlatformCaps_TurnOffPll_ASPML1, /* PCIE Turn Off PLL in ASPM L1 */ + PHM_PlatformCaps_EnableHTLinkControl, /* indicates HT Link can be controlled by ACPI or CLMC overrided/automated mode. */ + PHM_PlatformCaps_PerformanceStateOnly, /* indicates only performance power state to be used on current system. */ + PHM_PlatformCaps_ExclusiveModeAlwaysHigh, /* In Exclusive (3D) mode always stay in High state. */ + PHM_PlatformCaps_DisableMGClockGating, /* to disable Medium Grain Clock Gating or not */ + PHM_PlatformCaps_DisableMGCGTSSM, /* TO disable Medium Grain Clock Gating Shader Complex control */ + PHM_PlatformCaps_UVDAlwaysHigh, /* In UVD mode always stay in High state */ + PHM_PlatformCaps_DisablePowerGating, /* to disable power gating */ + PHM_PlatformCaps_CustomThermalPolicy, /* indicates only performance power state to be used on current system. */ + PHM_PlatformCaps_StayInBootState, /* Stay in Boot State, do not do clock/voltage or PCIe Lane and Gen switching (RV7xx and up). */ + PHM_PlatformCaps_SMCAllowSeparateSWThermalState, /* SMC use separate SW thermal state, instead of the default SMC thermal policy. */ + PHM_PlatformCaps_MultiUVDStateSupport, /* Powerplay state table supports multi UVD states. */ + PHM_PlatformCaps_EnableSCLKDeepSleepForUVD, /* With HW ECOs, we don't need to disable SCLK Deep Sleep for UVD state. */ + PHM_PlatformCaps_EnableMCUHTLinkControl, /* Enable HT link control by MCU */ + PHM_PlatformCaps_ABM, /* ABM support.*/ + PHM_PlatformCaps_KongThermalPolicy, /* A thermal policy specific for Kong */ + PHM_PlatformCaps_SwitchVDDNB, /* if the users want to switch VDDNB */ + PHM_PlatformCaps_ULPS, /* support ULPS mode either through ACPI state or ULPS state */ + PHM_PlatformCaps_NativeULPS, /* hardware capable of ULPS state (other than through the ACPI state) */ + PHM_PlatformCaps_EnableMVDDControl, /* indicates that memory voltage can be controlled */ + PHM_PlatformCaps_ControlVDDCI, /* Control VDDCI separately from VDDC. */ + PHM_PlatformCaps_DisableDCODT, /* indicates if DC ODT apply or not */ + PHM_PlatformCaps_DynamicACTiming, /* if the SMC dynamically re-programs MC SEQ register values */ + PHM_PlatformCaps_EnableThermalIntByGPIO, /* enable throttle control through GPIO */ + PHM_PlatformCaps_BootStateOnAlert, /* Go to boot state on alerts, e.g. on an AC->DC transition. */ + PHM_PlatformCaps_DontWaitForVBlankOnAlert, /* Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). */ + PHM_PlatformCaps_Force3DClockSupport, /* indicates if the platform supports force 3D clock. */ + PHM_PlatformCaps_MicrocodeFanControl, /* Fan is controlled by the SMC microcode. */ + PHM_PlatformCaps_AdjustUVDPriorityForSP, + PHM_PlatformCaps_DisableLightSleep, /* Light sleep for evergreen family. */ + PHM_PlatformCaps_DisableMCLS, /* MC Light sleep */ + PHM_PlatformCaps_RegulatorHot, /* Enable throttling on 'regulator hot' events. */ + PHM_PlatformCaps_BACO, /* Support Bus Alive Chip Off mode */ + PHM_PlatformCaps_DisableDPM, /* Disable DPM, supported from Llano */ + PHM_PlatformCaps_DynamicM3Arbiter, /* support dynamically change m3 arbitor parameters */ + PHM_PlatformCaps_SclkDeepSleep, /* support sclk deep sleep */ + PHM_PlatformCaps_DynamicPatchPowerState, /* this ASIC supports to patch power state dynamically */ + PHM_PlatformCaps_ThermalAutoThrottling, /* enabling auto thermal throttling, */ + PHM_PlatformCaps_SumoThermalPolicy, /* A thermal policy specific for Sumo */ + PHM_PlatformCaps_PCIEPerformanceRequest, /* support to change RC voltage */ + PHM_PlatformCaps_BLControlledByGPU, /* support varibright */ + PHM_PlatformCaps_PowerContainment, /* support DPM2 power containment (AKA TDP clamping) */ + PHM_PlatformCaps_SQRamping, /* support DPM2 SQ power throttle */ + PHM_PlatformCaps_CAC, /* support Capacitance * Activity power estimation */ + PHM_PlatformCaps_NIChipsets, /* Northern Island and beyond chipsets */ + PHM_PlatformCaps_TrinityChipsets, /* Trinity chipset */ + PHM_PlatformCaps_EvergreenChipsets, /* Evergreen family chipset */ + PHM_PlatformCaps_PowerControl, /* Cayman and beyond chipsets */ + PHM_PlatformCaps_DisableLSClockGating, /* to disable Light Sleep control for HDP memories */ + PHM_PlatformCaps_BoostState, /* this ASIC supports boost state */ + PHM_PlatformCaps_UserMaxClockForMultiDisplays, /* indicates if max memory clock is used for all status when multiple displays are connected */ + PHM_PlatformCaps_RegWriteDelay, /* indicates if back to back reg write delay is required */ + PHM_PlatformCaps_NonABMSupportInPPLib, /* ABM is not supported in PPLIB, (moved from PPLIB to DAL) */ + PHM_PlatformCaps_GFXDynamicMGPowerGating, /* Enable Dynamic MG PowerGating on Trinity */ + PHM_PlatformCaps_DisableSMUUVDHandshake, /* Disable SMU UVD Handshake */ + PHM_PlatformCaps_DTE, /* Support Digital Temperature Estimation */ + PHM_PlatformCaps_W5100Specifc_SmuSkipMsgDTE, /* This is for the feature requested by David B., and Tonny W.*/ + PHM_PlatformCaps_UVDPowerGating, /* enable UVD power gating, supported from Llano */ + PHM_PlatformCaps_UVDDynamicPowerGating, /* enable UVD Dynamic power gating, supported from UVD5 */ + PHM_PlatformCaps_VCEPowerGating, /* Enable VCE power gating, supported for TN and later ASICs */ + PHM_PlatformCaps_SamuPowerGating, /* Enable SAMU power gating, supported for KV and later ASICs */ + PHM_PlatformCaps_UVDDPM, /* UVD clock DPM */ + PHM_PlatformCaps_VCEDPM, /* VCE clock DPM */ + PHM_PlatformCaps_SamuDPM, /* SAMU clock DPM */ + PHM_PlatformCaps_AcpDPM, /* ACP clock DPM */ + PHM_PlatformCaps_SclkDeepSleepAboveLow, /* Enable SCLK Deep Sleep on all DPM states */ + PHM_PlatformCaps_DynamicUVDState, /* Dynamic UVD State */ + PHM_PlatformCaps_WantSAMClkWithDummyBackEnd, /* Set SAM Clk With Dummy Back End */ + PHM_PlatformCaps_WantUVDClkWithDummyBackEnd, /* Set UVD Clk With Dummy Back End */ + PHM_PlatformCaps_WantVCEClkWithDummyBackEnd, /* Set VCE Clk With Dummy Back End */ + PHM_PlatformCaps_WantACPClkWithDummyBackEnd, /* Set SAM Clk With Dummy Back End */ + PHM_PlatformCaps_OD6inACSupport, /* indicates that the ASIC/back end supports OD6 */ + PHM_PlatformCaps_OD6inDCSupport, /* indicates that the ASIC/back end supports OD6 in DC */ + PHM_PlatformCaps_EnablePlatformPowerManagement, /* indicates that Platform Power Management feature is supported */ + PHM_PlatformCaps_SurpriseRemoval, /* indicates that surprise removal feature is requested */ + PHM_PlatformCaps_NewCACVoltage, /* indicates new CAC voltage table support */ + PHM_PlatformCaps_DBRamping, /* for dI/dT feature */ + PHM_PlatformCaps_TDRamping, /* for dI/dT feature */ + PHM_PlatformCaps_TCPRamping, /* for dI/dT feature */ + PHM_PlatformCaps_EnableSMU7ThermalManagement, /* SMC will manage thermal events */ + PHM_PlatformCaps_FPS, /* FPS support */ + PHM_PlatformCaps_ACP, /* ACP support */ + PHM_PlatformCaps_SclkThrottleLowNotification, /* SCLK Throttle Low Notification */ + PHM_PlatformCaps_XDMAEnabled, /* XDMA engine is enabled */ + PHM_PlatformCaps_UseDummyBackEnd, /* use dummy back end */ + PHM_PlatformCaps_EnableDFSBypass, /* Enable DFS bypass */ + PHM_PlatformCaps_VddNBDirectRequest, + PHM_PlatformCaps_PauseMMSessions, + PHM_PlatformCaps_UnTabledHardwareInterface, /* Tableless/direct call hardware interface for CI and newer ASICs */ + PHM_PlatformCaps_SMU7, /* indicates that vpuRecoveryBegin without SMU shutdown */ + PHM_PlatformCaps_RevertGPIO5Polarity, /* indicates revert GPIO5 plarity table support */ + PHM_PlatformCaps_Thermal2GPIO17, /* indicates thermal2GPIO17 table support */ + PHM_PlatformCaps_ThermalOutGPIO, /* indicates ThermalOutGPIO support, pin number is assigned by VBIOS */ + PHM_PlatformCaps_DisableMclkSwitchingForFrameLock, /* Disable memory clock switch during Framelock */ + PHM_PlatformCaps_VRHotGPIOConfigurable, /* indicates VR_HOT GPIO configurable */ + PHM_PlatformCaps_TempInversion, /* enable Temp Inversion feature */ + PHM_PlatformCaps_IOIC3, + PHM_PlatformCaps_ConnectedStandby, + PHM_PlatformCaps_EVV, + PHM_PlatformCaps_EnableLongIdleBACOSupport, + PHM_PlatformCaps_CombinePCCWithThermalSignal, + PHM_PlatformCaps_DisableUsingActualTemperatureForPowerCalc, + PHM_PlatformCaps_StablePState, + PHM_PlatformCaps_OD6PlusinACSupport, + PHM_PlatformCaps_OD6PlusinDCSupport, + PHM_PlatformCaps_ODThermalLimitUnlock, + PHM_PlatformCaps_ReducePowerLimit, + PHM_PlatformCaps_ODFuzzyFanControlSupport, + PHM_PlatformCaps_GeminiRegulatorFanControlSupport, + PHM_PlatformCaps_ControlVDDGFX, + PHM_PlatformCaps_BBBSupported, + PHM_PlatformCaps_DisableVoltageIsland, + PHM_PlatformCaps_FanSpeedInTableIsRPM, + PHM_PlatformCaps_GFXClockGatingManagedInCAIL, + PHM_PlatformCaps_IcelandULPSSWWorkAround, + PHM_PlatformCaps_FPSEnhancement, + PHM_PlatformCaps_LoadPostProductionFirmware, + PHM_PlatformCaps_VpuRecoveryInProgress, + PHM_PlatformCaps_Falcon_QuickTransition, + PHM_PlatformCaps_AVFS, + PHM_PlatformCaps_ClockStretcher, + PHM_PlatformCaps_TablelessHardwareInterface, + PHM_PlatformCaps_EnableDriverEVV, + PHM_PlatformCaps_Max +}; + +#define PHM_MAX_NUM_CAPS_BITS_PER_FIELD (sizeof(uint32_t)*8) + +/* Number of uint32_t entries used by CAPS table */ +#define PHM_MAX_NUM_CAPS_ULONG_ENTRIES \ + ((PHM_PlatformCaps_Max + ((PHM_MAX_NUM_CAPS_BITS_PER_FIELD) - 1)) / (PHM_MAX_NUM_CAPS_BITS_PER_FIELD)) + +struct pp_hw_descriptor { + uint32_t hw_caps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES]; +}; + +enum PHM_PerformanceLevelDesignation { + PHM_PerformanceLevelDesignation_Activity, + PHM_PerformanceLevelDesignation_PowerContainment +}; + +typedef enum PHM_PerformanceLevelDesignation PHM_PerformanceLevelDesignation; + +struct PHM_PerformanceLevel { + uint32_t coreClock; + uint32_t memory_clock; + uint32_t vddc; + uint32_t vddci; + uint32_t nonLocalMemoryFreq; + uint32_t nonLocalMemoryWidth; +}; + +typedef struct PHM_PerformanceLevel PHM_PerformanceLevel; + +/* Function for setting a platform cap */ +static inline void phm_cap_set(uint32_t *caps, + enum phm_platform_caps c) +{ + caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] |= (1UL << + (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1))); +} + +static inline void phm_cap_unset(uint32_t *caps, + enum phm_platform_caps c) +{ + caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &= ~(1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1))); +} + +static inline bool phm_cap_enabled(const uint32_t *caps, enum phm_platform_caps c) +{ + return (0 != (caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] & + (1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1))))); +} + +#define PP_PCIEGenInvalid 0xffff +enum PP_PCIEGen { + PP_PCIEGen1 = 0, /* PCIE 1.0 - Transfer rate of 2.5 GT/s */ + PP_PCIEGen2, /*PCIE 2.0 - Transfer rate of 5.0 GT/s */ + PP_PCIEGen3 /*PCIE 3.0 - Transfer rate of 8.0 GT/s */ +}; + +typedef enum PP_PCIEGen PP_PCIEGen; + +#define PP_Min_PCIEGen PP_PCIEGen1 +#define PP_Max_PCIEGen PP_PCIEGen3 +#define PP_Min_PCIELane 1 +#define PP_Max_PCIELane 32 + +enum phm_clock_Type { + PHM_DispClock = 1, + PHM_SClock, + PHM_MemClock +}; + +#define MAX_NUM_CLOCKS 16 + +struct PP_Clocks { + uint32_t engineClock; + uint32_t memoryClock; + uint32_t BusBandwidth; + uint32_t engineClockInSR; +}; + +struct phm_platform_descriptor { + uint32_t platformCaps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES]; + uint32_t vbiosInterruptId; + struct PP_Clocks overdriveLimit; + struct PP_Clocks clockStep; + uint32_t hardwareActivityPerformanceLevels; + uint32_t minimumClocksReductionPercentage; + uint32_t minOverdriveVDDC; + uint32_t maxOverdriveVDDC; + uint32_t overdriveVDDCStep; + uint32_t hardwarePerformanceLevels; + uint16_t powerBudget; + uint32_t TDPLimit; + uint32_t nearTDPLimit; + uint32_t nearTDPLimitAdjusted; + uint32_t SQRampingThreshold; + uint32_t CACLeakage; + uint16_t TDPODLimit; + uint32_t TDPAdjustment; + bool TDPAdjustmentPolarity; + uint16_t LoadLineSlope; + uint32_t VidMinLimit; + uint32_t VidMaxLimit; + uint32_t VidStep; + uint32_t VidAdjustment; + bool VidAdjustmentPolarity; +}; + +struct phm_clocks { + uint32_t num_of_entries; + uint32_t clock[MAX_NUM_CLOCKS]; +}; + +enum PP_DAL_POWERLEVEL { + PP_DAL_POWERLEVEL_INVALID = 0, + PP_DAL_POWERLEVEL_ULTRALOW, + PP_DAL_POWERLEVEL_LOW, + PP_DAL_POWERLEVEL_NOMINAL, + PP_DAL_POWERLEVEL_PERFORMANCE, + + PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW, + PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW, + PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL, + PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE, + PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1, + PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1, + PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1, + PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1, +}; + + +extern int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr); +extern int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate); +extern int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate); +extern int phm_powerdown_uvd(struct pp_hwmgr *hwmgr); +extern int phm_setup_asic(struct pp_hwmgr *hwmgr); +extern int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr); +extern void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr); +extern bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr); +extern int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block); +extern int phm_set_power_state(struct pp_hwmgr *hwmgr, + const struct pp_hw_power_state *pcurrent_state, + const struct pp_hw_power_state *pnew_power_state); + +extern int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, + struct pp_power_state *adjusted_ps, + const struct pp_power_state *current_ps); + +extern int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level); +extern int phm_display_configuration_changed(struct pp_hwmgr *hwmgr); +extern int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr); +extern int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info); +extern int phm_start_thermal_controller(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *temperature_range); +extern int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr); +extern bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr); + +extern int phm_check_states_equal(struct pp_hwmgr *hwmgr, + const struct pp_hw_power_state *pstate1, + const struct pp_hw_power_state *pstate2, + bool *equal); + +extern int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr, + const struct amd_pp_display_configuration *display_config); + +extern int phm_get_dal_power_level(struct pp_hwmgr *hwmgr, + struct amd_pp_dal_clock_info*info); + +extern int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr); + +extern int phm_power_down_asic(struct pp_hwmgr *hwmgr); + +#endif /* _HARDWARE_MANAGER_H_ */ + diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h new file mode 100644 index 000000000000..aeaa3dbba525 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h @@ -0,0 +1,801 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _HWMGR_H_ +#define _HWMGR_H_ + +#include <linux/seq_file.h> +#include "amd_powerplay.h" +#include "pp_instance.h" +#include "hardwaremanager.h" +#include "pp_power_source.h" +#include "hwmgr_ppt.h" +#include "ppatomctrl.h" +#include "hwmgr_ppt.h" + +struct pp_instance; +struct pp_hwmgr; +struct pp_hw_power_state; +struct pp_power_state; +struct PP_VCEState; +struct phm_fan_speed_info; +struct pp_atomctrl_voltage_table; + + +enum DISPLAY_GAP { + DISPLAY_GAP_VBLANK_OR_WM = 0, /* Wait for vblank or MCHG watermark. */ + DISPLAY_GAP_VBLANK = 1, /* Wait for vblank. */ + DISPLAY_GAP_WATERMARK = 2, /* Wait for MCHG watermark. (Note that HW may deassert WM in VBI depending on DC_STUTTER_CNTL.) */ + DISPLAY_GAP_IGNORE = 3 /* Do not wait. */ +}; +typedef enum DISPLAY_GAP DISPLAY_GAP; + + +struct vi_dpm_level { + bool enabled; + uint32_t value; + uint32_t param1; +}; + +struct vi_dpm_table { + uint32_t count; + struct vi_dpm_level dpm_level[1]; +}; + +enum PP_Result { + PP_Result_TableImmediateExit = 0x13, +}; + +#define PCIE_PERF_REQ_REMOVE_REGISTRY 0 +#define PCIE_PERF_REQ_FORCE_LOWPOWER 1 +#define PCIE_PERF_REQ_GEN1 2 +#define PCIE_PERF_REQ_GEN2 3 +#define PCIE_PERF_REQ_GEN3 4 + +enum PHM_BackEnd_Magic { + PHM_Dummy_Magic = 0xAA5555AA, + PHM_RV770_Magic = 0xDCBAABCD, + PHM_Kong_Magic = 0x239478DF, + PHM_NIslands_Magic = 0x736C494E, + PHM_Sumo_Magic = 0x8339FA11, + PHM_SIslands_Magic = 0x369431AC, + PHM_Trinity_Magic = 0x96751873, + PHM_CIslands_Magic = 0x38AC78B0, + PHM_Kv_Magic = 0xDCBBABC0, + PHM_VIslands_Magic = 0x20130307, + PHM_Cz_Magic = 0x67DCBA25 +}; + + +#define PHM_PCIE_POWERGATING_TARGET_GFX 0 +#define PHM_PCIE_POWERGATING_TARGET_DDI 1 +#define PHM_PCIE_POWERGATING_TARGET_PLLCASCADE 2 +#define PHM_PCIE_POWERGATING_TARGET_PHY 3 + +typedef int (*phm_table_function)(struct pp_hwmgr *hwmgr, void *input, + void *output, void *storage, int result); + +typedef bool (*phm_check_function)(struct pp_hwmgr *hwmgr); + +struct phm_set_power_state_input { + const struct pp_hw_power_state *pcurrent_state; + const struct pp_hw_power_state *pnew_state; +}; + +struct phm_acp_arbiter { + uint32_t acpclk; +}; + +struct phm_uvd_arbiter { + uint32_t vclk; + uint32_t dclk; + uint32_t vclk_ceiling; + uint32_t dclk_ceiling; +}; + +struct phm_vce_arbiter { + uint32_t evclk; + uint32_t ecclk; +}; + +struct phm_gfx_arbiter { + uint32_t sclk; + uint32_t mclk; + uint32_t sclk_over_drive; + uint32_t mclk_over_drive; + uint32_t sclk_threshold; + uint32_t num_cus; +}; + +/* Entries in the master tables */ +struct phm_master_table_item { + phm_check_function isFunctionNeededInRuntimeTable; + phm_table_function tableFunction; +}; + +enum phm_master_table_flag { + PHM_MasterTableFlag_None = 0, + PHM_MasterTableFlag_ExitOnError = 1, +}; + +/* The header of the master tables */ +struct phm_master_table_header { + uint32_t storage_size; + uint32_t flags; + struct phm_master_table_item *master_list; +}; + +struct phm_runtime_table_header { + uint32_t storage_size; + bool exit_error; + phm_table_function *function_list; +}; + +struct phm_clock_array { + uint32_t count; + uint32_t values[1]; +}; + +struct phm_clock_voltage_dependency_record { + uint32_t clk; + uint32_t v; +}; + +struct phm_vceclock_voltage_dependency_record { + uint32_t ecclk; + uint32_t evclk; + uint32_t v; +}; + +struct phm_uvdclock_voltage_dependency_record { + uint32_t vclk; + uint32_t dclk; + uint32_t v; +}; + +struct phm_samuclock_voltage_dependency_record { + uint32_t samclk; + uint32_t v; +}; + +struct phm_acpclock_voltage_dependency_record { + uint32_t acpclk; + uint32_t v; +}; + +struct phm_clock_voltage_dependency_table { + uint32_t count; /* Number of entries. */ + struct phm_clock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */ +}; + +struct phm_phase_shedding_limits_record { + uint32_t Voltage; + uint32_t Sclk; + uint32_t Mclk; +}; + + +extern int phm_dispatch_table(struct pp_hwmgr *hwmgr, + struct phm_runtime_table_header *rt_table, + void *input, void *output); + +extern int phm_construct_table(struct pp_hwmgr *hwmgr, + struct phm_master_table_header *master_table, + struct phm_runtime_table_header *rt_table); + +extern int phm_destroy_table(struct pp_hwmgr *hwmgr, + struct phm_runtime_table_header *rt_table); + + +struct phm_uvd_clock_voltage_dependency_record { + uint32_t vclk; + uint32_t dclk; + uint32_t v; +}; + +struct phm_uvd_clock_voltage_dependency_table { + uint8_t count; + struct phm_uvd_clock_voltage_dependency_record entries[1]; +}; + +struct phm_acp_clock_voltage_dependency_record { + uint32_t acpclk; + uint32_t v; +}; + +struct phm_acp_clock_voltage_dependency_table { + uint32_t count; + struct phm_acp_clock_voltage_dependency_record entries[1]; +}; + +struct phm_vce_clock_voltage_dependency_record { + uint32_t ecclk; + uint32_t evclk; + uint32_t v; +}; + +struct phm_phase_shedding_limits_table { + uint32_t count; + struct phm_phase_shedding_limits_record entries[1]; +}; + +struct phm_vceclock_voltage_dependency_table { + uint8_t count; /* Number of entries. */ + struct phm_vceclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */ +}; + +struct phm_uvdclock_voltage_dependency_table { + uint8_t count; /* Number of entries. */ + struct phm_uvdclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */ +}; + +struct phm_samuclock_voltage_dependency_table { + uint8_t count; /* Number of entries. */ + struct phm_samuclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */ +}; + +struct phm_acpclock_voltage_dependency_table { + uint32_t count; /* Number of entries. */ + struct phm_acpclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */ +}; + +struct phm_vce_clock_voltage_dependency_table { + uint8_t count; + struct phm_vce_clock_voltage_dependency_record entries[1]; +}; + +struct pp_hwmgr_func { + int (*backend_init)(struct pp_hwmgr *hw_mgr); + int (*backend_fini)(struct pp_hwmgr *hw_mgr); + int (*asic_setup)(struct pp_hwmgr *hw_mgr); + int (*get_power_state_size)(struct pp_hwmgr *hw_mgr); + + int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr, + struct pp_power_state *prequest_ps, + const struct pp_power_state *pcurrent_ps); + + int (*force_dpm_level)(struct pp_hwmgr *hw_mgr, + enum amd_dpm_forced_level level); + + int (*dynamic_state_management_enable)( + struct pp_hwmgr *hw_mgr); + + int (*patch_boot_state)(struct pp_hwmgr *hwmgr, + struct pp_hw_power_state *hw_ps); + + int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr, + unsigned long, struct pp_power_state *); + int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr); + int (*powerdown_uvd)(struct pp_hwmgr *hwmgr); + int (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate); + int (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate); + int (*get_mclk)(struct pp_hwmgr *hwmgr, bool low); + int (*get_sclk)(struct pp_hwmgr *hwmgr, bool low); + int (*power_state_set)(struct pp_hwmgr *hwmgr, + const void *state); + void (*print_current_perforce_level)(struct pp_hwmgr *hwmgr, + struct seq_file *m); + int (*enable_clock_power_gating)(struct pp_hwmgr *hwmgr); + int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr); + int (*display_config_changed)(struct pp_hwmgr *hwmgr); + int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr); + int (*update_clock_gatings)(struct pp_hwmgr *hwmgr, + const uint32_t *msg_id); + int (*set_max_fan_rpm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm); + int (*set_max_fan_pwm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm); + int (*get_temperature)(struct pp_hwmgr *hwmgr); + int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr); + int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info); + int (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode); + int (*get_fan_control_mode)(struct pp_hwmgr *hwmgr); + int (*set_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t percent); + int (*get_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t *speed); + int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t percent); + int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed); + int (*reset_fan_speed_to_default)(struct pp_hwmgr *hwmgr); + int (*uninitialize_thermal_controller)(struct pp_hwmgr *hwmgr); + int (*register_internal_thermal_interrupt)(struct pp_hwmgr *hwmgr, + const void *thermal_interrupt_info); + bool (*check_smc_update_required_for_display_configuration)(struct pp_hwmgr *hwmgr); + int (*check_states_equal)(struct pp_hwmgr *hwmgr, + const struct pp_hw_power_state *pstate1, + const struct pp_hw_power_state *pstate2, + bool *equal); + int (*set_cpu_power_state)(struct pp_hwmgr *hwmgr); + int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time, + bool cc6_disable, bool pstate_disable, + bool pstate_switch_disable); + int (*get_dal_power_level)(struct pp_hwmgr *hwmgr, + struct amd_pp_dal_clock_info *info); + int (*power_off_asic)(struct pp_hwmgr *hwmgr); +}; + +struct pp_table_func { + int (*pptable_init)(struct pp_hwmgr *hw_mgr); + int (*pptable_fini)(struct pp_hwmgr *hw_mgr); + int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr); + int (*pptable_get_vce_state_table_entry)( + struct pp_hwmgr *hwmgr, + unsigned long i, + struct PP_VCEState *vce_state, + void **clock_info, + unsigned long *flag); +}; + +union phm_cac_leakage_record { + struct { + uint16_t Vddc; /* in CI, we use it for StdVoltageHiSidd */ + uint32_t Leakage; /* in CI, we use it for StdVoltageLoSidd */ + }; + struct { + uint16_t Vddc1; + uint16_t Vddc2; + uint16_t Vddc3; + }; +}; + +struct phm_cac_leakage_table { + uint32_t count; + union phm_cac_leakage_record entries[1]; +}; + +struct phm_samu_clock_voltage_dependency_record { + uint32_t samclk; + uint32_t v; +}; + + +struct phm_samu_clock_voltage_dependency_table { + uint8_t count; + struct phm_samu_clock_voltage_dependency_record entries[1]; +}; + +struct phm_cac_tdp_table { + uint16_t usTDP; + uint16_t usConfigurableTDP; + uint16_t usTDC; + uint16_t usBatteryPowerLimit; + uint16_t usSmallPowerLimit; + uint16_t usLowCACLeakage; + uint16_t usHighCACLeakage; + uint16_t usMaximumPowerDeliveryLimit; + uint16_t usOperatingTempMinLimit; + uint16_t usOperatingTempMaxLimit; + uint16_t usOperatingTempStep; + uint16_t usOperatingTempHyst; + uint16_t usDefaultTargetOperatingTemp; + uint16_t usTargetOperatingTemp; + uint16_t usPowerTuneDataSetID; + uint16_t usSoftwareShutdownTemp; + uint16_t usClockStretchAmount; + uint16_t usTemperatureLimitHotspot; + uint16_t usTemperatureLimitLiquid1; + uint16_t usTemperatureLimitLiquid2; + uint16_t usTemperatureLimitVrVddc; + uint16_t usTemperatureLimitVrMvdd; + uint16_t usTemperatureLimitPlx; + uint8_t ucLiquid1_I2C_address; + uint8_t ucLiquid2_I2C_address; + uint8_t ucLiquid_I2C_Line; + uint8_t ucVr_I2C_address; + uint8_t ucVr_I2C_Line; + uint8_t ucPlx_I2C_address; + uint8_t ucPlx_I2C_Line; +}; + +struct phm_ppm_table { + uint8_t ppm_design; + uint16_t cpu_core_number; + uint32_t platform_tdp; + uint32_t small_ac_platform_tdp; + uint32_t platform_tdc; + uint32_t small_ac_platform_tdc; + uint32_t apu_tdp; + uint32_t dgpu_tdp; + uint32_t dgpu_ulv_power; + uint32_t tj_max; +}; + +struct phm_vq_budgeting_record { + uint32_t ulCUs; + uint32_t ulSustainableSOCPowerLimitLow; + uint32_t ulSustainableSOCPowerLimitHigh; + uint32_t ulMinSclkLow; + uint32_t ulMinSclkHigh; + uint8_t ucDispConfig; + uint32_t ulDClk; + uint32_t ulEClk; + uint32_t ulSustainableSclk; + uint32_t ulSustainableCUs; +}; + +struct phm_vq_budgeting_table { + uint8_t numEntries; + struct phm_vq_budgeting_record entries[1]; +}; + +struct phm_clock_and_voltage_limits { + uint32_t sclk; + uint32_t mclk; + uint16_t vddc; + uint16_t vddci; + uint16_t vddgfx; +}; + +/* Structure to hold PPTable information */ + +struct phm_ppt_v1_information { + struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk; + struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk; + struct phm_clock_array *valid_sclk_values; + struct phm_clock_array *valid_mclk_values; + struct phm_clock_and_voltage_limits max_clock_voltage_on_dc; + struct phm_clock_and_voltage_limits max_clock_voltage_on_ac; + struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl; + struct phm_ppm_table *ppm_parameter_table; + struct phm_cac_tdp_table *cac_dtp_table; + struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table; + struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table; + struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table; + struct phm_ppt_v1_pcie_table *pcie_table; + uint16_t us_ulv_voltage_offset; +}; + +struct phm_dynamic_state_info { + struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk; + struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk; + struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk; + struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk; + struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl; + struct phm_clock_array *valid_sclk_values; + struct phm_clock_array *valid_mclk_values; + struct phm_clock_and_voltage_limits max_clock_voltage_on_dc; + struct phm_clock_and_voltage_limits max_clock_voltage_on_ac; + uint32_t mclk_sclk_ratio; + uint32_t sclk_mclk_delta; + uint32_t vddc_vddci_delta; + uint32_t min_vddc_for_pcie_gen2; + struct phm_cac_leakage_table *cac_leakage_table; + struct phm_phase_shedding_limits_table *vddc_phase_shed_limits_table; + + struct phm_vce_clock_voltage_dependency_table + *vce_clock_voltage_dependency_table; + struct phm_uvd_clock_voltage_dependency_table + *uvd_clock_voltage_dependency_table; + struct phm_acp_clock_voltage_dependency_table + *acp_clock_voltage_dependency_table; + struct phm_samu_clock_voltage_dependency_table + *samu_clock_voltage_dependency_table; + + struct phm_ppm_table *ppm_parameter_table; + struct phm_cac_tdp_table *cac_dtp_table; + struct phm_clock_voltage_dependency_table *vdd_gfx_dependency_on_sclk; + struct phm_vq_budgeting_table *vq_budgeting_table; +}; + +struct pp_fan_info { + bool bNoFan; + uint8_t ucTachometerPulsesPerRevolution; + uint32_t ulMinRPM; + uint32_t ulMaxRPM; +}; + +struct pp_advance_fan_control_parameters { + uint16_t usTMin; /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */ + uint16_t usTMed; /* The middle temperature where we change slopes. */ + uint16_t usTHigh; /* The high temperature for setting the second slope. */ + uint16_t usPWMMin; /* The minimum PWM value in percent (0.01% increments). */ + uint16_t usPWMMed; /* The PWM value (in percent) at TMed. */ + uint16_t usPWMHigh; /* The PWM value at THigh. */ + uint8_t ucTHyst; /* Temperature hysteresis. Integer. */ + uint32_t ulCycleDelay; /* The time between two invocations of the fan control routine in microseconds. */ + uint16_t usTMax; /* The max temperature */ + uint8_t ucFanControlMode; + uint16_t usFanPWMMinLimit; + uint16_t usFanPWMMaxLimit; + uint16_t usFanPWMStep; + uint16_t usDefaultMaxFanPWM; + uint16_t usFanOutputSensitivity; + uint16_t usDefaultFanOutputSensitivity; + uint16_t usMaxFanPWM; /* The max Fan PWM value for Fuzzy Fan Control feature */ + uint16_t usFanRPMMinLimit; /* Minimum limit range in percentage, need to calculate based on minRPM/MaxRpm */ + uint16_t usFanRPMMaxLimit; /* Maximum limit range in percentage, usually set to 100% by default */ + uint16_t usFanRPMStep; /* Step increments/decerements, in percent */ + uint16_t usDefaultMaxFanRPM; /* The max Fan RPM value for Fuzzy Fan Control feature, default from PPTable */ + uint16_t usMaxFanRPM; /* The max Fan RPM value for Fuzzy Fan Control feature, user defined */ + uint16_t usFanCurrentLow; /* Low current */ + uint16_t usFanCurrentHigh; /* High current */ + uint16_t usFanRPMLow; /* Low RPM */ + uint16_t usFanRPMHigh; /* High RPM */ + uint32_t ulMinFanSCLKAcousticLimit; /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */ + uint8_t ucTargetTemperature; /* Advanced fan controller target temperature. */ + uint8_t ucMinimumPWMLimit; /* The minimum PWM that the advanced fan controller can set. This should be set to the highest PWM that will run the fan at its lowest RPM. */ + uint16_t usFanGainEdge; /* The following is added for Fiji */ + uint16_t usFanGainHotspot; + uint16_t usFanGainLiquid; + uint16_t usFanGainVrVddc; + uint16_t usFanGainVrMvdd; + uint16_t usFanGainPlx; + uint16_t usFanGainHbm; +}; + +struct pp_thermal_controller_info { + uint8_t ucType; + uint8_t ucI2cLine; + uint8_t ucI2cAddress; + struct pp_fan_info fanInfo; + struct pp_advance_fan_control_parameters advanceFanControlParameters; +}; + +struct phm_microcode_version_info { + uint32_t SMC; + uint32_t DMCU; + uint32_t MC; + uint32_t NB; +}; + +/** + * The main hardware manager structure. + */ +struct pp_hwmgr { + uint32_t chip_family; + uint32_t chip_id; + uint32_t hw_revision; + uint32_t sub_sys_id; + uint32_t sub_vendor_id; + + void *device; + struct pp_smumgr *smumgr; + const void *soft_pp_table; + bool need_pp_table_upload; + enum amd_dpm_forced_level dpm_level; + bool block_hw_access; + struct phm_gfx_arbiter gfx_arbiter; + struct phm_acp_arbiter acp_arbiter; + struct phm_uvd_arbiter uvd_arbiter; + struct phm_vce_arbiter vce_arbiter; + uint32_t usec_timeout; + void *pptable; + struct phm_platform_descriptor platform_descriptor; + void *backend; + enum PP_DAL_POWERLEVEL dal_power_level; + struct phm_dynamic_state_info dyn_state; + struct phm_runtime_table_header setup_asic; + struct phm_runtime_table_header power_down_asic; + struct phm_runtime_table_header disable_dynamic_state_management; + struct phm_runtime_table_header enable_dynamic_state_management; + struct phm_runtime_table_header set_power_state; + struct phm_runtime_table_header enable_clock_power_gatings; + struct phm_runtime_table_header display_configuration_changed; + struct phm_runtime_table_header start_thermal_controller; + struct phm_runtime_table_header set_temperature_range; + const struct pp_hwmgr_func *hwmgr_func; + const struct pp_table_func *pptable_func; + struct pp_power_state *ps; + enum pp_power_source power_source; + uint32_t num_ps; + struct pp_thermal_controller_info thermal_controller; + bool fan_ctrl_is_in_default_mode; + uint32_t fan_ctrl_default_mode; + uint32_t tmin; + struct phm_microcode_version_info microcode_version_info; + uint32_t ps_size; + struct pp_power_state *current_ps; + struct pp_power_state *request_ps; + struct pp_power_state *boot_ps; + struct pp_power_state *uvd_ps; + struct amd_pp_display_configuration display_config; +}; + + +extern int hwmgr_init(struct amd_pp_init *pp_init, + struct pp_instance *handle); + +extern int hwmgr_fini(struct pp_hwmgr *hwmgr); + +extern int hw_init_power_state_table(struct pp_hwmgr *hwmgr); + +extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index, + uint32_t value, uint32_t mask); + +extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr, + uint32_t index, uint32_t value, uint32_t mask); + +extern uint32_t phm_read_indirect_register(struct pp_hwmgr *hwmgr, + uint32_t indirect_port, uint32_t index); + +extern void phm_write_indirect_register(struct pp_hwmgr *hwmgr, + uint32_t indirect_port, + uint32_t index, + uint32_t value); + +extern void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr, + uint32_t indirect_port, + uint32_t index, + uint32_t value, + uint32_t mask); + +extern void phm_wait_for_indirect_register_unequal( + struct pp_hwmgr *hwmgr, + uint32_t indirect_port, + uint32_t index, + uint32_t value, + uint32_t mask); + +extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr); +extern bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr); +extern bool phm_cf_want_microcode_fan_ctrl(struct pp_hwmgr *hwmgr); + +extern int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table); +extern int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table); +extern int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table); +extern int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_voltage_lookup_table *lookup_table); +extern void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table); +extern int phm_reset_single_dpm_table(void *table, uint32_t count, int max); +extern void phm_setup_pcie_table_entry(void *table, uint32_t index, uint32_t pcie_gen, uint32_t pcie_lanes); +extern int32_t phm_get_dpm_level_enable_mask_value(void *table); +extern uint8_t phm_get_voltage_index(struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage); +extern uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci); +extern int phm_find_boot_level(void *table, uint32_t value, uint32_t *boot_level); +extern int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table, + uint16_t virtual_voltage_id, int32_t *sclk); +extern int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr); +extern int phm_hwmgr_backend_fini(struct pp_hwmgr *hwmgr); +extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask); + + +#define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU + +#define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT +#define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK + +#define PHM_SET_FIELD(origval, reg, field, fieldval) \ + (((origval) & ~PHM_FIELD_MASK(reg, field)) | \ + (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field)))) + +#define PHM_GET_FIELD(value, reg, field) \ + (((value) & PHM_FIELD_MASK(reg, field)) >> \ + PHM_FIELD_SHIFT(reg, field)) + + +#define PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, index, value, mask) \ + phm_wait_on_register(hwmgr, index, value, mask) + +#define PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, index, value, mask) \ + phm_wait_for_register_unequal(hwmgr, index, value, mask) + +#define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \ + phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask) + +#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \ + phm_wait_for_indirect_register_unequal(hwmgr, mm##port##_INDEX, index, value, mask) + +#define PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \ + phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX_0, index, value, mask) + +#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \ + phm_wait_for_indirect_register_unequal(hwmgr, mm##port##_INDEX_0, index, value, mask) + +/* Operations on named registers. */ + +#define PHM_WAIT_REGISTER(hwmgr, reg, value, mask) \ + PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg, value, mask) + +#define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask) \ + PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg, value, mask) + +#define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \ + PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask) + +#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \ + PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask) + +#define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \ + PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask) + +#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \ + PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask) + +/* Operations on named fields. */ + +#define PHM_READ_FIELD(device, reg, field) \ + PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field) + +#define PHM_READ_INDIRECT_FIELD(device, port, reg, field) \ + PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ + reg, field) + +#define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \ + PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ + reg, field) + +#define PHM_WRITE_FIELD(device, reg, field, fieldval) \ + cgs_write_register(device, mm##reg, PHM_SET_FIELD( \ + cgs_read_register(device, mm##reg), reg, field, fieldval)) + +#define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval) \ + cgs_write_ind_register(device, port, ix##reg, \ + PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ + reg, field, fieldval)) + +#define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval) \ + cgs_write_ind_register(device, port, ix##reg, \ + PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ + reg, field, fieldval)) + +#define PHM_WAIT_FIELD(hwmgr, reg, field, fieldval) \ + PHM_WAIT_REGISTER(hwmgr, reg, (fieldval) \ + << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field)) + +#define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \ + PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \ + << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field)) + +#define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \ + PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \ + << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field)) + +#define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval) \ + PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, (fieldval) \ + << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field)) + +#define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \ + PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, (fieldval) \ + << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field)) + +#define PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \ + PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, (fieldval) \ + << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field)) + +/* Operations on arrays of registers & fields. */ + +#define PHM_READ_ARRAY_REGISTER(device, reg, offset) \ + cgs_read_register(device, mm##reg + (offset)) + +#define PHM_WRITE_ARRAY_REGISTER(device, reg, offset, value) \ + cgs_write_register(device, mm##reg + (offset), value) + +#define PHM_WAIT_ARRAY_REGISTER(hwmgr, reg, offset, value, mask) \ + PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg + (offset), value, mask) + +#define PHM_WAIT_ARRAY_REGISTER_UNEQUAL(hwmgr, reg, offset, value, mask) \ + PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg + (offset), value, mask) + +#define PHM_READ_ARRAY_FIELD(hwmgr, reg, offset, field) \ + PHM_GET_FIELD(PHM_READ_ARRAY_REGISTER(hwmgr->device, reg, offset), reg, field) + +#define PHM_WRITE_ARRAY_FIELD(hwmgr, reg, offset, field, fieldvalue) \ + PHM_WRITE_ARRAY_REGISTER(hwmgr->device, reg, offset, \ + PHM_SET_FIELD(PHM_READ_ARRAY_REGISTER(hwmgr->device, reg, offset), \ + reg, field, fieldvalue)) + +#define PHM_WAIT_ARRAY_FIELD(hwmgr, reg, offset, field, fieldvalue) \ + PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg + (offset), \ + (fieldvalue) << PHM_FIELD_SHIFT(reg, field), \ + PHM_FIELD_MASK(reg, field)) + +#define PHM_WAIT_ARRAY_FIELD_UNEQUAL(hwmgr, reg, offset, field, fieldvalue) \ + PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg + (offset), \ + (fieldvalue) << PHM_FIELD_SHIFT(reg, field), \ + PHM_FIELD_MASK(reg, field)) + +#endif /* _HWMGR_H_ */ diff --git a/drivers/gpu/drm/amd/powerplay/inc/power_state.h b/drivers/gpu/drm/amd/powerplay/inc/power_state.h new file mode 100644 index 000000000000..a3f0ce4d5835 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/power_state.h @@ -0,0 +1,200 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef PP_POWERSTATE_H +#define PP_POWERSTATE_H + +struct pp_hw_power_state { + unsigned int magic; +}; + +struct pp_power_state; + + +#define PP_INVALID_POWER_STATE_ID (0) + + +/* + * An item of a list containing Power States. + */ + +struct PP_StateLinkedList { + struct pp_power_state *next; + struct pp_power_state *prev; +}; + + +enum PP_StateUILabel { + PP_StateUILabel_None, + PP_StateUILabel_Battery, + PP_StateUILabel_MiddleLow, + PP_StateUILabel_Balanced, + PP_StateUILabel_MiddleHigh, + PP_StateUILabel_Performance, + PP_StateUILabel_BACO +}; + +enum PP_StateClassificationFlag { + PP_StateClassificationFlag_Boot = 0x0001, + PP_StateClassificationFlag_Thermal = 0x0002, + PP_StateClassificationFlag_LimitedPowerSource = 0x0004, + PP_StateClassificationFlag_Rest = 0x0008, + PP_StateClassificationFlag_Forced = 0x0010, + PP_StateClassificationFlag_User3DPerformance = 0x0020, + PP_StateClassificationFlag_User2DPerformance = 0x0040, + PP_StateClassificationFlag_3DPerformance = 0x0080, + PP_StateClassificationFlag_ACOverdriveTemplate = 0x0100, + PP_StateClassificationFlag_Uvd = 0x0200, + PP_StateClassificationFlag_3DPerformanceLow = 0x0400, + PP_StateClassificationFlag_ACPI = 0x0800, + PP_StateClassificationFlag_HD2 = 0x1000, + PP_StateClassificationFlag_UvdHD = 0x2000, + PP_StateClassificationFlag_UvdSD = 0x4000, + PP_StateClassificationFlag_UserDCPerformance = 0x8000, + PP_StateClassificationFlag_DCOverdriveTemplate = 0x10000, + PP_StateClassificationFlag_BACO = 0x20000, + PP_StateClassificationFlag_LimitedPowerSource_2 = 0x40000, + PP_StateClassificationFlag_ULV = 0x80000, + PP_StateClassificationFlag_UvdMVC = 0x100000, +}; + +typedef unsigned int PP_StateClassificationFlags; + +struct PP_StateClassificationBlock { + enum PP_StateUILabel ui_label; + enum PP_StateClassificationFlag flags; + int bios_index; + bool temporary_state; + bool to_be_deleted; +}; + +struct PP_StatePcieBlock { + unsigned int lanes; +}; + +enum PP_RefreshrateSource { + PP_RefreshrateSource_EDID, + PP_RefreshrateSource_Explicit +}; + +struct PP_StateDisplayBlock { + bool disableFrameModulation; + bool limitRefreshrate; + enum PP_RefreshrateSource refreshrateSource; + int explicitRefreshrate; + int edidRefreshrateIndex; + bool enableVariBright; +}; + +struct PP_StateMemroyBlock { + bool dllOff; + uint8_t m3arb; + uint8_t unused[3]; +}; + +struct PP_StateSoftwareAlgorithmBlock { + bool disableLoadBalancing; + bool enableSleepForTimestamps; +}; + +#define PP_TEMPERATURE_UNITS_PER_CENTIGRADES 1000 + +/** + * Type to hold a temperature range. + */ +struct PP_TemperatureRange { + uint32_t min; + uint32_t max; +}; + +struct PP_StateValidationBlock { + bool singleDisplayOnly; + bool disallowOnDC; + uint8_t supportedPowerLevels; +}; + +struct PP_UVD_CLOCKS { + uint32_t VCLK; + uint32_t DCLK; +}; + +/** +* Structure to hold a PowerPlay Power State. +*/ +struct pp_power_state { + uint32_t id; + struct PP_StateLinkedList orderedList; + struct PP_StateLinkedList allStatesList; + + struct PP_StateClassificationBlock classification; + struct PP_StateValidationBlock validation; + struct PP_StatePcieBlock pcie; + struct PP_StateDisplayBlock display; + struct PP_StateMemroyBlock memory; + struct PP_TemperatureRange temperatures; + struct PP_StateSoftwareAlgorithmBlock software; + struct PP_UVD_CLOCKS uvd_clocks; + struct pp_hw_power_state hardware; +}; + + +/*Structure to hold a VCE state entry*/ +struct PP_VCEState { + uint32_t evclk; + uint32_t ecclk; + uint32_t sclk; + uint32_t mclk; +}; + +enum PP_MMProfilingState { + PP_MMProfilingState_NA = 0, + PP_MMProfilingState_Started, + PP_MMProfilingState_Stopped +}; + +struct PP_Clock_Engine_Request { + unsigned long clientType; + unsigned long ctxid; + uint64_t context_handle; + unsigned long sclk; + unsigned long sclkHardMin; + unsigned long mclk; + unsigned long iclk; + unsigned long evclk; + unsigned long ecclk; + unsigned long ecclkHardMin; + unsigned long vclk; + unsigned long dclk; + unsigned long samclk; + unsigned long acpclk; + unsigned long sclkOverdrive; + unsigned long mclkOverdrive; + unsigned long sclk_threshold; + unsigned long flag; + unsigned long vclk_ceiling; + unsigned long dclk_ceiling; + unsigned long num_cus; + unsigned long pmflag; + enum PP_MMProfilingState MMProfilingState; +}; + +#endif diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_acpi.h b/drivers/gpu/drm/amd/powerplay/inc/pp_acpi.h new file mode 100644 index 000000000000..3bd5e69b9045 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/pp_acpi.h @@ -0,0 +1,28 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +extern bool acpi_atcs_functions_supported(void *device, + uint32_t index); +extern int acpi_pcie_perf_request(void *device, + uint8_t perf_req, + bool advertise); diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_asicblocks.h b/drivers/gpu/drm/amd/powerplay/inc/pp_asicblocks.h new file mode 100644 index 000000000000..0c1593e53654 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/pp_asicblocks.h @@ -0,0 +1,47 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef PP_ASICBLOCKS_H +#define PP_ASICBLOCKS_H + + +enum PHM_AsicBlock { + PHM_AsicBlock_GFX, + PHM_AsicBlock_UVD_MVC, + PHM_AsicBlock_UVD, + PHM_AsicBlock_UVD_HD, + PHM_AsicBlock_UVD_SD, + PHM_AsicBlock_Count +}; + +enum PHM_ClockGateSetting { + PHM_ClockGateSetting_StaticOn, + PHM_ClockGateSetting_StaticOff, + PHM_ClockGateSetting_Dynamic +}; + +struct phm_asic_blocks { + bool gfx : 1; + bool uvd : 1; +}; + +#endif diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h b/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h new file mode 100644 index 000000000000..d7d83b7c7f95 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h @@ -0,0 +1,47 @@ + +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef PP_DEBUG_H +#define PP_DEBUG_H + +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/slab.h> + +#define PP_ASSERT_WITH_CODE(cond, msg, code) \ + do { \ + if (!(cond)) { \ + printk("%s\n", msg); \ + code; \ + } \ + } while (0) + + +#define PP_DBG_LOG(fmt, ...) \ + do { \ + if(0)printk(KERN_INFO "[ pp_dbg ] " fmt, ##__VA_ARGS__); \ + } while (0) + + +#endif /* PP_DEBUG_H */ + diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_feature.h b/drivers/gpu/drm/amd/powerplay/inc/pp_feature.h new file mode 100644 index 000000000000..0faf6a25c18b --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/pp_feature.h @@ -0,0 +1,67 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _PP_FEATURE_H_ +#define _PP_FEATURE_H_ + +/** + * PowerPlay feature ids. + */ +enum pp_feature { + PP_Feature_PowerPlay = 0, + PP_Feature_User2DPerformance, + PP_Feature_User3DPerformance, + PP_Feature_VariBright, + PP_Feature_VariBrightOnPowerXpress, + PP_Feature_ReducedRefreshRate, + PP_Feature_GFXClockGating, + PP_Feature_OverdriveTest, + PP_Feature_OverDrive, + PP_Feature_PowerBudgetWaiver, + PP_Feature_PowerControl, + PP_Feature_PowerControl_2, + PP_Feature_MultiUVDState, + PP_Feature_Force3DClock, + PP_Feature_BACO, + PP_Feature_PowerDown, + PP_Feature_DynamicUVDState, + PP_Feature_VCEDPM, + PP_Feature_PPM, + PP_Feature_ACP_POWERGATING, + PP_Feature_FFC, + PP_Feature_FPS, + PP_Feature_ViPG, + PP_Feature_Max +}; + +/** + * Struct for PowerPlay feature info. + */ +struct pp_feature_info { + bool supported; /* feature supported by PowerPlay */ + bool enabled; /* feature enabled in PowerPlay */ + bool enabled_default; /* default enable status of the feature */ + uint32_t version; /* feature version */ +}; + +#endif /* _PP_FEATURE_H_ */ diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h b/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h new file mode 100644 index 000000000000..4d8ed1f33de4 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h @@ -0,0 +1,39 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _PP_INSTANCE_H_ +#define _PP_INSTANCE_H_ + +#include "smumgr.h" +#include "hwmgr.h" +#include "eventmgr.h" + +#define PP_VALID 0x1F1F1F1F + +struct pp_instance { + uint32_t pp_valid; + struct pp_smumgr *smu_mgr; + struct pp_hwmgr *hwmgr; + struct pp_eventmgr *eventmgr; +}; + +#endif diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_power_source.h b/drivers/gpu/drm/amd/powerplay/inc/pp_power_source.h new file mode 100644 index 000000000000..b43315cc5d58 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/pp_power_source.h @@ -0,0 +1,36 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef PP_POWERSOURCE_H +#define PP_POWERSOURCE_H + +enum pp_power_source { + PP_PowerSource_AC = 0, + PP_PowerSource_DC, + PP_PowerSource_LimitedPower, + PP_PowerSource_LimitedPower_2, + PP_PowerSource_Max +}; + + +#endif diff --git a/drivers/gpu/drm/amd/powerplay/inc/ppinterrupt.h b/drivers/gpu/drm/amd/powerplay/inc/ppinterrupt.h new file mode 100644 index 000000000000..c067e0925b6b --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/ppinterrupt.h @@ -0,0 +1,46 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _PP_INTERRUPT_H_ +#define _PP_INTERRUPT_H_ + +enum amd_thermal_irq { + AMD_THERMAL_IRQ_LOW_TO_HIGH = 0, + AMD_THERMAL_IRQ_HIGH_TO_LOW, + + AMD_THERMAL_IRQ_LAST +}; + +/* The type of the interrupt callback functions in PowerPlay */ +typedef int (*irq_handler_func_t)(void *private_data, + unsigned src_id, const uint32_t *iv_entry); + +/* Event Manager action chain list information */ +struct pp_interrupt_registration_info { + irq_handler_func_t call_back; /* Pointer to callback function */ + void *context; /* Pointer to callback function context */ + uint32_t src_id; /* Registered interrupt id */ + const uint32_t *iv_entry; +}; + +#endif /* _PP_INTERRUPT_H_ */ diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu7.h b/drivers/gpu/drm/amd/powerplay/inc/smu7.h new file mode 100644 index 000000000000..75a380a15292 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/smu7.h @@ -0,0 +1,170 @@ +/* + * Copyright 2013 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef SMU7_H +#define SMU7_H + +#pragma pack(push, 1) + +#define SMU7_CONTEXT_ID_SMC 1 +#define SMU7_CONTEXT_ID_VBIOS 2 + + +#define SMU7_CONTEXT_ID_SMC 1 +#define SMU7_CONTEXT_ID_VBIOS 2 + +#define SMU7_MAX_LEVELS_VDDC 8 +#define SMU7_MAX_LEVELS_VDDCI 4 +#define SMU7_MAX_LEVELS_MVDD 4 +#define SMU7_MAX_LEVELS_VDDNB 8 + +#define SMU7_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE // SCLK + SQ DPM + ULV +#define SMU7_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS // MCLK Levels DPM +#define SMU7_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS // LCLK Levels +#define SMU7_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS // PCIe speed and number of lanes. +#define SMU7_MAX_LEVELS_UVD 8 // VCLK/DCLK levels for UVD. +#define SMU7_MAX_LEVELS_VCE 8 // ECLK levels for VCE. +#define SMU7_MAX_LEVELS_ACP 8 // ACLK levels for ACP. +#define SMU7_MAX_LEVELS_SAMU 8 // SAMCLK levels for SAMU. +#define SMU7_MAX_ENTRIES_SMIO 32 // Number of entries in SMIO table. + +#define DPM_NO_LIMIT 0 +#define DPM_NO_UP 1 +#define DPM_GO_DOWN 2 +#define DPM_GO_UP 3 + +#define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0 +#define SMU7_FIRST_DPM_MEMORY_LEVEL 0 + +#define GPIO_CLAMP_MODE_VRHOT 1 +#define GPIO_CLAMP_MODE_THERM 2 +#define GPIO_CLAMP_MODE_DC 4 + +#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0 +#define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT) +#define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3 +#define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT) +#define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6 +#define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT) +#define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9 +#define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT) +#define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12 +#define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT) +#define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15 +#define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT) +#define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18 +#define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT) +#define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21 +#define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT) +#define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24 +#define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT) +#define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27 +#define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT) + + +struct SMU7_PIDController +{ + uint32_t Ki; + int32_t LFWindupUL; + int32_t LFWindupLL; + uint32_t StatePrecision; + uint32_t LfPrecision; + uint32_t LfOffset; + uint32_t MaxState; + uint32_t MaxLfFraction; + uint32_t StateShift; +}; + +typedef struct SMU7_PIDController SMU7_PIDController; + +// ------------------------------------------------------------------------------------------------------------------------- +#define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */ + +#define SMU7_SCLK_DPM_CONFIG_MASK 0x01 +#define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02 +#define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04 +#define SMU7_MCLK_DPM_CONFIG_MASK 0x08 +#define SMU7_UVD_DPM_CONFIG_MASK 0x10 +#define SMU7_VCE_DPM_CONFIG_MASK 0x20 +#define SMU7_ACP_DPM_CONFIG_MASK 0x40 +#define SMU7_SAMU_DPM_CONFIG_MASK 0x80 +#define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100 + +#define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001 +#define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002 +#define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100 +#define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200 +#define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000 +#define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000 + +struct SMU7_Firmware_Header +{ + uint32_t Digest[5]; + uint32_t Version; + uint32_t HeaderSize; + uint32_t Flags; + uint32_t EntryPoint; + uint32_t CodeSize; + uint32_t ImageSize; + + uint32_t Rtos; + uint32_t SoftRegisters; + uint32_t DpmTable; + uint32_t FanTable; + uint32_t CacConfigTable; + uint32_t CacStatusTable; + + uint32_t mcRegisterTable; + + uint32_t mcArbDramTimingTable; + + uint32_t PmFuseTable; + uint32_t Globals; + uint32_t Reserved[42]; + uint32_t Signature; +}; + +typedef struct SMU7_Firmware_Header SMU7_Firmware_Header; + +#define SMU7_FIRMWARE_HEADER_LOCATION 0x20000 + +enum DisplayConfig { + PowerDown = 1, + DP54x4, + DP54x2, + DP54x1, + DP27x4, + DP27x2, + DP27x1, + HDMI297, + HDMI162, + LVDS, + DP324x4, + DP324x2, + DP324x1 +}; + +#pragma pack(pop) + +#endif + diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu72.h b/drivers/gpu/drm/amd/powerplay/inc/smu72.h new file mode 100644 index 000000000000..b73d6b59ac32 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/smu72.h @@ -0,0 +1,664 @@ +#ifndef SMU72_H +#define SMU72_H + +#if !defined(SMC_MICROCODE) +#pragma pack(push, 1) +#endif + +#define SMU__NUM_SCLK_DPM_STATE 8 +#define SMU__NUM_MCLK_DPM_LEVELS 4 +#define SMU__NUM_LCLK_DPM_LEVELS 8 +#define SMU__NUM_PCIE_DPM_LEVELS 8 + +enum SID_OPTION { + SID_OPTION_HI, + SID_OPTION_LO, + SID_OPTION_COUNT +}; + +enum Poly3rdOrderCoeff { + LEAKAGE_TEMPERATURE_SCALAR, + LEAKAGE_VOLTAGE_SCALAR, + DYNAMIC_VOLTAGE_SCALAR, + POLY_3RD_ORDER_COUNT +}; + +struct SMU7_Poly3rdOrder_Data { + int32_t a; + int32_t b; + int32_t c; + int32_t d; + uint8_t a_shift; + uint8_t b_shift; + uint8_t c_shift; + uint8_t x_shift; +}; + +typedef struct SMU7_Poly3rdOrder_Data SMU7_Poly3rdOrder_Data; + +struct Power_Calculator_Data { + uint16_t NoLoadVoltage; + uint16_t LoadVoltage; + uint16_t Resistance; + uint16_t Temperature; + uint16_t BaseLeakage; + uint16_t LkgTempScalar; + uint16_t LkgVoltScalar; + uint16_t LkgAreaScalar; + uint16_t LkgPower; + uint16_t DynVoltScalar; + uint32_t Cac; + uint32_t DynPower; + uint32_t TotalCurrent; + uint32_t TotalPower; +}; + +typedef struct Power_Calculator_Data PowerCalculatorData_t; + +struct Gc_Cac_Weight_Data { + uint8_t index; + uint32_t value; +}; + +typedef struct Gc_Cac_Weight_Data GcCacWeight_Data; + + +typedef struct { + uint32_t high; + uint32_t low; +} data_64_t; + +typedef struct { + data_64_t high; + data_64_t low; +} data_128_t; + +#define SMU7_CONTEXT_ID_SMC 1 +#define SMU7_CONTEXT_ID_VBIOS 2 + +#define SMU72_MAX_LEVELS_VDDC 16 +#define SMU72_MAX_LEVELS_VDDGFX 16 +#define SMU72_MAX_LEVELS_VDDCI 8 +#define SMU72_MAX_LEVELS_MVDD 4 + +#define SMU_MAX_SMIO_LEVELS 4 + +#define SMU72_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE /* SCLK + SQ DPM + ULV */ +#define SMU72_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS /* MCLK Levels DPM */ +#define SMU72_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS /* LCLK Levels */ +#define SMU72_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS /* PCIe speed and number of lanes. */ +#define SMU72_MAX_LEVELS_UVD 8 /* VCLK/DCLK levels for UVD. */ +#define SMU72_MAX_LEVELS_VCE 8 /* ECLK levels for VCE. */ +#define SMU72_MAX_LEVELS_ACP 8 /* ACLK levels for ACP. */ +#define SMU72_MAX_LEVELS_SAMU 8 /* SAMCLK levels for SAMU. */ +#define SMU72_MAX_ENTRIES_SMIO 32 /* Number of entries in SMIO table. */ + +#define DPM_NO_LIMIT 0 +#define DPM_NO_UP 1 +#define DPM_GO_DOWN 2 +#define DPM_GO_UP 3 + +#define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0 +#define SMU7_FIRST_DPM_MEMORY_LEVEL 0 + +#define GPIO_CLAMP_MODE_VRHOT 1 +#define GPIO_CLAMP_MODE_THERM 2 +#define GPIO_CLAMP_MODE_DC 4 + +#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0 +#define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT) +#define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3 +#define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT) +#define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6 +#define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT) +#define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9 +#define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT) +#define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12 +#define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT) +#define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15 +#define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT) +#define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18 +#define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT) +#define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21 +#define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT) +#define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24 +#define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT) +#define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27 +#define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT) + +/* Virtualization Defines */ +#define CG_XDMA_MASK 0x1 +#define CG_XDMA_SHIFT 0 +#define CG_UVD_MASK 0x2 +#define CG_UVD_SHIFT 1 +#define CG_VCE_MASK 0x4 +#define CG_VCE_SHIFT 2 +#define CG_SAMU_MASK 0x8 +#define CG_SAMU_SHIFT 3 +#define CG_GFX_MASK 0x10 +#define CG_GFX_SHIFT 4 +#define CG_SDMA_MASK 0x20 +#define CG_SDMA_SHIFT 5 +#define CG_HDP_MASK 0x40 +#define CG_HDP_SHIFT 6 +#define CG_MC_MASK 0x80 +#define CG_MC_SHIFT 7 +#define CG_DRM_MASK 0x100 +#define CG_DRM_SHIFT 8 +#define CG_ROM_MASK 0x200 +#define CG_ROM_SHIFT 9 +#define CG_BIF_MASK 0x400 +#define CG_BIF_SHIFT 10 + +#define SMU72_DTE_ITERATIONS 5 +#define SMU72_DTE_SOURCES 3 +#define SMU72_DTE_SINKS 1 +#define SMU72_NUM_CPU_TES 0 +#define SMU72_NUM_GPU_TES 1 +#define SMU72_NUM_NON_TES 2 +#define SMU72_DTE_FAN_SCALAR_MIN 0x100 +#define SMU72_DTE_FAN_SCALAR_MAX 0x166 +#define SMU72_DTE_FAN_TEMP_MAX 93 +#define SMU72_DTE_FAN_TEMP_MIN 83 + +#if defined SMU__FUSION_ONLY +#define SMU7_DTE_ITERATIONS 5 +#define SMU7_DTE_SOURCES 5 +#define SMU7_DTE_SINKS 3 +#define SMU7_NUM_CPU_TES 2 +#define SMU7_NUM_GPU_TES 1 +#define SMU7_NUM_NON_TES 2 +#endif + +struct SMU7_HystController_Data { + uint8_t waterfall_up; + uint8_t waterfall_down; + uint8_t waterfall_limit; + uint8_t spare; + uint16_t release_cnt; + uint16_t release_limit; +}; + +typedef struct SMU7_HystController_Data SMU7_HystController_Data; + +struct SMU72_PIDController { + uint32_t Ki; + int32_t LFWindupUpperLim; + int32_t LFWindupLowerLim; + uint32_t StatePrecision; + uint32_t LfPrecision; + uint32_t LfOffset; + uint32_t MaxState; + uint32_t MaxLfFraction; + uint32_t StateShift; +}; + +typedef struct SMU72_PIDController SMU72_PIDController; + +struct SMU7_LocalDpmScoreboard { + uint32_t PercentageBusy; + + int32_t PIDError; + int32_t PIDIntegral; + int32_t PIDOutput; + + uint32_t SigmaDeltaAccum; + uint32_t SigmaDeltaOutput; + uint32_t SigmaDeltaLevel; + + uint32_t UtilizationSetpoint; + + uint8_t TdpClampMode; + uint8_t TdcClampMode; + uint8_t ThermClampMode; + uint8_t VoltageBusy; + + int8_t CurrLevel; + int8_t TargLevel; + uint8_t LevelChangeInProgress; + uint8_t UpHyst; + + uint8_t DownHyst; + uint8_t VoltageDownHyst; + uint8_t DpmEnable; + uint8_t DpmRunning; + + uint8_t DpmForce; + uint8_t DpmForceLevel; + uint8_t DisplayWatermark; + uint8_t McArbIndex; + + uint32_t MinimumPerfSclk; + + uint8_t AcpiReq; + uint8_t AcpiAck; + uint8_t GfxClkSlow; + uint8_t GpioClampMode; /* bit0 = VRHOT: bit1 = THERM: bit2 = DC */ + + uint8_t FpsFilterWeight; + uint8_t EnabledLevelsChange; + uint8_t DteClampMode; + uint8_t FpsClampMode; + + uint16_t LevelResidencyCounters[SMU72_MAX_LEVELS_GRAPHICS]; + uint16_t LevelSwitchCounters[SMU72_MAX_LEVELS_GRAPHICS]; + + void (*TargetStateCalculator)(uint8_t); + void (*SavedTargetStateCalculator)(uint8_t); + + uint16_t AutoDpmInterval; + uint16_t AutoDpmRange; + + uint8_t FpsEnabled; + uint8_t MaxPerfLevel; + uint8_t AllowLowClkInterruptToHost; + uint8_t FpsRunning; + + uint32_t MaxAllowedFrequency; + + uint32_t FilteredSclkFrequency; + uint32_t LastSclkFrequency; + uint32_t FilteredSclkFrequencyCnt; +}; + +typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard; + +#define SMU7_MAX_VOLTAGE_CLIENTS 12 + +typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t); + +struct SMU_VoltageLevel { + uint8_t Vddc; + uint8_t Vddci; + uint8_t VddGfx; + uint8_t Phases; +}; + +typedef struct SMU_VoltageLevel SMU_VoltageLevel; + +struct SMU7_VoltageScoreboard { + SMU_VoltageLevel CurrentVoltage; + SMU_VoltageLevel TargetVoltage; + uint16_t MaxVid; + uint8_t HighestVidOffset; + uint8_t CurrentVidOffset; + + uint8_t ControllerBusy; + uint8_t CurrentVid; + uint8_t CurrentVddciVid; + uint8_t VddGfxShutdown; /* 0 = normal mode, 1 = shut down */ + + SMU_VoltageLevel RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS]; + uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS]; + + uint8_t TargetIndex; + uint8_t Delay; + uint8_t ControllerEnable; + uint8_t ControllerRunning; + uint16_t CurrentStdVoltageHiSidd; + uint16_t CurrentStdVoltageLoSidd; + uint8_t OverrideVoltage; + uint8_t VddcUseUlvOffset; + uint8_t VddGfxUseUlvOffset; + uint8_t padding; + + VoltageChangeHandler_t ChangeVddc; + VoltageChangeHandler_t ChangeVddGfx; + VoltageChangeHandler_t ChangeVddci; + VoltageChangeHandler_t ChangePhase; + VoltageChangeHandler_t ChangeMvdd; + + VoltageChangeHandler_t functionLinks[6]; + + uint8_t *VddcFollower1; + uint8_t *VddcFollower2; + int16_t Driver_OD_RequestedVidOffset1; + int16_t Driver_OD_RequestedVidOffset2; + +}; + +typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard; + +#define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */ + +struct SMU7_PCIeLinkSpeedScoreboard { + uint8_t DpmEnable; + uint8_t DpmRunning; + uint8_t DpmForce; + uint8_t DpmForceLevel; + + uint8_t CurrentLinkSpeed; + uint8_t EnabledLevelsChange; + uint16_t AutoDpmInterval; + + uint16_t AutoDpmRange; + uint16_t AutoDpmCount; + + uint8_t DpmMode; + uint8_t AcpiReq; + uint8_t AcpiAck; + uint8_t CurrentLinkLevel; + +}; + +typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard; + +/* -------------------------------------------------------- CAC table ------------------------------------------------------ */ +#define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16 +#define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16 +#define SMU7_SCALE_I 7 +#define SMU7_SCALE_R 12 + +struct SMU7_PowerScoreboard { + PowerCalculatorData_t VddGfxPowerData[SID_OPTION_COUNT]; + PowerCalculatorData_t VddcPowerData[SID_OPTION_COUNT]; + + uint32_t TotalGpuPower; + uint32_t TdcCurrent; + + uint16_t VddciTotalPower; + uint16_t sparesasfsdfd; + uint16_t Vddr1Power; + uint16_t RocPower; + + uint16_t CalcMeasPowerBlend; + uint8_t SidOptionPower; + uint8_t SidOptionCurrent; + + uint32_t WinTime; + + uint16_t Telemetry_1_slope; + uint16_t Telemetry_2_slope; + int32_t Telemetry_1_offset; + int32_t Telemetry_2_offset; + + uint32_t VddcCurrentTelemetry; + uint32_t VddGfxCurrentTelemetry; + uint32_t VddcPowerTelemetry; + uint32_t VddGfxPowerTelemetry; + uint32_t VddciPowerTelemetry; + + uint32_t VddcPower; + uint32_t VddGfxPower; + uint32_t VddciPower; + + uint32_t TelemetryCurrent[2]; + uint32_t TelemetryVoltage[2]; + uint32_t TelemetryPower[2]; +}; + +typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard; + +struct SMU7_ThermalScoreboard { + int16_t GpuLimit; + int16_t GpuHyst; + uint16_t CurrGnbTemp; + uint16_t FilteredGnbTemp; + + uint8_t ControllerEnable; + uint8_t ControllerRunning; + uint8_t AutoTmonCalInterval; + uint8_t AutoTmonCalEnable; + + uint8_t ThermalDpmEnabled; + uint8_t SclkEnabledMask; + uint8_t spare[2]; + int32_t temperature_gradient; + + SMU7_HystController_Data HystControllerData; + int32_t WeightedSensorTemperature; + uint16_t TemperatureLimit[SMU72_MAX_LEVELS_GRAPHICS]; + uint32_t Alpha; +}; + +typedef struct SMU7_ThermalScoreboard SMU7_ThermalScoreboard; + +/* For FeatureEnables: */ +#define SMU7_SCLK_DPM_CONFIG_MASK 0x01 +#define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02 +#define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04 +#define SMU7_MCLK_DPM_CONFIG_MASK 0x08 +#define SMU7_UVD_DPM_CONFIG_MASK 0x10 +#define SMU7_VCE_DPM_CONFIG_MASK 0x20 +#define SMU7_ACP_DPM_CONFIG_MASK 0x40 +#define SMU7_SAMU_DPM_CONFIG_MASK 0x80 +#define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100 + +#define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001 +#define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002 +#define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100 +#define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200 +#define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000 +#define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000 + +/* All 'soft registers' should be uint32_t. */ +struct SMU72_SoftRegisters { + uint32_t RefClockFrequency; + uint32_t PmTimerPeriod; + uint32_t FeatureEnables; + + uint32_t PreVBlankGap; + uint32_t VBlankTimeout; + uint32_t TrainTimeGap; + + uint32_t MvddSwitchTime; + uint32_t LongestAcpiTrainTime; + uint32_t AcpiDelay; + uint32_t G5TrainTime; + uint32_t DelayMpllPwron; + uint32_t VoltageChangeTimeout; + + uint32_t HandshakeDisables; + + uint8_t DisplayPhy1Config; + uint8_t DisplayPhy2Config; + uint8_t DisplayPhy3Config; + uint8_t DisplayPhy4Config; + + uint8_t DisplayPhy5Config; + uint8_t DisplayPhy6Config; + uint8_t DisplayPhy7Config; + uint8_t DisplayPhy8Config; + + uint32_t AverageGraphicsActivity; + uint32_t AverageMemoryActivity; + uint32_t AverageGioActivity; + + uint8_t SClkDpmEnabledLevels; + uint8_t MClkDpmEnabledLevels; + uint8_t LClkDpmEnabledLevels; + uint8_t PCIeDpmEnabledLevels; + + uint8_t UVDDpmEnabledLevels; + uint8_t SAMUDpmEnabledLevels; + uint8_t ACPDpmEnabledLevels; + uint8_t VCEDpmEnabledLevels; + + uint32_t DRAM_LOG_ADDR_H; + uint32_t DRAM_LOG_ADDR_L; + uint32_t DRAM_LOG_PHY_ADDR_H; + uint32_t DRAM_LOG_PHY_ADDR_L; + uint32_t DRAM_LOG_BUFF_SIZE; + uint32_t UlvEnterCount; + uint32_t UlvTime; + uint32_t UcodeLoadStatus; + uint32_t Reserved[2]; + +}; + +typedef struct SMU72_SoftRegisters SMU72_SoftRegisters; + +struct SMU72_Firmware_Header { + uint32_t Digest[5]; + uint32_t Version; + uint32_t HeaderSize; + uint32_t Flags; + uint32_t EntryPoint; + uint32_t CodeSize; + uint32_t ImageSize; + + uint32_t Rtos; + uint32_t SoftRegisters; + uint32_t DpmTable; + uint32_t FanTable; + uint32_t CacConfigTable; + uint32_t CacStatusTable; + uint32_t mcRegisterTable; + uint32_t mcArbDramTimingTable; + uint32_t PmFuseTable; + uint32_t Globals; + uint32_t ClockStretcherTable; + uint32_t Reserved[41]; + uint32_t Signature; +}; + +typedef struct SMU72_Firmware_Header SMU72_Firmware_Header; + +#define SMU72_FIRMWARE_HEADER_LOCATION 0x20000 + +enum DisplayConfig { + PowerDown = 1, + DP54x4, + DP54x2, + DP54x1, + DP27x4, + DP27x2, + DP27x1, + HDMI297, + HDMI162, + LVDS, + DP324x4, + DP324x2, + DP324x1 +}; + +#define MC_BLOCK_COUNT 1 +#define CPL_BLOCK_COUNT 5 +#define SE_BLOCK_COUNT 15 +#define GC_BLOCK_COUNT 24 + +struct SMU7_Local_Cac { + uint8_t BlockId; + uint8_t SignalId; + uint8_t Threshold; + uint8_t Padding; +}; + +typedef struct SMU7_Local_Cac SMU7_Local_Cac; + +struct SMU7_Local_Cac_Table { + SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT]; + SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT]; + SMU7_Local_Cac SeLocalCac[SE_BLOCK_COUNT]; + SMU7_Local_Cac GcLocalCac[GC_BLOCK_COUNT]; +}; + +typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table; + +#if !defined(SMC_MICROCODE) +#pragma pack(pop) +#endif + +/* Description of Clock Gating bitmask for Tonga: */ +/* System Clock Gating */ +#define CG_SYS_BITMASK_FIRST_BIT 0 /* First bit of Sys CG bitmask */ +#define CG_SYS_BITMASK_LAST_BIT 9 /* Last bit of Sys CG bitmask */ +#define CG_SYS_BIF_MGLS_SHIFT 0 +#define CG_SYS_ROM_SHIFT 1 +#define CG_SYS_MC_MGCG_SHIFT 2 +#define CG_SYS_MC_MGLS_SHIFT 3 +#define CG_SYS_SDMA_MGCG_SHIFT 4 +#define CG_SYS_SDMA_MGLS_SHIFT 5 +#define CG_SYS_DRM_MGCG_SHIFT 6 +#define CG_SYS_HDP_MGCG_SHIFT 7 +#define CG_SYS_HDP_MGLS_SHIFT 8 +#define CG_SYS_DRM_MGLS_SHIFT 9 + +#define CG_SYS_BIF_MGLS_MASK 0x1 +#define CG_SYS_ROM_MASK 0x2 +#define CG_SYS_MC_MGCG_MASK 0x4 +#define CG_SYS_MC_MGLS_MASK 0x8 +#define CG_SYS_SDMA_MGCG_MASK 0x10 +#define CG_SYS_SDMA_MGLS_MASK 0x20 +#define CG_SYS_DRM_MGCG_MASK 0x40 +#define CG_SYS_HDP_MGCG_MASK 0x80 +#define CG_SYS_HDP_MGLS_MASK 0x100 +#define CG_SYS_DRM_MGLS_MASK 0x200 + +/* Graphics Clock Gating */ +#define CG_GFX_BITMASK_FIRST_BIT 16 /* First bit of Gfx CG bitmask */ +#define CG_GFX_BITMASK_LAST_BIT 20 /* Last bit of Gfx CG bitmask */ +#define CG_GFX_CGCG_SHIFT 16 +#define CG_GFX_CGLS_SHIFT 17 +#define CG_CPF_MGCG_SHIFT 18 +#define CG_RLC_MGCG_SHIFT 19 +#define CG_GFX_OTHERS_MGCG_SHIFT 20 + +#define CG_GFX_CGCG_MASK 0x00010000 +#define CG_GFX_CGLS_MASK 0x00020000 +#define CG_CPF_MGCG_MASK 0x00040000 +#define CG_RLC_MGCG_MASK 0x00080000 +#define CG_GFX_OTHERS_MGCG_MASK 0x00100000 + +/* Voltage Regulator Configuration */ +/* VR Config info is contained in dpmTable.VRConfig */ + +#define VRCONF_VDDC_MASK 0x000000FF +#define VRCONF_VDDC_SHIFT 0 +#define VRCONF_VDDGFX_MASK 0x0000FF00 +#define VRCONF_VDDGFX_SHIFT 8 +#define VRCONF_VDDCI_MASK 0x00FF0000 +#define VRCONF_VDDCI_SHIFT 16 +#define VRCONF_MVDD_MASK 0xFF000000 +#define VRCONF_MVDD_SHIFT 24 + +#define VR_MERGED_WITH_VDDC 0 +#define VR_SVI2_PLANE_1 1 +#define VR_SVI2_PLANE_2 2 +#define VR_SMIO_PATTERN_1 3 +#define VR_SMIO_PATTERN_2 4 +#define VR_STATIC_VOLTAGE 5 + +/* Clock Stretcher Configuration */ + +#define CLOCK_STRETCHER_MAX_ENTRIES 0x4 +#define CKS_LOOKUPTable_MAX_ENTRIES 0x4 + +/* The 'settings' field is subdivided in the following way: */ +#define CLOCK_STRETCHER_SETTING_DDT_MASK 0x01 +#define CLOCK_STRETCHER_SETTING_DDT_SHIFT 0x0 +#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_MASK 0x1E +#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_SHIFT 0x1 +#define CLOCK_STRETCHER_SETTING_ENABLE_MASK 0x80 +#define CLOCK_STRETCHER_SETTING_ENABLE_SHIFT 0x7 + +struct SMU_ClockStretcherDataTableEntry { + uint8_t minVID; + uint8_t maxVID; + + uint16_t setting; +}; +typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry; + +struct SMU_ClockStretcherDataTable { + SMU_ClockStretcherDataTableEntry ClockStretcherDataTableEntry[CLOCK_STRETCHER_MAX_ENTRIES]; +}; +typedef struct SMU_ClockStretcherDataTable SMU_ClockStretcherDataTable; + +struct SMU_CKS_LOOKUPTableEntry { + uint16_t minFreq; + uint16_t maxFreq; + + uint8_t setting; + uint8_t padding[3]; +}; +typedef struct SMU_CKS_LOOKUPTableEntry SMU_CKS_LOOKUPTableEntry; + +struct SMU_CKS_LOOKUPTable { + SMU_CKS_LOOKUPTableEntry CKS_LOOKUPTableEntry[CKS_LOOKUPTable_MAX_ENTRIES]; +}; +typedef struct SMU_CKS_LOOKUPTable SMU_CKS_LOOKUPTable; + +#endif + + diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h b/drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h new file mode 100644 index 000000000000..98f76e925e65 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h @@ -0,0 +1,760 @@ +#ifndef SMU72_DISCRETE_H +#define SMU72_DISCRETE_H + +#include "smu72.h" + +#if !defined(SMC_MICROCODE) +#pragma pack(push, 1) +#endif + +struct SMIO_Pattern { + uint16_t Voltage; + uint8_t Smio; + uint8_t padding; +}; + +typedef struct SMIO_Pattern SMIO_Pattern; + +struct SMIO_Table { + SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS]; +}; + +typedef struct SMIO_Table SMIO_Table; + +struct SMU72_Discrete_GraphicsLevel { + SMU_VoltageLevel MinVoltage; + + uint32_t SclkFrequency; + + uint8_t pcieDpmLevel; + uint8_t DeepSleepDivId; + uint16_t ActivityLevel; + + uint32_t CgSpllFuncCntl3; + uint32_t CgSpllFuncCntl4; + uint32_t SpllSpreadSpectrum; + uint32_t SpllSpreadSpectrum2; + uint32_t CcPwrDynRm; + uint32_t CcPwrDynRm1; + uint8_t SclkDid; + uint8_t DisplayWatermark; + uint8_t EnabledForActivity; + uint8_t EnabledForThrottle; + uint8_t UpHyst; + uint8_t DownHyst; + uint8_t VoltageDownHyst; + uint8_t PowerThrottle; +}; + +typedef struct SMU72_Discrete_GraphicsLevel SMU72_Discrete_GraphicsLevel; + +struct SMU72_Discrete_ACPILevel { + uint32_t Flags; + SMU_VoltageLevel MinVoltage; + uint32_t SclkFrequency; + uint8_t SclkDid; + uint8_t DisplayWatermark; + uint8_t DeepSleepDivId; + uint8_t padding; + uint32_t CgSpllFuncCntl; + uint32_t CgSpllFuncCntl2; + uint32_t CgSpllFuncCntl3; + uint32_t CgSpllFuncCntl4; + uint32_t SpllSpreadSpectrum; + uint32_t SpllSpreadSpectrum2; + uint32_t CcPwrDynRm; + uint32_t CcPwrDynRm1; +}; + +typedef struct SMU72_Discrete_ACPILevel SMU72_Discrete_ACPILevel; + +struct SMU72_Discrete_Ulv { + uint32_t CcPwrDynRm; + uint32_t CcPwrDynRm1; + uint16_t VddcOffset; + uint8_t VddcOffsetVid; + uint8_t VddcPhase; + uint32_t Reserved; +}; + +typedef struct SMU72_Discrete_Ulv SMU72_Discrete_Ulv; + +struct SMU72_Discrete_MemoryLevel { + SMU_VoltageLevel MinVoltage; + uint32_t MinMvdd; + + uint32_t MclkFrequency; + + uint8_t EdcReadEnable; + uint8_t EdcWriteEnable; + uint8_t RttEnable; + uint8_t StutterEnable; + + uint8_t StrobeEnable; + uint8_t StrobeRatio; + uint8_t EnabledForThrottle; + uint8_t EnabledForActivity; + + uint8_t UpHyst; + uint8_t DownHyst; + uint8_t VoltageDownHyst; + uint8_t padding; + + uint16_t ActivityLevel; + uint8_t DisplayWatermark; + uint8_t padding1; + + uint32_t MpllFuncCntl; + uint32_t MpllFuncCntl_1; + uint32_t MpllFuncCntl_2; + uint32_t MpllAdFuncCntl; + uint32_t MpllDqFuncCntl; + uint32_t MclkPwrmgtCntl; + uint32_t DllCntl; + uint32_t MpllSs1; + uint32_t MpllSs2; +}; + +typedef struct SMU72_Discrete_MemoryLevel SMU72_Discrete_MemoryLevel; + +struct SMU72_Discrete_LinkLevel { + uint8_t PcieGenSpeed; /*< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 */ + uint8_t PcieLaneCount; /*< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */ + uint8_t EnabledForActivity; + uint8_t SPC; + uint32_t DownThreshold; + uint32_t UpThreshold; + uint32_t Reserved; +}; + +typedef struct SMU72_Discrete_LinkLevel SMU72_Discrete_LinkLevel; + +/* MC ARB DRAM Timing registers. */ +struct SMU72_Discrete_MCArbDramTimingTableEntry { + uint32_t McArbDramTiming; + uint32_t McArbDramTiming2; + uint8_t McArbBurstTime; + uint8_t padding[3]; +}; + +typedef struct SMU72_Discrete_MCArbDramTimingTableEntry SMU72_Discrete_MCArbDramTimingTableEntry; + +struct SMU72_Discrete_MCArbDramTimingTable { + SMU72_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS]; +}; + +typedef struct SMU72_Discrete_MCArbDramTimingTable SMU72_Discrete_MCArbDramTimingTable; + +/* UVD VCLK/DCLK state (level) definition. */ +struct SMU72_Discrete_UvdLevel { + uint32_t VclkFrequency; + uint32_t DclkFrequency; + SMU_VoltageLevel MinVoltage; + uint8_t VclkDivider; + uint8_t DclkDivider; + uint8_t padding[2]; +}; + +typedef struct SMU72_Discrete_UvdLevel SMU72_Discrete_UvdLevel; + +/* Clocks for other external blocks (VCE, ACP, SAMU). */ +struct SMU72_Discrete_ExtClkLevel { + uint32_t Frequency; + SMU_VoltageLevel MinVoltage; + uint8_t Divider; + uint8_t padding[3]; +}; + +typedef struct SMU72_Discrete_ExtClkLevel SMU72_Discrete_ExtClkLevel; + +struct SMU72_Discrete_StateInfo { + uint32_t SclkFrequency; + uint32_t MclkFrequency; + uint32_t VclkFrequency; + uint32_t DclkFrequency; + uint32_t SamclkFrequency; + uint32_t AclkFrequency; + uint32_t EclkFrequency; + uint16_t MvddVoltage; + uint16_t padding16; + uint8_t DisplayWatermark; + uint8_t McArbIndex; + uint8_t McRegIndex; + uint8_t SeqIndex; + uint8_t SclkDid; + int8_t SclkIndex; + int8_t MclkIndex; + uint8_t PCIeGen; + +}; + +typedef struct SMU72_Discrete_StateInfo SMU72_Discrete_StateInfo; + +struct SMU72_Discrete_DpmTable { + /* Multi-DPM controller settings */ + SMU72_PIDController GraphicsPIDController; + SMU72_PIDController MemoryPIDController; + SMU72_PIDController LinkPIDController; + + uint32_t SystemFlags; + + /* SMIO masks for voltage and phase controls */ + uint32_t VRConfig; + uint32_t SmioMask1; + uint32_t SmioMask2; + SMIO_Table SmioTable1; + SMIO_Table SmioTable2; + + uint32_t VddcLevelCount; + uint32_t VddciLevelCount; + uint32_t VddGfxLevelCount; + uint32_t MvddLevelCount; + + uint16_t VddcTable[SMU72_MAX_LEVELS_VDDC]; + uint16_t VddGfxTable[SMU72_MAX_LEVELS_VDDGFX]; + uint16_t VddciTable[SMU72_MAX_LEVELS_VDDCI]; + + uint8_t BapmVddGfxVidHiSidd[SMU72_MAX_LEVELS_VDDGFX]; + uint8_t BapmVddGfxVidLoSidd[SMU72_MAX_LEVELS_VDDGFX]; + uint8_t BapmVddGfxVidHiSidd2[SMU72_MAX_LEVELS_VDDGFX]; + + uint8_t BapmVddcVidHiSidd[SMU72_MAX_LEVELS_VDDC]; + uint8_t BapmVddcVidLoSidd[SMU72_MAX_LEVELS_VDDC]; + uint8_t BapmVddcVidHiSidd2[SMU72_MAX_LEVELS_VDDC]; + + uint8_t GraphicsDpmLevelCount; + uint8_t MemoryDpmLevelCount; + uint8_t LinkLevelCount; + uint8_t MasterDeepSleepControl; + + uint8_t UvdLevelCount; + uint8_t VceLevelCount; + uint8_t AcpLevelCount; + uint8_t SamuLevelCount; + + uint8_t ThermOutGpio; + uint8_t ThermOutPolarity; + uint8_t ThermOutMode; + uint8_t DPMFreezeAndForced; + uint32_t Reserved[4]; + + /* State table entries for each DPM state */ + SMU72_Discrete_GraphicsLevel GraphicsLevel[SMU72_MAX_LEVELS_GRAPHICS]; + SMU72_Discrete_MemoryLevel MemoryACPILevel; + SMU72_Discrete_MemoryLevel MemoryLevel[SMU72_MAX_LEVELS_MEMORY]; + SMU72_Discrete_LinkLevel LinkLevel[SMU72_MAX_LEVELS_LINK]; + SMU72_Discrete_ACPILevel ACPILevel; + SMU72_Discrete_UvdLevel UvdLevel[SMU72_MAX_LEVELS_UVD]; + SMU72_Discrete_ExtClkLevel VceLevel[SMU72_MAX_LEVELS_VCE]; + SMU72_Discrete_ExtClkLevel AcpLevel[SMU72_MAX_LEVELS_ACP]; + SMU72_Discrete_ExtClkLevel SamuLevel[SMU72_MAX_LEVELS_SAMU]; + SMU72_Discrete_Ulv Ulv; + + uint32_t SclkStepSize; + uint32_t Smio[SMU72_MAX_ENTRIES_SMIO]; + + uint8_t UvdBootLevel; + uint8_t VceBootLevel; + uint8_t AcpBootLevel; + uint8_t SamuBootLevel; + + uint8_t GraphicsBootLevel; + uint8_t GraphicsVoltageChangeEnable; + uint8_t GraphicsThermThrottleEnable; + uint8_t GraphicsInterval; + + uint8_t VoltageInterval; + uint8_t ThermalInterval; + uint16_t TemperatureLimitHigh; + + uint16_t TemperatureLimitLow; + uint8_t MemoryBootLevel; + uint8_t MemoryVoltageChangeEnable; + + uint16_t BootMVdd; + uint8_t MemoryInterval; + uint8_t MemoryThermThrottleEnable; + + uint16_t VoltageResponseTime; + uint16_t PhaseResponseTime; + + uint8_t PCIeBootLinkLevel; + uint8_t PCIeGenInterval; + uint8_t DTEInterval; + uint8_t DTEMode; + + uint8_t SVI2Enable; + uint8_t VRHotGpio; + uint8_t AcDcGpio; + uint8_t ThermGpio; + + uint16_t PPM_PkgPwrLimit; + uint16_t PPM_TemperatureLimit; + + uint16_t DefaultTdp; + uint16_t TargetTdp; + + uint16_t FpsHighThreshold; + uint16_t FpsLowThreshold; + + uint16_t BAPMTI_R[SMU72_DTE_ITERATIONS][SMU72_DTE_SOURCES][SMU72_DTE_SINKS]; + uint16_t BAPMTI_RC[SMU72_DTE_ITERATIONS][SMU72_DTE_SOURCES][SMU72_DTE_SINKS]; + + uint8_t DTEAmbientTempBase; + uint8_t DTETjOffset; + uint8_t GpuTjMax; + uint8_t GpuTjHyst; + + SMU_VoltageLevel BootVoltage; + + uint32_t BAPM_TEMP_GRADIENT; + + uint32_t LowSclkInterruptThreshold; + uint32_t VddGfxReChkWait; + + uint8_t ClockStretcherAmount; + + uint8_t Sclk_CKS_masterEn0_7; + uint8_t Sclk_CKS_masterEn8_15; + uint8_t padding[1]; + + uint8_t Sclk_voltageOffset[8]; + + SMU_ClockStretcherDataTable ClockStretcherDataTable; + SMU_CKS_LOOKUPTable CKS_LOOKUPTable; +}; + +typedef struct SMU72_Discrete_DpmTable SMU72_Discrete_DpmTable; + +/* --------------------------------------------------- AC Timing Parameters ------------------------------------------------ */ +#define SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE 16 +#define SMU72_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU72_MAX_LEVELS_MEMORY /* DPM */ + +struct SMU72_Discrete_MCRegisterAddress { + uint16_t s0; + uint16_t s1; +}; + +typedef struct SMU72_Discrete_MCRegisterAddress SMU72_Discrete_MCRegisterAddress; + +struct SMU72_Discrete_MCRegisterSet { + uint32_t value[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE]; +}; + +typedef struct SMU72_Discrete_MCRegisterSet SMU72_Discrete_MCRegisterSet; + +struct SMU72_Discrete_MCRegisters { + uint8_t last; + uint8_t reserved[3]; + SMU72_Discrete_MCRegisterAddress address[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE]; + SMU72_Discrete_MCRegisterSet data[SMU72_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT]; +}; + +typedef struct SMU72_Discrete_MCRegisters SMU72_Discrete_MCRegisters; + + +/* --------------------------------------------------- Fan Table ----------------------------------------------------------- */ + +struct SMU72_Discrete_FanTable { + uint16_t FdoMode; + int16_t TempMin; + int16_t TempMed; + int16_t TempMax; + int16_t Slope1; + int16_t Slope2; + int16_t FdoMin; + int16_t HystUp; + int16_t HystDown; + int16_t HystSlope; + int16_t TempRespLim; + int16_t TempCurr; + int16_t SlopeCurr; + int16_t PwmCurr; + uint32_t RefreshPeriod; + int16_t FdoMax; + uint8_t TempSrc; + int8_t FanControl_GL_Flag; +}; + +typedef struct SMU72_Discrete_FanTable SMU72_Discrete_FanTable; + +#define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4 +#define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG) + +struct SMU7_MclkDpmScoreboard { + + uint32_t PercentageBusy; + + int32_t PIDError; + int32_t PIDIntegral; + int32_t PIDOutput; + + uint32_t SigmaDeltaAccum; + uint32_t SigmaDeltaOutput; + uint32_t SigmaDeltaLevel; + + uint32_t UtilizationSetpoint; + + uint8_t TdpClampMode; + uint8_t TdcClampMode; + uint8_t ThermClampMode; + uint8_t VoltageBusy; + + int8_t CurrLevel; + int8_t TargLevel; + uint8_t LevelChangeInProgress; + uint8_t UpHyst; + + uint8_t DownHyst; + uint8_t VoltageDownHyst; + uint8_t DpmEnable; + uint8_t DpmRunning; + + uint8_t DpmForce; + uint8_t DpmForceLevel; + uint8_t DisplayWatermark; + uint8_t McArbIndex; + + uint32_t MinimumPerfMclk; + + uint8_t AcpiReq; + uint8_t AcpiAck; + uint8_t MclkSwitchInProgress; + uint8_t MclkSwitchCritical; + + uint8_t IgnoreVBlank; + uint8_t TargetMclkIndex; + uint8_t TargetMvddIndex; + uint8_t MclkSwitchResult; + + uint16_t VbiFailureCount; + uint8_t VbiWaitCounter; + uint8_t EnabledLevelsChange; + + uint16_t LevelResidencyCountersN[SMU72_MAX_LEVELS_MEMORY]; + uint16_t LevelSwitchCounters[SMU72_MAX_LEVELS_MEMORY]; + + void (*TargetStateCalculator)(uint8_t); + void (*SavedTargetStateCalculator)(uint8_t); + + uint16_t AutoDpmInterval; + uint16_t AutoDpmRange; + + uint16_t VbiTimeoutCount; + uint16_t MclkSwitchingTime; + + uint8_t fastSwitch; + uint8_t Save_PIC_VDDGFX_EXIT; + uint8_t Save_PIC_VDDGFX_ENTER; + uint8_t padding; + +}; + +typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard; + +struct SMU7_UlvScoreboard { + uint8_t EnterUlv; + uint8_t ExitUlv; + uint8_t UlvActive; + uint8_t WaitingForUlv; + uint8_t UlvEnable; + uint8_t UlvRunning; + uint8_t UlvMasterEnable; + uint8_t padding; + uint32_t UlvAbortedCount; + uint32_t UlvTimeStamp; +}; + +typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard; + +struct VddgfxSavedRegisters { + uint32_t GPU_DBG[3]; + uint32_t MEC_BaseAddress_Hi; + uint32_t MEC_BaseAddress_Lo; + uint32_t THM_TMON0_CTRL2__RDIR_PRESENT; + uint32_t THM_TMON1_CTRL2__RDIR_PRESENT; + uint32_t CP_INT_CNTL; +}; + +typedef struct VddgfxSavedRegisters VddgfxSavedRegisters; + +struct SMU7_VddGfxScoreboard { + uint8_t VddGfxEnable; + uint8_t VddGfxActive; + uint8_t VPUResetOccured; + uint8_t padding; + + uint32_t VddGfxEnteredCount; + uint32_t VddGfxAbortedCount; + + uint32_t VddGfxVid; + + VddgfxSavedRegisters SavedRegisters; +}; + +typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard; + +struct SMU7_TdcLimitScoreboard { + uint8_t Enable; + uint8_t Running; + uint16_t Alpha; + uint32_t FilteredIddc; + uint32_t IddcLimit; + uint32_t IddcHyst; + SMU7_HystController_Data HystControllerData; +}; + +typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard; + +struct SMU7_PkgPwrLimitScoreboard { + uint8_t Enable; + uint8_t Running; + uint16_t Alpha; + uint32_t FilteredPkgPwr; + uint32_t Limit; + uint32_t Hyst; + uint32_t LimitFromDriver; + SMU7_HystController_Data HystControllerData; +}; + +typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard; + +struct SMU7_BapmScoreboard { + uint32_t source_powers[SMU72_DTE_SOURCES]; + uint32_t source_powers_last[SMU72_DTE_SOURCES]; + int32_t entity_temperatures[SMU72_NUM_GPU_TES]; + int32_t initial_entity_temperatures[SMU72_NUM_GPU_TES]; + int32_t Limit; + int32_t Hyst; + int32_t therm_influence_coeff_table[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS * 2]; + int32_t therm_node_table[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS]; + uint16_t ConfigTDPPowerScalar; + uint16_t FanSpeedPowerScalar; + uint16_t OverDrivePowerScalar; + uint16_t OverDriveLimitScalar; + uint16_t FinalPowerScalar; + uint8_t VariantID; + uint8_t spare997; + + SMU7_HystController_Data HystControllerData; + + int32_t temperature_gradient_slope; + int32_t temperature_gradient; + uint32_t measured_temperature; +}; + + +typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard; + +struct SMU7_AcpiScoreboard { + uint32_t SavedInterruptMask[2]; + uint8_t LastACPIRequest; + uint8_t CgBifResp; + uint8_t RequestType; + uint8_t Padding; + SMU72_Discrete_ACPILevel D0Level; +}; + +typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard; + +struct SMU72_Discrete_PmFuses { + /* dw1 */ + uint8_t SviLoadLineEn; + uint8_t SviLoadLineVddC; + uint8_t SviLoadLineTrimVddC; + uint8_t SviLoadLineOffsetVddC; + + /* dw2 */ + uint16_t TDC_VDDC_PkgLimit; + uint8_t TDC_VDDC_ThrottleReleaseLimitPerc; + uint8_t TDC_MAWt; + + /* dw3 */ + uint8_t TdcWaterfallCtl; + uint8_t LPMLTemperatureMin; + uint8_t LPMLTemperatureMax; + uint8_t Reserved; + + /* dw4-dw7 */ + uint8_t LPMLTemperatureScaler[16]; + + /* dw8-dw9 */ + int16_t FuzzyFan_ErrorSetDelta; + int16_t FuzzyFan_ErrorRateSetDelta; + int16_t FuzzyFan_PwmSetDelta; + uint16_t Reserved6; + + /* dw10-dw14 */ + uint8_t GnbLPML[16]; + + /* dw15 */ + uint8_t GnbLPMLMaxVid; + uint8_t GnbLPMLMinVid; + uint8_t Reserved1[2]; + + /* dw16 */ + uint16_t BapmVddCBaseLeakageHiSidd; + uint16_t BapmVddCBaseLeakageLoSidd; +}; + +typedef struct SMU72_Discrete_PmFuses SMU72_Discrete_PmFuses; + +struct SMU7_Discrete_Log_Header_Table { + uint32_t version; + uint32_t asic_id; + uint16_t flags; + uint16_t entry_size; + uint32_t total_size; + uint32_t num_of_entries; + uint8_t type; + uint8_t mode; + uint8_t filler_0[2]; + uint32_t filler_1[2]; +}; + +typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table; + +struct SMU7_Discrete_Log_Cntl { + uint8_t Enabled; + uint8_t Type; + uint8_t padding[2]; + uint32_t BufferSize; + uint32_t SamplesLogged; + uint32_t SampleSize; + uint32_t AddrL; + uint32_t AddrH; +}; + +typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl; + +#define CAC_ACC_NW_NUM_OF_SIGNALS 87 + +struct SMU7_Discrete_Cac_Collection_Table { + uint32_t temperature; + uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS]; +}; + +typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table; + +struct SMU7_Discrete_Cac_Verification_Table { + uint32_t VddcTotalPower; + uint32_t VddcLeakagePower; + uint32_t VddcConstantPower; + uint32_t VddcGfxDynamicPower; + uint32_t VddcUvdDynamicPower; + uint32_t VddcVceDynamicPower; + uint32_t VddcAcpDynamicPower; + uint32_t VddcPcieDynamicPower; + uint32_t VddcDceDynamicPower; + uint32_t VddcCurrent; + uint32_t VddcVoltage; + uint32_t VddciTotalPower; + uint32_t VddciLeakagePower; + uint32_t VddciConstantPower; + uint32_t VddciDynamicPower; + uint32_t Vddr1TotalPower; + uint32_t Vddr1LeakagePower; + uint32_t Vddr1ConstantPower; + uint32_t Vddr1DynamicPower; + uint32_t spare[4]; + uint32_t temperature; +}; + +typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table; + +struct SMU7_Discrete_Pm_Status_Table { + /* Thermal entities */ + int32_t T_meas_max; + int32_t T_meas_acc; + int32_t T_calc_max; + int32_t T_calc_acc; + uint32_t P_scalar_acc; + uint32_t P_calc_max; + uint32_t P_calc_acc; + + /*Voltage domains */ + uint32_t I_calc_max; + uint32_t I_calc_acc; + uint32_t I_calc_acc_vddci; + uint32_t V_calc_noload_acc; + uint32_t V_calc_load_acc; + uint32_t V_calc_noload_acc_vddci; + uint32_t P_meas_acc; + uint32_t V_meas_noload_acc; + uint32_t V_meas_load_acc; + uint32_t I_meas_acc; + uint32_t P_meas_acc_vddci; + uint32_t V_meas_noload_acc_vddci; + uint32_t V_meas_load_acc_vddci; + uint32_t I_meas_acc_vddci; + + /*Frequency */ + uint16_t Sclk_dpm_residency[8]; + uint16_t Uvd_dpm_residency[8]; + uint16_t Vce_dpm_residency[8]; + uint16_t Mclk_dpm_residency[4]; + + /*Chip */ + uint32_t P_vddci_acc; + uint32_t P_vddr1_acc; + uint32_t P_nte1_acc; + uint32_t PkgPwr_max; + uint32_t PkgPwr_acc; + uint32_t MclkSwitchingTime_max; + uint32_t MclkSwitchingTime_acc; + uint32_t FanPwm_acc; + uint32_t FanRpm_acc; + + uint32_t AccCnt; +}; + +typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table; + +/*FIXME THESE NEED TO BE UPDATED */ +#define SMU7_SCLK_CAC 0x561 +#define SMU7_MCLK_CAC 0xF9 +#define SMU7_VCLK_CAC 0x2DE +#define SMU7_DCLK_CAC 0x2DE +#define SMU7_ECLK_CAC 0x25E +#define SMU7_ACLK_CAC 0x25E +#define SMU7_SAMCLK_CAC 0x25E +#define SMU7_DISPCLK_CAC 0x100 +#define SMU7_CAC_CONSTANT 0x2EE3430 +#define SMU7_CAC_CONSTANT_SHIFT 18 + +#define SMU7_VDDCI_MCLK_CONST 1765 +#define SMU7_VDDCI_MCLK_CONST_SHIFT 16 +#define SMU7_VDDCI_VDDCI_CONST 50958 +#define SMU7_VDDCI_VDDCI_CONST_SHIFT 14 +#define SMU7_VDDCI_CONST 11781 + +#define SMU7_12C_VDDCI_MCLK_CONST 1623 +#define SMU7_12C_VDDCI_MCLK_CONST_SHIFT 15 +#define SMU7_12C_VDDCI_VDDCI_CONST 40088 +#define SMU7_12C_VDDCI_VDDCI_CONST_SHIFT 13 +#define SMU7_12C_VDDCI_CONST 20856 + +#define SMU7_VDDCI_STROBE_PWR 1331 + +#define SMU7_VDDR1_CONST 693 +#define SMU7_VDDR1_CAC_WEIGHT 20 +#define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19 +#define SMU7_VDDR1_STROBE_PWR 512 + +#define SMU7_AREA_COEFF_UVD 0xA78 +#define SMU7_AREA_COEFF_VCE 0x190A +#define SMU7_AREA_COEFF_ACP 0x22D1 +#define SMU7_AREA_COEFF_SAMU 0x534 + +/*ThermOutMode values */ +#define SMU7_THERM_OUT_MODE_DISABLE 0x0 +#define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1 +#define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2 + +#if !defined(SMC_MICROCODE) +#pragma pack(pop) +#endif + + +#endif + diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu73.h b/drivers/gpu/drm/amd/powerplay/inc/smu73.h new file mode 100644 index 000000000000..c6b12a4c00db --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/smu73.h @@ -0,0 +1,720 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _SMU73_H_ +#define _SMU73_H_ + +#pragma pack(push, 1) +enum SID_OPTION { + SID_OPTION_HI, + SID_OPTION_LO, + SID_OPTION_COUNT +}; + +enum Poly3rdOrderCoeff { + LEAKAGE_TEMPERATURE_SCALAR, + LEAKAGE_VOLTAGE_SCALAR, + DYNAMIC_VOLTAGE_SCALAR, + POLY_3RD_ORDER_COUNT +}; + +struct SMU7_Poly3rdOrder_Data +{ + int32_t a; + int32_t b; + int32_t c; + int32_t d; + uint8_t a_shift; + uint8_t b_shift; + uint8_t c_shift; + uint8_t x_shift; +}; + +typedef struct SMU7_Poly3rdOrder_Data SMU7_Poly3rdOrder_Data; + +struct Power_Calculator_Data +{ + uint16_t NoLoadVoltage; + uint16_t LoadVoltage; + uint16_t Resistance; + uint16_t Temperature; + uint16_t BaseLeakage; + uint16_t LkgTempScalar; + uint16_t LkgVoltScalar; + uint16_t LkgAreaScalar; + uint16_t LkgPower; + uint16_t DynVoltScalar; + uint32_t Cac; + uint32_t DynPower; + uint32_t TotalCurrent; + uint32_t TotalPower; +}; + +typedef struct Power_Calculator_Data PowerCalculatorData_t; + +struct Gc_Cac_Weight_Data +{ + uint8_t index; + uint32_t value; +}; + +typedef struct Gc_Cac_Weight_Data GcCacWeight_Data; + + +typedef struct { + uint32_t high; + uint32_t low; +} data_64_t; + +typedef struct { + data_64_t high; + data_64_t low; +} data_128_t; + +#define SMU__NUM_SCLK_DPM_STATE 8 +#define SMU__NUM_MCLK_DPM_LEVELS 4 +#define SMU__NUM_LCLK_DPM_LEVELS 8 +#define SMU__NUM_PCIE_DPM_LEVELS 8 + +#define SMU7_CONTEXT_ID_SMC 1 +#define SMU7_CONTEXT_ID_VBIOS 2 + +#define SMU73_MAX_LEVELS_VDDC 16 +#define SMU73_MAX_LEVELS_VDDGFX 16 +#define SMU73_MAX_LEVELS_VDDCI 8 +#define SMU73_MAX_LEVELS_MVDD 4 + +#define SMU_MAX_SMIO_LEVELS 4 + +#define SMU73_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE // SCLK + SQ DPM + ULV +#define SMU73_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS // MCLK Levels DPM +#define SMU73_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS // LCLK Levels +#define SMU73_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS // PCIe speed and number of lanes. +#define SMU73_MAX_LEVELS_UVD 8 // VCLK/DCLK levels for UVD. +#define SMU73_MAX_LEVELS_VCE 8 // ECLK levels for VCE. +#define SMU73_MAX_LEVELS_ACP 8 // ACLK levels for ACP. +#define SMU73_MAX_LEVELS_SAMU 8 // SAMCLK levels for SAMU. +#define SMU73_MAX_ENTRIES_SMIO 32 // Number of entries in SMIO table. + +#define DPM_NO_LIMIT 0 +#define DPM_NO_UP 1 +#define DPM_GO_DOWN 2 +#define DPM_GO_UP 3 + +#define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0 +#define SMU7_FIRST_DPM_MEMORY_LEVEL 0 + +#define GPIO_CLAMP_MODE_VRHOT 1 +#define GPIO_CLAMP_MODE_THERM 2 +#define GPIO_CLAMP_MODE_DC 4 + +#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0 +#define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT) +#define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3 +#define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT) +#define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6 +#define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT) +#define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9 +#define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT) +#define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12 +#define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT) +#define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15 +#define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT) +#define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18 +#define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT) +#define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21 +#define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT) +#define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24 +#define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT) +#define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27 +#define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT) + +// Virtualization Defines +#define CG_XDMA_MASK 0x1 +#define CG_XDMA_SHIFT 0 +#define CG_UVD_MASK 0x2 +#define CG_UVD_SHIFT 1 +#define CG_VCE_MASK 0x4 +#define CG_VCE_SHIFT 2 +#define CG_SAMU_MASK 0x8 +#define CG_SAMU_SHIFT 3 +#define CG_GFX_MASK 0x10 +#define CG_GFX_SHIFT 4 +#define CG_SDMA_MASK 0x20 +#define CG_SDMA_SHIFT 5 +#define CG_HDP_MASK 0x40 +#define CG_HDP_SHIFT 6 +#define CG_MC_MASK 0x80 +#define CG_MC_SHIFT 7 +#define CG_DRM_MASK 0x100 +#define CG_DRM_SHIFT 8 +#define CG_ROM_MASK 0x200 +#define CG_ROM_SHIFT 9 +#define CG_BIF_MASK 0x400 +#define CG_BIF_SHIFT 10 + +#define SMU73_DTE_ITERATIONS 5 +#define SMU73_DTE_SOURCES 3 +#define SMU73_DTE_SINKS 1 +#define SMU73_NUM_CPU_TES 0 +#define SMU73_NUM_GPU_TES 1 +#define SMU73_NUM_NON_TES 2 +#define SMU73_DTE_FAN_SCALAR_MIN 0x100 +#define SMU73_DTE_FAN_SCALAR_MAX 0x166 +#define SMU73_DTE_FAN_TEMP_MAX 93 +#define SMU73_DTE_FAN_TEMP_MIN 83 + +#define SMU73_THERMAL_INPUT_LOOP_COUNT 6 +#define SMU73_THERMAL_CLAMP_MODE_COUNT 8 + + +struct SMU7_HystController_Data +{ + uint16_t waterfall_up; + uint16_t waterfall_down; + uint16_t waterfall_limit; + uint16_t release_cnt; + uint16_t release_limit; + uint16_t spare; +}; + +typedef struct SMU7_HystController_Data SMU7_HystController_Data; + +struct SMU73_PIDController +{ + uint32_t Ki; + int32_t LFWindupUpperLim; + int32_t LFWindupLowerLim; + uint32_t StatePrecision; + + uint32_t LfPrecision; + uint32_t LfOffset; + uint32_t MaxState; + uint32_t MaxLfFraction; + uint32_t StateShift; +}; + +typedef struct SMU73_PIDController SMU73_PIDController; + +struct SMU7_LocalDpmScoreboard +{ + uint32_t PercentageBusy; + + int32_t PIDError; + int32_t PIDIntegral; + int32_t PIDOutput; + + uint32_t SigmaDeltaAccum; + uint32_t SigmaDeltaOutput; + uint32_t SigmaDeltaLevel; + + uint32_t UtilizationSetpoint; + + uint8_t TdpClampMode; + uint8_t TdcClampMode; + uint8_t ThermClampMode; + uint8_t VoltageBusy; + + int8_t CurrLevel; + int8_t TargLevel; + uint8_t LevelChangeInProgress; + uint8_t UpHyst; + + uint8_t DownHyst; + uint8_t VoltageDownHyst; + uint8_t DpmEnable; + uint8_t DpmRunning; + + uint8_t DpmForce; + uint8_t DpmForceLevel; + uint8_t DisplayWatermark; + uint8_t McArbIndex; + + uint32_t MinimumPerfSclk; + + uint8_t AcpiReq; + uint8_t AcpiAck; + uint8_t GfxClkSlow; + uint8_t GpioClampMode; + + uint8_t spare2; + uint8_t EnabledLevelsChange; + uint8_t DteClampMode; + uint8_t FpsClampMode; + + uint16_t LevelResidencyCounters [SMU73_MAX_LEVELS_GRAPHICS]; + uint16_t LevelSwitchCounters [SMU73_MAX_LEVELS_GRAPHICS]; + + void (*TargetStateCalculator)(uint8_t); + void (*SavedTargetStateCalculator)(uint8_t); + + uint16_t AutoDpmInterval; + uint16_t AutoDpmRange; + + uint8_t FpsEnabled; + uint8_t MaxPerfLevel; + uint8_t AllowLowClkInterruptToHost; + uint8_t FpsRunning; + + uint32_t MaxAllowedFrequency; + + uint32_t FilteredSclkFrequency; + uint32_t LastSclkFrequency; + uint32_t FilteredSclkFrequencyCnt; + + uint8_t LedEnable; + uint8_t LedPin0; + uint8_t LedPin1; + uint8_t LedPin2; + uint32_t LedAndMask; + + uint16_t FpsAlpha; + uint16_t DeltaTime; + uint32_t CurrentFps; + uint32_t FilteredFps; + uint32_t FrameCount; + uint32_t FrameCountLast; + uint16_t FpsTargetScalar; + uint16_t FpsWaterfallLimitScalar; + uint16_t FpsAlphaScalar; + uint16_t spare8; + SMU7_HystController_Data HystControllerData; +}; + +typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard; + +#define SMU7_MAX_VOLTAGE_CLIENTS 12 + +typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t); + +#define VDDC_MASK 0x00007FFF +#define VDDC_SHIFT 0 +#define VDDCI_MASK 0x3FFF8000 +#define VDDCI_SHIFT 15 +#define PHASES_MASK 0xC0000000 +#define PHASES_SHIFT 30 + +typedef uint32_t SMU_VoltageLevel; + +struct SMU7_VoltageScoreboard +{ + SMU_VoltageLevel TargetVoltage; + uint16_t MaxVid; + uint8_t HighestVidOffset; + uint8_t CurrentVidOffset; + + uint16_t CurrentVddc; + uint16_t CurrentVddci; + + + uint8_t ControllerBusy; + uint8_t CurrentVid; + uint8_t CurrentVddciVid; + uint8_t padding; + + SMU_VoltageLevel RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS]; + SMU_VoltageLevel TargetVoltageState; + uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS]; + + uint8_t padding2; + uint8_t padding3; + uint8_t ControllerEnable; + uint8_t ControllerRunning; + uint16_t CurrentStdVoltageHiSidd; + uint16_t CurrentStdVoltageLoSidd; + uint8_t OverrideVoltage; + uint8_t padding4; + uint8_t padding5; + uint8_t CurrentPhases; + + VoltageChangeHandler_t ChangeVddc; + + VoltageChangeHandler_t ChangeVddci; + VoltageChangeHandler_t ChangePhase; + VoltageChangeHandler_t ChangeMvdd; + + VoltageChangeHandler_t functionLinks[6]; + + uint16_t * VddcFollower1; + + int16_t Driver_OD_RequestedVidOffset1; + int16_t Driver_OD_RequestedVidOffset2; + +}; + +typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard; + +// ------------------------------------------------------------------------------------------------------------------------- +#define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */ + +struct SMU7_PCIeLinkSpeedScoreboard +{ + uint8_t DpmEnable; + uint8_t DpmRunning; + uint8_t DpmForce; + uint8_t DpmForceLevel; + + uint8_t CurrentLinkSpeed; + uint8_t EnabledLevelsChange; + uint16_t AutoDpmInterval; + + uint16_t AutoDpmRange; + uint16_t AutoDpmCount; + + uint8_t DpmMode; + uint8_t AcpiReq; + uint8_t AcpiAck; + uint8_t CurrentLinkLevel; + +}; + +typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard; + +// -------------------------------------------------------- CAC table ------------------------------------------------------ +#define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16 +#define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16 + +#define SMU7_SCALE_I 7 +#define SMU7_SCALE_R 12 + +struct SMU7_PowerScoreboard +{ + uint32_t GpuPower; + + uint32_t VddcPower; + uint32_t VddcVoltage; + uint32_t VddcCurrent; + + uint32_t MvddPower; + uint32_t MvddVoltage; + uint32_t MvddCurrent; + + uint32_t RocPower; + + uint16_t Telemetry_1_slope; + uint16_t Telemetry_2_slope; + int32_t Telemetry_1_offset; + int32_t Telemetry_2_offset; +}; +typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard; + +// For FeatureEnables: +#define SMU7_SCLK_DPM_CONFIG_MASK 0x01 +#define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02 +#define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04 +#define SMU7_MCLK_DPM_CONFIG_MASK 0x08 +#define SMU7_UVD_DPM_CONFIG_MASK 0x10 +#define SMU7_VCE_DPM_CONFIG_MASK 0x20 +#define SMU7_ACP_DPM_CONFIG_MASK 0x40 +#define SMU7_SAMU_DPM_CONFIG_MASK 0x80 +#define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100 + +#define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001 +#define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002 +#define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100 +#define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200 +#define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000 +#define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000 + +// All 'soft registers' should be uint32_t. +struct SMU73_SoftRegisters +{ + uint32_t RefClockFrequency; + uint32_t PmTimerPeriod; + uint32_t FeatureEnables; + + uint32_t PreVBlankGap; + uint32_t VBlankTimeout; + uint32_t TrainTimeGap; + + uint32_t MvddSwitchTime; + uint32_t LongestAcpiTrainTime; + uint32_t AcpiDelay; + uint32_t G5TrainTime; + uint32_t DelayMpllPwron; + uint32_t VoltageChangeTimeout; + + uint32_t HandshakeDisables; + + uint8_t DisplayPhy1Config; + uint8_t DisplayPhy2Config; + uint8_t DisplayPhy3Config; + uint8_t DisplayPhy4Config; + + uint8_t DisplayPhy5Config; + uint8_t DisplayPhy6Config; + uint8_t DisplayPhy7Config; + uint8_t DisplayPhy8Config; + + uint32_t AverageGraphicsActivity; + uint32_t AverageMemoryActivity; + uint32_t AverageGioActivity; + + uint8_t SClkDpmEnabledLevels; + uint8_t MClkDpmEnabledLevels; + uint8_t LClkDpmEnabledLevels; + uint8_t PCIeDpmEnabledLevels; + + uint8_t UVDDpmEnabledLevels; + uint8_t SAMUDpmEnabledLevels; + uint8_t ACPDpmEnabledLevels; + uint8_t VCEDpmEnabledLevels; + + uint32_t DRAM_LOG_ADDR_H; + uint32_t DRAM_LOG_ADDR_L; + uint32_t DRAM_LOG_PHY_ADDR_H; + uint32_t DRAM_LOG_PHY_ADDR_L; + uint32_t DRAM_LOG_BUFF_SIZE; + uint32_t UlvEnterCount; + uint32_t UlvTime; + uint32_t UcodeLoadStatus; + uint32_t Reserved[2]; + +}; + +typedef struct SMU73_SoftRegisters SMU73_SoftRegisters; + +struct SMU73_Firmware_Header +{ + uint32_t Digest[5]; + uint32_t Version; + uint32_t HeaderSize; + uint32_t Flags; + uint32_t EntryPoint; + uint32_t CodeSize; + uint32_t ImageSize; + + uint32_t Rtos; + uint32_t SoftRegisters; + uint32_t DpmTable; + uint32_t FanTable; + uint32_t CacConfigTable; + uint32_t CacStatusTable; + + + uint32_t mcRegisterTable; + + + uint32_t mcArbDramTimingTable; + + + + + uint32_t PmFuseTable; + uint32_t Globals; + uint32_t ClockStretcherTable; + uint32_t Reserved[41]; + uint32_t Signature; +}; + +typedef struct SMU73_Firmware_Header SMU73_Firmware_Header; + +#define SMU7_FIRMWARE_HEADER_LOCATION 0x20000 + +enum DisplayConfig { + PowerDown = 1, + DP54x4, + DP54x2, + DP54x1, + DP27x4, + DP27x2, + DP27x1, + HDMI297, + HDMI162, + LVDS, + DP324x4, + DP324x2, + DP324x1 +}; + + +#define MC_BLOCK_COUNT 1 +#define CPL_BLOCK_COUNT 5 +#define SE_BLOCK_COUNT 15 +#define GC_BLOCK_COUNT 24 + +struct SMU7_Local_Cac { + uint8_t BlockId; + uint8_t SignalId; + uint8_t Threshold; + uint8_t Padding; +}; + +typedef struct SMU7_Local_Cac SMU7_Local_Cac; + +struct SMU7_Local_Cac_Table { + + SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT]; + SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT]; + SMU7_Local_Cac SeLocalCac[SE_BLOCK_COUNT]; + SMU7_Local_Cac GcLocalCac[GC_BLOCK_COUNT]; +}; + +typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table; + +#if !defined(SMC_MICROCODE) +#pragma pack(pop) +#endif + +// Description of Clock Gating bitmask for Tonga: +// System Clock Gating +#define CG_SYS_BITMASK_FIRST_BIT 0 // First bit of Sys CG bitmask +#define CG_SYS_BITMASK_LAST_BIT 9 // Last bit of Sys CG bitmask +#define CG_SYS_BIF_MGLS_SHIFT 0 +#define CG_SYS_ROM_SHIFT 1 +#define CG_SYS_MC_MGCG_SHIFT 2 +#define CG_SYS_MC_MGLS_SHIFT 3 +#define CG_SYS_SDMA_MGCG_SHIFT 4 +#define CG_SYS_SDMA_MGLS_SHIFT 5 +#define CG_SYS_DRM_MGCG_SHIFT 6 +#define CG_SYS_HDP_MGCG_SHIFT 7 +#define CG_SYS_HDP_MGLS_SHIFT 8 +#define CG_SYS_DRM_MGLS_SHIFT 9 + +#define CG_SYS_BIF_MGLS_MASK 0x1 +#define CG_SYS_ROM_MASK 0x2 +#define CG_SYS_MC_MGCG_MASK 0x4 +#define CG_SYS_MC_MGLS_MASK 0x8 +#define CG_SYS_SDMA_MGCG_MASK 0x10 +#define CG_SYS_SDMA_MGLS_MASK 0x20 +#define CG_SYS_DRM_MGCG_MASK 0x40 +#define CG_SYS_HDP_MGCG_MASK 0x80 +#define CG_SYS_HDP_MGLS_MASK 0x100 +#define CG_SYS_DRM_MGLS_MASK 0x200 + +// Graphics Clock Gating +#define CG_GFX_BITMASK_FIRST_BIT 16 // First bit of Gfx CG bitmask +#define CG_GFX_BITMASK_LAST_BIT 20 // Last bit of Gfx CG bitmask +#define CG_GFX_CGCG_SHIFT 16 +#define CG_GFX_CGLS_SHIFT 17 +#define CG_CPF_MGCG_SHIFT 18 +#define CG_RLC_MGCG_SHIFT 19 +#define CG_GFX_OTHERS_MGCG_SHIFT 20 + +#define CG_GFX_CGCG_MASK 0x00010000 +#define CG_GFX_CGLS_MASK 0x00020000 +#define CG_CPF_MGCG_MASK 0x00040000 +#define CG_RLC_MGCG_MASK 0x00080000 +#define CG_GFX_OTHERS_MGCG_MASK 0x00100000 + + + +// Voltage Regulator Configuration +// VR Config info is contained in dpmTable.VRConfig + +#define VRCONF_VDDC_MASK 0x000000FF +#define VRCONF_VDDC_SHIFT 0 +#define VRCONF_VDDGFX_MASK 0x0000FF00 +#define VRCONF_VDDGFX_SHIFT 8 +#define VRCONF_VDDCI_MASK 0x00FF0000 +#define VRCONF_VDDCI_SHIFT 16 +#define VRCONF_MVDD_MASK 0xFF000000 +#define VRCONF_MVDD_SHIFT 24 + +#define VR_MERGED_WITH_VDDC 0 +#define VR_SVI2_PLANE_1 1 +#define VR_SVI2_PLANE_2 2 +#define VR_SMIO_PATTERN_1 3 +#define VR_SMIO_PATTERN_2 4 +#define VR_STATIC_VOLTAGE 5 + +// Clock Stretcher Configuration + +#define CLOCK_STRETCHER_MAX_ENTRIES 0x4 +#define CKS_LOOKUPTable_MAX_ENTRIES 0x4 + +// The 'settings' field is subdivided in the following way: +#define CLOCK_STRETCHER_SETTING_DDT_MASK 0x01 +#define CLOCK_STRETCHER_SETTING_DDT_SHIFT 0x0 +#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_MASK 0x1E +#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_SHIFT 0x1 +#define CLOCK_STRETCHER_SETTING_ENABLE_MASK 0x80 +#define CLOCK_STRETCHER_SETTING_ENABLE_SHIFT 0x7 + +struct SMU_ClockStretcherDataTableEntry { + uint8_t minVID; + uint8_t maxVID; + + + uint16_t setting; +}; +typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry; + +struct SMU_ClockStretcherDataTable { + SMU_ClockStretcherDataTableEntry ClockStretcherDataTableEntry[CLOCK_STRETCHER_MAX_ENTRIES]; +}; +typedef struct SMU_ClockStretcherDataTable SMU_ClockStretcherDataTable; + +struct SMU_CKS_LOOKUPTableEntry { + uint16_t minFreq; + uint16_t maxFreq; + + uint8_t setting; + uint8_t padding[3]; +}; +typedef struct SMU_CKS_LOOKUPTableEntry SMU_CKS_LOOKUPTableEntry; + +struct SMU_CKS_LOOKUPTable { + SMU_CKS_LOOKUPTableEntry CKS_LOOKUPTableEntry[CKS_LOOKUPTable_MAX_ENTRIES]; +}; +typedef struct SMU_CKS_LOOKUPTable SMU_CKS_LOOKUPTable; + +struct AgmAvfsData_t { + uint16_t avgPsmCount[28]; + uint16_t minPsmCount[28]; +}; +typedef struct AgmAvfsData_t AgmAvfsData_t; + +// AVFS DEFINES + +enum VFT_COLUMNS { + SCLK0, + SCLK1, + SCLK2, + SCLK3, + SCLK4, + SCLK5, + SCLK6, + SCLK7, + + NUM_VFT_COLUMNS +}; + +#define TEMP_RANGE_MAXSTEPS 12 +struct VFT_CELL_t { + uint16_t Voltage; +}; + +typedef struct VFT_CELL_t VFT_CELL_t; + +struct VFT_TABLE_t { + VFT_CELL_t Cell[TEMP_RANGE_MAXSTEPS][NUM_VFT_COLUMNS]; + uint16_t AvfsGbv [NUM_VFT_COLUMNS]; + uint16_t BtcGbv [NUM_VFT_COLUMNS]; + uint16_t Temperature [TEMP_RANGE_MAXSTEPS]; + + uint8_t NumTemperatureSteps; + uint8_t padding[3]; +}; +typedef struct VFT_TABLE_t VFT_TABLE_t; + +#endif diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h b/drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h new file mode 100644 index 000000000000..5916be08a7fe --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h @@ -0,0 +1,799 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _SMU73_DISCRETE_H_ +#define _SMU73_DISCRETE_H_ + +#include "smu73.h" + +#pragma pack(push, 1) + +struct SMIO_Pattern +{ + uint16_t Voltage; + uint8_t Smio; + uint8_t padding; +}; + +typedef struct SMIO_Pattern SMIO_Pattern; + +struct SMIO_Table +{ + SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS]; +}; + +typedef struct SMIO_Table SMIO_Table; + +struct SMU73_Discrete_GraphicsLevel { + uint32_t MinVoltage; + + uint32_t SclkFrequency; + + uint8_t pcieDpmLevel; + uint8_t DeepSleepDivId; + uint16_t ActivityLevel; + uint32_t CgSpllFuncCntl3; + uint32_t CgSpllFuncCntl4; + uint32_t SpllSpreadSpectrum; + uint32_t SpllSpreadSpectrum2; + uint32_t CcPwrDynRm; + uint32_t CcPwrDynRm1; + uint8_t SclkDid; + uint8_t DisplayWatermark; + uint8_t EnabledForActivity; + uint8_t EnabledForThrottle; + uint8_t UpHyst; + uint8_t DownHyst; + uint8_t VoltageDownHyst; + uint8_t PowerThrottle; +}; + +typedef struct SMU73_Discrete_GraphicsLevel SMU73_Discrete_GraphicsLevel; + +struct SMU73_Discrete_ACPILevel { + uint32_t Flags; + uint32_t MinVoltage; + uint32_t SclkFrequency; + uint8_t SclkDid; + uint8_t DisplayWatermark; + uint8_t DeepSleepDivId; + uint8_t padding; + uint32_t CgSpllFuncCntl; + uint32_t CgSpllFuncCntl2; + uint32_t CgSpllFuncCntl3; + uint32_t CgSpllFuncCntl4; + uint32_t SpllSpreadSpectrum; + uint32_t SpllSpreadSpectrum2; + uint32_t CcPwrDynRm; + uint32_t CcPwrDynRm1; +}; + +typedef struct SMU73_Discrete_ACPILevel SMU73_Discrete_ACPILevel; + +struct SMU73_Discrete_Ulv { + uint32_t CcPwrDynRm; + uint32_t CcPwrDynRm1; + uint16_t VddcOffset; + uint8_t VddcOffsetVid; + uint8_t VddcPhase; + uint32_t Reserved; +}; + +typedef struct SMU73_Discrete_Ulv SMU73_Discrete_Ulv; + +struct SMU73_Discrete_MemoryLevel +{ + uint32_t MinVoltage; + uint32_t MinMvdd; + + uint32_t MclkFrequency; + + uint8_t StutterEnable; + uint8_t FreqRange; + uint8_t EnabledForThrottle; + uint8_t EnabledForActivity; + + uint8_t UpHyst; + uint8_t DownHyst; + uint8_t VoltageDownHyst; + uint8_t padding; + + uint16_t ActivityLevel; + uint8_t DisplayWatermark; + uint8_t MclkDivider; +}; + +typedef struct SMU73_Discrete_MemoryLevel SMU73_Discrete_MemoryLevel; + +struct SMU73_Discrete_LinkLevel +{ + uint8_t PcieGenSpeed; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 + uint8_t PcieLaneCount; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 + uint8_t EnabledForActivity; + uint8_t SPC; + uint32_t DownThreshold; + uint32_t UpThreshold; + uint32_t Reserved; +}; + +typedef struct SMU73_Discrete_LinkLevel SMU73_Discrete_LinkLevel; + + +// MC ARB DRAM Timing registers. +struct SMU73_Discrete_MCArbDramTimingTableEntry +{ + uint32_t McArbDramTiming; + uint32_t McArbDramTiming2; + uint8_t McArbBurstTime; + uint8_t TRRDS; + uint8_t TRRDL; + uint8_t padding; +}; + +typedef struct SMU73_Discrete_MCArbDramTimingTableEntry SMU73_Discrete_MCArbDramTimingTableEntry; + +struct SMU73_Discrete_MCArbDramTimingTable +{ + SMU73_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS]; +}; + +typedef struct SMU73_Discrete_MCArbDramTimingTable SMU73_Discrete_MCArbDramTimingTable; + +// UVD VCLK/DCLK state (level) definition. +struct SMU73_Discrete_UvdLevel +{ + uint32_t VclkFrequency; + uint32_t DclkFrequency; + uint32_t MinVoltage; + uint8_t VclkDivider; + uint8_t DclkDivider; + uint8_t padding[2]; +}; + +typedef struct SMU73_Discrete_UvdLevel SMU73_Discrete_UvdLevel; + +// Clocks for other external blocks (VCE, ACP, SAMU). +struct SMU73_Discrete_ExtClkLevel +{ + uint32_t Frequency; + uint32_t MinVoltage; + uint8_t Divider; + uint8_t padding[3]; +}; + +typedef struct SMU73_Discrete_ExtClkLevel SMU73_Discrete_ExtClkLevel; + +struct SMU73_Discrete_StateInfo +{ + uint32_t SclkFrequency; + uint32_t MclkFrequency; + uint32_t VclkFrequency; + uint32_t DclkFrequency; + uint32_t SamclkFrequency; + uint32_t AclkFrequency; + uint32_t EclkFrequency; + uint16_t MvddVoltage; + uint16_t padding16; + uint8_t DisplayWatermark; + uint8_t McArbIndex; + uint8_t McRegIndex; + uint8_t SeqIndex; + uint8_t SclkDid; + int8_t SclkIndex; + int8_t MclkIndex; + uint8_t PCIeGen; + +}; + +typedef struct SMU73_Discrete_StateInfo SMU73_Discrete_StateInfo; + +struct SMU73_Discrete_DpmTable +{ + // Multi-DPM controller settings + SMU73_PIDController GraphicsPIDController; + SMU73_PIDController MemoryPIDController; + SMU73_PIDController LinkPIDController; + + uint32_t SystemFlags; + + // SMIO masks for voltage and phase controls + uint32_t VRConfig; + uint32_t SmioMask1; + uint32_t SmioMask2; + SMIO_Table SmioTable1; + SMIO_Table SmioTable2; + + uint32_t MvddLevelCount; + + + uint8_t BapmVddcVidHiSidd [SMU73_MAX_LEVELS_VDDC]; + uint8_t BapmVddcVidLoSidd [SMU73_MAX_LEVELS_VDDC]; + uint8_t BapmVddcVidHiSidd2 [SMU73_MAX_LEVELS_VDDC]; + + uint8_t GraphicsDpmLevelCount; + uint8_t MemoryDpmLevelCount; + uint8_t LinkLevelCount; + uint8_t MasterDeepSleepControl; + + uint8_t UvdLevelCount; + uint8_t VceLevelCount; + uint8_t AcpLevelCount; + uint8_t SamuLevelCount; + + uint8_t ThermOutGpio; + uint8_t ThermOutPolarity; + uint8_t ThermOutMode; + uint8_t BootPhases; + uint32_t Reserved[4]; + + // State table entries for each DPM state + SMU73_Discrete_GraphicsLevel GraphicsLevel [SMU73_MAX_LEVELS_GRAPHICS]; + SMU73_Discrete_MemoryLevel MemoryACPILevel; + SMU73_Discrete_MemoryLevel MemoryLevel [SMU73_MAX_LEVELS_MEMORY]; + SMU73_Discrete_LinkLevel LinkLevel [SMU73_MAX_LEVELS_LINK]; + SMU73_Discrete_ACPILevel ACPILevel; + SMU73_Discrete_UvdLevel UvdLevel [SMU73_MAX_LEVELS_UVD]; + SMU73_Discrete_ExtClkLevel VceLevel [SMU73_MAX_LEVELS_VCE]; + SMU73_Discrete_ExtClkLevel AcpLevel [SMU73_MAX_LEVELS_ACP]; + SMU73_Discrete_ExtClkLevel SamuLevel [SMU73_MAX_LEVELS_SAMU]; + SMU73_Discrete_Ulv Ulv; + + uint32_t SclkStepSize; + uint32_t Smio [SMU73_MAX_ENTRIES_SMIO]; + + uint8_t UvdBootLevel; + uint8_t VceBootLevel; + uint8_t AcpBootLevel; + uint8_t SamuBootLevel; + + uint8_t GraphicsBootLevel; + uint8_t GraphicsVoltageChangeEnable; + uint8_t GraphicsThermThrottleEnable; + uint8_t GraphicsInterval; + + uint8_t VoltageInterval; + uint8_t ThermalInterval; + uint16_t TemperatureLimitHigh; + + uint16_t TemperatureLimitLow; + uint8_t MemoryBootLevel; + uint8_t MemoryVoltageChangeEnable; + + uint16_t BootMVdd; + uint8_t MemoryInterval; + uint8_t MemoryThermThrottleEnable; + + uint16_t VoltageResponseTime; + uint16_t PhaseResponseTime; + + uint8_t PCIeBootLinkLevel; + uint8_t PCIeGenInterval; + uint8_t DTEInterval; + uint8_t DTEMode; + + uint8_t SVI2Enable; + uint8_t VRHotGpio; + uint8_t AcDcGpio; + uint8_t ThermGpio; + + uint16_t PPM_PkgPwrLimit; + uint16_t PPM_TemperatureLimit; + + uint16_t DefaultTdp; + uint16_t TargetTdp; + + uint16_t FpsHighThreshold; + uint16_t FpsLowThreshold; + + uint16_t TemperatureLimitEdge; + uint16_t TemperatureLimitHotspot; + uint16_t TemperatureLimitLiquid1; + uint16_t TemperatureLimitLiquid2; + uint16_t TemperatureLimitVrVddc; + uint16_t TemperatureLimitVrMvdd; + uint16_t TemperatureLimitPlx; + + uint16_t FanGainEdge; + uint16_t FanGainHotspot; + uint16_t FanGainLiquid; + uint16_t FanGainVrVddc; + uint16_t FanGainVrMvdd; + uint16_t FanGainPlx; + uint16_t FanGainHbm; + + uint8_t Liquid1_I2C_address; + uint8_t Liquid2_I2C_address; + uint8_t Vr_I2C_address; + uint8_t Plx_I2C_address; + + uint8_t GeminiMode; + uint8_t spare17[3]; + uint32_t GeminiApertureHigh; + uint32_t GeminiApertureLow; + + uint8_t Liquid_I2C_LineSCL; + uint8_t Liquid_I2C_LineSDA; + uint8_t Vr_I2C_LineSCL; + uint8_t Vr_I2C_LineSDA; + uint8_t Plx_I2C_LineSCL; + uint8_t Plx_I2C_LineSDA; + + uint8_t spare1253[2]; + uint32_t spare123[2]; + + uint8_t DTEAmbientTempBase; + uint8_t DTETjOffset; + uint8_t GpuTjMax; + uint8_t GpuTjHyst; + + uint16_t BootVddc; + uint16_t BootVddci; + + uint32_t BAPM_TEMP_GRADIENT; + + uint32_t LowSclkInterruptThreshold; + uint32_t VddGfxReChkWait; + + uint8_t ClockStretcherAmount; + uint8_t Sclk_CKS_masterEn0_7; + uint8_t Sclk_CKS_masterEn8_15; + uint8_t DPMFreezeAndForced; + + uint8_t Sclk_voltageOffset[8]; + + SMU_ClockStretcherDataTable ClockStretcherDataTable; + SMU_CKS_LOOKUPTable CKS_LOOKUPTable; +}; + +typedef struct SMU73_Discrete_DpmTable SMU73_Discrete_DpmTable; + + +// --------------------------------------------------- Fan Table ----------------------------------------------------------- +struct SMU73_Discrete_FanTable +{ + uint16_t FdoMode; + int16_t TempMin; + int16_t TempMed; + int16_t TempMax; + int16_t Slope1; + int16_t Slope2; + int16_t FdoMin; + int16_t HystUp; + int16_t HystDown; + int16_t HystSlope; + int16_t TempRespLim; + int16_t TempCurr; + int16_t SlopeCurr; + int16_t PwmCurr; + uint32_t RefreshPeriod; + int16_t FdoMax; + uint8_t TempSrc; + int8_t Padding; +}; + +typedef struct SMU73_Discrete_FanTable SMU73_Discrete_FanTable; + +#define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4 +#define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG) + + + +struct SMU7_MclkDpmScoreboard +{ + + uint32_t PercentageBusy; + + int32_t PIDError; + int32_t PIDIntegral; + int32_t PIDOutput; + + uint32_t SigmaDeltaAccum; + uint32_t SigmaDeltaOutput; + uint32_t SigmaDeltaLevel; + + uint32_t UtilizationSetpoint; + + uint8_t TdpClampMode; + uint8_t TdcClampMode; + uint8_t ThermClampMode; + uint8_t VoltageBusy; + + int8_t CurrLevel; + int8_t TargLevel; + uint8_t LevelChangeInProgress; + uint8_t UpHyst; + + uint8_t DownHyst; + uint8_t VoltageDownHyst; + uint8_t DpmEnable; + uint8_t DpmRunning; + + uint8_t DpmForce; + uint8_t DpmForceLevel; + uint8_t DisplayWatermark; + uint8_t McArbIndex; + + uint32_t MinimumPerfMclk; + + uint8_t AcpiReq; + uint8_t AcpiAck; + uint8_t MclkSwitchInProgress; + uint8_t MclkSwitchCritical; + + uint8_t IgnoreVBlank; + uint8_t TargetMclkIndex; + uint8_t TargetMvddIndex; + uint8_t MclkSwitchResult; + + uint16_t VbiFailureCount; + uint8_t VbiWaitCounter; + uint8_t EnabledLevelsChange; + + uint16_t LevelResidencyCounters [SMU73_MAX_LEVELS_MEMORY]; + uint16_t LevelSwitchCounters [SMU73_MAX_LEVELS_MEMORY]; + + void (*TargetStateCalculator)(uint8_t); + void (*SavedTargetStateCalculator)(uint8_t); + + uint16_t AutoDpmInterval; + uint16_t AutoDpmRange; + + uint16_t VbiTimeoutCount; + uint16_t MclkSwitchingTime; + + uint8_t fastSwitch; + uint8_t Save_PIC_VDDGFX_EXIT; + uint8_t Save_PIC_VDDGFX_ENTER; + uint8_t padding; + +}; + +typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard; + +struct SMU7_UlvScoreboard +{ + uint8_t EnterUlv; + uint8_t ExitUlv; + uint8_t UlvActive; + uint8_t WaitingForUlv; + uint8_t UlvEnable; + uint8_t UlvRunning; + uint8_t UlvMasterEnable; + uint8_t padding; + uint32_t UlvAbortedCount; + uint32_t UlvTimeStamp; +}; + +typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard; + +struct VddgfxSavedRegisters +{ + uint32_t GPU_DBG[3]; + uint32_t MEC_BaseAddress_Hi; + uint32_t MEC_BaseAddress_Lo; + uint32_t THM_TMON0_CTRL2__RDIR_PRESENT; + uint32_t THM_TMON1_CTRL2__RDIR_PRESENT; + uint32_t CP_INT_CNTL; +}; + +typedef struct VddgfxSavedRegisters VddgfxSavedRegisters; + +struct SMU7_VddGfxScoreboard +{ + uint8_t VddGfxEnable; + uint8_t VddGfxActive; + uint8_t VPUResetOccured; + uint8_t padding; + + uint32_t VddGfxEnteredCount; + uint32_t VddGfxAbortedCount; + + uint32_t VddGfxVid; + + VddgfxSavedRegisters SavedRegisters; +}; + +typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard; + +struct SMU7_TdcLimitScoreboard { + uint8_t Enable; + uint8_t Running; + uint16_t Alpha; + uint32_t FilteredIddc; + uint32_t IddcLimit; + uint32_t IddcHyst; + SMU7_HystController_Data HystControllerData; +}; + +typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard; + +struct SMU7_PkgPwrLimitScoreboard { + uint8_t Enable; + uint8_t Running; + uint16_t Alpha; + uint32_t FilteredPkgPwr; + uint32_t Limit; + uint32_t Hyst; + uint32_t LimitFromDriver; + SMU7_HystController_Data HystControllerData; +}; + +typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard; + +struct SMU7_BapmScoreboard { + uint32_t source_powers[SMU73_DTE_SOURCES]; + uint32_t source_powers_last[SMU73_DTE_SOURCES]; + int32_t entity_temperatures[SMU73_NUM_GPU_TES]; + int32_t initial_entity_temperatures[SMU73_NUM_GPU_TES]; + int32_t Limit; + int32_t Hyst; + int32_t therm_influence_coeff_table[SMU73_DTE_ITERATIONS * SMU73_DTE_SOURCES * SMU73_DTE_SINKS * 2]; + int32_t therm_node_table[SMU73_DTE_ITERATIONS * SMU73_DTE_SOURCES * SMU73_DTE_SINKS]; + uint16_t ConfigTDPPowerScalar; + uint16_t FanSpeedPowerScalar; + uint16_t OverDrivePowerScalar; + uint16_t OverDriveLimitScalar; + uint16_t FinalPowerScalar; + uint8_t VariantID; + uint8_t spare997; + + SMU7_HystController_Data HystControllerData; + + int32_t temperature_gradient_slope; + int32_t temperature_gradient; + uint32_t measured_temperature; +}; + + +typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard; + +struct SMU7_AcpiScoreboard { + uint32_t SavedInterruptMask[2]; + uint8_t LastACPIRequest; + uint8_t CgBifResp; + uint8_t RequestType; + uint8_t Padding; + SMU73_Discrete_ACPILevel D0Level; +}; + +typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard; + +struct SMU_QuadraticCoeffs { + int32_t m1; + uint32_t b; + + int16_t m2; + uint8_t m1_shift; + uint8_t m2_shift; +}; + +typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs; + +struct SMU73_Discrete_PmFuses { + /* dw0-dw1 */ + uint8_t BapmVddCVidHiSidd[8]; + + /* dw2-dw3 */ + uint8_t BapmVddCVidLoSidd[8]; + + /* dw4-dw5 */ + uint8_t VddCVid[8]; + + /* dw1*/ + uint8_t SviLoadLineEn; + uint8_t SviLoadLineVddC; + uint8_t SviLoadLineTrimVddC; + uint8_t SviLoadLineOffsetVddC; + + /* dw2 */ + uint16_t TDC_VDDC_PkgLimit; + uint8_t TDC_VDDC_ThrottleReleaseLimitPerc; + uint8_t TDC_MAWt; + + /* dw3 */ + uint8_t TdcWaterfallCtl; + uint8_t LPMLTemperatureMin; + uint8_t LPMLTemperatureMax; + uint8_t Reserved; + + /* dw4-dw7 */ + uint8_t LPMLTemperatureScaler[16]; + + /* dw8-dw9 */ + int16_t FuzzyFan_ErrorSetDelta; + int16_t FuzzyFan_ErrorRateSetDelta; + int16_t FuzzyFan_PwmSetDelta; + uint16_t Reserved6; + + /* dw10-dw14 */ + uint8_t GnbLPML[16]; + + /* dw15 */ + uint8_t GnbLPMLMaxVid; + uint8_t GnbLPMLMinVid; + uint8_t Reserved1[2]; + + /* dw16 */ + uint16_t BapmVddCBaseLeakageHiSidd; + uint16_t BapmVddCBaseLeakageLoSidd; + + /* AVFS */ + uint16_t VFT_Temp[3]; + uint16_t padding; + + SMU_QuadraticCoeffs VFT_ATE[3]; + + SMU_QuadraticCoeffs AVFS_GB; + SMU_QuadraticCoeffs ATE_ACBTC_GB; + + SMU_QuadraticCoeffs P2V; + + uint32_t PsmCharzFreq; + + uint16_t InversionVoltage; + uint16_t PsmCharzTemp; + + uint32_t EnabledAvfsModules; +}; + +typedef struct SMU73_Discrete_PmFuses SMU73_Discrete_PmFuses; + +struct SMU7_Discrete_Log_Header_Table { + uint32_t version; + uint32_t asic_id; + uint16_t flags; + uint16_t entry_size; + uint32_t total_size; + uint32_t num_of_entries; + uint8_t type; + uint8_t mode; + uint8_t filler_0[2]; + uint32_t filler_1[2]; +}; + +typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table; + +struct SMU7_Discrete_Log_Cntl { + uint8_t Enabled; + uint8_t Type; + uint8_t padding[2]; + uint32_t BufferSize; + uint32_t SamplesLogged; + uint32_t SampleSize; + uint32_t AddrL; + uint32_t AddrH; +}; + +typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl; + +#define CAC_ACC_NW_NUM_OF_SIGNALS 87 + +struct SMU7_Discrete_Cac_Collection_Table { + uint32_t temperature; + uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS]; +}; + +typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table; + +struct SMU7_Discrete_Cac_Verification_Table { + uint32_t VddcTotalPower; + uint32_t VddcLeakagePower; + uint32_t VddcConstantPower; + uint32_t VddcGfxDynamicPower; + uint32_t VddcUvdDynamicPower; + uint32_t VddcVceDynamicPower; + uint32_t VddcAcpDynamicPower; + uint32_t VddcPcieDynamicPower; + uint32_t VddcDceDynamicPower; + uint32_t VddcCurrent; + uint32_t VddcVoltage; + uint32_t VddciTotalPower; + uint32_t VddciLeakagePower; + uint32_t VddciConstantPower; + uint32_t VddciDynamicPower; + uint32_t Vddr1TotalPower; + uint32_t Vddr1LeakagePower; + uint32_t Vddr1ConstantPower; + uint32_t Vddr1DynamicPower; + uint32_t spare[4]; + uint32_t temperature; +}; + +typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table; + +struct SMU7_Discrete_Pm_Status_Table { + //Thermal entities + int32_t T_meas_max[SMU73_THERMAL_INPUT_LOOP_COUNT]; + int32_t T_meas_acc[SMU73_THERMAL_INPUT_LOOP_COUNT]; + int32_t T_meas_acc_cnt[SMU73_THERMAL_INPUT_LOOP_COUNT]; + uint32_t T_hbm_acc; + + //Voltage domains + uint32_t I_calc_max; + uint32_t I_calc_acc; + uint32_t P_meas_acc; + uint32_t V_meas_load_acc; + uint32_t I_meas_acc; + uint32_t P_meas_acc_vddci; + uint32_t V_meas_load_acc_vddci; + uint32_t I_meas_acc_vddci; + + //Frequency + uint16_t Sclk_dpm_residency[8]; + uint16_t Uvd_dpm_residency[8]; + uint16_t Vce_dpm_residency[8]; + + //Chip + uint32_t P_roc_acc; + uint32_t PkgPwr_max; + uint32_t PkgPwr_acc; + uint32_t MclkSwitchingTime_max; + uint32_t MclkSwitchingTime_acc; + uint32_t FanPwm_acc; + uint32_t FanRpm_acc; + uint32_t Gfx_busy_acc; + uint32_t Mc_busy_acc; + uint32_t Fps_acc; + + uint32_t AccCnt; +}; + +typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table; + +//FIXME THESE NEED TO BE UPDATED +#define SMU7_SCLK_CAC 0x561 +#define SMU7_MCLK_CAC 0xF9 +#define SMU7_VCLK_CAC 0x2DE +#define SMU7_DCLK_CAC 0x2DE +#define SMU7_ECLK_CAC 0x25E +#define SMU7_ACLK_CAC 0x25E +#define SMU7_SAMCLK_CAC 0x25E +#define SMU7_DISPCLK_CAC 0x100 +#define SMU7_CAC_CONSTANT 0x2EE3430 +#define SMU7_CAC_CONSTANT_SHIFT 18 + +#define SMU7_VDDCI_MCLK_CONST 1765 +#define SMU7_VDDCI_MCLK_CONST_SHIFT 16 +#define SMU7_VDDCI_VDDCI_CONST 50958 +#define SMU7_VDDCI_VDDCI_CONST_SHIFT 14 +#define SMU7_VDDCI_CONST 11781 +#define SMU7_VDDCI_STROBE_PWR 1331 + +#define SMU7_VDDR1_CONST 693 +#define SMU7_VDDR1_CAC_WEIGHT 20 +#define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19 +#define SMU7_VDDR1_STROBE_PWR 512 + +#define SMU7_AREA_COEFF_UVD 0xA78 +#define SMU7_AREA_COEFF_VCE 0x190A +#define SMU7_AREA_COEFF_ACP 0x22D1 +#define SMU7_AREA_COEFF_SAMU 0x534 + +//ThermOutMode values +#define SMU7_THERM_OUT_MODE_DISABLE 0x0 +#define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1 +#define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2 + +#pragma pack(pop) + +#endif + diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h b/drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h new file mode 100644 index 000000000000..0b0b404ff091 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h @@ -0,0 +1,514 @@ +/* + * Copyright 2013 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef SMU7_DISCRETE_H +#define SMU7_DISCRETE_H + +#include "smu7.h" + +#pragma pack(push, 1) + +#define SMU7_DTE_ITERATIONS 5 +#define SMU7_DTE_SOURCES 3 +#define SMU7_DTE_SINKS 1 +#define SMU7_NUM_CPU_TES 0 +#define SMU7_NUM_GPU_TES 1 +#define SMU7_NUM_NON_TES 2 + +struct SMU7_SoftRegisters +{ + uint32_t RefClockFrequency; + uint32_t PmTimerP; + uint32_t FeatureEnables; + uint32_t PreVBlankGap; + uint32_t VBlankTimeout; + uint32_t TrainTimeGap; + + uint32_t MvddSwitchTime; + uint32_t LongestAcpiTrainTime; + uint32_t AcpiDelay; + uint32_t G5TrainTime; + uint32_t DelayMpllPwron; + uint32_t VoltageChangeTimeout; + uint32_t HandshakeDisables; + + uint8_t DisplayPhy1Config; + uint8_t DisplayPhy2Config; + uint8_t DisplayPhy3Config; + uint8_t DisplayPhy4Config; + + uint8_t DisplayPhy5Config; + uint8_t DisplayPhy6Config; + uint8_t DisplayPhy7Config; + uint8_t DisplayPhy8Config; + + uint32_t AverageGraphicsA; + uint32_t AverageMemoryA; + uint32_t AverageGioA; + + uint8_t SClkDpmEnabledLevels; + uint8_t MClkDpmEnabledLevels; + uint8_t LClkDpmEnabledLevels; + uint8_t PCIeDpmEnabledLevels; + + uint8_t UVDDpmEnabledLevels; + uint8_t SAMUDpmEnabledLevels; + uint8_t ACPDpmEnabledLevels; + uint8_t VCEDpmEnabledLevels; + + uint32_t DRAM_LOG_ADDR_H; + uint32_t DRAM_LOG_ADDR_L; + uint32_t DRAM_LOG_PHY_ADDR_H; + uint32_t DRAM_LOG_PHY_ADDR_L; + uint32_t DRAM_LOG_BUFF_SIZE; + uint32_t UlvEnterC; + uint32_t UlvTime; + uint32_t Reserved[3]; + +}; + +typedef struct SMU7_SoftRegisters SMU7_SoftRegisters; + +struct SMU7_Discrete_VoltageLevel +{ + uint16_t Voltage; + uint16_t StdVoltageHiSidd; + uint16_t StdVoltageLoSidd; + uint8_t Smio; + uint8_t padding; +}; + +typedef struct SMU7_Discrete_VoltageLevel SMU7_Discrete_VoltageLevel; + +struct SMU7_Discrete_GraphicsLevel +{ + uint32_t Flags; + uint32_t MinVddc; + uint32_t MinVddcPhases; + + uint32_t SclkFrequency; + + uint8_t padding1[2]; + uint16_t ActivityLevel; + + uint32_t CgSpllFuncCntl3; + uint32_t CgSpllFuncCntl4; + uint32_t SpllSpreadSpectrum; + uint32_t SpllSpreadSpectrum2; + uint32_t CcPwrDynRm; + uint32_t CcPwrDynRm1; + uint8_t SclkDid; + uint8_t DisplayWatermark; + uint8_t EnabledForActivity; + uint8_t EnabledForThrottle; + uint8_t UpH; + uint8_t DownH; + uint8_t VoltageDownH; + uint8_t PowerThrottle; + uint8_t DeepSleepDivId; + uint8_t padding[3]; +}; + +typedef struct SMU7_Discrete_GraphicsLevel SMU7_Discrete_GraphicsLevel; + +struct SMU7_Discrete_ACPILevel +{ + uint32_t Flags; + uint32_t MinVddc; + uint32_t MinVddcPhases; + uint32_t SclkFrequency; + uint8_t SclkDid; + uint8_t DisplayWatermark; + uint8_t DeepSleepDivId; + uint8_t padding; + uint32_t CgSpllFuncCntl; + uint32_t CgSpllFuncCntl2; + uint32_t CgSpllFuncCntl3; + uint32_t CgSpllFuncCntl4; + uint32_t SpllSpreadSpectrum; + uint32_t SpllSpreadSpectrum2; + uint32_t CcPwrDynRm; + uint32_t CcPwrDynRm1; +}; + +typedef struct SMU7_Discrete_ACPILevel SMU7_Discrete_ACPILevel; + +struct SMU7_Discrete_Ulv +{ + uint32_t CcPwrDynRm; + uint32_t CcPwrDynRm1; + uint16_t VddcOffset; + uint8_t VddcOffsetVid; + uint8_t VddcPhase; + uint32_t Reserved; +}; + +typedef struct SMU7_Discrete_Ulv SMU7_Discrete_Ulv; + +struct SMU7_Discrete_MemoryLevel +{ + uint32_t MinVddc; + uint32_t MinVddcPhases; + uint32_t MinVddci; + uint32_t MinMvdd; + + uint32_t MclkFrequency; + + uint8_t EdcReadEnable; + uint8_t EdcWriteEnable; + uint8_t RttEnable; + uint8_t StutterEnable; + + uint8_t StrobeEnable; + uint8_t StrobeRatio; + uint8_t EnabledForThrottle; + uint8_t EnabledForActivity; + + uint8_t UpH; + uint8_t DownH; + uint8_t VoltageDownH; + uint8_t padding; + + uint16_t ActivityLevel; + uint8_t DisplayWatermark; + uint8_t padding1; + + uint32_t MpllFuncCntl; + uint32_t MpllFuncCntl_1; + uint32_t MpllFuncCntl_2; + uint32_t MpllAdFuncCntl; + uint32_t MpllDqFuncCntl; + uint32_t MclkPwrmgtCntl; + uint32_t DllCntl; + uint32_t MpllSs1; + uint32_t MpllSs2; +}; + +typedef struct SMU7_Discrete_MemoryLevel SMU7_Discrete_MemoryLevel; + +struct SMU7_Discrete_LinkLevel +{ + uint8_t PcieGenSpeed; + uint8_t PcieLaneCount; + uint8_t EnabledForActivity; + uint8_t Padding; + uint32_t DownT; + uint32_t UpT; + uint32_t Reserved; +}; + +typedef struct SMU7_Discrete_LinkLevel SMU7_Discrete_LinkLevel; + + +struct SMU7_Discrete_MCArbDramTimingTableEntry +{ + uint32_t McArbDramTiming; + uint32_t McArbDramTiming2; + uint8_t McArbBurstTime; + uint8_t padding[3]; +}; + +typedef struct SMU7_Discrete_MCArbDramTimingTableEntry SMU7_Discrete_MCArbDramTimingTableEntry; + +struct SMU7_Discrete_MCArbDramTimingTable +{ + SMU7_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS]; +}; + +typedef struct SMU7_Discrete_MCArbDramTimingTable SMU7_Discrete_MCArbDramTimingTable; + +struct SMU7_Discrete_UvdLevel +{ + uint32_t VclkFrequency; + uint32_t DclkFrequency; + uint16_t MinVddc; + uint8_t MinVddcPhases; + uint8_t VclkDivider; + uint8_t DclkDivider; + uint8_t padding[3]; +}; + +typedef struct SMU7_Discrete_UvdLevel SMU7_Discrete_UvdLevel; + +struct SMU7_Discrete_ExtClkLevel +{ + uint32_t Frequency; + uint16_t MinVoltage; + uint8_t MinPhases; + uint8_t Divider; +}; + +typedef struct SMU7_Discrete_ExtClkLevel SMU7_Discrete_ExtClkLevel; + +struct SMU7_Discrete_StateInfo +{ + uint32_t SclkFrequency; + uint32_t MclkFrequency; + uint32_t VclkFrequency; + uint32_t DclkFrequency; + uint32_t SamclkFrequency; + uint32_t AclkFrequency; + uint32_t EclkFrequency; + uint16_t MvddVoltage; + uint16_t padding16; + uint8_t DisplayWatermark; + uint8_t McArbIndex; + uint8_t McRegIndex; + uint8_t SeqIndex; + uint8_t SclkDid; + int8_t SclkIndex; + int8_t MclkIndex; + uint8_t PCIeGen; + +}; + +typedef struct SMU7_Discrete_StateInfo SMU7_Discrete_StateInfo; + + +struct SMU7_Discrete_DpmTable +{ + SMU7_PIDController GraphicsPIDController; + SMU7_PIDController MemoryPIDController; + SMU7_PIDController LinkPIDController; + + uint32_t SystemFlags; + + + uint32_t SmioMaskVddcVid; + uint32_t SmioMaskVddcPhase; + uint32_t SmioMaskVddciVid; + uint32_t SmioMaskMvddVid; + + uint32_t VddcLevelCount; + uint32_t VddciLevelCount; + uint32_t MvddLevelCount; + + SMU7_Discrete_VoltageLevel VddcLevel [SMU7_MAX_LEVELS_VDDC]; +// SMU7_Discrete_VoltageLevel VddcStandardReference [SMU7_MAX_LEVELS_VDDC]; + SMU7_Discrete_VoltageLevel VddciLevel [SMU7_MAX_LEVELS_VDDCI]; + SMU7_Discrete_VoltageLevel MvddLevel [SMU7_MAX_LEVELS_MVDD]; + + uint8_t GraphicsDpmLevelCount; + uint8_t MemoryDpmLevelCount; + uint8_t LinkLevelCount; + uint8_t UvdLevelCount; + uint8_t VceLevelCount; + uint8_t AcpLevelCount; + uint8_t SamuLevelCount; + uint8_t MasterDeepSleepControl; + uint32_t Reserved[5]; +// uint32_t SamuDefaultLevel; + + SMU7_Discrete_GraphicsLevel GraphicsLevel [SMU7_MAX_LEVELS_GRAPHICS]; + SMU7_Discrete_MemoryLevel MemoryACPILevel; + SMU7_Discrete_MemoryLevel MemoryLevel [SMU7_MAX_LEVELS_MEMORY]; + SMU7_Discrete_LinkLevel LinkLevel [SMU7_MAX_LEVELS_LINK]; + SMU7_Discrete_ACPILevel ACPILevel; + SMU7_Discrete_UvdLevel UvdLevel [SMU7_MAX_LEVELS_UVD]; + SMU7_Discrete_ExtClkLevel VceLevel [SMU7_MAX_LEVELS_VCE]; + SMU7_Discrete_ExtClkLevel AcpLevel [SMU7_MAX_LEVELS_ACP]; + SMU7_Discrete_ExtClkLevel SamuLevel [SMU7_MAX_LEVELS_SAMU]; + SMU7_Discrete_Ulv Ulv; + + uint32_t SclkStepSize; + uint32_t Smio [SMU7_MAX_ENTRIES_SMIO]; + + uint8_t UvdBootLevel; + uint8_t VceBootLevel; + uint8_t AcpBootLevel; + uint8_t SamuBootLevel; + + uint8_t UVDInterval; + uint8_t VCEInterval; + uint8_t ACPInterval; + uint8_t SAMUInterval; + + uint8_t GraphicsBootLevel; + uint8_t GraphicsVoltageChangeEnable; + uint8_t GraphicsThermThrottleEnable; + uint8_t GraphicsInterval; + + uint8_t VoltageInterval; + uint8_t ThermalInterval; + uint16_t TemperatureLimitHigh; + + uint16_t TemperatureLimitLow; + uint8_t MemoryBootLevel; + uint8_t MemoryVoltageChangeEnable; + + uint8_t MemoryInterval; + uint8_t MemoryThermThrottleEnable; + uint16_t VddcVddciDelta; + + uint16_t VoltageResponseTime; + uint16_t PhaseResponseTime; + + uint8_t PCIeBootLinkLevel; + uint8_t PCIeGenInterval; + uint8_t DTEInterval; + uint8_t DTEMode; + + uint8_t SVI2Enable; + uint8_t VRHotGpio; + uint8_t AcDcGpio; + uint8_t ThermGpio; + + uint16_t PPM_PkgPwrLimit; + uint16_t PPM_TemperatureLimit; + + uint16_t DefaultTdp; + uint16_t TargetTdp; + + uint16_t FpsHighT; + uint16_t FpsLowT; + + uint16_t BAPMTI_R [SMU7_DTE_ITERATIONS][SMU7_DTE_SOURCES][SMU7_DTE_SINKS]; + uint16_t BAPMTI_RC [SMU7_DTE_ITERATIONS][SMU7_DTE_SOURCES][SMU7_DTE_SINKS]; + + uint8_t DTEAmbientTempBase; + uint8_t DTETjOffset; + uint8_t GpuTjMax; + uint8_t GpuTjHyst; + + uint16_t BootVddc; + uint16_t BootVddci; + + uint16_t BootMVdd; + uint16_t padding; + + uint32_t BAPM_TEMP_GRADIENT; + + uint32_t LowSclkInterruptT; +}; + +typedef struct SMU7_Discrete_DpmTable SMU7_Discrete_DpmTable; + +#define SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 16 +#define SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU7_MAX_LEVELS_MEMORY + +struct SMU7_Discrete_MCRegisterAddress +{ + uint16_t s0; + uint16_t s1; +}; + +typedef struct SMU7_Discrete_MCRegisterAddress SMU7_Discrete_MCRegisterAddress; + +struct SMU7_Discrete_MCRegisterSet +{ + uint32_t value[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; +}; + +typedef struct SMU7_Discrete_MCRegisterSet SMU7_Discrete_MCRegisterSet; + +struct SMU7_Discrete_MCRegisters +{ + uint8_t last; + uint8_t reserved[3]; + SMU7_Discrete_MCRegisterAddress address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; + SMU7_Discrete_MCRegisterSet data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT]; +}; + +typedef struct SMU7_Discrete_MCRegisters SMU7_Discrete_MCRegisters; + +struct SMU7_Discrete_FanTable +{ + uint16_t FdoMode; + int16_t TempMin; + int16_t TempMed; + int16_t TempMax; + int16_t Slope1; + int16_t Slope2; + int16_t FdoMin; + int16_t HystUp; + int16_t HystDown; + int16_t HystSlope; + int16_t TempRespLim; + int16_t TempCurr; + int16_t SlopeCurr; + int16_t PwmCurr; + uint32_t RefreshPeriod; + int16_t FdoMax; + uint8_t TempSrc; + int8_t Padding; +}; + +typedef struct SMU7_Discrete_FanTable SMU7_Discrete_FanTable; + + +struct SMU7_Discrete_PmFuses { + // dw0-dw1 + uint8_t BapmVddCVidHiSidd[8]; + + // dw2-dw3 + uint8_t BapmVddCVidLoSidd[8]; + + // dw4-dw5 + uint8_t VddCVid[8]; + + // dw6 + uint8_t SviLoadLineEn; + uint8_t SviLoadLineVddC; + uint8_t SviLoadLineTrimVddC; + uint8_t SviLoadLineOffsetVddC; + + // dw7 + uint16_t TDC_VDDC_PkgLimit; + uint8_t TDC_VDDC_ThrottleReleaseLimitPerc; + uint8_t TDC_MAWt; + + // dw8 + uint8_t TdcWaterfallCtl; + uint8_t LPMLTemperatureMin; + uint8_t LPMLTemperatureMax; + uint8_t Reserved; + + // dw9-dw10 + uint8_t BapmVddCVidHiSidd2[8]; + + // dw11-dw12 + int16_t FuzzyFan_ErrorSetDelta; + int16_t FuzzyFan_ErrorRateSetDelta; + int16_t FuzzyFan_PwmSetDelta; + uint16_t CalcMeasPowerBlend; + + // dw13-dw16 + uint8_t GnbLPML[16]; + + // dw17 + uint8_t GnbLPMLMaxVid; + uint8_t GnbLPMLMinVid; + uint8_t Reserved1[2]; + + // dw18 + uint16_t BapmVddCBaseLeakageHiSidd; + uint16_t BapmVddCBaseLeakageLoSidd; +}; + +typedef struct SMU7_Discrete_PmFuses SMU7_Discrete_PmFuses; + + +#pragma pack(pop) + +#endif + diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h b/drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h new file mode 100644 index 000000000000..78ada9ffd508 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h @@ -0,0 +1,300 @@ +/* + * Copyright 2013 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef SMU7_FUSION_H +#define SMU7_FUSION_H + +#include "smu7.h" + +#pragma pack(push, 1) + +#define SMU7_DTE_ITERATIONS 5 +#define SMU7_DTE_SOURCES 5 +#define SMU7_DTE_SINKS 3 +#define SMU7_NUM_CPU_TES 2 +#define SMU7_NUM_GPU_TES 1 +#define SMU7_NUM_NON_TES 2 + +// All 'soft registers' should be uint32_t. +struct SMU7_SoftRegisters +{ + uint32_t RefClockFrequency; + uint32_t PmTimerP; + uint32_t FeatureEnables; + uint32_t HandshakeDisables; + + uint8_t DisplayPhy1Config; + uint8_t DisplayPhy2Config; + uint8_t DisplayPhy3Config; + uint8_t DisplayPhy4Config; + + uint8_t DisplayPhy5Config; + uint8_t DisplayPhy6Config; + uint8_t DisplayPhy7Config; + uint8_t DisplayPhy8Config; + + uint32_t AverageGraphicsA; + uint32_t AverageMemoryA; + uint32_t AverageGioA; + + uint8_t SClkDpmEnabledLevels; + uint8_t MClkDpmEnabledLevels; + uint8_t LClkDpmEnabledLevels; + uint8_t PCIeDpmEnabledLevels; + + uint8_t UVDDpmEnabledLevels; + uint8_t SAMUDpmEnabledLevels; + uint8_t ACPDpmEnabledLevels; + uint8_t VCEDpmEnabledLevels; + + uint32_t DRAM_LOG_ADDR_H; + uint32_t DRAM_LOG_ADDR_L; + uint32_t DRAM_LOG_PHY_ADDR_H; + uint32_t DRAM_LOG_PHY_ADDR_L; + uint32_t DRAM_LOG_BUFF_SIZE; + uint32_t UlvEnterC; + uint32_t UlvTime; + uint32_t Reserved[3]; + +}; + +typedef struct SMU7_SoftRegisters SMU7_SoftRegisters; + +struct SMU7_Fusion_GraphicsLevel +{ + uint32_t MinVddNb; + + uint32_t SclkFrequency; + + uint8_t Vid; + uint8_t VidOffset; + uint16_t AT; + + uint8_t PowerThrottle; + uint8_t GnbSlow; + uint8_t ForceNbPs1; + uint8_t SclkDid; + + uint8_t DisplayWatermark; + uint8_t EnabledForActivity; + uint8_t EnabledForThrottle; + uint8_t UpH; + + uint8_t DownH; + uint8_t VoltageDownH; + uint8_t DeepSleepDivId; + + uint8_t ClkBypassCntl; + + uint32_t reserved; +}; + +typedef struct SMU7_Fusion_GraphicsLevel SMU7_Fusion_GraphicsLevel; + +struct SMU7_Fusion_GIOLevel +{ + uint8_t EnabledForActivity; + uint8_t LclkDid; + uint8_t Vid; + uint8_t VoltageDownH; + + uint32_t MinVddNb; + + uint16_t ResidencyCounter; + uint8_t UpH; + uint8_t DownH; + + uint32_t LclkFrequency; + + uint8_t ActivityLevel; + uint8_t EnabledForThrottle; + + uint8_t ClkBypassCntl; + + uint8_t padding; +}; + +typedef struct SMU7_Fusion_GIOLevel SMU7_Fusion_GIOLevel; + +// UVD VCLK/DCLK state (level) definition. +struct SMU7_Fusion_UvdLevel +{ + uint32_t VclkFrequency; + uint32_t DclkFrequency; + uint16_t MinVddNb; + uint8_t VclkDivider; + uint8_t DclkDivider; + + uint8_t VClkBypassCntl; + uint8_t DClkBypassCntl; + + uint8_t padding[2]; + +}; + +typedef struct SMU7_Fusion_UvdLevel SMU7_Fusion_UvdLevel; + +// Clocks for other external blocks (VCE, ACP, SAMU). +struct SMU7_Fusion_ExtClkLevel +{ + uint32_t Frequency; + uint16_t MinVoltage; + uint8_t Divider; + uint8_t ClkBypassCntl; + + uint32_t Reserved; +}; +typedef struct SMU7_Fusion_ExtClkLevel SMU7_Fusion_ExtClkLevel; + +struct SMU7_Fusion_ACPILevel +{ + uint32_t Flags; + uint32_t MinVddNb; + uint32_t SclkFrequency; + uint8_t SclkDid; + uint8_t GnbSlow; + uint8_t ForceNbPs1; + uint8_t DisplayWatermark; + uint8_t DeepSleepDivId; + uint8_t padding[3]; +}; + +typedef struct SMU7_Fusion_ACPILevel SMU7_Fusion_ACPILevel; + +struct SMU7_Fusion_NbDpm +{ + uint8_t DpmXNbPsHi; + uint8_t DpmXNbPsLo; + uint8_t Dpm0PgNbPsHi; + uint8_t Dpm0PgNbPsLo; + uint8_t EnablePsi1; + uint8_t SkipDPM0; + uint8_t SkipPG; + uint8_t Hysteresis; + uint8_t EnableDpmPstatePoll; + uint8_t padding[3]; +}; + +typedef struct SMU7_Fusion_NbDpm SMU7_Fusion_NbDpm; + +struct SMU7_Fusion_StateInfo +{ + uint32_t SclkFrequency; + uint32_t LclkFrequency; + uint32_t VclkFrequency; + uint32_t DclkFrequency; + uint32_t SamclkFrequency; + uint32_t AclkFrequency; + uint32_t EclkFrequency; + uint8_t DisplayWatermark; + uint8_t McArbIndex; + int8_t SclkIndex; + int8_t MclkIndex; +}; + +typedef struct SMU7_Fusion_StateInfo SMU7_Fusion_StateInfo; + +struct SMU7_Fusion_DpmTable +{ + uint32_t SystemFlags; + + SMU7_PIDController GraphicsPIDController; + SMU7_PIDController GioPIDController; + + uint8_t GraphicsDpmLevelCount; + uint8_t GIOLevelCount; + uint8_t UvdLevelCount; + uint8_t VceLevelCount; + + uint8_t AcpLevelCount; + uint8_t SamuLevelCount; + uint16_t FpsHighT; + + SMU7_Fusion_GraphicsLevel GraphicsLevel [SMU__NUM_SCLK_DPM_STATE]; + SMU7_Fusion_ACPILevel ACPILevel; + SMU7_Fusion_UvdLevel UvdLevel [SMU7_MAX_LEVELS_UVD]; + SMU7_Fusion_ExtClkLevel VceLevel [SMU7_MAX_LEVELS_VCE]; + SMU7_Fusion_ExtClkLevel AcpLevel [SMU7_MAX_LEVELS_ACP]; + SMU7_Fusion_ExtClkLevel SamuLevel [SMU7_MAX_LEVELS_SAMU]; + + uint8_t UvdBootLevel; + uint8_t VceBootLevel; + uint8_t AcpBootLevel; + uint8_t SamuBootLevel; + uint8_t UVDInterval; + uint8_t VCEInterval; + uint8_t ACPInterval; + uint8_t SAMUInterval; + + uint8_t GraphicsBootLevel; + uint8_t GraphicsInterval; + uint8_t GraphicsThermThrottleEnable; + uint8_t GraphicsVoltageChangeEnable; + + uint8_t GraphicsClkSlowEnable; + uint8_t GraphicsClkSlowDivider; + uint16_t FpsLowT; + + uint32_t DisplayCac; + uint32_t LowSclkInterruptT; + + uint32_t DRAM_LOG_ADDR_H; + uint32_t DRAM_LOG_ADDR_L; + uint32_t DRAM_LOG_PHY_ADDR_H; + uint32_t DRAM_LOG_PHY_ADDR_L; + uint32_t DRAM_LOG_BUFF_SIZE; + +}; + +struct SMU7_Fusion_GIODpmTable +{ + + SMU7_Fusion_GIOLevel GIOLevel [SMU7_MAX_LEVELS_GIO]; + + SMU7_PIDController GioPIDController; + + uint32_t GIOLevelCount; + + uint8_t Enable; + uint8_t GIOVoltageChangeEnable; + uint8_t GIOBootLevel; + uint8_t padding; + uint8_t padding1[2]; + uint8_t TargetState; + uint8_t CurrenttState; + uint8_t ThrottleOnHtc; + uint8_t ThermThrottleStatus; + uint8_t ThermThrottleTempSelect; + uint8_t ThermThrottleEnable; + uint16_t TemperatureLimitHigh; + uint16_t TemperatureLimitLow; + +}; + +typedef struct SMU7_Fusion_DpmTable SMU7_Fusion_DpmTable; +typedef struct SMU7_Fusion_GIODpmTable SMU7_Fusion_GIODpmTable; + +#pragma pack(pop) + +#endif + diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu8.h b/drivers/gpu/drm/amd/powerplay/inc/smu8.h new file mode 100644 index 000000000000..d758d07b6a31 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/smu8.h @@ -0,0 +1,72 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef SMU8_H +#define SMU8_H + +#pragma pack(push, 1) + +#define ENABLE_DEBUG_FEATURES + +struct SMU8_Firmware_Header { + uint32_t Version; + uint32_t ImageSize; + uint32_t CodeSize; + uint32_t HeaderSize; + uint32_t EntryPoint; + uint32_t Rtos; + uint32_t UcodeLoadStatus; + uint32_t DpmTable; + uint32_t FanTable; + uint32_t PmFuseTable; + uint32_t Globals; + uint32_t Reserved[20]; + uint32_t Signature; +}; + +struct SMU8_MultimediaPowerLogData { + uint32_t avgTotalPower; + uint32_t avgGpuPower; + uint32_t avgUvdPower; + uint32_t avgVcePower; + + uint32_t avgSclk; + uint32_t avgDclk; + uint32_t avgVclk; + uint32_t avgEclk; + + uint32_t startTimeHi; + uint32_t startTimeLo; + + uint32_t endTimeHi; + uint32_t endTimeLo; +}; + +#define SMU8_FIRMWARE_HEADER_LOCATION 0x1FF80 +#define SMU8_UNBCSR_START_ADDR 0xC0100000 + +#define SMN_MP1_SRAM_START_ADDR 0x10000000 + +#pragma pack(pop) + +#endif diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h b/drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h new file mode 100644 index 000000000000..0c37c94e9414 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h @@ -0,0 +1,135 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef SMU8_FUSION_H +#define SMU8_FUSION_H + +#include "smu8.h" + +#pragma pack(push, 1) + +#define SMU8_MAX_CUS 2 +#define SMU8_PSMS_PER_CU 4 +#define SMU8_CACS_PER_CU 4 + +struct SMU8_GfxCuPgScoreboard { + uint8_t Enabled; + uint8_t spare[3]; +}; + +struct SMU8_Port80MonitorTable { + uint32_t MmioAddress; + uint32_t MemoryBaseHi; + uint32_t MemoryBaseLo; + uint16_t MemoryBufferSize; + uint16_t MemoryPosition; + uint16_t PollingInterval; + uint8_t EnableCsrShadow; + uint8_t EnableDramShadow; +}; + +/* Display specific power management parameters */ +#define PWRMGT_SEPARATION_TIME_SHIFT 0 +#define PWRMGT_SEPARATION_TIME_MASK 0xFFFF +#define PWRMGT_DISABLE_CPU_CSTATES_SHIFT 16 +#define PWRMGT_DISABLE_CPU_CSTATES_MASK 0x1 +#define PWRMGT_DISABLE_CPU_PSTATES_SHIFT 24 +#define PWRMGT_DISABLE_CPU_PSTATES_MASK 0x1 + +/* Clock Table Definitions */ +#define NUM_SCLK_LEVELS 8 +#define NUM_LCLK_LEVELS 8 +#define NUM_UVD_LEVELS 8 +#define NUM_ECLK_LEVELS 8 +#define NUM_ACLK_LEVELS 8 + +struct SMU8_Fusion_ClkLevel { + uint8_t GnbVid; + uint8_t GfxVid; + uint8_t DfsDid; + uint8_t DeepSleepDid; + uint32_t DfsBypass; + uint32_t Frequency; +}; + +struct SMU8_Fusion_SclkBreakdownTable { + struct SMU8_Fusion_ClkLevel ClkLevel[NUM_SCLK_LEVELS]; + struct SMU8_Fusion_ClkLevel DpmOffLevel; + /* SMU8_Fusion_ClkLevel PwrOffLevel; */ + uint32_t SclkValidMask; + uint32_t MaxSclkIndex; +}; + +struct SMU8_Fusion_LclkBreakdownTable { + struct SMU8_Fusion_ClkLevel ClkLevel[NUM_LCLK_LEVELS]; + struct SMU8_Fusion_ClkLevel DpmOffLevel; + /* SMU8_Fusion_ClkLevel PwrOffLevel; */ + uint32_t LclkValidMask; + uint32_t MaxLclkIndex; +}; + +struct SMU8_Fusion_EclkBreakdownTable { + struct SMU8_Fusion_ClkLevel ClkLevel[NUM_ECLK_LEVELS]; + struct SMU8_Fusion_ClkLevel DpmOffLevel; + struct SMU8_Fusion_ClkLevel PwrOffLevel; + uint32_t EclkValidMask; + uint32_t MaxEclkIndex; +}; + +struct SMU8_Fusion_VclkBreakdownTable { + struct SMU8_Fusion_ClkLevel ClkLevel[NUM_UVD_LEVELS]; + struct SMU8_Fusion_ClkLevel DpmOffLevel; + struct SMU8_Fusion_ClkLevel PwrOffLevel; + uint32_t VclkValidMask; + uint32_t MaxVclkIndex; +}; + +struct SMU8_Fusion_DclkBreakdownTable { + struct SMU8_Fusion_ClkLevel ClkLevel[NUM_UVD_LEVELS]; + struct SMU8_Fusion_ClkLevel DpmOffLevel; + struct SMU8_Fusion_ClkLevel PwrOffLevel; + uint32_t DclkValidMask; + uint32_t MaxDclkIndex; +}; + +struct SMU8_Fusion_AclkBreakdownTable { + struct SMU8_Fusion_ClkLevel ClkLevel[NUM_ACLK_LEVELS]; + struct SMU8_Fusion_ClkLevel DpmOffLevel; + struct SMU8_Fusion_ClkLevel PwrOffLevel; + uint32_t AclkValidMask; + uint32_t MaxAclkIndex; +}; + + +struct SMU8_Fusion_ClkTable { + struct SMU8_Fusion_SclkBreakdownTable SclkBreakdownTable; + struct SMU8_Fusion_LclkBreakdownTable LclkBreakdownTable; + struct SMU8_Fusion_EclkBreakdownTable EclkBreakdownTable; + struct SMU8_Fusion_VclkBreakdownTable VclkBreakdownTable; + struct SMU8_Fusion_DclkBreakdownTable DclkBreakdownTable; + struct SMU8_Fusion_AclkBreakdownTable AclkBreakdownTable; +}; + +#pragma pack(pop) + +#endif diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_cz.h b/drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_cz.h new file mode 100644 index 000000000000..f8ba071f39c8 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_cz.h @@ -0,0 +1,147 @@ +// CZ Ucode Loading Definitions +#ifndef SMU_UCODE_XFER_CZ_H +#define SMU_UCODE_XFER_CZ_H + +#define NUM_JOBLIST_ENTRIES 32 + +#define TASK_TYPE_NO_ACTION 0 +#define TASK_TYPE_UCODE_LOAD 1 +#define TASK_TYPE_UCODE_SAVE 2 +#define TASK_TYPE_REG_LOAD 3 +#define TASK_TYPE_REG_SAVE 4 +#define TASK_TYPE_INITIALIZE 5 + +#define TASK_ARG_REG_SMCIND 0 +#define TASK_ARG_REG_MMIO 1 +#define TASK_ARG_REG_FCH 2 +#define TASK_ARG_REG_UNB 3 + +#define TASK_ARG_INIT_MM_PWR_LOG 0 +#define TASK_ARG_INIT_CLK_TABLE 1 + +#define JOB_GFX_SAVE 0 +#define JOB_GFX_RESTORE 1 +#define JOB_FCH_SAVE 2 +#define JOB_FCH_RESTORE 3 +#define JOB_UNB_SAVE 4 +#define JOB_UNB_RESTORE 5 +#define JOB_GMC_SAVE 6 +#define JOB_GMC_RESTORE 7 +#define JOB_GNB_SAVE 8 +#define JOB_GNB_RESTORE 9 + +#define IGNORE_JOB 0xff +#define END_OF_TASK_LIST (uint16_t)0xffff + +// Size of DRAM regions (in bytes) requested by SMU: +#define SMU_DRAM_REQ_MM_PWR_LOG 48 + +#define UCODE_ID_SDMA0 0 +#define UCODE_ID_SDMA1 1 +#define UCODE_ID_CP_CE 2 +#define UCODE_ID_CP_PFP 3 +#define UCODE_ID_CP_ME 4 +#define UCODE_ID_CP_MEC_JT1 5 +#define UCODE_ID_CP_MEC_JT2 6 +#define UCODE_ID_GMCON_RENG 7 +#define UCODE_ID_RLC_G 8 +#define UCODE_ID_RLC_SCRATCH 9 +#define UCODE_ID_RLC_SRM_ARAM 10 +#define UCODE_ID_RLC_SRM_DRAM 11 +#define UCODE_ID_DMCU_ERAM 12 +#define UCODE_ID_DMCU_IRAM 13 + +#define UCODE_ID_SDMA0_MASK 0x00000001 +#define UCODE_ID_SDMA1_MASK 0x00000002 +#define UCODE_ID_CP_CE_MASK 0x00000004 +#define UCODE_ID_CP_PFP_MASK 0x00000008 +#define UCODE_ID_CP_ME_MASK 0x00000010 +#define UCODE_ID_CP_MEC_JT1_MASK 0x00000020 +#define UCODE_ID_CP_MEC_JT2_MASK 0x00000040 +#define UCODE_ID_GMCON_RENG_MASK 0x00000080 +#define UCODE_ID_RLC_G_MASK 0x00000100 +#define UCODE_ID_RLC_SCRATCH_MASK 0x00000200 +#define UCODE_ID_RLC_SRM_ARAM_MASK 0x00000400 +#define UCODE_ID_RLC_SRM_DRAM_MASK 0x00000800 +#define UCODE_ID_DMCU_ERAM_MASK 0x00001000 +#define UCODE_ID_DMCU_IRAM_MASK 0x00002000 + +#define UCODE_ID_SDMA0_SIZE_BYTE 10368 +#define UCODE_ID_SDMA1_SIZE_BYTE 10368 +#define UCODE_ID_CP_CE_SIZE_BYTE 8576 +#define UCODE_ID_CP_PFP_SIZE_BYTE 16768 +#define UCODE_ID_CP_ME_SIZE_BYTE 16768 +#define UCODE_ID_CP_MEC_JT1_SIZE_BYTE 384 +#define UCODE_ID_CP_MEC_JT2_SIZE_BYTE 384 +#define UCODE_ID_GMCON_RENG_SIZE_BYTE 4096 +#define UCODE_ID_RLC_G_SIZE_BYTE 2048 +#define UCODE_ID_RLC_SCRATCH_SIZE_BYTE 132 +#define UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE 8192 +#define UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE 4096 +#define UCODE_ID_DMCU_ERAM_SIZE_BYTE 24576 +#define UCODE_ID_DMCU_IRAM_SIZE_BYTE 1024 + +#define NUM_UCODES 14 + +typedef struct { + uint32_t high; + uint32_t low; +} data_64_t; + +struct SMU_Task { + uint8_t type; + uint8_t arg; + uint16_t next; + data_64_t addr; + uint32_t size_bytes; +}; +typedef struct SMU_Task SMU_Task; + +struct TOC { + uint8_t JobList[NUM_JOBLIST_ENTRIES]; + SMU_Task tasks[1]; +}; + +// META DATA COMMAND Definitions +#define METADATA_CMD_MODE0 0x00000103 +#define METADATA_CMD_MODE1 0x00000113 +#define METADATA_CMD_MODE2 0x00000123 +#define METADATA_CMD_MODE3 0x00000133 +#define METADATA_CMD_DELAY 0x00000203 +#define METADATA_CMD_CHNG_REGSPACE 0x00000303 +#define METADATA_PERFORM_ON_SAVE 0x00001000 +#define METADATA_PERFORM_ON_LOAD 0x00002000 +#define METADATA_CMD_ARG_MASK 0xFFFF0000 +#define METADATA_CMD_ARG_SHIFT 16 + +// Simple register addr/data fields +struct SMU_MetaData_Mode0 { + uint32_t register_address; + uint32_t register_data; +}; +typedef struct SMU_MetaData_Mode0 SMU_MetaData_Mode0; + +// Register addr/data with mask +struct SMU_MetaData_Mode1 { + uint32_t register_address; + uint32_t register_mask; + uint32_t register_data; +}; +typedef struct SMU_MetaData_Mode1 SMU_MetaData_Mode1; + +struct SMU_MetaData_Mode2 { + uint32_t register_address; + uint32_t register_mask; + uint32_t target_value; +}; +typedef struct SMU_MetaData_Mode2 SMU_MetaData_Mode2; + +// Always write data (even on a save operation) +struct SMU_MetaData_Mode3 { + uint32_t register_address; + uint32_t register_mask; + uint32_t register_data; +}; +typedef struct SMU_MetaData_Mode3 SMU_MetaData_Mode3; + +#endif diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h b/drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h new file mode 100644 index 000000000000..c24a81eebc7c --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h @@ -0,0 +1,100 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef SMU_UCODE_XFER_VI_H +#define SMU_UCODE_XFER_VI_H + +#define SMU_DRAMData_TOC_VERSION 1 +#define MAX_IH_REGISTER_COUNT 65535 +#define SMU_DIGEST_SIZE_BYTES 20 +#define SMU_FB_SIZE_BYTES 1048576 +#define SMU_MAX_ENTRIES 12 + +#define UCODE_ID_SMU 0 +#define UCODE_ID_SDMA0 1 +#define UCODE_ID_SDMA1 2 +#define UCODE_ID_CP_CE 3 +#define UCODE_ID_CP_PFP 4 +#define UCODE_ID_CP_ME 5 +#define UCODE_ID_CP_MEC 6 +#define UCODE_ID_CP_MEC_JT1 7 +#define UCODE_ID_CP_MEC_JT2 8 +#define UCODE_ID_GMCON_RENG 9 +#define UCODE_ID_RLC_G 10 +#define UCODE_ID_IH_REG_RESTORE 11 +#define UCODE_ID_VBIOS 12 +#define UCODE_ID_MISC_METADATA 13 +#define UCODE_ID_RLC_SCRATCH 32 +#define UCODE_ID_RLC_SRM_ARAM 33 +#define UCODE_ID_RLC_SRM_DRAM 34 +#define UCODE_ID_MEC_STORAGE 35 +#define UCODE_ID_VBIOS_PARAMETERS 36 +#define UCODE_META_DATA 0xFF + +#define UCODE_ID_SMU_MASK 0x00000001 +#define UCODE_ID_SDMA0_MASK 0x00000002 +#define UCODE_ID_SDMA1_MASK 0x00000004 +#define UCODE_ID_CP_CE_MASK 0x00000008 +#define UCODE_ID_CP_PFP_MASK 0x00000010 +#define UCODE_ID_CP_ME_MASK 0x00000020 +#define UCODE_ID_CP_MEC_MASK 0x00000040 +#define UCODE_ID_CP_MEC_JT1_MASK 0x00000080 +#define UCODE_ID_CP_MEC_JT2_MASK 0x00000100 +#define UCODE_ID_GMCON_RENG_MASK 0x00000200 +#define UCODE_ID_RLC_G_MASK 0x00000400 +#define UCODE_ID_IH_REG_RESTORE_MASK 0x00000800 +#define UCODE_ID_VBIOS_MASK 0x00001000 + +#define UCODE_FLAG_UNHALT_MASK 0x1 + +struct SMU_Entry { +#ifndef __BIG_ENDIAN + uint16_t id; + uint16_t version; + uint32_t image_addr_high; + uint32_t image_addr_low; + uint32_t meta_data_addr_high; + uint32_t meta_data_addr_low; + uint32_t data_size_byte; + uint16_t flags; + uint16_t num_register_entries; +#else + uint16_t version; + uint16_t id; + uint32_t image_addr_high; + uint32_t image_addr_low; + uint32_t meta_data_addr_high; + uint32_t meta_data_addr_low; + uint32_t data_size_byte; + uint16_t num_register_entries; + uint16_t flags; +#endif +}; + +struct SMU_DRAMData_TOC { + uint32_t structure_version; + uint32_t num_entries; + struct SMU_Entry entry[SMU_MAX_ENTRIES]; +}; + +#endif diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h new file mode 100644 index 000000000000..504f035d1843 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h @@ -0,0 +1,182 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _SMUMGR_H_ +#define _SMUMGR_H_ +#include <linux/types.h> +#include "pp_instance.h" +#include "amd_powerplay.h" + +struct pp_smumgr; +struct pp_instance; + +#define smu_lower_32_bits(n) ((uint32_t)(n)) +#define smu_upper_32_bits(n) ((uint32_t)(((n)>>16)>>16)) + +struct pp_smumgr_func { + int (*smu_init)(struct pp_smumgr *smumgr); + int (*smu_fini)(struct pp_smumgr *smumgr); + int (*start_smu)(struct pp_smumgr *smumgr); + int (*check_fw_load_finish)(struct pp_smumgr *smumgr, + uint32_t firmware); + int (*request_smu_load_fw)(struct pp_smumgr *smumgr); + int (*request_smu_load_specific_fw)(struct pp_smumgr *smumgr, + uint32_t firmware); + int (*get_argument)(struct pp_smumgr *smumgr); + int (*send_msg_to_smc)(struct pp_smumgr *smumgr, uint16_t msg); + int (*send_msg_to_smc_with_parameter)(struct pp_smumgr *smumgr, + uint16_t msg, uint32_t parameter); + int (*download_pptable_settings)(struct pp_smumgr *smumgr, + void **table); + int (*upload_pptable_settings)(struct pp_smumgr *smumgr); +}; + +struct pp_smumgr { + uint32_t chip_family; + uint32_t chip_id; + uint32_t hw_revision; + void *device; + void *backend; + uint32_t usec_timeout; + bool reload_fw; + const struct pp_smumgr_func *smumgr_funcs; +}; + + +extern int smum_init(struct amd_pp_init *pp_init, + struct pp_instance *handle); + +extern int smum_fini(struct pp_smumgr *smumgr); + +extern int smum_get_argument(struct pp_smumgr *smumgr); + +extern int smum_download_powerplay_table(struct pp_smumgr *smumgr, void **table); + +extern int smum_upload_powerplay_table(struct pp_smumgr *smumgr); + +extern int smum_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg); + +extern int smum_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, + uint16_t msg, uint32_t parameter); + +extern int smum_wait_on_register(struct pp_smumgr *smumgr, + uint32_t index, uint32_t value, uint32_t mask); + +extern int smum_wait_for_register_unequal(struct pp_smumgr *smumgr, + uint32_t index, uint32_t value, uint32_t mask); + +extern int smum_wait_on_indirect_register(struct pp_smumgr *smumgr, + uint32_t indirect_port, uint32_t index, + uint32_t value, uint32_t mask); + + +extern void smum_wait_for_indirect_register_unequal( + struct pp_smumgr *smumgr, + uint32_t indirect_port, uint32_t index, + uint32_t value, uint32_t mask); + +extern int smu_allocate_memory(void *device, uint32_t size, + enum cgs_gpu_mem_type type, + uint32_t byte_align, uint64_t *mc_addr, + void **kptr, void *handle); + +extern int smu_free_memory(void *device, void *handle); + +#define SMUM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT + +#define SMUM_FIELD_MASK(reg, field) reg##__##field##_MASK + +#define SMUM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, \ + port, index, value, mask) \ + smum_wait_on_indirect_register(smumgr, \ + mm##port##_INDEX, index, value, mask) + + +#define SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, \ + index, value, mask) \ + smum_wait_for_register_unequal(smumgr, \ + index, value, mask) + +#define SMUM_WAIT_REGISTER_UNEQUAL(smumgr, reg, value, mask) \ + SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, \ + mm##reg, value, mask) + +#define SMUM_WAIT_FIELD_UNEQUAL(smumgr, reg, field, fieldval) \ + SMUM_WAIT_REGISTER_UNEQUAL(smumgr, reg, \ + (fieldval) << SMUM_FIELD_SHIFT(reg, field), \ + SMUM_FIELD_MASK(reg, field)) + +#define SMUM_GET_FIELD(value, reg, field) \ + (((value) & SMUM_FIELD_MASK(reg, field)) \ + >> SMUM_FIELD_SHIFT(reg, field)) + +#define SMUM_READ_FIELD(device, reg, field) \ + SMUM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field) + +#define SMUM_SET_FIELD(value, reg, field, field_val) \ + (((value) & ~SMUM_FIELD_MASK(reg, field)) | \ + (SMUM_FIELD_MASK(reg, field) & ((field_val) << \ + SMUM_FIELD_SHIFT(reg, field)))) + +#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, \ + port, index, value, mask) \ + smum_wait_on_indirect_register(smumgr, \ + mm##port##_INDEX_0, index, value, mask) + +#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, \ + port, index, value, mask) \ + smum_wait_for_indirect_register_unequal(smumgr, \ + mm##port##_INDEX_0, index, value, mask) + + +#define SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, port, reg, value, mask) \ + SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, port, ix##reg, value, mask) + +#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, value, mask) \ + SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, ix##reg, value, mask) + + +/*Operations on named fields.*/ + +#define SMUM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \ + SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ + reg, field) + +#define SMUM_WRITE_FIELD(device, reg, field, fieldval) \ + cgs_write_register(device, mm##reg, \ + SMUM_SET_FIELD(cgs_read_register(device, mm##reg), reg, field, fieldval)) + +#define SMUM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval) \ + cgs_write_ind_register(device, port, ix##reg, \ + SMUM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ + reg, field, fieldval)) + +#define SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, port, reg, field, fieldval) \ + SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, port, reg, \ + (fieldval) << SMUM_FIELD_SHIFT(reg, field), \ + SMUM_FIELD_MASK(reg, field)) + +#define SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, port, reg, field, fieldval) \ + SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, \ + (fieldval) << SMUM_FIELD_SHIFT(reg, field), \ + SMUM_FIELD_MASK(reg, field)) +#endif diff --git a/drivers/gpu/drm/amd/powerplay/inc/tonga_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/tonga_ppsmc.h new file mode 100644 index 000000000000..63631296d751 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/inc/tonga_ppsmc.h @@ -0,0 +1,420 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef TONGA_PP_SMC_H +#define TONGA_PP_SMC_H + +#pragma pack(push, 1) + +#define PPSMC_SWSTATE_FLAG_DC 0x01 +#define PPSMC_SWSTATE_FLAG_UVD 0x02 +#define PPSMC_SWSTATE_FLAG_VCE 0x04 +#define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08 + +#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00 +#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01 +#define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff + +#define PPSMC_SYSTEMFLAG_GPIO_DC 0x01 +#define PPSMC_SYSTEMFLAG_STEPVDDC 0x02 +#define PPSMC_SYSTEMFLAG_GDDR5 0x04 + +#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08 + +#define PPSMC_SYSTEMFLAG_REGULATOR_HOT 0x10 +#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG 0x20 +#define PPSMC_SYSTEMFLAG_12CHANNEL 0x40 + + +#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK 0x07 +#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK 0x08 + +#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE 0x00 +#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE 0x01 + +#define PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH 0x10 +#define PPSMC_EXTRAFLAGS_DRIVER_TO_GPIO17 0x20 +#define PPSMC_EXTRAFLAGS_PCC_TO_GPIO17 0x40 + +/* Defines for DPM 2.0 */ +#define PPSMC_DPM2FLAGS_TDPCLMP 0x01 +#define PPSMC_DPM2FLAGS_PWRSHFT 0x02 +#define PPSMC_DPM2FLAGS_OCP 0x04 + +/* Defines for display watermark level */ + +#define PPSMC_DISPLAY_WATERMARK_LOW 0 +#define PPSMC_DISPLAY_WATERMARK_HIGH 1 + +/* In the HW performance level's state flags:*/ +#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01 +#define PPSMC_STATEFLAG_POWERBOOST 0x02 +#define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT 0x04 +#define PPSMC_STATEFLAG_POWERSHIFT 0x08 +#define PPSMC_STATEFLAG_SLOW_READ_MARGIN 0x10 +#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20 +#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS 0x40 + +/* Fan control algorithm:*/ +#define FDO_MODE_HARDWARE 0 +#define FDO_MODE_PIECE_WISE_LINEAR 1 + +enum FAN_CONTROL { + FAN_CONTROL_FUZZY, + FAN_CONTROL_TABLE +}; + +/* Return codes for driver to SMC communication.*/ + +#define PPSMC_Result_OK ((uint16_t)0x01) +#define PPSMC_Result_NoMore ((uint16_t)0x02) +#define PPSMC_Result_NotNow ((uint16_t)0x03) + +#define PPSMC_Result_Failed ((uint16_t)0xFF) +#define PPSMC_Result_UnknownCmd ((uint16_t)0xFE) +#define PPSMC_Result_UnknownVT ((uint16_t)0xFD) + +typedef uint16_t PPSMC_Result; + +#define PPSMC_isERROR(x) ((uint16_t)0x80 & (x)) + + +#define PPSMC_MSG_Halt ((uint16_t)0x10) +#define PPSMC_MSG_Resume ((uint16_t)0x11) +#define PPSMC_MSG_EnableDPMLevel ((uint16_t)0x12) +#define PPSMC_MSG_ZeroLevelsDisabled ((uint16_t)0x13) +#define PPSMC_MSG_OneLevelsDisabled ((uint16_t)0x14) +#define PPSMC_MSG_TwoLevelsDisabled ((uint16_t)0x15) +#define PPSMC_MSG_EnableThermalInterrupt ((uint16_t)0x16) +#define PPSMC_MSG_RunningOnAC ((uint16_t)0x17) +#define PPSMC_MSG_LevelUp ((uint16_t)0x18) +#define PPSMC_MSG_LevelDown ((uint16_t)0x19) +#define PPSMC_MSG_ResetDPMCounters ((uint16_t)0x1a) +#define PPSMC_MSG_SwitchToSwState ((uint16_t)0x20) + +#define PPSMC_MSG_SwitchToSwStateLast ((uint16_t)0x3f) +#define PPSMC_MSG_SwitchToInitialState ((uint16_t)0x40) +#define PPSMC_MSG_NoForcedLevel ((uint16_t)0x41) +#define PPSMC_MSG_ForceHigh ((uint16_t)0x42) +#define PPSMC_MSG_ForceMediumOrHigh ((uint16_t)0x43) + +#define PPSMC_MSG_SwitchToMinimumPower ((uint16_t)0x51) +#define PPSMC_MSG_ResumeFromMinimumPower ((uint16_t)0x52) +#define PPSMC_MSG_EnableCac ((uint16_t)0x53) +#define PPSMC_MSG_DisableCac ((uint16_t)0x54) +#define PPSMC_DPMStateHistoryStart ((uint16_t)0x55) +#define PPSMC_DPMStateHistoryStop ((uint16_t)0x56) +#define PPSMC_CACHistoryStart ((uint16_t)0x57) +#define PPSMC_CACHistoryStop ((uint16_t)0x58) +#define PPSMC_TDPClampingActive ((uint16_t)0x59) +#define PPSMC_TDPClampingInactive ((uint16_t)0x5A) +#define PPSMC_StartFanControl ((uint16_t)0x5B) +#define PPSMC_StopFanControl ((uint16_t)0x5C) +#define PPSMC_NoDisplay ((uint16_t)0x5D) +#define PPSMC_HasDisplay ((uint16_t)0x5E) +#define PPSMC_MSG_UVDPowerOFF ((uint16_t)0x60) +#define PPSMC_MSG_UVDPowerON ((uint16_t)0x61) +#define PPSMC_MSG_EnableULV ((uint16_t)0x62) +#define PPSMC_MSG_DisableULV ((uint16_t)0x63) +#define PPSMC_MSG_EnterULV ((uint16_t)0x64) +#define PPSMC_MSG_ExitULV ((uint16_t)0x65) +#define PPSMC_PowerShiftActive ((uint16_t)0x6A) +#define PPSMC_PowerShiftInactive ((uint16_t)0x6B) +#define PPSMC_OCPActive ((uint16_t)0x6C) +#define PPSMC_OCPInactive ((uint16_t)0x6D) +#define PPSMC_CACLongTermAvgEnable ((uint16_t)0x6E) +#define PPSMC_CACLongTermAvgDisable ((uint16_t)0x6F) +#define PPSMC_MSG_InferredStateSweep_Start ((uint16_t)0x70) +#define PPSMC_MSG_InferredStateSweep_Stop ((uint16_t)0x71) +#define PPSMC_MSG_SwitchToLowestInfState ((uint16_t)0x72) +#define PPSMC_MSG_SwitchToNonInfState ((uint16_t)0x73) +#define PPSMC_MSG_AllStateSweep_Start ((uint16_t)0x74) +#define PPSMC_MSG_AllStateSweep_Stop ((uint16_t)0x75) +#define PPSMC_MSG_SwitchNextLowerInfState ((uint16_t)0x76) +#define PPSMC_MSG_SwitchNextHigherInfState ((uint16_t)0x77) +#define PPSMC_MSG_MclkRetrainingTest ((uint16_t)0x78) +#define PPSMC_MSG_ForceTDPClamping ((uint16_t)0x79) +#define PPSMC_MSG_CollectCAC_PowerCorreln ((uint16_t)0x7A) +#define PPSMC_MSG_CollectCAC_WeightCalib ((uint16_t)0x7B) +#define PPSMC_MSG_CollectCAC_SQonly ((uint16_t)0x7C) +#define PPSMC_MSG_CollectCAC_TemperaturePwr ((uint16_t)0x7D) + +#define PPSMC_MSG_ExtremitiesTest_Start ((uint16_t)0x7E) +#define PPSMC_MSG_ExtremitiesTest_Stop ((uint16_t)0x7F) +#define PPSMC_FlushDataCache ((uint16_t)0x80) +#define PPSMC_FlushInstrCache ((uint16_t)0x81) + +#define PPSMC_MSG_SetEnabledLevels ((uint16_t)0x82) +#define PPSMC_MSG_SetForcedLevels ((uint16_t)0x83) + +#define PPSMC_MSG_ResetToDefaults ((uint16_t)0x84) + +#define PPSMC_MSG_SetForcedLevelsAndJump ((uint16_t)0x85) +#define PPSMC_MSG_SetCACHistoryMode ((uint16_t)0x86) +#define PPSMC_MSG_EnableDTE ((uint16_t)0x87) +#define PPSMC_MSG_DisableDTE ((uint16_t)0x88) + +#define PPSMC_MSG_SmcSpaceSetAddress ((uint16_t)0x89) +#define PPSMC_MSG_ChangeNearTDPLimit ((uint16_t)0x90) +#define PPSMC_MSG_ChangeSafePowerLimit ((uint16_t)0x91) + +#define PPSMC_MSG_DPMStateSweepStart ((uint16_t)0x92) +#define PPSMC_MSG_DPMStateSweepStop ((uint16_t)0x93) + +#define PPSMC_MSG_OVRDDisableSCLKDS ((uint16_t)0x94) +#define PPSMC_MSG_CancelDisableOVRDSCLKDS ((uint16_t)0x95) +#define PPSMC_MSG_ThrottleOVRDSCLKDS ((uint16_t)0x96) +#define PPSMC_MSG_CancelThrottleOVRDSCLKDS ((uint16_t)0x97) +#define PPSMC_MSG_GPIO17 ((uint16_t)0x98) + +#define PPSMC_MSG_API_SetSvi2Volt_Vddc ((uint16_t)0x99) +#define PPSMC_MSG_API_SetSvi2Volt_Vddci ((uint16_t)0x9A) +#define PPSMC_MSG_API_SetSvi2Volt_Mvdd ((uint16_t)0x9B) +#define PPSMC_MSG_API_GetSvi2Volt_Vddc ((uint16_t)0x9C) +#define PPSMC_MSG_API_GetSvi2Volt_Vddci ((uint16_t)0x9D) +#define PPSMC_MSG_API_GetSvi2Volt_Mvdd ((uint16_t)0x9E) + +#define PPSMC_MSG_BREAK ((uint16_t)0xF8) + +/* Trinity Specific Messages*/ +#define PPSMC_MSG_Test ((uint16_t) 0x100) +#define PPSMC_MSG_DPM_Voltage_Pwrmgt ((uint16_t) 0x101) +#define PPSMC_MSG_DPM_Config ((uint16_t) 0x102) +#define PPSMC_MSG_PM_Controller_Start ((uint16_t) 0x103) +#define PPSMC_MSG_DPM_ForceState ((uint16_t) 0x104) +#define PPSMC_MSG_PG_PowerDownSIMD ((uint16_t) 0x105) +#define PPSMC_MSG_PG_PowerUpSIMD ((uint16_t) 0x106) +#define PPSMC_MSG_PM_Controller_Stop ((uint16_t) 0x107) +#define PPSMC_MSG_PG_SIMD_Config ((uint16_t) 0x108) +#define PPSMC_MSG_Voltage_Cntl_Enable ((uint16_t) 0x109) +#define PPSMC_MSG_Thermal_Cntl_Enable ((uint16_t) 0x10a) +#define PPSMC_MSG_Reset_Service ((uint16_t) 0x10b) +#define PPSMC_MSG_VCEPowerOFF ((uint16_t) 0x10e) +#define PPSMC_MSG_VCEPowerON ((uint16_t) 0x10f) +#define PPSMC_MSG_DPM_Disable_VCE_HS ((uint16_t) 0x110) +#define PPSMC_MSG_DPM_Enable_VCE_HS ((uint16_t) 0x111) +#define PPSMC_MSG_DPM_N_LevelsDisabled ((uint16_t) 0x112) +#define PPSMC_MSG_DCEPowerOFF ((uint16_t) 0x113) +#define PPSMC_MSG_DCEPowerON ((uint16_t) 0x114) +#define PPSMC_MSG_PCIE_DDIPowerDown ((uint16_t) 0x117) +#define PPSMC_MSG_PCIE_DDIPowerUp ((uint16_t) 0x118) +#define PPSMC_MSG_PCIE_CascadePLLPowerDown ((uint16_t) 0x119) +#define PPSMC_MSG_PCIE_CascadePLLPowerUp ((uint16_t) 0x11a) +#define PPSMC_MSG_SYSPLLPowerOff ((uint16_t) 0x11b) +#define PPSMC_MSG_SYSPLLPowerOn ((uint16_t) 0x11c) +#define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint16_t) 0x11d) +#define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint16_t) 0x11e) +#define PPSMC_MSG_DISPLAYPHYStatusNotify ((uint16_t) 0x11f) +#define PPSMC_MSG_EnableBAPM ((uint16_t) 0x120) +#define PPSMC_MSG_DisableBAPM ((uint16_t) 0x121) +#define PPSMC_MSG_PCIE_PHYPowerDown ((uint16_t) 0x122) +#define PPSMC_MSG_PCIE_PHYPowerUp ((uint16_t) 0x123) +#define PPSMC_MSG_UVD_DPM_Config ((uint16_t) 0x124) +#define PPSMC_MSG_Spmi_Enable ((uint16_t) 0x122) +#define PPSMC_MSG_Spmi_Timer ((uint16_t) 0x123) +#define PPSMC_MSG_LCLK_DPM_Config ((uint16_t) 0x124) +#define PPSMC_MSG_NBDPM_Config ((uint16_t) 0x125) +#define PPSMC_MSG_PCIE_DDIPhyPowerDown ((uint16_t) 0x126) +#define PPSMC_MSG_PCIE_DDIPhyPowerUp ((uint16_t) 0x127) +#define PPSMC_MSG_MCLKDPM_Config ((uint16_t) 0x128) + +#define PPSMC_MSG_UVDDPM_Config ((uint16_t) 0x129) +#define PPSMC_MSG_VCEDPM_Config ((uint16_t) 0x12A) +#define PPSMC_MSG_ACPDPM_Config ((uint16_t) 0x12B) +#define PPSMC_MSG_SAMUDPM_Config ((uint16_t) 0x12C) +#define PPSMC_MSG_UVDDPM_SetEnabledMask ((uint16_t) 0x12D) +#define PPSMC_MSG_VCEDPM_SetEnabledMask ((uint16_t) 0x12E) +#define PPSMC_MSG_ACPDPM_SetEnabledMask ((uint16_t) 0x12F) +#define PPSMC_MSG_SAMUDPM_SetEnabledMask ((uint16_t) 0x130) +#define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131) +#define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132) +#define PPSMC_MSG_Thermal_Cntl_Disable ((uint16_t) 0x133) +#define PPSMC_MSG_SetTDPLimit ((uint16_t) 0x134) +#define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135) +#define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136) +#define PPSMC_MSG_ACPPowerOFF ((uint16_t) 0x137) +#define PPSMC_MSG_ACPPowerON ((uint16_t) 0x138) +#define PPSMC_MSG_SAMPowerOFF ((uint16_t) 0x139) +#define PPSMC_MSG_SAMPowerON ((uint16_t) 0x13a) +#define PPSMC_MSG_SDMAPowerOFF ((uint16_t) 0x13b) +#define PPSMC_MSG_SDMAPowerON ((uint16_t) 0x13c) +#define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d) +#define PPSMC_MSG_IOMMUPowerOFF ((uint16_t) 0x13e) +#define PPSMC_MSG_IOMMUPowerON ((uint16_t) 0x13f) +#define PPSMC_MSG_NBDPM_Enable ((uint16_t) 0x140) +#define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0x141) +#define PPSMC_MSG_NBDPM_ForceNominal ((uint16_t) 0x142) +#define PPSMC_MSG_NBDPM_ForcePerformance ((uint16_t) 0x143) +#define PPSMC_MSG_NBDPM_UnForce ((uint16_t) 0x144) +#define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0x145) +#define PPSMC_MSG_MCLKDPM_SetEnabledMask ((uint16_t) 0x146) +#define PPSMC_MSG_PCIeDPM_ForceLevel ((uint16_t) 0x147) +#define PPSMC_MSG_PCIeDPM_UnForceLevel ((uint16_t) 0x148) +#define PPSMC_MSG_EnableACDCGPIOInterrupt ((uint16_t) 0x149) +#define PPSMC_MSG_EnableVRHotGPIOInterrupt ((uint16_t) 0x14a) +#define PPSMC_MSG_SwitchToAC ((uint16_t) 0x14b) + +#define PPSMC_MSG_XDMAPowerOFF ((uint16_t) 0x14c) +#define PPSMC_MSG_XDMAPowerON ((uint16_t) 0x14d) + +#define PPSMC_MSG_DPM_Enable ((uint16_t)0x14e) +#define PPSMC_MSG_DPM_Disable ((uint16_t)0x14f) +#define PPSMC_MSG_MCLKDPM_Enable ((uint16_t)0x150) +#define PPSMC_MSG_MCLKDPM_Disable ((uint16_t)0x151) +#define PPSMC_MSG_LCLKDPM_Enable ((uint16_t)0x152) +#define PPSMC_MSG_LCLKDPM_Disable ((uint16_t)0x153) +#define PPSMC_MSG_UVDDPM_Enable ((uint16_t)0x154) +#define PPSMC_MSG_UVDDPM_Disable ((uint16_t)0x155) +#define PPSMC_MSG_SAMUDPM_Enable ((uint16_t)0x156) +#define PPSMC_MSG_SAMUDPM_Disable ((uint16_t)0x157) +#define PPSMC_MSG_ACPDPM_Enable ((uint16_t)0x158) +#define PPSMC_MSG_ACPDPM_Disable ((uint16_t)0x159) +#define PPSMC_MSG_VCEDPM_Enable ((uint16_t)0x15a) +#define PPSMC_MSG_VCEDPM_Disable ((uint16_t)0x15b) +#define PPSMC_MSG_LCLKDPM_SetEnabledMask ((uint16_t)0x15c) + +#define PPSMC_MSG_DPM_FPS_Mode ((uint16_t) 0x15d) +#define PPSMC_MSG_DPM_Activity_Mode ((uint16_t) 0x15e) +#define PPSMC_MSG_VddC_Request ((uint16_t) 0x15f) +#define PPSMC_MSG_MCLKDPM_GetEnabledMask ((uint16_t) 0x160) +#define PPSMC_MSG_LCLKDPM_GetEnabledMask ((uint16_t) 0x161) +#define PPSMC_MSG_SCLKDPM_GetEnabledMask ((uint16_t) 0x162) +#define PPSMC_MSG_UVDDPM_GetEnabledMask ((uint16_t) 0x163) +#define PPSMC_MSG_SAMUDPM_GetEnabledMask ((uint16_t) 0x164) +#define PPSMC_MSG_ACPDPM_GetEnabledMask ((uint16_t) 0x165) +#define PPSMC_MSG_VCEDPM_GetEnabledMask ((uint16_t) 0x166) +#define PPSMC_MSG_PCIeDPM_SetEnabledMask ((uint16_t) 0x167) +#define PPSMC_MSG_PCIeDPM_GetEnabledMask ((uint16_t) 0x168) +#define PPSMC_MSG_TDCLimitEnable ((uint16_t) 0x169) +#define PPSMC_MSG_TDCLimitDisable ((uint16_t) 0x16a) +#define PPSMC_MSG_DPM_AutoRotate_Mode ((uint16_t) 0x16b) +#define PPSMC_MSG_DISPCLK_FROM_FCH ((uint16_t)0x16c) +#define PPSMC_MSG_DISPCLK_FROM_DFS ((uint16_t)0x16d) +#define PPSMC_MSG_DPREFCLK_FROM_FCH ((uint16_t)0x16e) +#define PPSMC_MSG_DPREFCLK_FROM_DFS ((uint16_t)0x16f) +#define PPSMC_MSG_PmStatusLogStart ((uint16_t)0x170) +#define PPSMC_MSG_PmStatusLogSample ((uint16_t)0x171) +#define PPSMC_MSG_SCLK_AutoDPM_ON ((uint16_t) 0x172) +#define PPSMC_MSG_MCLK_AutoDPM_ON ((uint16_t) 0x173) +#define PPSMC_MSG_LCLK_AutoDPM_ON ((uint16_t) 0x174) +#define PPSMC_MSG_UVD_AutoDPM_ON ((uint16_t) 0x175) +#define PPSMC_MSG_SAMU_AutoDPM_ON ((uint16_t) 0x176) +#define PPSMC_MSG_ACP_AutoDPM_ON ((uint16_t) 0x177) +#define PPSMC_MSG_VCE_AutoDPM_ON ((uint16_t) 0x178) +#define PPSMC_MSG_PCIe_AutoDPM_ON ((uint16_t) 0x179) +#define PPSMC_MSG_MASTER_AutoDPM_ON ((uint16_t) 0x17a) +#define PPSMC_MSG_MASTER_AutoDPM_OFF ((uint16_t) 0x17b) +#define PPSMC_MSG_DYNAMICDISPPHYPOWER ((uint16_t) 0x17c) +#define PPSMC_MSG_CAC_COLLECTION_ON ((uint16_t) 0x17d) +#define PPSMC_MSG_CAC_COLLECTION_OFF ((uint16_t) 0x17e) +#define PPSMC_MSG_CAC_CORRELATION_ON ((uint16_t) 0x17f) +#define PPSMC_MSG_CAC_CORRELATION_OFF ((uint16_t) 0x180) +#define PPSMC_MSG_PM_STATUS_TO_DRAM_ON ((uint16_t) 0x181) +#define PPSMC_MSG_PM_STATUS_TO_DRAM_OFF ((uint16_t) 0x182) +#define PPSMC_MSG_UVD_HANDSHAKE_OFF ((uint16_t) 0x183) +#define PPSMC_MSG_ALLOW_LOWSCLK_INTERRUPT ((uint16_t) 0x184) +#define PPSMC_MSG_PkgPwrLimitEnable ((uint16_t) 0x185) +#define PPSMC_MSG_PkgPwrLimitDisable ((uint16_t) 0x186) +#define PPSMC_MSG_PkgPwrSetLimit ((uint16_t) 0x187) +#define PPSMC_MSG_OverDriveSetTargetTdp ((uint16_t) 0x188) +#define PPSMC_MSG_SCLKDPM_FreezeLevel ((uint16_t) 0x189) +#define PPSMC_MSG_SCLKDPM_UnfreezeLevel ((uint16_t) 0x18A) +#define PPSMC_MSG_MCLKDPM_FreezeLevel ((uint16_t) 0x18B) +#define PPSMC_MSG_MCLKDPM_UnfreezeLevel ((uint16_t) 0x18C) +#define PPSMC_MSG_START_DRAM_LOGGING ((uint16_t) 0x18D) +#define PPSMC_MSG_STOP_DRAM_LOGGING ((uint16_t) 0x18E) +#define PPSMC_MSG_MASTER_DeepSleep_ON ((uint16_t) 0x18F) +#define PPSMC_MSG_MASTER_DeepSleep_OFF ((uint16_t) 0x190) +#define PPSMC_MSG_Remove_DC_Clamp ((uint16_t) 0x191) +#define PPSMC_MSG_DisableACDCGPIOInterrupt ((uint16_t) 0x192) +#define PPSMC_MSG_OverrideVoltageControl_SetVddc ((uint16_t) 0x193) +#define PPSMC_MSG_OverrideVoltageControl_SetVddci ((uint16_t) 0x194) +#define PPSMC_MSG_SetVidOffset_1 ((uint16_t) 0x195) +#define PPSMC_MSG_SetVidOffset_2 ((uint16_t) 0x207) +#define PPSMC_MSG_GetVidOffset_1 ((uint16_t) 0x196) +#define PPSMC_MSG_GetVidOffset_2 ((uint16_t) 0x208) +#define PPSMC_MSG_THERMAL_OVERDRIVE_Enable ((uint16_t) 0x197) +#define PPSMC_MSG_THERMAL_OVERDRIVE_Disable ((uint16_t) 0x198) +#define PPSMC_MSG_SetTjMax ((uint16_t) 0x199) +#define PPSMC_MSG_SetFanPwmMax ((uint16_t) 0x19A) + +#define PPSMC_MSG_WaitForMclkSwitchFinish ((uint16_t) 0x19B) +#define PPSMC_MSG_ENABLE_THERMAL_DPM ((uint16_t) 0x19C) +#define PPSMC_MSG_DISABLE_THERMAL_DPM ((uint16_t) 0x19D) +#define PPSMC_MSG_Enable_PCC ((uint16_t) 0x19E) +#define PPSMC_MSG_Disable_PCC ((uint16_t) 0x19F) + +#define PPSMC_MSG_API_GetSclkFrequency ((uint16_t) 0x200) +#define PPSMC_MSG_API_GetMclkFrequency ((uint16_t) 0x201) +#define PPSMC_MSG_API_GetSclkBusy ((uint16_t) 0x202) +#define PPSMC_MSG_API_GetMclkBusy ((uint16_t) 0x203) +#define PPSMC_MSG_API_GetAsicPower ((uint16_t) 0x204) +#define PPSMC_MSG_SetFanRpmMax ((uint16_t) 0x205) +#define PPSMC_MSG_SetFanSclkTarget ((uint16_t) 0x206) +#define PPSMC_MSG_SetFanMinPwm ((uint16_t) 0x209) +#define PPSMC_MSG_SetFanTemperatureTarget ((uint16_t) 0x20A) + +#define PPSMC_MSG_BACO_StartMonitor ((uint16_t) 0x240) +#define PPSMC_MSG_BACO_Cancel ((uint16_t) 0x241) +#define PPSMC_MSG_EnableVddGfx ((uint16_t) 0x242) +#define PPSMC_MSG_DisableVddGfx ((uint16_t) 0x243) +#define PPSMC_MSG_UcodeAddressLow ((uint16_t) 0x244) +#define PPSMC_MSG_UcodeAddressHigh ((uint16_t) 0x245) +#define PPSMC_MSG_UcodeLoadStatus ((uint16_t) 0x246) + +#define PPSMC_MSG_DRV_DRAM_ADDR_HI ((uint16_t) 0x250) +#define PPSMC_MSG_DRV_DRAM_ADDR_LO ((uint16_t) 0x251) +#define PPSMC_MSG_SMU_DRAM_ADDR_HI ((uint16_t) 0x252) +#define PPSMC_MSG_SMU_DRAM_ADDR_LO ((uint16_t) 0x253) +#define PPSMC_MSG_LoadUcodes ((uint16_t) 0x254) +#define PPSMC_MSG_PowerStateNotify ((uint16_t) 0x255) +#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_HI ((uint16_t) 0x256) +#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_LO ((uint16_t) 0x257) +#define PPSMC_MSG_VBIOS_DRAM_ADDR_HI ((uint16_t) 0x258) +#define PPSMC_MSG_VBIOS_DRAM_ADDR_LO ((uint16_t) 0x259) +#define PPSMC_MSG_LoadVBios ((uint16_t) 0x25A) +#define PPSMC_MSG_GetUcodeVersion ((uint16_t) 0x25B) +#define DMCUSMC_MSG_PSREntry ((uint16_t) 0x25C) +#define DMCUSMC_MSG_PSRExit ((uint16_t) 0x25D) +#define PPSMC_MSG_EnableClockGatingFeature ((uint16_t) 0x260) +#define PPSMC_MSG_DisableClockGatingFeature ((uint16_t) 0x261) +#define PPSMC_MSG_IsDeviceRunning ((uint16_t) 0x262) +#define PPSMC_MSG_LoadMetaData ((uint16_t) 0x263) +#define PPSMC_MSG_TMON_AutoCaliberate_Enable ((uint16_t) 0x264) +#define PPSMC_MSG_TMON_AutoCaliberate_Disable ((uint16_t) 0x265) +#define PPSMC_MSG_GetTelemetry1Slope ((uint16_t) 0x266) +#define PPSMC_MSG_GetTelemetry1Offset ((uint16_t) 0x267) +#define PPSMC_MSG_GetTelemetry2Slope ((uint16_t) 0x268) +#define PPSMC_MSG_GetTelemetry2Offset ((uint16_t) 0x269) + +typedef uint16_t PPSMC_Msg; + +/* If the SMC firmware has an event status soft register this is what the individual bits mean.*/ +#define PPSMC_EVENT_STATUS_THERMAL 0x00000001 +#define PPSMC_EVENT_STATUS_REGULATORHOT 0x00000002 +#define PPSMC_EVENT_STATUS_DC 0x00000004 +#define PPSMC_EVENT_STATUS_GPIO17 0x00000008 + + +#pragma pack(pop) +#endif |